SN74CBTLV1G125 LOW-VOLTAGE SINGLE FET BUS SWITCH www.ti.com SCDS057H – MARCH 1998 – REVISED JUNE 2006 FEATURES • • • 5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation DBV PACKAGE (TOP VIEW) OE 1 A 2 GND 3 DCK PACKAGE (TOP VIEW) OE 1 A 2 GND 3 VCC 5 5 VCC 4 B B 4 See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION The SN74CBTLV1G125 features a single high-speed line switch. The switch is disabled when the output-enable (OE) input is high. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION TA –40°C to 85°C (1) (2) PACKAGE (1) TOP-SIDE MARKING (2) ORDERABLE PART NUMBER SOT (SOT-23) – DBV Reel of 3000 SN74CBTLV1G125DBVR V25_ SOT (SC-70) – DCK Reel of 3000 SN74CBTLV1G125DCKR VM_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. The actual top-side marking has one additional character that designates the assembly/test site. FUNCTION TABLE INPUT OE FUNCTION L A port = B port H Disconnect LOGIC DIAGRAM (POSITIVE LOGIC) 2 A OE 4 SW B 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998–2006, Texas Instruments Incorporated SN74CBTLV1G125 LOW-VOLTAGE SINGLE FET BUS SWITCH www.ti.com SCDS057H – MARCH 1998 – REVISED JUNE 2006 SIMPLIFIED SCHEMATIC, EACH FET SWITCH A B (OE) Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 4.6 V VI Input voltage range (2) –0.5 4.6 V 128 V VI/O < 0 –50 mA DBV package 206 DCK package 252 Continuous channel current IIK Input clamp current θJA Package thermal impedance (3) Tstg Storage temperature range (1) (2) (3) –65 150 UNIT °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) VCC VIH High-level control input voltage VIL Low-level control input voltage TA Operating free-air temperature (1) 2 Supply voltage MIN MAX 2.3 3.6 VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 V V VCC = 2.3 V to 2.7 V 0.7 VCC = 2.7 V to 3.6 V 0.8 –40 UNIT 85 V °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback SN74CBTLV1G125 LOW-VOLTAGE SINGLE FET BUS SWITCH www.ti.com SCDS057H – MARCH 1998 – REVISED JUNE 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP (1) MAX TEST CONDITIONS VIK VCC = 3 V, II = –18 mA II UNIT –1.2 V VCC = 3.6 V, VI = VCC or GND ±1 µA Ioff VCC = 0, VI or VO = 0 to 3.6 V 10 µA ICC VCC = 3.6 V, IO = 0, VI = VCC or GND 10 µA 300 µA ∆ICC (2) Control inputs VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND Ci Control inputs VI = 3 V or 0 Cio(OFF) 2.5 VO = 3 V or 0, OE = VCC VCC = 2.3 V, TYP at VCC = 2.5 V ron (3) II = 64 mA VI = 0 VI = 1.7 V, VI = 0 VCC = 3 V VI = 2.4 V, (1) (2) (3) pF 7 pF 7 10 II = 24 mA 7 10 II = 15 mA 15 25 II = 64 mA 5 7 II = 24 mA 5 7 II = 15 mA 10 15 Ω All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Measured by the voltage drop between A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) (1) VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V FROM (INPUT) TO (OUTPUT) tpd (1) A or B B or A ten OE A or B 1 4 tdis OE A or B 1 5 PARAMETER MIN MAX MIN 0.15 UNIT MAX 0.25 ns 1 4 ns 1 4.1 ns The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance). Submit Documentation Feedback 3 SN74CBTLV1G125 LOW-VOLTAGE SINGLE FET BUS SWITCH www.ti.com SCDS057H – MARCH 1998 – REVISED JUNE 2006 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND RL LOAD CIRCUIT VCC CL RL V∆ 2.5 V ±0.2 V 3.3 V ±0.3 V 30 pF 50 pF 500 Ω 500 Ω 0.15 V 0.3 V VCC Timing Input VCC/2 0V tw tsu VCC VCC/2 Input th VCC VCC/2 VCC/2 Data Input VCC/2 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC VCC/2 Input 0V tPHL tPLH VOH VCC/2 Output VCC/2 VOL tPHL Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH VOH Output VCC/2 VCC Output Control VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VCC/2 0V tPZL tPLZ VCC VCC/2 tPZH VOL + V∆ VOH − V∆ VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Submit Documentation Feedback VOL tPHZ VCC/2 Figure 1. Load Circuit and Voltage Waveforms 4 VCC/2 VOH ≈0 V PACKAGE OPTION ADDENDUM www.ti.com 29-May-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74CBTLV1G125CRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74CBTLV1G125CRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74CBTLV1G125DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74CBTLV1G125DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74CBTLV1G125DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBTLV1G125DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBTLV1G125DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Dec-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74CBTLV1G125DBVR DBV 5 SITE 35 180 9 3.23 3.17 1.37 4 8 Q3 SN74CBTLV1G125DBVR DBV 5 SITE 34 180 9 3.23 3.17 1.37 4 8 Q3 SN74CBTLV1G125DCKR DCK 5 SITE 35 180 9 2.24 2.34 1.22 4 8 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Dec-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74CBTLV1G125DBVR DBV 5 SITE 35 202.0 201.0 28.0 SN74CBTLV1G125DBVR DBV 5 SITE 34 205.0 200.0 33.0 SN74CBTLV1G125DCKR DCK 5 SITE 35 202.0 201.0 28.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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