AGERE TMXF84622

Advance Data Sheet, Rev. 2
July 2001
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
1 Features
■
Versatile IC supports 622 Mbits/s/155 Mbits/s
SONET/SDH interface solutions for T3/E3, DS2,
T1/E1/J1, and DS0/E0/J0 applications.
PDH Interfaces
■
6 DS3, 21 x DS2, or 6 E3, 12 x E2.
■
Twenty-one framed or unframed DS1 or E1 interfaces.
■
Two additional protection channels for DS2/DS1/
E1.
■
Implementation supports both linear (1 + 1, unprotected) and ring (UPSR) network topologies.
■
Provides full termination of up to 63 (21 x 3) E1,
84 (28 x 3) T1, or 84 (28 x 3) J1.
■
Low 3.3 V power supply.
■
–40 °C to +85 °C industrial temperature range.
■
Interprets STS/AU/TU-3 pointers.
■
700-pin ball grid array (PBGA) package.
■
■
Complies with Telecordia Technologies*, ITU,
ANSI †, ETSI, and Japanese TTC standards: GR253-CORE, GR-499, (ATT) TR-62411, ITU-T
G.707, G.704, G.706, G.783, G.962, G.964,
G.965, Q.542, T1.105, JT-G704, JT-G706, JTG707, JT-I431-a, ETS 300 417-1-1, ETS 300 011,
T1.107, T1.404.
Synchronizes 8 kHz frame and 2 kHz superframe
to system-shelf-timing reference by setting the
transmit STS-3/STM-1 pointers to a fixed value
of 522 with an adjustable frame location.
■
Monitors/terminates SPE path overhead.
SONET/SDH Interface
STS/STM Pointer Interpreter
STS3 Serial Interconnect
■
Serial interface to mate devices.
■
4 Ultramapper devices, 3 configured as mate
devices, provide full termination of an STS-12/
STM-4. A 4 chip solution to terminate
336 DS1s/J1s or 252 E1s.
■
Termination of a single 622 Mbits/s STS-12/STM-4
or single 155 Mbits/s STS-3/STM-1.
■
Built-in clock and data recovery circuit at
622 Mbits/s STS-12/STM-4 interface.
■
Supports overhead processing for all transport and
path overhead bytes.
VT Termination/Generation 84/63 (3x28/21)
■
Optional insertion and extraction of overhead bytes
via a serial transport overhead access channel.
Configurable as dedicated DCC channels.
■
Supports TIM-V generation and termination for all
84/63 (3x28/21) VT/TU signals.
■
■
Software controlled linear 1 + 1 protection via dedicated interface to protection card.
■
Full path termination and SPE extraction/insertion.
Synchronizes VT/TU SPE to system-shelf-timing
reference by setting the transmit VT/TU pointers to
fixed values for asynchronous mapping or by
dynamically changing the transmit VT/TU pointers
for byte synchronous mapping.
■
SONET/SDH compliant condition and alarm
reporting.
■
Fixed pointer generation in transmit side for asynchronous mapping.
■
Built-in diagnostic loopback modes.
■
■
8 kHz line frame synchronizing output.
Dynamic pointer generation in transmit side for
byte-synchronous mapping.
* Telecordia Technologies is a trademark of Telecordia Technologies Inc.
† ANSI is a registered trademark of American National Standards
Institute, Inc.
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
Features (continued)
E13 Features (3)
Mapping/Multiplexing Modes 84/63 (3x28/21)
■
Configurable multiplexer/demultiplexer for up to
16 E1 signals, or 4 E2 signals to/from an E3 signal.
■
Maps DS3 clear channel or framed signal into STS-1
or TUG-3.
■
Independently configurable 4 E12 multiplexer/demultiplexers for up to 16 E1 signals to/from 4 E2 signals.
■
Maps T1/E1/J1 into VT/TU structures.
■
■
Maps T1 into VT1.5/TU-11/TU-12.
Provisionable time-slot selection for E1, E2 insertion,
or drop via the cross connect macro.
■
Maps J1 into VT1.5/TU-11/TU-12.
■
■
Maps E1 into VT2/TU-12.
■
Supports asynchronous, byte-synchronous, and bitsynchronous mapping.
E12 multiplexers capable of generating alarm indication signal (AIS) and remote alarm indicator (RAI)
signals.
■
■
Supports UPSR applications via the dedicated ring
interface and an external tributary selector.
E23 multiplexer capable of generating AIS and RAI
signals.
■
■
Supports all valid T1/E1/J1 multiplexing structures
into STS-1 and STS-3/STM-1.
Configurable HDB3 encoder/decoder for E3 output/
input.
■
■
STS-3/STS-1/SPE/VTG/VTx.
E1 and E2 transmit path monitors that detect loss of
clock (LOC) and AIS.
■
■
STM-1/AU-3/TUG-2/TU-1x/VC-1x.
E2 receive path monitor that detects LOC, AIS, and
RAI.
■
STM-1/AU-4/TUG-3/TUG-2/TU-1x/VC-1x.
■
■
Allows grooming of VTs/TUs in granularity of TUG-2s
within the STS-3/STM-1 signal.
E3 receive monitor that detects loss of signal (LOS),
LOC, bipolar violation (BPV), AIS, and RAI.
■
E3 and E2 loopback modes.
■
Supports J2 trace identifier monitoring/insertion.
■
■
Configurable VT/TU slot selection for DS1, E1, J1
insertion and drop.
Complies with ITU’s G.703, G.742, G.751, and
G.775.
■
Automatic receive monitor functions include VT/TU
RDI-V, REI-V, BIP-2 errors, AIS-V, LOP-V.
■
Complies with GR-253-CORE, GR-499, ITU-T
G.707, G.704, G.783, T1.105, JT-G707, ETS 300
417-1-1.
DS3/DS2/DS1/E1 Cross Connect Features
■
Configurable crosspoint interconnect for up to 28 x 3
DS1 signals or 21 x 3 E1 signals to/from the framer,
30 external pins, and 28 x 3 signal channels to/from
the M13 and VT mapper. Also supports up to 7 x 3
DS2 signals to/from the external pins or M12 MUXes,
connecting to the M13 MUX M23 block.
M13 Features (3)
■
Configurable multiplexer/demultiplexer for
28 DS1 signals, 21 E1 signals, or 7 DS2 signals to/
from a DS3 signal.
■
Connects six clear channel DS3, E3, and STS-1 signals from the external pins to the M13, E13,
SPE_mapper, and STS1-LT.
■
Operates in either M23 or C-bit parity mode.
■
■
Provisionable time-slot selection for DS1, E1, and
DS2 insertion or drop.
Also connects three unchannelized DS3 and E3 signal to/from the external NSMI interface to the SPE,
M13, E13, framer, or TPG blocks.
■
Full alarm monitoring and generation (LOS, BPV,
EXZ, OOF, SEF, AIS, RAI, FEAC, P-bit and C-bit parity errors, FEBE).
■
The three NSMI pins can also be shared for STS-1
LT.
■
Any mix of 168 DS1, E1 signals may be interconnected. Any of the available DS1/E1 signal sources
may be connected to any of 168 signal destinations
in the DS1/E1 cross connect. Multicast or broadcast
operation (one port to many) is supported for up to
168 channels. Also, any channel n at the source can
be connected to its corresponding destination channel n, where n ranges from 1 to 84 for most sources
and destinations.
■
HDLC transmitter with 128-byte data buffer and
HDLC receiver with 128-byte data FIFO for the C-bit
parity path maintenance data link.
■
DS3, DS2, DS1, and E1 loopback and loopback
request generation.
■
Complies with T1.102, T1.107, T1.231, T1.403,
T1.404, GR 499, G.747, and G.775.
2
Agere Systems Inc.
Advance Data Sheet, Rev. 2
July 2001
Features (continued)
■
■
■
■
■
■
■
■
■
■
■
Any mix of DS2, DS3, or E3 signals may be interconnected.
Cross connect allows 16 x 3 E1 signals to/from E13
modules to framer, M13, VT mapper, and external
pins.
There are 4 x 3 E2 signals to/from E13 to external
pins, TPG generator/monitor.
There are 3 E3 signals to/from the E13 block to
external pins, TPG generator/monitor, and SPE mapper.
Jitter attenuation may also be inserted in-line on any
DS1/E1 channel. (Note that cascading of jitter attenuators is not allowed.)
Standard network loopback or straightaway facility
testing is supported for DS1/E1 and DS3/E3. Any
source or transmitter may be replaced by a test-pattern generator capable of injecting idle standardsbased pseudorandom bit sequence test patterns, or
AIS (blue) alarm. Any sink or receiver may be
replaced by a test-pattern monitor, which can detect/
count bit errors in a pseudorandom test sequence, or
loss of frame or loss of synchronization.
One to any loopback is supported for up to
168 channels in DS1/E1 channels in blocks VT mapper, M13, E13, and framer. One-to-one loopback is
supported in all DS1/E1 channels. One-to-one loopback for DS3/E3/STS-1 channels in blocks M13,
E13, and SPE mapper.
Loopbacks may be configured to sectionalize a circuit for identifying faults or misconfiguration during
out of service maintenance.
Fast alarm channels are supported for VT mapper,
E13, or M13 to framer interconnects for alarm indication signal (AIS or blue alarm), and VT mapper only
for remote alarm indicator (RAI or yellow alarm). This
feature reduces the propagation delay of the alarms
by eliminating multiple integration of alarm conditions.
Supports framer-only, transport (framer LIU, M13,
E13, and VT mapper), and switching (CHI and PSB)
modes of operation.
TOAC outputs are available in DS1/E1 framed format
at any destination. Any DS1/E1 channel can be used
as TOAC inputs.
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
DS3/E3 Digital Jitter Attenuation Features
■
The PLL bandwidth, damping factor, and sampling
rates are programmable.
■
The DJA macro accepts/delivers DS3/E3 clock and
data from/to the cross connect macrocell.
T1/E1/J1 Framing Features 84/63 (3x28/21)
■
28/21 T1/E1/J1 channels.
■
Line coding: B8ZS, HDB3, ZCS, AMI, and
CMI (JJ20-11).
■
■
E1 framing: G.704 basic and CRC-4 multiframe consistent with G.706.
■
J1 framing modes: JESF (Japan).
■
Supports T1 and E1 unframed and transparent transmission format.
■
T1 signaling modes: transparent; register and system access for ESF 2-state, 4-state, and 16-state;
D4 2-state, 4-state, and 16-state; SLC-96 2-state,
4-state, and 16-state; J-ESF handling groups maintenance and signaling; VT 1.5 SPE 2-, 4-, 16-state.
■
E1 signaling modes: transparent; register and system access for entire TS16 multiframe structure as
per ITU G.732.
■
Signaling debounce and change of state interrupt.
■
V5.2 Sa7 processing.
■
Alarm reporting and performance monitoring per
AT&T, ANSI, ITU-T, and ETSI standards.
■
Facility data link features:
— HDLC or transparent access for either ESF or
DDS+ FDL frame formats.
— Register/stack access for SLC-96 transmit and
receive data.
— Extended superframe (ESF): automatic transmission of the ESF performance report messages
(PRM). Automatic transmission of the ANSI
T1.403 ESF performance report messages.
Automatic detection and transmission of the ANSI
T1.403 ESF FDL bit-oriented codes.
— Register/stack access for all CEPT Sa-bits transmit and receive data.
■
HDLC features:
— HDLC or transparent mode.
— Programmable logical channel assignment: any
time slot, any bit for ISDN D-channel, also inserts/
extracts C-channels for V5.1, V5.2 interfaces.
— 64 logical channels in both transmit and receive
direction (any framing format).
DS1/E1 Digital Jitter Attenuation Features
■
PLL-free receive operation using built-in digital jitter
attenuator (in VT/VC mode or M13 mode).
■
Configurable to meet jitter and MTIE requirements.
Agere Systems Inc.
T1 framing modes: ESF, D4, SLC ®-96, T1 DM DDS,
and SF (Ft only).
3
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Features (continued)
— Maximum channel data rate: 64 kbits/s.
— Minimum channel data rate: 4 kbits/s (DS1-FDL or
E1 Sa-bit).
— 128-byte FIFO per channel in both transmit and
receive direction.
— Tx to Rx loopback supported.
■
System interfaces:
— Concentration highway interface.
— Single clock and frame synchronizing signals;
programmable clock rates at 2.048 MHz,
4.096 MHz, 8.192 MHz, and 16.384 MHz;
programmable data rates at 2.048 Mbits/s,
4.096 Mbits/s, and 8.192 Mbits/s;
programmable clock edges and bit/byte offsets.
— Parallel system bus interface at 19.44 MHz for
data and signaling: single clock and frame synchronizing signals.
— Time-division multiplex data rate serial interface at
1.544 MHz or 2.048 MHz. Twenty-eight receive
data, clock, and frame synchronizing signals.
Twenty-eight transmit data signals with a global
clock and frame synchronization.
— Network serial multiplexed interface (NSMI) minimal pin count serial interface at 51.84 MHz optimized for data and IMA applications.
Advance Data Sheet, Rev. 2
July 2001
SPEMPR Features
■
The SPE mapper accepts/delivers TUG-2 data from/
to the VT mapper. The TUG-2 data is mapped/
demapped either to/from an AU-3/STS-1 signal for
the North American digital systems or to/from a
TUG-3 signal for the ITU-based systems.
■
The SPE mapper accepts/delivers DS3 data from/to
the M13 MUX/deMUX. The DS3 data is mapped/
demapped either to/from an AU-3/STS-1 signal for
the North American digital systems or to/from a
TUG-3 signal for the ITU-based systems.
■
The SPE mapper accepts/delivers a clear DS3 signal
at 44.736 Mbits/s rate. The clear DS3 signal is
mapped/demapped essentially the same way as
M13 signal described above.
■
The SPE mapper accepts/delivers E3 data from/to
the E13 MUX/deMUX. The E3 data is mapped/
demapped either to/from an AU-3/STS-1 signal for
the North American digital systems or to/from a
TUG-3 signal for the ITU-based systems.
■
The SPE mapper accepts/delivers a clear E3 signal
at 34.368 Mbits/s rate. The clear E3 signal is
mapped/demapped essentially the same way as E13
signal described above.
■
The SPE mapper has a DS3/E3 loopback circuit
placed for the functions of demapping and remapping a DS3/E3 signal. It is particularly useful in cases
where a DS3/E3 signal mapped as an AU-3/STS-1
signal has to be remapped as a TUG-3 signal or vice
versa.
■
The SPE mapper supports a path overhead access
channel more commonly known as the POAC channel. Seven path overhead bytes namely J1, C2, F2,
H4, F3, K3, and N1 may be inserted/dropped
through this channel. This channel works as the
master, which means that this channel provides a
clock in both transmit and receive directions and
POH data may be inserted by the user on the transmit side or dropped by the block in the receive side.
■
Path overhead byte B3 (BIP error) generation/detection and programmable BIP-8 bit error rate insertion.
■
Programmable clear on read/clear on write registers.
■
Signal fail and signal degrade indicators available to
report bit error rates above a certain programmable
threshold.
MPU Features
■
21-bit address/16-bit data bus microprocessor interface.
■
Synchronous (16 MHz to 66 MHz)/asynchronous
microprocessor interface modes.
■
Microprocessor data bus parity monitoring.
■
Summary of 2 level priority interrupts from major
functional blocks/maskable.
■
Separate device interrupt outputs for automatic protection switch and the Ultramapper global interrupt.
■
Global configuration of network performance monitoring counters operation.
■
Global software resets.
■
Global enabling and powering down of major functional blocks.
■
Miscellaneous global configuration and control.
4
Agere Systems Inc.
Advance Data Sheet, Rev. 2
July 2001
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Features (continued)
■
Capable of detecting/inserting alarm indication signals (AIS), remote defect indication signals (RDI),
and remote error indication signals (REI).
■
Numerous monitoring functions provided on all the
TUG-3 path overhead bytes.
■
Supports unidirectional path switch ring (UPSR)
applications.
■
N1 tandem connection support is provided.
■
The TUG3 pointer processor can be used for an add/
drop multiplexer.
■
Complies with GR-253-CORE, T1.105, ITU-T G.707,
ITU-T G.831, G.783, ETS 300 417-1-1.
STS12 Pointer Processor Features
■
SONET and SDH compliant.
■
Configurable STS-3/STM-1 or STS-12/STM-4 mode.
■
Supporting an arbitrary mix of STS-1 and STS3c tributaries, and SDH equivalents.
■
■
Configurable connection for up to 3 STS1 signals
from 3 STS1LT PP blocks to any 1 up to 3 STS1 slots
of any 1 of 4 TMUX transmit interfaces. Clock and
control signals are provided by the TMUX transmit
interfaces and data is supplied by the STS1LT
receive blocks.
■
Configurable connection for up to 12 STS1 signals
from the STS12PP transmit block to any 1 up to
3 STS1 slots of any 1 of 4 TMUX transmit interfaces.
Clock and control signals are provided by the TMUX
transmit interfaces and data is supplied by the
STS12PP transmit blocks.
■
Configurable connection for up to 9 STS1 signals
from 3 CDR receive blocks to any 1 up to 3 STS1
slots of any 1 of 4 TMUX transmit interfaces. Clock
and control signals are provided by the TMUX transmit interfaces and data is supplied by the CDR
receive blocks.
■
Configurable connection for up to 3 STS1 signals
from 6 SPE mapper transmit blocks to any 1 of
3 STS1LT transmit blocks. Clock and control signals
are provided by the STS1LT transmit block and data
is supplied by the SPE mapper transmit block.
■
Configurable connection for up to 3 STS1 signals
from any 1 up to 3 STS1 slots of any 1 of 4 TMUX
receive interfaces to any 1 of 3 STS1LT transmit
blocks. Data is provided by the TMUX receive interfaces for this transfer.
■
Configurable connection for up to 9 STS1 signals
from any 1 up to 3 STS1 slots of any 1 of 4 TMUX
receive interfaces to any 1 of 3 CDR transmit blocks.
Clock, control signals, and data are provided by the
TMUX receive interfaces for this transfer.
■
Configurable connection for up to 3 STS1 signals
from 3 STS1LT receive blocks to any 1 of 6 SPE
mapper receive blocks. Clock, control signals, and
data are provided by the STS1LT receive block for
this transfer.
■
Configurable connection for up to 6 STS1 signals
from any 1 up to 3 STS1 slots of any 1 of 4 TMUX
receive interfaces to any 1 of 6 SPE mapper receive
blocks. Clock, control signals, and data are provided
by the TMUX receive interfaces for this transfer.
■
Loss of clock detectors on three serial 155 MHz clock
inputs from three CRD RX blocks and one serial
155 MHz clock input from CDR TX block.
Complies with GR-253-CORE, T1.105, G.707,
G.783, G.806, G.821, and ETSI 417-1-1.
STS1LT Features
■
Supports standard SPE mappings for sub-STS-1
payloads (VT mapped: 28 DS1, 28 J1, or 21 E1 signals).
■
Supports standard SPE mappings for STS-1 payloads ( DS3).
■
Detects STS-1 loss-of-signal (LOS) conditions.
■
Detects STS-1 out-of-frame and loss-of-frame (OOF/
LOF) conditions.
■
Provides an 8-bit parallel bus interface for an STS-1
signal.
■
Provides STS-1 selectable scrambler/descrambler
functions and B1/B2/B3 generation/detection.
■
Provides STS-1 pointer interpretation. Detects AIS-P
and LOP.
■
Provides STS-1 pointer processing.
■
Complies with GR-253-CORE, T1.105, G.707,
G.783, G.826, G.821, and ETSI 417-1-1.
STS1 XC Features
■
3 STS1 slots of any 1 of 4 TMUX transmit interfaces.
Clock and control signals are provided by the TMUX
transmit interfaces and data is supplied by the SPE
mapper transmit blocks.
Configurable connection for up to 6 STS1 signals
from 6 SPE mapper transmit blocks to any 1 up to
Agere Systems Inc.
5
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Features (continued)
Advance Data Sheet, Rev. 2
July 2001
VT/TU Features
■
LOF detection, OOF detection, REI monitoring, RDI
monitoring, and B2 error detection is performed on
the three serial 155 Mbits/s data inputs from the CDR
receive blocks.
■
Maps T1/E1/J1 into VT/TU structures:
— T1 into VT1.5/TU-11/TU-12.
— J1 into VT1.5/TU-11/TU-12.
— E1 into VT2/TU-12.
■
REI and RDI are generated from the received data
and sent to the transmit side for insertion in the transmitted serial 155 Mbits/s data.
■
Maps VC-11/VC-12 into VTG/TUG-2 structures:
— VC-11 into VT1.5/TU-11/TU-12/VTG/TUG-2.
— VC-12 into VT2/TU-12/VTG/TUG-2.
■
B2 is calculated and inserted in the transmitted serial
data. B2 error insertion is allowed.
■
Supports asynchronous, byte synchronous, and bit
synchronous mappings.
■
Supports automatic generation or microprocessor
overwrite of one bit RDI-V and one bit RFI-V.
■
Multiplexes twelve STS-1 signals or four STS-3c signals into a SONET STS-12 signal.
Supports automatic generation or microprocessor
overwrite of enhanced RDI-V.
■
Multiplexes three STS-1 signals into a SONET
STS-3 signal.
Supports ADM applications with tributary loopback
and tributary pointer processing.
■
Supports unidirectional path switch ring (UPSR)
applications with a low-order path overhead access
channel.
■
Supports TIM-V generation and termination for all
28/21 VT/TU signals.
■
Supports BIP-V BER insertion and detection.
■
Demultiplexes twelve STS-1 signals or four STS-3c
signals from a SONET STS-12 signal.
Supports fast AIS generation for downstream
devices.
■
Demultiplexes three STS-1 signals from a SONET
STS-3 signal.
Supports one second error counters for BIP-V and
REI-V.
■
Complies with GR-253-CORE, G.707, T1.105,
G.704, G.783, JT-G707, GR-499, ETS 300 417-1-1.
TMUX Features
■
■
■
Multiplexes four STM-1 (AU-4 or 3xAU-3) signals into
an SDH STM-4 signal.
■
Multiplexes three VC-3 signals into an SDH STM-1
(3xAU-3) signal.
■
Multiplexes three VC-3 signals into an SDH STM-1
(AU-4) signal via a TUG-3 construction.
■
■
■
Demultiplexes four STM-1 (AU-4 or 3xAU-3) signals
from an SDH STM-4.
■
Demultiplexes three VC-3 signals from an SDH STM1 (3xAU-3) signal.
Test Pattern Generator Features
■
Demultiplexes three VC-3 signals from an SDH STM1 (AU-4) signal via a TUG-3 deconstruction.
■
Configurable test pattern generator: DS1, E1, DS2,
E3, DS3, and STS1 formats.
■
Provides STS1-only mode for receive and transmit
directions.
■
■
Provides complete functionality for SDH MSP 1 + 1
protection switching.
■
Provides SONET/SDH loss-of-signal (LOS), out-offrame (OOF) and loss-of-frame (LOF) detection.
Pseudorandom bit sequence (PRBS, also known as
pseudonoise or PN sequences) based on maximallength feedback shift register sequences; PN codes
selectable from the following options: QRSS,
PRBS15, PRBS20, PRBS23, ALT_01, ALL_ONES,
USER pattern (16 bits, repeating).
Provides STS-12/STM-4/STS-3/STM-1/STS1 selectable scrambler/descrambler functions.
■
■
The test pattern can be transmitted either unframed
or as the payload of a framed signal as defined in
ITU-T.
■
Provides STS-12/STM-4/STS-3/STM-1/STS1 B1/B2/
B3 generation/detection.
■
Single bit errors or framing errors may be injected
into any test pattern, under register control.
■
Provides STS-12/STM-1/STS-3/STM-1/STS1/
pointer interpretation.
■
■
Complies with GR-253-CORE, T1.105, G.707,
G.783, G.806, G.821, and ETSI 417-1-1.
Any sink or receiving channel may be replaced by a
test pattern monitor, which can detect and count bit
errors or misconfigurations, and/or detect idle conditions or AIS.
6
Agere Systems Inc.
Advance Data Sheet, Rev. 2
July 2001
Features (continued)
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
System Test and Maintenance
■
DataLink (DS1-ESF DL) and SSM (E1 multiframe
Sa) fields read/writable.
■
A variety of loopback modes implemented on
SONET/SDH side as well as on framer level.
■
Supports all Ultramapper modes of operation.
■
■
Complies with T1.107, T1.231, T1.403, G.703,
G.704, O.150.
Built-in test pattern generator and monitor configurable for simultaneously testing E1, DS1, DS2, E3,
DS3, and STS1 (one channel each).
CDR Features
Microprocessor Interface
■
Receives data at OC-12/STS-12 (622.08 Mbits/s)
data rate.
■
21-bit address and 16-bit data interface with 16 MHz
to 66 MHz read and write access.
■
Single low-voltage power supply.
■
Compatible with most industry-standard processors.
■
155.52 MHz or 77.76 MHz input reference clock for
on-chip PLL.
■
On-chip PLL for clock synthesis, requiring only one
external resistor, generating 16 phases, providing
resolution of ~100 ps.
■
PLL bypass mode for functional test.
■
Modular design to incorporate n = 2 to 16 channels.
■
Meets type B jitter tolerance specification of ITU-T
Recommendation G.958.
■
No output clock drift in absence of data transitions
once lock is acquired.
■
Built-in test features.
Chip Testing and Maintenance
■
IEEE * 1149.1 JTAG boundary scan.
Interface to Other Agere Devices
Seamless interface to the following Agere Systems
devices:
■
TADM042G5
■
Super Mapper
* IEEE is a registered trademark of the Institute of Electrical and
Electronics Engineers, Inc
Agere Systems Inc.
7
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
2 The SONET/SDH Ultramapper
2.1 Overview
The SONET/SDH Ultramapper device integrates the SONET/SDH line, path, and tributary termination functions
with M13/E13 multiplex functions and the primary rate framing function. It is designed to drive either an OC-12/
STM-4 or OC-3/STM-1 optical signal directly or to allow for modular growth in terminal or add/drop applications.
The Ultramapper provides a versatile interface for all STS-12/STM-4, STS-3/STM-1, and STS-1 termination applications in point-to-point scenarios and for ring applications. This chip can be used in tributary shelf applications for
up to 84 T1 or J1 or 63 E1 line cards, providing all possible mappings into SONET/SDH, because of the flexibility of
the mappings, software upgrades from M13/E13 mapped connections to VT/TU mapped connections are possible.
This device can also be used for DS3/E3/DS2 applications.
A single Ultramapper is capable of processing the aggregate bandwidth of one STS-3/STM-1 to 84/63 DS1/E1s.
Further, a single Ultramapper can process the aggregate bandwidth of two STS-3/STM-1s, terminated as an STS12/STM-4, to six DS3/E3s. Additionally, a single Ultramapper can function as an STS-12/STS-3/STM-4/STM-1
add-drop MUX by terminating up to three STS-1/STM-0 channels or one AU-4 channel and using the internal
pointer processors to forward any nonterminated channels. By communicating to three other mate devices via the
serial STS-3/STM-1 link interface, it is capable of terminating a full STS-12/STM-4 signal.
X8/X63 PDH
TRIBUTARY TERMINATION
X12/X4 SONET/SDH
ADM FRONT END
5
FRM
X84/X63
DS1/J1/E1
HIGH-SPEED IF
4
CDR
STS1LT
(X3)
622 Mbits/STS12/
STM4
155 Mbits/STS-3/
STM-1
PLL INTERFACE
TPG/TPM
42
SYSTEM
INTERFACES
(X6) DS3/E3
(X3) STS1
TMUX
CLOCK/SYNC
RX/TX CLKS AND SYNC
8
11
STSPP
MRXC
S
T
S
X
C
STS12/
STM4/
STS3/
STM1
SPEMPR
(X3)
(0—2)
24
(X3) NSMI
(X3) STS1
DS1/J1/E1
(X3)
VT/TU
X28/X21
VTMPR
DS2/E2
204
SHARED LOW-SPEED I/O
DS3/E3
SWITCHING MODES:
PSB (X16—X48/X63 DS1/J1/E1
X2016 DS0/E0
CHI (X42—X2016 DS0/E0
JTAG IF
MPU IF
6
6
6
(X3)
(X3)
(X3)
DS3/E3 PLL IF
STS3/STM1
MATE
(OPTIONAL)
INTERCONNECT
LOPOH
(SUPPORTS UPSR)
X84/X63
DS1/E1
DJA
DS1/J1/E1 (X30—x28/x21 + PROT.
DS2/E2 (X30—x21/x12 + PROT.
VT/TU/(X30—X28/X21 + PROT.
6
X6
DS3/E3
DJA
CDR
14
JTAG
MPU
TRANSPORT MODES:
(X3)
M13/E13
MUX
6
CDR
5
622 Mbits/STS12/
STM4
155 Mbits/STS-3/
STM-1
4
49
MSP 1 + 1
SPEMPR
(X3)
(3—5)
TOAC POAC
2351(F)
Figure 1. Functional Diagram of Ultramapper
8
Agere Systems Inc.
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
2 The SONET/SDH Ultramapper (continued)
2.2 Application Diagrams
TDM BUS
2417
2417
TSI
ULTRA
MAPPERS
ULTRA
MAPPER
TO MATE
DEVICES
MUX
PP
DS3/E3
XC
SPE/AU3
MAP
M13
MUX
DS0/E0
(CHI OR PSB)
DS1/E1
T1/E1
FRAMER
VT/TU
MAP
DS1/E1
(PSB OR NSMI)
1938 (F)
Figure 2. Switching Application of the Ultramapper
NONTERMINATED DS1/E1s
OR VT/TUs LOOPED BACK
DS3/E3
MUX
PP
XC
SPE/AU3
MAP
M13
MUX
T1/E1
FRAMER
VT/TU
MAP
VT/TU
PM
DS1/E1
NONTERMINATED TUG-3s
LOOPED BACK
1939 (F)
Figure 3. Transport Application of the Ultramapper
Agere Systems Inc.
9
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
2 The SONET/SDH Ultramapper (continued)
SYSTEM BUS
INTERFACE
MSP 1 + 1
UMPR #1, #2, #3, #4
PM
MPR
PM
MPR
PM
MPR FRMR
OHP
PM
MPR
FRMR 28/21
OHP
FRMR
OHP
M13
FRMR
OHP
M13
M13
M13
OPTICS
1417
DS0
E0
SWITCH
MSP 1 + 1
PM
MPR
OPTICS
1417
FRMR
OHP
M13
1084 (F)
Note: In this application, 84/63 DS1/E1s per Ultramapper can be MUXed to a total of three DS3/E3 and then mapped to STS-1/AU-3, STS-3/
STM-1, or STS-12/STM-4 as desired. Alternatively, 84/63 DS1/E1s per Ultramapper can be mapped to 84.63 VT/TU and then mapped to
STS-1/AU-3, STS-3/STM-1, or STS-12/STM-4 as desired.
Figure 4. Switching Application: Four Ultramappers Terminating STS-12/STM-4; One Ultramapper
Terminating STS-3/STM-1
MSP 1 + 1
OPTICS
1417
PM
MPR
OPTICS
1417
T1/E1
OHP
FRMR
28/21
M13
PM
TLIU04C1
1081 (F)
Note: Possible application would be add-drop of 28/21 T1/E1s to/from STS-12/STM-4/STS-3/STM-1.
Figure 5. Transport Application: Ultramapper Terminating 28/21 T1/E1s Directly to LIUs in Transport Mode
10
Agere Systems Inc.
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
2 The SONET/SDH Ultramapper (continued)
MSP 1 + 1
UMPR #1, #2, #3, #4
OPTICS
1417
PM
MPR
PM
MPR
PM
MPR FRMR
OHP
PM
MPR FRMR
OHP
FRMR
OHP
M13
FRMR
PM
OHP
M13
PM
M13
PM
M13
PM
DS3/E3/STS1
DS3/E3 LIU
1085 (F)
Note: In this application, up to three DS3, E3, or EC1 per Ultramapper can be deMUXed to 84/63 DS1/E1, mapped to 84/63 VT/TU, and then
mapped to STS-1/AU-3, STS-3/STM-1, or STS-12/STM-4 as desired.
Figure 6. TransMUX Application: Four Ultramappers Mapping Clear Channel DS3/E3/EC-1 to VT/TU and
Terminating as STS-12/STM-4
SWITCH
BACKPLANE
STS12/STM4
UMPR #1
PM
MPR
OHP
FRMR
M13
PM
3 x STS1
PM
1 x STS3
MPR
OHP
FRMR
M13
PM
UMPR #2
1083 (F)
Note: In this application, up to three DS3 or E3 embedded in STS-1/AU-3 per Ultramapper can be deMUXed to 84/63 DS1/E1, mapped to 84/63
VT/TU, and then mapped to STS-1/AU-3. Simultaneously, up to 84/63 VT/TU embedded in STS-1/AU-3 per Ultramapper can be
demapped to 84/63 DS1/E1, then multiplexed to
3 DS3 or E3 embedded in STS-1/AU-3.
Figure 7. Portless TransMUX Application: Two Ultramappers Required for STS-12/STM-4 to Map 6 x STS-1
(DS3 MApped) to/from 6 x STS-1 (VT Mapped)
Agere Systems Inc.
11
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
2 The SONET/SDH Ultramapper (continued)
DS3/E3 LIUs
6
6
MPR
MPR
PM
FRMR
FRMR
OHP
OHP
OPTICS
1417
M13
M13
PM
PM
1086 (F)
Note: In this application, each Ultramapper maps six clear channels DS3s or E3s (any combination) through the SPE/AU-3 mapper to STS-1s
or TUG-3s. Utilizing the mate interface, one Ultramapper provides an STS-12/STM-4 termination.
Figure 8. DS3/E3 Mapped to SONET/SDH-2 Ultramappers Mapping 12 DS3/E3 into STS-1s or TUGs and
Ultimately to STS-12/STM-4
SYSTEM BUS
INTERFACE
DS3/E3 LIUs
PM
MPR
OHP
FRMR
DS1/E1 3x
(x28/x21)
(NSMI MODE)
M13
PM
1082 (F)
Note: Using the DS1/E1 framers, DS3/E3 framers, and the M13 MUX, the Ultramapper can be used to MUX up to 84/63 T1/E1s to three DS3/
E3s.
Figure 9. M13 MUX and Framing Application: 84/63 DS1/E1 (NSMI System Bus) MUXed to Three DS3/E3
12
Agere Systems Inc.
Advance Data Sheet, Rev. 2
July 2001
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
2 The SONET/SDH Ultramapper (continued)
2.3 High-Speed Line Interfaces and Clock and Data Recovery
In the receive direction, the Ultramapper accepts either a differential serial data signal at 155.52 Mbits/s (STS-3/
STM-1 mode) or a serial STS-1 clock and data at 51.84 MHz (STS-1 mode). For the STS-1 case, the input is
retimed with the input clock. A clock and data recovery circuit is used for the 155 Mbits/s case with the high-speed
transmit input clock as the clock reference. In the event that external clock and data recovery is provided, this feature can be bypassed. The clock and date circuit can be used for recovering clock at 51 MHz, but a 155 MHz clock
reference must still be supplied.
On the transmit side, in STS-3/STM-1 mode, the Ultramapper receives a differential 155.52 MHz transmit clock and
transmit frame synchronizing signal and outputs a differential serial data signal. In STS-1 mode, it receives a
51.84 MHz transmit clock and frame synchronizing signal and outputs serial data.
Loss of input clock or recovered clock is detected, as well as a loss-of-signal condition, by monitoring an external
signal pin or an internal an all-zeros/ones pattern.
Built-in loopbacks at both high-speed interfaces provide maximum flexibility for maintenance testing.
2.3.1 Receive Direction
Terminating the transport overhead (TOH), the Ultramapper performs frame alignment (STS-3/STM-1 or STS-1),
B1 BIP-8 check, J0 monitoring, descrambling, F1 monitoring, B2 BIP-8 check, APS and K2 monitoring, AIS-L and
RDI-L detection, M1 REI-L detection, S1 synchronization status monitoring, and transport overhead access channel (RTOAC) drop.
The states of the framer as well as all state changes are reported, and, if not masked, cause an interrupt.
The B1 and B2 parity check supports bit and block mode. The counters count up to one second worth of BIP
errors. They stay at their maximum value in case of overflow or rollover and should be read (and cleared) at least
once per second.
The J0 monitor supports nonframed, SONET-framed, and SDH-framed 16-byte sequences, as well as single
J0 byte monitoring modes.
APS monitoring is performed on K1[7:0] and K2[7:3]. The value is stored and changes are reported. Bits [2:0] of
the K2 byte are monitored independently.
Line AIS (AIS-L/MS-AIS) and remote defect indication (RDI-L/MS-RDI) are monitored separately and changes are
reported. This information is also sent to the protection device for ADM applications.
The M1 monitor operates either in bit or block mode and allows accessing of the remote error indication (REI-L/
MS-REI) errored bit count.
The S1 byte can be monitored in two modes: as an entire 8-bit word or as one 4-bit nibble (bits 7:4).
Continuous N times detection counters are implemented for these monitoring functions. All automatic receive monitoring functions can be configured to provide an interrupt to the control system, or the device can be operated in a
polled mode.
The receive transport overhead access channel (RTOAC) provides access to all of the line section overhead bytes.
Even or odd parity is calculated over all bytes. It has a data rate of 5.184 Mbits/s and consists of a clock, data, and
an 8 kHz synchronizing pulse. Alternatively, only the data communication channels D1:D3 or D4:D12 may transmit
a serial 192 kbits/s or a 576 kbits/s data stream.
Agere Systems Inc.
13
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
2 The SONET/SDH Ultramapper (continued)
2.3.2 Transmit Direction
In the transmit direction, the Ultramapper performs transmit transport overhead access channel (TTOAC) insertion,
synchronizing status byte (S1) insertion, M0/M1—REI-L insertion, K1 and K2 insertion, AIS-L insertion, B2 calculation and insertion, F1 byte insertion, B1 generation and error insertion, scrambler, J0 insert control, and A2 error
insertion. All insert control functions that are inhibited will optionally insert either all zeros or all ones. The TTOAC
allows the users to insert the following overhead bytes: E1, F1, D1:D3, D4:D12, S1, and E2. Even or odd parity is
checked over all bytes. Bytes which are not enabled for insertion are set to an all-ones or all-zeros stuff value. The
Ultramapper sources a clock and an 8 kHz synchronizing pulse and receives the data at a data rate of
5.184 Mbits/s. Alternatively, only the data communication channels D1—D3 or D4—D12 may receive a serial
192 kbits/s or a 576 kbits/s data stream.
The insertion (overwrite of TTOAC) of programmed S1, F1, J0, Z0-2, and Z0-3 bytes can be enabled.
Automatic insertion of M0/M1 may be inhibited. A protection switch selects the REI-L value for insertion to be taken
from the protection board rather than from the receive side.
The entire APS value or K2[2:0] can be inserted via microprocessor control. Automatic RDI insertion is supported
with individual inhibit for each contributor. A protection switch selects the RDI-L value for insertion to be taken from
the protection board rather than from the receive side.
B1 and B2 BIP-8 values are calculated and inserted. Both values can be inverted.
2.4 Multiplex Section Protection (MSP 1 + 1)
The TMUX block supports a payload 1 + 1 protection switch. In the receive direction, this occurs prior to pointer
interpretation. If the protection switch is activated, then the data is selected from the receive protection interface
rather than from the high-speed input path.
In the transmit direction, the signal is broadcast to the high-speed output path and the protection interface.
The interface consists of a 155.52 MHz or 51.84 MHz clock, data, and synchronizing pulse in each direction.
2.4.1 Pointer Interpreter
This state machine implements the pointer interpretation algorithm described in ETS 300 417-1-1: January 1996—
Annex B.
The pointer interpreter evaluates the current pointer state for the normal state, path AIS state, or LOP (loss of
pointer) conditions, as well as pointer increments and decrements. The current pointer state and any changes in
pointer condition are reported to the control system. The number of consecutive frames for invalid pointer and
invalid concatenation indication is fixed at nine.
2.4.2 Path Termination Function
The path termination function is performed on either all three STS-1s or on the VC-4 POH only.
It includes on the receive side: J1 monitoring, B3 BIP-8 checking, C2 signal label monitoring, REI-P and RDI-P
detection, H4 multiframe monitoring; F2, F3, and K3 automatic protection switch monitoring, N1 tandem connection
monitoring, signal degrade BER and signal fail BER detection; path overhead access channel (RPOAC) drop,
AIS-P/HO-AIS insertion, and automatic AIS generation (with individual inhibit).
The J1 monitor provides five modes of operation on a programmable length (1 byte—64 bytes) of the trace identifier: cyclic checking against the last received sequence, comparing against a programmed sequence, SONET
framing mode, SDH framing mode, and consecutive consistent occurrences of a new pattern.
14
Agere Systems Inc.
Advance Data Sheet, Rev. 2
July 2001
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
2 The SONET/SDH Ultramapper (continued)
B3 is monitored either in bit or block mode. Provisionable N-times detection counters are implemented for C2, F2,
F3, N1, and K3 bytes. The K3 APS byte and N1 TCM byte can be monitored as an entire 8-bit word or two 4-bit nibbles.
The receive path overhead access channel (RPOAC) provides access to all the path overhead bytes. Even or odd
parity is calculated over all bytes. It has a data rate of 8 bytes per 8 kHz frame and consists of clock, data, and an
8 kHz synchronizing pulse.
In the transmit direction, J1 path trace insertion, B3 calculation and insertion, C2 signal label insertion, REI-P and
RDI-P insertion; F2 insertion, H4 multiframe insertion, F3 path user byte insertion, K3 insertion, N1 byte insertion,
and AIS-P insertion via POAC or software control is supported.
The transmit path overhead access channel (TPOAC) allows the insertion of all overhead bytes besides B3 which
is automatically calculated. Even or odd parity is checked over all bytes. Bytes which are not enabled for insertion
are set to an all-ones or all-zeros stuff value. The Ultramapper sources a clock and an 8 kHz synchronizing pulse
and receives the data at a rate of 8 bytes per 8 kHz frame.
2.5 STS-3/STM-1 Overhead Termination and Pointer Processing
The information on overhead termination and pointer processing is not available at this time.
2.6 STS-3/STM-1 MUX-DeMUX
The STS-3/STM-1 (AU-4) multiplexer provides three modes of operation: STS-3, AU-4, and STS-1.
In STS-3 mode, the block multiplexes and demultiplexes up to three STS-1 signals to/from a SONET STS-3 signal.
In AU-4 mode, it provides the functionality to MUX/deMUX up to three AU-3 signals to/from a STM-1 (AU-4) signal.
In STS-1 mode, it provides the functions to generate and terminate a single STS-1 signal.
The STS-3/STM-1 MUX function takes the bytes in the order they are present on the telecom bus and multiplexes
them into the high-speed signal. Grooming of the VTs/VCs is performed in the SPE mapper of each of the three
devices.
2.7 STS-3 Serial Interconnect
The information on the STS-3 serial interconnect is not available at this time.
2.8 STS-12/STM-4 Pointer Processor
The information on the STS-12/STM-4 pointer processor is not available at this time.
2.9 STS-3/STM-1 Interface to Mate Devices
The Ultramapper can communicate with up to three mate devices via STS-3/STM-1 interfaces. One Ultramapper is
provisioned as a master and the other three are provisioned as slaves. This provides for full external termination of
the STS-12/STM-4 payload.
Agere Systems Inc.
15
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
2 The SONET/SDH Ultramapper (continued)
2.10 SPE/AU-3 Mapper (DS3 Mapper)
The SPE mapper block is a highly configurable mapper. It operates either as an AU-3/STS-1 mapper or as a TUG3 mapper. In both modes, it maps/demaps data from/to either the VT mapper, the M13 MUX/deMUX, the DS3 clear
channel, or the DS3 loopback channel. The SPE mapper supports numerous automatic monitoring functions and
provides interrupts to the control system, or it can be operated in a polled mode. In TU mapping mode, the SPE
mapper provides flexibility down to TUG-2 level for choosing which TUG-2s (out of 7) are mapped/dropped
into/from which TUG-3s (between 1 and 3) for generating STM-1 signals. This allows grooming of the VTs/TUs on
the STM-1 level (over all three devices). In a full STM-1 application, with two other devices sitting on the telecom
bus, care has to be taken for the provisioning of the time slots when each block drives the telecom bus.
In DS3 mapping mode, the SPE mapper block accepts/delivers structured DS3 data from/to the M13 block or a
clear DS3 signal at 44.736 Mbits/s rate and maps/demaps it asynchronously into/from the STS-1 SPE or a TU-3.
The DS3 mapper generates a fixed pointer value of 522. On the receive side, pointer interpretation is performed
detecting LOP, AIS, NDF, NORM, INC, and DEC. A DS3 loopback mode allows demapping and remapping of a
DS3 signal. It is particularly useful in cases where a DS3 signal mapped as an AU-3/STS-1 signal is needed to be
remapped as a TU-3 signal or vice versa. B3ZS encoding/decoding is included.
The same path overhead monitoring functions (as described above) are implemented in this block.
This block also connects to the path overhead access channel (POAC) to insert/drop the path overhead bytes J1,
C2, F2, H4, F3, K3, and N1 into the STS-1 SPE or VC-3.
Supports unidirectional path switch ring (UPSR) applications as well as N1 tandem connection function.
Complies with GR-253-CORE, T1.105, ITU-T G.707, ITU-T G.831, G.783, and ETS 300 417-1-1.
2.11 VT/TU Mapper
The VT/TU mapper maps any valid combination of DS1 and E1 signals into a stream at a rate of 51.84 Mbits/s
(STS-1 or AU-3). The mapping methods (VT1.5, VT2, and VT group in ANSI nomenclature; TU-11, TU-12, and
TUG-2 in ITU nomenclature) are analogous. The VT/VC mapper supports the following mappings:
■
84 asynchronous, byte-, or bit-synchronous DS1 signals are mapped into seven VT groups or TUG-2s.
■
84 asynchronous, byte-, or bit-synchronous J1 signals are mapped into seven VT groups or TUG-2s.
■
63 asynchronous, byte-, or bit-synchronous E1 signals are mapped into seven VT groups or TUG-2s.
■
Maps T1 into VT1.5/TU-11/TU-12, J1 into VT1.5/TU-11/TU-12, and E1 into VT2/TU-12.
ADM and unidirectional path switch ring (UPSR) applications are supported via tributary loopback, tributary pointer
processing, and low-order path overhead access channel.
Supports automatic generation or microprocessor overwrite 1-bit RDI, enhanced RDI, 1-bit RFI, automatic downstream AIS generation, and five J2 trace identifier modes.
Complies with GR-253-CORE, G.707, T1.105, G.704, G.783, JT-G707, GR-499, and ETS 300 417-1-1.
2.11.1 Receive Direction
In the receive direction, the VT mapper terminates the data stream it receives from the SPE mapper. It demultiplexes the AU-3/TUG-3 into the VTs/TUs and checks the H4 multiframe alignment. Pointer interpreters for up to
84 VTs/TUs detect LOP, AIS, NDF, NORM, INC, and DEC on each channel.
16
Agere Systems Inc.
Advance Data Sheet, Rev. 2
July 2001
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
2 The SONET/SDH Ultramapper (continued)
The low-order path termination includes V5 byte termination, J2 path trace, Z6/N2 tandem connection, Z7/K4
enhanced RDI and low-order APS monitor, and the payload termination for asynchronous, byte- or bit-synchronous
signals. The V5 byte termination performs BIP-2 check (bit- or block-mode), REI count, RFI and RDI detection, signal label monitor, and automatic AIS insertion (which can be inhibited). The J2 monitor supports four different
modes as follows:
■
Cyclic check
■
SONET framing mode
■
SDH framing mode
■
Single byte check
In byte-synchronous modes, the receive demapper generates a frame synchronization signal to indicate the DS1
frame bit or the MSB of the E1 time-slot 0. Additionally, it provides the framer access to the received signaling bits.
Output of the VT mapper is a DS1/J1/E1 signal with a gapped clock. It can be overwritten with AIS automatically or
upon microprocessor request.
2.11.2 Transmit Direction
In the transmit direction, the VT mapper gets a clock, data, and frame synchronization signal from the cross connect. The input is retimed and checked for a digital loss of clock (LOC), an AIS condition, and low zeros density. In
byte-synchronous mode, the input signal is additionally checked for loss of frame synchronization (LOFS).
A transmit elastic store synchronizes the incoming DS1/J1/E1 signals to the local STS-1 clock. In asynchronous
and bit-synchronous mode, it works as a bit-oriented (64-bit) FIFO, and in byte-synchronous mode as a byte-wide
(8-byte) buffer using a V5 byte marker bit (8-bit). Overflow or underflow conditions are monitored and reported.
In asynchronous and bit-synchronous mode, a fixed VT pointer of 78 (VT1.5/TU-11) and 105 (VT2/TU-12) is generated and the payload is mapped into the container using positive/null/negative bit stuffing mechanism (C- and
S-bits). In bit-synchronous mode, the bit stuffing mechanism is disabled. In byte-synchronous mode, a dynamic VT
pointer value is generated using the V5 marker implementing NORM, NDF, INC, and DEC pointers.
The VT POH generation comprises V5 byte with BIP2-generation, AIS-, signal label-, UNEQ-insertion, automatic
REI-, RFI-, RDI-, and enhanced RDI-generation (Bellcore*, ITU-T), J2 path trace insertion via microprocessor,
Z6/N2 byte insertion, and Z7/K4 byte insertion via microprocessor or low-order path overhead (LOPOH) access
channel.
The data stream is synchronized to the received 2 kHz synchronization pulse and multiplexed to form the
STS-1/AU-3 signal, which is then output to the SPE mapper.
When operating in byte-synchronous mode, the phase and signaling bits from the framer are stored and inserted
into the mapped frame.
2.12 M13/M23 Multiplexer
The M13 is a highly-configurable multiplexer/demultiplexer. It can operate as an M13 in either the C-bit parity or
M23 mode, a mixed M13/M23, or an M23. In the C-bit parity mode, the M13 provides a far-end alarm and control
(FEAC) code generator and receiver, an HDLC transmitter and receiver, and automatic far-end block error (FEBE)
generation.
* Bellcore is now Telecordia TEchnologies, Inc.
Agere Systems Inc.
17
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
2 The SONET/SDH Ultramapper (continued)
Each internal M12 MUX/deMUX and the M23 MUX/deMUX may be configured to operate as independent
MUXs/deMUXs. 84 DS1 inputs in groups of four or 63 E1 input signals in groups of three can feed into individual
M12 MUXs, while the M23 MUX can take DS2 signals from outputs of M12 MUXs, or direct DS2 inputs, or loopback
deMUXed DS2s.
The M13 supports numerous automatic monitoring functions. It can provide an interrupt to the control system or it
can be operated in a polled mode.
Complies with T1.102, T1.107, T1.231, T1.403, T1.404, GR-499, G.747, and G.775.
2.12.1 Receive Direction
The receive DS3 is monitored for loss of clock and checked for loss of signal (LOS) according to T1.231. The B3ZS
decoder accepts either unipolar clock and data or unipolar clock, positive and negative data. It also checks for bipolar coding violations. The transmit DS3 can be looped back into the receive side after B3ZS decoding. The M23
demultiplexer checks for valid DS3 framing by finding the frame alignment pattern (F bits), and then locating the
multiframe alignment signal (M bits). During each M frame, the data stream is checked for the presence of the AIS
(1010) or idle (1100) pattern.
C bits 13, 14, and 15 can be used as a 28.2 kbits/s data link and are available directly at device output via an internal HDLC receiver. The receiver is composed of a 128-byte FIFO, a CRC-16 frame check sequence (FCS) error
detector, and control circuits.
Within the M23 demultiplexer, there are four performance monitoring counters for F- or M-bit, P-bit, E-bit parity, and
FEBE errors. Each M12 demultiplexer contains two performance monitoring counters.
2.12.2 Transmit Direction
The incoming DS1/E1 clocks are first checked for activity or loss of clock (LOC). The data signals are retimed and
checked for AIS and activity. DS1/E1 loopback selectors allow DS1 or E1 received within the DS2 or DS3 inputs
from the deMUX path to be looped back. This loopback can be performed automatically or the user can force a
DS1 or E1 loopback.
The four DS1 or three E1 signals for each M12 MUX are fed into single-bit, 16-word-deep FIFOs to synchronize the
signals to the DS2 frame generation clock. The fill level of each FIFO determines the need for bit stuffing its
DS1/E1 input. The M13 can handle DS1/E1 signals with nominal frequency offsets of ±130 ppm and up to five unit
intervals peak jitter. The DS2/DS3 transmit clock is used to derive the clock source for DS2 frame generation.
The M23 multiplexer generates a transmit DS3 frame, and fills the information bits in the frame with data from the
seven DS2 select blocks. The M23 MUX can be provisioned to operate in either the M23 mode or the C-bit parity
mode. It contains seven DS2 FIFOs each with a depth of 8. The fill level of each FIFO determines the need for bit
stuffing its DS2 input.
The transmit DS3 output can either be in the form of unipolar clock and data or unipolar clock, positive and negative
data. The DS3 data is B3ZS encoded and can be looped back from the receive DS3 input.
2.13 E13/E23 Multiplexer
The information on the E13/E23 multiplexer is not available at this time.
18
Agere Systems Inc.
Advance Data Sheet, Rev. 2
July 2001
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
2 The SONET/SDH Ultramapper (continued)
2.14 Cross Connect Block
The cross connect (XC) is a highly configurable nonblocking crosspoint switch for DS1/E1/DS2 signals, configuration of DS3 signal paths, and configuration of the path overhead access I/O. The cross connect plays a major role
in configuring the interconnection of major function blocks to satisfy an application’s implementation.
The cross connect provides the flexibly to tie DS1/E1/DS2 channels from the framer or external pins to the M13
mapper or to the VT mapper. It is also capable of multicast or broadcast operation (one port to many), handling
injected test patterns, idles, or alarm conditions to any channel, and can provide system loopback testing support.
Jitter attenuation may also be inserted in-line on any DS1/E1 channel.
The cross connect can interconnect up to 84 individual DS1/E1 channels between the framer, M13 multiplexer, VT
mapper, jitter attenuator, or external I/O. The external I/O pins support an application dependent mix of up to
29 T1/E1 interfaces (one dedicated protection channel), seven DS2 interfaces, or one of four available framer system interfaces.
The cross connect supports an independent signal path for remote alarm indication (RAI), alarm indication signal
(AIS), and byte-synchronous frame synchronizing signals on channels between the VT mapper or M13 and the
framer. Receive pointer adjustment information is routed to the jitter attenuator block for each channel originating in
the VT mapper.
The cross connect has independent DS2 interfaces for the M12 and M23 blocks of the M13 MUX. Full split access
to the external I/O device pins provides the capability to add, drop, or rearrange the DS2 signals within the M13.
For DS3 signals, the cross connect supports configuration of interconnects between the M13 and the SPE, or
external I/O interconnection to the M13 or SPE, or insertion/monitoring of DS3 test patterns from the test-pattern
generator block.
The test-pattern generator block (TPG) provides test signals and monitors inputs (TPM) for signals to and from the
cross connect. The TPG can generate a set of test signals or idles at DS1, E1, DS2, or DS3 rates. There is only
one test pattern generator and monitor per signal rate.
Device pins for the path overhead access channel may be configured to connect to the SPE mapper or TMUX
blocks.
2.15 DS1 Digital Jitter Attenuator
The digital jitter attenuator (DJA) contains 28 copies of the digital jitter attenuator block. These digital jitter attenuator blocks can operate in two different modes, as a DS1 or as an E1 jitter attenuator.
In both modes, the digital jitter attenuator can be provisioned to always operate as a second-order PLL, or it can
switch to a act as a first-order PLL during VT pointer adjustments to help meet MTIE requirements. The period of
time in the first-order mode is provisionable. The PLL bandwidth is provisionable between 0.1 Hz and 0.5 Hz, and
the damping factor for these bandwidths varies between 2 and 0.5 to accommodate a number of different system
constraints.
The block will also insert the proper AIS signal if the primary block AIS control input is active.
2.16 DS3 Digital Jitter Attenuator
The information on the DS3 digital jitter attenuator is not available at this time.
Agere Systems Inc.
19
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
2 The SONET/SDH Ultramapper (continued)
2.17 Test Pattern Generator
The test pattern generator and monitor (TPG and TPM) is a set of configurable test pattern generators and monitors for local self-test, maintenance, and troubleshooting operations.
The TPG feeds one or more T1/E1/DS2 test signals (via data, clock, and FS or AIS signal paths) to the crosspoint
switch which can redistribute or broadcast these signals to any valid channel in the framer, external I/O, M13 mapper, or VT mapper blocks. The TPG can also generate DS3 test signals.
Any channel arriving at the cross connect may be routed to the test monitor. The test monitors can automatically
detect/count bit errors in a pseudorandom test sequence, loss of frame, or loss of synchronization. The TPM can
provide an interrupt to the control system or it can be operated in a polled mode.
Simultaneous testing of DS1, E1, DS2, and DS3 signals is supported (one channel each).
Supported test patterns are: pseudorandom bit sequence (PRBS15, PRBS20), alternating zeros/ones, and an allones pattern.
The test pattern can be transmitted either unframed or as the payload of a framed signal, as defined in ITU-T Recommendation O.150.
Single bit-errors may be injected into any test pattern, under register control.
2.18 28-Channel Framer
The block diagrams of the 84 T1/63E1-channel framer in the switching application in the CHI, parallel system bus,
and CHI with byte-synchronous VT mapping, are shown in Figure 10, Figure 11, and Figure 12 (only the major
functional blocks are shown). The block diagrams of the 84 T1/63E1-channel framers in the transport application
are shown in Figure 13 and Figure 14 (only the major functional blocks are shown).
TFS1, TCLK1, TDATA28
SIGNALING
PROCESSOR
(EXTRACTION)
RECEIVE
HDLC
RECEIVE
FACILITY DATA
LINK
TRANSMIT
SYSTEM
INTERFACE
RECEIVE
FRAME
ALIGNER
ULTRAMAPPER
VT MAPPER
INTERFACE
RFS1, RCLK1, RDATA28
DS0 INTERFACE
PERFORMANCE
MONITOR
ESF PRM PATH
ULTRAMAPPER
M12 MULTIPLEXER
INTERFACE
TRANSMIT
HDLC
RECEIVE
SYSTEM
INTERFACE
MAPPER
TO
FRAMER
DS1
CROSS
CONNECT
TRANSMIT
FRAME
FORMATTER
SIGNAL
PROCESSOR
(INSERTION)
TRANSMIT
FACILITY DATA
LINK
ULTRAMAPPER: FRAMER
5-8926.a (F)
Figure 10. Ultramapper Switching Mode for Framer in Concentration Highway Interface (CHI) Configuration
20
Agere Systems Inc.
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
SIGNALING
PROCESSOR
(EXTRACTION)
RFS1, RCLK1, RDATA8,
RDATA_PARITYA1, RSIGNALING8,
RSIGNALING_PARITYA1
RECEIVE
HDLC
RECEIVE
FACILITY DATA
LINK
TRANSMIT
SYSTEM
INTERFACE
RECEIVE
FRAME
ALIGNER
ULTRAMAPPER
VT MAPPER
INTERFACE
PERFORMANCE
MONITOR
DS0
INTERFACE
TFS1, TCLK1, TDATA8,
TDATA_PARITYA1, TSIGNALING8,
TSIGNALING_PARITYA1
2 The SONET/SDH Ultramapper (continued)
ESF PRM PATH
ULTRAMAPPER
M12 MULTIPLEXER
INTERFACE
TRANSMIT
HDLC
RECEIVE
SYSTEM
INTERFACE
MAPPER
TO
FRAMER
DS1
CROSS
CONNECT
TRANSMIT
FRAME
FORMATTER
SIGNAL
PROCESSOR
(INSERTION)
TRANSMIT
FACILITY DATA
LINK
ULTRAMAPPER: FRAMER
5-8927.a (F)
Figure 11. Ultramapper Switching Mode for Framer in Parallel System Bus Configuration
Agere Systems Inc.
21
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
2 The SONET/SDH Ultramapper (continued)
In the byte-synchronization mode, the frame synchronization and signaling (VT SPE) information are also passed
to the mapper. In the receive direction, the mapper block provides the line data, line clock, frame synchronization
(byte-synchronization mode), and signaling information (byte-synchronization mode) to the Ultra Framer. Performance reports, in the form of HDLC packets (PRMs), are sent from the receive performance monitor block to the
transmit HDLC block.
RECEIVE SIGNALING DATA
(TO SIGNALING REGISTERS)
TFS1, TCLK1, TDATA28
SIGNALING
PROCESSOR
(EXTRACTION)
RECEIVE
HDLC
VT MAPPER:
BYTE-SYNCHRONOUS
ROBBED-bit SIGNALING
RECEIVE DATA
RECEIVE
FACILITY DATA
LINK
TRANSMIT
SYSTEM
INTERFACE
RECEIVE
FRAME
ALIGNER
ULTRAMAPPER
VT MAPPER
INTERFACE
RFS1, RCLK1, RDATA28
DS0
INTERFACE
PERFORMANCE
MONITOR
ESF PRM PATH
ULTRAMAPPER
M12 MULTIPLEXER
INTERFACE
TRANSMIT
HDLC
RECEIVE
SYSTEM
INTERFACE
SIGNALING STOMP
DATA
SIGNAL
PROCESSOR
(INSERTION)
ULTRAMAPPER: FRAMER
MAPPER
TO
FRAMER
DS1
CROSS
CONNECT
TRANSMIT
FRAME
FORMATTER
TRANSMIT
FACILITY DATA
LINK
TRANSMIT SIGNALING DATA
(EXTRACTED FROM SYSTEM
OF SIGNALING REGISTERS)
VT MAPPER:
BYTE-SYNCHRONOUS
ROBBED-bit SIGNALING
TRANSMIT DATA
5-8928.a (F)
Figure 12. Ultramapper Switching Mode CHI Configuration with Byte-Synchronous VT Mapping Enabled
22
Agere Systems Inc.
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
2 The SONET/SDH Ultramapper (continued)
VT MAPPER:
BYTE-SYNCHRONOUS
ROBBED-bit SIGNALING
RECEIVE DATA
RECEIVE
HDLC
LINE
ENCODER
RCLK28, RPD28, RND28
SIGNALING
PROCESSOR
(TRANSMIT)
RECEIVE
FACILITY DATA
LINK
TRANSMIT
FRAME
FORMATTER
(LINE
INTERFACE)
RECEIVE
FRAME
ALIGNER
ULTRAMAPPER
VT MAPPER
INTERFACE
PERFORMANCE
MONITOR
DS1
INTERFACE
MAPPER
TO
FRAMER
DS1
CROSS
CONNECT
LINE
DECODER
TCLK28, TPD28, TND28
PERFORMANCE
MONITOR
RECEIVE
FRAME
ALIGNER
(LINE
INTERFACE)
ULTRAMAPPER
M12 MULTIPLEXER
INTERFACE
SIGNALING STOMP
DATA
SIGNALING
PROCESSOR
(RECEIVE)
TRANSMIT
FRAME
FORMATTER
TRANSMIT
FACILITY DATA
LINK
VT MAPPER:
BYTE-SYNCHRONOUS
ROBBED-bit SIGNALING
TRANSMIT DATA
ULTRAMAPPER: PERFORMANCE MONITORING FRAMER
5-8929.a (F)
Figure 13. Ultramapper Byte-Synchronous Transport Mode: Passive Performance Monitoring
Agere Systems Inc.
23
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
2 The SONET/SDH Ultramapper (continued)
VT MAPPER:
BYTE-SYNCHRONOUS
ROBBED-bit SIGNALING
RECEIVE DATA
RECEIVE
HDLC
LINE
RCLK28, RPD28, RND28
SIGNALING
PROCESSOR
(TRANSMIT)
RECEIVE
FACILITY DATA
LINK
TRANSMIT
FRAME
FORMATTER
(LINE
INTERFACE)
RECEIVE
FRAME
ALIGNER
DS1
INTERFACE
TRANSMIT
HDLC
MAPPER
TO
FRAMER
DS1
CROSS
CONNECT
INTRUSIVE
PERFORMANCE
MONITOR
LINE
PERFORMANCE
MONITOR
TCLK28, TPD28, TND28
ULTRAMAPPER
VT MAPPER
INTERFACE
PERFORMANCE
MONITOR
RECEIVE
FRAME
ALIGNER
(LINE
INTERFACE)
TRANSMIT
HDLC
SIGNALING STOMP
DATA
SIGNALING
PROCESSOR
(RECEIVE)
ULTRAMAPPER
M12 MULTIPLEXER
INTERFACE
TRANSMIT
FRAME
FORMATTER
TRANSMIT
FACILITY DATA
LINK
VT MAPPER:
BYTE-SYNCHRONOUS
ROBBED-bit SIGNALING
TRANSMIT DATA
ULTRAMAPPER: PERFORMANCE MONITORING FRAMER
5-8930.a (F)
Figure 14. Ultramapper Byte-Synchronous Transport Mode: Intrusive Performance Monitoring
24
Agere Systems Inc.
Advance Data Sheet, Rev. 2
July 2001
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
2 The SONET/SDH Ultramapper (continued)
2.19 Line Decoder/Encoder
■
The line decoder/encoder supports either single-rail or dual-rail transmission. In dual-rail mode, the line codes
supported are as follows.
■
Alternate mark inversion (AMI).
■
DS1 binary 8 zero code suppression (B8ZS).
■
ITU-CEPT high-density bipolar of order 3 (HDB3).
In the single-rail mode, a line interface unit (LIU) decodes/encodes the data.
In the dual-rail mode, loss of signal is monitored.
In the case of coded mark inversion (CMI) coding (Japanese TTC standard JJ-20.11), the LIU decodes the data,
indicating both the CMI coding rule violations (CRVs) and line coding violations as bipolar violations. (In the CMI
mode, the framer is in the single-rail mode.)
2.20 Receive Frame Aligner/Transmit Frame Formatter
The receive frame aligner and transmit frame formatter support the following frame formats:
■
D4 Ultraframe.
■
SF D4 Ultraframe: FT framing only.
■
J-D4 Ultraframe with Japanese remote alarm.
■
DDS.
■
SLC-96.
■
ESF.
■
J-ESF (J1 standard with different CRC-6 algorithm).
■
Nonalign DS1 (193 bits—clear channel).
■
CEPT basic frame (ITU G.706).
■
CEPT CRC-4 multiframe with 100 ms timer (ITU G.706).
■
CEPT CRC-4 multiframe with 400 ms timer (automatic CRC-4/non-CRC-4 equipment interworking) (ITU G.706
Annex B).
■
Nonalign E1 (256 bits—clear channel).
■
2.048 coded mark inversion (CMI) coded interface (TTC standards JJ-20.11).
2.20.1 Receive Performance Monitor
The receive framer monitors the following alarms: loss of receive clock, loss of signal, loss of frame, alarm indication signal (AIS), remote frame alarms, and remote multiframe alarms. These alarms are detected as defined by
the appropriate ANSI, AT&T, ITU, and ETSI standards.
Performance monitoring as specified by AT&T, ANSI, and ITU is provided through counters monitoring bipolar violation, frame bit errors, CRC errors, errored events, errored seconds, bursty errored seconds, and severely errored
seconds.
In-band loopback activation and deactivation codes can be transmitted to the line via the payload or the facility data
link. In-band loopback activation and deactivation codes in the payload or the facility data link are detected.
Agere Systems Inc.
25
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
2 The SONET/SDH Ultramapper (continued)
2.21 Signaling Processor
The signaling processor supports the following modes:
■
Ultraframe (D4, SLC-96): 2-state, 4-state, and 16-state.
■
VT 1.5 SPE: 2-state, 4-state, and 16-state.
■
Extended Ultraframe: 2-state, 4-state, and 16-state.
■
CEPT: common channel signaling (CCS) (TS-16).
■
Transparent (pass through) signaling.
■
J-ESF handling groups.
Signaling features supported per channel are as follows:
■
Signaling debounce.
■
Signaling freeze.
■
Signaling interrupt upon change of state.
■
Associated signaling mode (ASM).
■
Signaling inhibit.
■
Signaling stomp.
In the DS1 robbed-bit signaling modes and voice and data channels are programmable. The entire payload can be
forced into a data-only (no signaling channels) mode, i.e., transparent mode by programming one control bit.
Signaling access can be through the on-chip signaling registers or the system interface. Data and its associated
signaling information can be accessed through the system in either DS1 or CEPT-E1 modes.
2.22 Facility Data Link (FDL) Processor
The bit-oriented ESF data-link messages defined in ANSI T1.403 are monitored by the receive facility data link unit.
The transmit facility data link unit overrides the FDL-FIFO for the transmission of the bit-oriented ESF data-link
messages defined in ANSI T1.403-1995.
The FDL processor extracts and stores data link bits from three different frame types as follows:
■
D bits and delineator bits from the SLC-96 multi-Ultraframe.
■
Data link bits from DDS frames (bit 6 of time-slot 24).
■
Two multiframes of Sa[4:8] bits from time slot 0 in CEPT basic and CRC-4 multiframes.
The respective bits will always be extracted from frame-aligned frames and stored in a stack. The processor will
have control of being alerted to stack updates through the interrupt mask registers.
The transmit FDL block performs the transmission of D bits into SLC-96 Ultraframes, Sa-bits in CEPT frames, and
D bits in DDS frames.
■
In SLC-96 frames, the D and delineator-bits are always sourced from this block when the block is enabled for
insertion.
■
In DDS frames, the data link bits are always sourced from this block when this block is enabled for insertion. This
block also provides the capability to transmit BOMs in the data link channel of ESF links.
■
In CEPT frames, the Sa-bits are sourced from either the Sa stack within this block or from the system interface.
The data link block only responds with valid data when selected by the Sa source control bits.
26
Agere Systems Inc.
Advance Data Sheet, Rev. 2
July 2001
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
2 The SONET/SDH Ultramapper (continued)
2.23 HDLC Unit
The HDLC processor formats the HDLC packets for insertion into the programmable channels. A channel can be
any number of bits (1 to 8) from a time slot.
The maximum number of channels is 64. The maximum channel bit rate is 64 kbits/s. The minimum channel bit rate
is 4 kbits/s. Each channel is allocated 128 bytes of storage.
HDLC processing of data on the facility data link (PRMs, Sa bits, or otherwise) is implemented by assigning the
FDL bit position to a logic HDLC channel.
2.24 System Interface and Transport Modes
The system interface block provides a programmable interface. It can be configured to work in the following four different modes:
■
Concentration highway interface (serial time division multiplex interface):
— Global frame synchronization.
— Global clock: 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz.
— 84 transmit and receive data ports; data rates 2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s, or 16.384 Mbits/s.
■
Parallel system bus (parallel time-division multiplex interface/transmit and receive):
— Global frame synchronization.
— Global clock: 19 MHz.
— Data rate: 19 MHz.
— 8 bits of data + associated parity bit.
— 4 bits of signaling + 2 bits of signaling control + 1 bit of parity.
■
Time-division multiplex data rate serial interface:
— 28 receive frame synchronization (per port).
— 28 receive clock: 1.544 Mbits/s or 2.048 Mbits/s (per port).
— 28 receive ports.
— One transmit frame synchronization.
— One transmit clock: 1.544 Mbits/s or 2.048 Mbits/s.
— 28 transmit ports.
■
Network serial multiplexed bus:
— 6- or 8-pin serial interface.
— Transmit and receive clock and data at 51.84 MHz.
— Accommodates one DS3 of throughput.
— Provides a minimal pin count interface for data and inverse multiplexing for ATM (IMA) applications without slip
buffers.
— Three modes of operation:
Framer—NSMI payload assembled/disassembled into DS1/E1s.
M13—proprietary transport format with DS3 framing.
SPE—proprietary transport format mapped into an STS-1/AU-3.
Agere Systems Inc.
27
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information
Figure 15. 700 Pin PBGA
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
28
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
3.1 Introduction
Table 1 lists pin descriptions including the pin, symbol (or signal name), type, I/O, and description. Table 2, starting
on page 44, lists just the pin and symbol, sorted by pin number order. Table 3, starting on page 52, lists pins and
symbol names, sorted by symbol name order.
Table 1. Pin Descriptions
Pin
Symbol
AM5
AM6
AN4
AN5
RHSDP
RHSDN
RHSCP
RHSCN
AP6
AP7
AP4
AP5
AL15
THSCP
THSCN
THSCOP
THSCON
THSSYNC
AN7
AN8
THSDP
THSDN
AM8
AM9
AN10
AN11
AP10
AP11
AP8
AP9
RPSDP
RPSDN
RPSCP
RPSCN
TPSDP
TPSDN
TPSCP
TPSCN
Type
I/O*
Description
TMUX Block
High-Speed Receive I/O (4)
622/155 Mbits/s STS-12/STS-3 Input Data. Input for optional
LVDS
I
clock and data recovery (CDR). LVDS input.
LVDS
I
155 MHz Clock for STS-3 Input Data. LVDS input.
High-Speed Transmit I/O (7)
Transmit 622/155 MHz Clock and Reference Clock for
LVDS
I
CDR (optional). LVDS input.
LVDS
O
Output 622/155 MHz Clock. LVDS output.
—
I/O
LVDS
O
Transmit 8K Frame Sync for STS-12/STM-4, or STS-3/
STM-1Mode. If the register MPU_MASTER_SLAVE= 1,
THSSYNC is an output, otherwise, THSSYNC is an input.
Transmit Output Data for STS-12, STM-4, or STS-3 Mode.
LVDS output.
LVDS
Protection Switch I/O (8)
Receive Side 622/155 Mbits/s Serial Data Input from ProI
tection Board.
LVDS
I
Receive Side 155 MHz Clock Input from Protection Board.
LVDS
O
Transmit Side 622/155 Mbits/s Serial Data Output to Protection Board.
LVDS
O
Transmit Side 622/155 MHz Clock Output to Protection
Board.
* O1 indicates external pull-up recommended (unused or system required),
I/O2 indicates external pull-down recommended (unused or system required),
ID; I/OD indicate internal pull-down,
IU indicates internal pull-up.
Agere Systems Inc.
29
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin
Symbol
AP17, AP15,
AP13
AP18, AP16,
AP14
AN17, AN15,
AN13
AN18, AN16,
AN14
AK15
AL14
RLSDATAP[3:1]
AP3
Type
I/O*
Description
TMUX Block (continued)
STS3/STM1 Mate Interconnect (14)
155 Mbit/s STS-3/STM-1 Output Data. LVDS output.
LVDS
O
RLSDATAN[3:1]
TLSDATAP[3:1]
LVDS
I
155 Mbit/s STS-3/STM-1 Input Data. Input for clock and
Data Recovery (CDR). LVDS input.
TLSDATAN[3:1]
RLSCLK
TLSCLK
—
—
RESHI
—
19.44 MHz Receive Side Byte CLK.
O
19.44 MHz Transmit Side Byte CLK.
O
LVDS Control Pins (8)
External 100 Ω Resistor Pin 1.
I
AJ8
AJ6
AK6
AK8
RESLO
REF10
REF14
CTAPRH
—
—
—
—
I
I
I
—
AJ9
CTAPTH
—
—
AK9
CTAPRP
—
—
AJ13
CTAPTL
—
—
Note: A 100 W 1% resistor is required between RESHI and
RESLO pins as a reference for the LVDS input buffer
termination.
External 100 Ω Resistor Pin 2. See note in RESHI pin.
External 1 V Reference Voltage Pin.
External 1.4 V Reference Voltage Pin.
LVDS Buffer Terminator Center Tap for RHSDP/N and
RHSCP/N. Optional, 0.1 µF capacitor connected between
CTAP pin and ground, to improve the common mode rejection of the LVDS input buffers.
LVDS Buffer Terminator Center Tap for THSCP/N and
THSSYNNP/N. Optional, 0.1 µF capacitor connected
between CTAP pin and ground, to improve the common
mode rejection of the LVDS input buffers.
LVDS Buffer Terminator Center Tap for RPSDP/N and
RPSCP/N. Optional, 0.1 µF capacitor connected between
CTAP pin and ground, to improve the common mode rejection of the LVDS input buffers.
LVDS Buffer Terminator Center Tap for TLSDATAP/N.
Optional, 0.1 µF capacitor connected between CTAP pin and
ground, to improve the common mode rejection of the LVDS
input buffers.
* O1 indicates external pull-up recommended (unused or system required),
I/O2 indicates external pull-down recommended (unused or system required),
ID; I/OD indicate internal pull-down,
IU indicates internal pull-up.
30
Agere Systems Inc.
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin
Symbol
Type
I/O*
Description
TMUX Block (continued)
TOAC Input and Output Channels (6)
AM17
RTOACCLK
—
O
Receive Side Serial Access Channel Clock Output for the
Transport Overhead Bytes.
AJ17
RTOACDATA
—
O
Receive Side Serial Access Channel Data Output for the
Transport Overhead Bytes.
AM18
RTOACSYNC
—
O
Receive Side Sync Output for TOAC Channel. Active-high
during the LSB of the last byte.
AL18
TTOACCLK
—
O
Transmit Side Serial Access Channel Clock Output for
the Transport Overhead Bytes.
AP19
TTOACDATA
—
ID
Transmit Side Serial Access Channel Data Input for the
Transport Overhead Bytes.
AK18
TTOACSYNC
—
O
Transmit Side Sync Output for TOAC Channel. Active-high
during the LSB of the last byte.
AN19
RPOACCLK
—
O
Receive Side Serial Access Channel Clock Output for the
Path Overhead Bytes. This pin can be individually 3-stated.
AJ18
RPOACDATA
—
O
Receive Side Serial Access Channel Data Output for the
Path Overhead Bytes. This pin can be individually 3-stated.
AP20
RPOACSYNC
—
O
Receive Side Sync Output for POAC Channel. Active-high
during the LSB of the last byte. This pin can be individually
3-stated.
AN20
TPOACCLK
—
O
Transmit Side Serial Access Channel Clock Output for
the Path Overhead Bytes. This pin can be individually
3-stated.
AJ19
TPOACDATA
—
ID
Transmit Side Serial Access Channel Data Input for the
Path Overhead Bytes.
AM20
TPOACSYNC
—
O
Transmit Side Sync Output for POAC Channel. Activehigh during the LSB of the last byte. This pin can be individually
3-stated.
POAC Input and Output Channels (6)
Miscellaneous Signals (2)
AN21
LOSEXT
—
IU
External Loss of Signal Input.
AJ20
RHSFSYNCN
—
O
Receive Side Frame Sync Output Indicating the Frame
Location of the High-Speed Data Input.
* O1 indicates external pull-up recommended (unused or system required),
I/O2 indicates external pull-down recommended (unused or system required),
ID; I/OD indicate internal pull-down,
IU indicates internal pull-up.
Agere Systems Inc.
31
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin
Symbol
Type
I/O*
Description
SPE Mapper Block
External PLL Control (12)
AL1, AJ2,
AH2, AF5,
AE6, AG2
PHASEDETUP[6:1]
—
O
Phase Detector Up Signal Out to External PLL Circuit if SPEMPR Outputs DS3/E3 Data Without
Going Through Internal DS3/E3DJA.
If TSTMODE is high, these pin used for TSTMUX[5:0]
(test mode output).
AJ3, AJ1,
AK1, AF6,
AG5, AG3
PHASEDETDOWN[6:1]
—
O
Phase Detector Down Signal Out to External PLL
Circuit if SPEMPR outputs DS3/E3 Data Without
Going Through Internal DS3/E3DJA.
If TSTMODE is high, PHASEDETDOWN[4-1] used for
TSTMUX[9:6] (test mode output).
Multirate Cross Connect Block
DS3/E3/STS1 Output (24)
AF2, AD5,
AE1, AD1,
AA5, AB2
DS3POSDATAOUT[6:1
]
—
O
Serial DS3/E3/STS1 Positive Data Out to External
Circuit.
AF3, AC6,
AF1, AD2,
AA6, AB1
DS3NEGDATAOUT[6:1
]
—
O
Serial DS3/E3 Negative Data Out to External Circuit.
AD6, AG1,
AD3, AC3,
AC2, Y6
DS3DATAOUTCLK[6:1]
—
ID
44.736 MHz DS3/34.368 MHz E3/51.84 MHz
STS1Clock in from External Circuit.
AH1, AE2,
AC5, AB6,
AC1, AA3
DS3RXCLKOUT[6:1]
—
O
44.736 MHz DS3/34.368 MHz E3/51.84 MHz STS1
CLOCK out to External Circuit.
DS3/E3/STS1 Input (18)
AA1, Y2,
W6, V3, U3,
T2
DS3POSDATAIN[6:1]
—
ID
Serial DS3/E3/STS1 Positive Data from External
Device.
AA2, Y1, V6,
V5, U2, T1
DS3NEGDATAIN[6:1]
—
ID
Serial DS3/E3 Negative Data or Bipolar Violation
Input from External Device.
Y5, Y3, W2,
W1, V2, U5
DS3DATAINCLK[6:1]
—
ID
44.736 MHz DS3/34.368 MHz E3/51.84 MHz STS1
Clock In from External Device.
* O1 indicates external pull-up recommended (unused or system required),
I/O2 indicates external pull-down recommended (unused or system required),
ID; I/OD indicate internal pull-down,
IU indicates internal pull-up.
32
Agere Systems Inc.
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin
Symbol
Type I/O*
Description
Multifunction System Interface
Note: Pin functional descriptions are representative configurations. Configuration is limited by the I/O definition
and the flexibility of the internal cross-connect.
LINE Transmit Path Direction (60)†
A3, F8, B5, A4,
B6, B7, E9,
F10, B8, A7,
B9, E11, B10,
E12, A10, F13,
A11, F14, E14,
C14, F15, E15,
C15, B15, F17,
A16, C17, B18,
E18, B19
LINERXDATA[30:1]
—
ID
Configurable Inputs to the Internal Cross Connect.
Transport Modes:
Framer—LIU: Received positive-rail or single-rail DS1/E1
line data input (sourced from an external LIU).
M12 or E12: Normally used as receive DS1/E1 data input. If
DS1/E1’s come from internal source, these pins may also be
used as DS2/E2 inputs.
VT Mapper: Receive DS1/E1/VC data input.
M23 or E23: Receive DS2/E2 data input. Up to 21 DS2/12
E2 signals may be assigned to any of the 30 LINERXDATA
inputs.
E6, B4, C5, C6,
E8, A5, F9, A6,
C8, F11, C9,
A8, F12, A9,
C11, B11, C12,
B12, A12, B13,
A13, B14, A14,
F16, A15, B16,
E17, B17, C18,
A19
LINERXCLK[30:1]
—
I/OD Configurable Inputs to the Internal Cross Connect.
Transport Modes:
Framer—LIU: Receive DS1/E1 line clock input
M12 or E12: Normally used as receive DS1/E1 line clock
input (unless for demand clocking mode in which they are
used as clock outputs). If DS1/E1 signals come from internal
source, these pins may carry DS2/E2 clk input.
VT Mapper: Receive DS1/E1/VC line clock input
M23 or E23: Receive DS2/E2 clock input/output. Up to
21 DS2/12 E2 signals may be assigned to any of the 30 LINERXCLK inputs.
* O1 indicates external pull-up recommended (unused or system required),
I/O2 indicates external pull-down recommended (unused or system required),
ID; I/OD indicate internal pull-down,
IU indicates internal pull-up.
† Transmit path convention is toward the high-speed fiber output. Note that LINERX signals are labeled Receive, as seen from the cross connect perspective.
Agere Systems Inc.
33
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin
Symbol
Type
I/O*
Description
Multi-Function System Interface (continued)
LINE Receive Path Direction (60)†
A23, B23,
C23, B24,
C24, A26,
F23, A27,
C26, F24,
C27, A29,
F26, A30,
E27, C29,
C30, B31,
E29, E30,
C34, H29,
E33, D34,
F33,G33,
J30, K29,
H33, G34
LINETXDATA[30:1]
E21, F21,
A24, F22,
A25, E23,
B25, E24,
B26, A28,
B27, F25,
E26, B28,
B29, A31,
B30, F27,
A32, F29,
F30, D33,
E32, F32,
H30, E34,
J29, F34,
H32, L29
LINETXCLK[30:1]
—
O
Configurable Outputs from the Internal Cross Connect
and Can Be Individually 3-stated.
Transport modes:
Framer—LIU: Transmit positive-rail or single-rail DS1/E1 line
data output (to an external LIU).
M12 or E12 or VT Mapper: Transmit DS1/E1/VC/DS2/E2 data
output.
M23 or E23: Transmit DS2/E2 data output. Up to 21 DS2/12
E2 signals may be assigned to any of the 30 LINETXDATA
outputs.
—
I/O
Configurable Inputs/Outputs from the Internal Cross
Connect and Can Be Individually 3-Stated.
Transport mode:
Framer—LIU: Transmit DS1/E1 line clock output.
M12 or E12 or VT mapper: Transmit DS1/E1/VC line clock
output. If, in M12/E12 mode, DS1/E1 signals don’t go out of
the device, these pins may carry DS2 clock input/output for
M12/E12 deMUX.
M23 or E23: Transmit DS2/E2 clock input/output. Up to
21 DS2/12 E2 signals may be assigned to any of the 30
LINETXCLK outputs.
* O1 indicates external pull-up recommended (unused or system required),
I/O2 indicates external pull-down recommended (unused or system required),
ID; I/OD indicate internal pull-down,
IU indicates internal pull-up.
† Receive path convention is away from the high-speed fiber output. Note that LINETX signals are labeled “Transmit,” as seen from the cross
connect perspective.
34
Agere Systems Inc.
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin
Symbol
Type I/O*
Description
Multifunction System Interface (continued)
CHI Transmit PATH Direction (45 total, last 3 not indexed)†
J32, J33,
H34, L30,
M29, K33,
J34, M30,
L32, K34,
L33, N29,
M32, L34,
M33, P29,
M34, P30,
N33, P32,
N34, R29,
P33, R30,
P34, R32,
T29, R33,
R34, U29,
T33, T34,
U30, U32,
U33, V33,
V32, V30,
W34, W33,
V29, Y34
CHIRXDATA[42:1]
Y32
CHIRXGTCLK
—
I
Configurable Inputs to the Internal Cross Connect.
Switching modes:
CHI:
Receive system data or data and signaling input at
2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s, or 16.384 Mbits/s.
Parallel system bus:
CHIRXDATA[16:1]: Receive system data bus input is assigned to
the first 16 inputs (19.44 Mbits/s). MSB—CHIRXDATA[16]
through LSB to CHIRXDATA[1].
CHIRXDATA[42:17]: Not used in PSB mode only.
Transport modes:
Framer—LIU: CHIRXDATA[30:1] Received negative-rail
DS1/E1 line data input or 8k frame sync input.
M12 or E12: not used.
VT Mapper: 8 k SYNC for DS1/E1 or 2 k sync signal for VC.
M23 or E23: Stuff request input in demand clocking mode.
—
I
CHI: global transmit line clock input. Externally supplied
1.544 MHz for DS1 and 2.048 MHz low jitter clock phase-locked
to the receive CHI system clock (optional).
Parallel system bus: global transmit line clock input. Externally
supplied 1.544 MHz for DS1 and 2.048 MHz low jitter clock
phase-locked to the parallel system bus receive clock (optional).
W29
CHIRXGCLK
—
I
CHI: receive global system clock input (4.096 MHz, 8.192 MHz,
or 16.384 MHz).
Parallel system bus: Receive global clock input (19.44 MHz).
Y33
CHIRXGFS
—
I
CHI: Receive system frame sync input.
Parallel system bus: Receive system frame sync input.
* O1 indicates external pull-up recommended (unused or system required),
I/O2 indicates external pull-down recommended (unused or system required),
ID; I/OD indicate internal pull-down,
IU indicates internal pull-up.
† Transmit path convention is toward the high-speed fiber output. Note that CHIRX signals are labeled “Receive,” as seen from the cross connect perspective.
Agere Systems Inc.
35
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin
AA33, Y29,
AB34,
AA32,
AB33,
AA30,
AC34,
AA29,
AC33,
AD34,
AC32,
AB29,
AD33,
AE34,
AD32,
AC30,
AF34, AE33,
AC29,
AD30,
AG34,
AF33, AF32,
AH34,
AD29,
AG33,
AG32,
AE29, AJ34,
AF30, AF29,
AH33,
AK34, AJ33,
AG30,
AM34,
AJ30, AJ29,
AK29,
AP32,
AN31, AJ27
AA34
Y30
Symbol
Type I/O*
Description
Multifunction System Interface (continued)
CHI Receive Path Direction (44 total, last 2 not indexed)†
CHITXDATA[42:1]
—
I/O Configurable Outputs from the Internal Cross Connect.
Switching modes:
CHI: Transmit system data or data and signaling output
(2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s, or 16.384 Mbits/s).
Parallel system bus:
CHITXDATA[16:1]: Transmit system data bus output is restricted
to the first 16 outputs (19.44 Mbits/s). MSB—
CHITXDATA[16] through LSB to CHITXDATA[1].
CHITXDATA[42:17]: Not used in PSB mode only.
Transport modes:
Framer—LIU: Transmit negative-rail DS1/E1 line data output or
8 K frame sync output.
VT mapper: 8 K sync output for DS1/E1 or 2 K sync output for VC.
M12:
CHITXDATA [7:1]: Carry DS2 data output from the M12 MUX.
CHITXDATA [14:8]: Carry DS2 clock input/output of the M12 MUX.
CHITXDATA [21:15]: Carry DS2 data input to the M12 deMUX.
CHITXDATA [28:22]: Carry DS2 clock input to the M12 deMUX.
CHITXGFS
—
I
CHI: Transmit system frame sync input.
CHITXGCLK
—
I
Parallel system bus: Transmit system frame sync input.
Switching Modes: CHI: Transmit global system clock input
(4.096 MHz, 8.192 MHz, or 16.384 MHz).
Parallel system bus: Transmit global clock input (19.44 MHz).
* O1 indicates external pull-up recommended (unused or system required),
I/O2 indicates external pull-down recommended (unused or system required),
ID; I/OD indicate internal pull-down, IU indicates internal pull-up.
† Receive path convention is away from the high-speed fiber output. Note that CHITX signals are labeled Transmit, as seen from the cross connect perspective.
36
Agere Systems Inc.
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin
Symbol
Type I/O*
Description
NSMI Transmit Path Direction
I
(12)†
NSMI Receive Data Inputs or STS-1 Receive Data Inputs
for STS1LTs.
AP28, AK24,
AK23
NSMIRXDATA[3:1]
—
AJ24, AP27,
AP26
NSMIRXCLK[3:1]
—
I/O NSMI Receive Clock Input (51.84 MHz) for FRM or Transmit
Clock Output for M13 or SPE. These pins can also carry
STS-1 Rx clock inputs for STS1LTs.
AN27, AN26,
AN25
NSMIRXSYNC[3:1]
—
I/O NSMI Receive System Frame Sync Input for FRM or Transmit Control Signal for M13 or SPE. They may also carry
STS-1 transmit clock inputs for STS1LTs.
AM27,
AM26, AJ23
RXDATAEN[3:1]
—
O
Receive Data Enable for NSMI Mode.
NSMI Receive Path Direction (12)‡
AP31, AN28,
AJ25
NSMITXDATA[3:1]
—
O
NSMI Transmit Data Outputs or STS-1 Tx Data Outputs
from STS1LTs.
AM29,
AP30, AP29
NSMITXCLK[3:1]
—
O
NSMI Transmit Clock Output or STS-1 Tx Clock Outputs
from STS1LTs.
AN30, AN29,
AK26
NSMITXSYNC[3:1]
—
O
Transmit System Frame Sync Output.
AM30,
AK27, AJ26
TXDATAEN[3:1]
—
O
Transmit Data Enable for NSMI Mode.
* O1 indicates external pull-up recommended (unused or system required),
I/O2 indicates external pull-down recommended (unused or system required),
ID; I/OD indicate internal pull-down,
IU indicates internal pull-up.
† Transmit path convention is toward the high-speed fiber output. Note that CHIRX signals are labeled Receive, as seen from the cross connect
perspective.
‡ Receive path convention is away from the high-speed fiber output. Note that CHITX signals are labeled Transmit, as seen from the cross connect perspective.
Agere Systems Inc.
37
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin
Symbol
Type
I/O*
Description
M13/E13 Mux/DeMUX Block
Receive (DeMUX) Direction (6)
AP21
E1XCLK
—
ID
E1 X Clock. This clock signal is used to generate E1 AIS
(all 1s). It must be 2.048 MHz ± 50 ppm, or x16, x32 of
2.048 MHz.
AK20
DS1XCLK
—
ID
DS1 X Clock. This clock signal is used to generate DS1
AIS (all 1s). It must be 1.544 MHz ± 32 ppm, or x16, x32 of
1.544 MHz.
R1
DS2AISCLK
—
ID
DS2 AIS Clock. A 6.312 MHz ± 30 ppm clock input used as
DS2 AIS clock or DS2 data output clock.
VC11 AIS Clock. A 1.664 MHz input. In the VTMPR mode,
this clock is used to generate VC11 AIS.
U6
E2AISCLK
—
ID
E2 AIS Clock. A 8.448 MHz ± 30 ppm clock input used as
E2 AIS clock or E2 data output clock.
VC12 AIS Clock. A 2.224 MHz input. In the VTMPR mode,
this clock is used to generate VC12 AIS.
A21
DS3XCLK
—
ID
DS3 X Clock. A 44.736 MHz ± 20 ppm clock input for DS3
DJA.
F18
E3XCLK
—
ID
E3 X Clock. A 34.768 MHz ± 20 ppm clock input for E3
DJA.
VT Mapper Block
Transmit Direction (3)
B22
LOPOHCLKIN
—
ID
Low-Order Path Overhead Clock.
Low-Order Path Overhead Data (O-Bits, V5, J2, Z6/N2,
Z7, and K4 Byte).
Valid LOPOHDATAIN.
C21
LOPOHDATAIN
—
ID
A22
LOPOHVALIDIN
—
ID
F20
LOPOHCLKOUT
—
O
Low-Order Path Overhead Clock.
B21
LOPOHDATAOUT
—
O
Low-Order Path Overhead Data (Line and Path REI and
RDI, O-Bits, V5, J2, Z6/N2, and Z7/K4 Byte).
E20
LOPOHVALIDOUT
—
O
Valid LOPOHDATAOut.
Receive Direction (3)
* O1 indicates external pull-up recommended (unused or system required),
I/O2 indicates external pull-down recommended (unused or system required),
ID; I/OD indicate internal pull-down,
IU indicates internal pull-up.
38
Agere Systems Inc.
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin
Symbol
Type
I/O*
Description
ID
PLL Clock Input.
Framer PLL (4)
AJ32
CLKIN_PLL
—
AL33
CG_PLLCLKOUT
—
O
Clock generation for Framer 3.3 V PLL.
AK30
MODE2_PLL
—
ID
PLL Control Input for Mode 2/Testmode Output.
—
ID
PLL Control Input for Mode 0.
ID
PLL Control Input for Mode 1.
AG29
MODE0_PLL
AK32
MODE1_PLL
—
F5
MPCLK
—
I
Synchronous Microprocessor Clock (when MPMODE = 1).
The maximum clock frequency is 66 MHz. This clock is required
to properly sample address, data, and control signals from the
microprocessor in both asynchronous and synchronous modes
of operation. This clock must be within the range of 16 MHz to
66 MHz.
F6
MPMODE
—
I
Microprocessor Mode Select. If the microprocessor interface
is synchronous, MPMODE should be set to 1. If the microprocessor interface is asynchronous, MPMODE should be set to 0.
C1
CSN
—
IU
Chip Select (Active-Low). For synchronous mode, it should be
stable beyond a certain setup time before the rising clock edge
when ADSN is active. For asynchronous mode, it should be stable before DSN is asserted.
D2
ADSN
—
I
Address Strobe (Active-Low). Active-low address strobe that
is a one MPCLK cycle wide pulse for synchronous mode and
active for the entire read/write cycle for asynchronous mode.
Address bus signals, ADDR(20:0), are transparently latched into
Ultramapper when ADSN is low. The address bus should
remain valid for the duration of ADSN.
H6
RWN
—
I
Read/Write Cycle Selection. RWN is set high for a read operation, or set low for write operation.
E3
DSN
—
I
Data Strobe (Active-Low). DSN is not used for synchronous
mode. For asynchronous mode, write operation, DSN becomes
active after data is stable. For read operation, it is similar to
ADSN.
Microprocessor Interface (49)
* O1 indicates external pull-up recommended (unused or system required),
I/O2 indicates external pull-down recommended (unused or system required),
ID; I/OD indicate internal pull-down,
IU indicates internal pull-up.
Agere Systems Inc.
39
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin
Symbol
Type
I/O*
Description
Microprocessor Interface (continued) (49)
21-Bit Address Bus, for 16-Bit Data Bus. The address bus sig—
I
nals are latched transparently when ADSN is low.
ADDR20—MSB.
ADDR0—LSB.
K2, M6, L5,
H1, J2, J3,
G1, L6, H2,
H3, K6, F1,
J5, J6, G2,
E1, F2, H5,
D1, F3, E2
ADDR[20:0]
R6, N1, P3,
N2, P5, M1,
P6, M2, L1,
M3, N6, L2,
K1, L3, M5, J1
R5, P2
DATA[15:0]
—
PAR[1:0]
—
P1
DTN
—
R3
HP_INTN
—
T6
LP_INTN
—
R2
APS_INTN
—
I/O
Note: The Ultramapper is little-endian, the least significant byte is
stored in the lowest address and the most significant byte is
stored in the highest address. Care must be exercised in
connection to microprocessors that use big-endian byte
ordering.
16-Bit Data Bus. Device inputs for write operation and outputs for
read operation.
DATA15—MSB.
DATA0—LSB.
Data Parity. Byte-wide parity bits for data. PAR[1] is the parity for
DATA[15:8] and PAR[0] is the parity for DATA[7:0].
Open Data Transfer Acknowledge. In synchronous microprocessor
Drain mode, the delay associated with DTN going low depends on the
O1 Ultramapper block being accessed, the address within that block,
and the operating mode. In asynchronous microprocessor mode,
after qualification of ADSN and DSN by TLSC52 clock, DTN going
low depends on the Ultramapper block being accessed, the
address within that block, and the operating mode. Under all conditions the user should wait until DTN is asserted before starting
the next operation. DTN goes high along with the rising edge of
ADSN.
Open Ultramapper High Priority Interrupt Request (Active-Low).
Drain
O1
Open Ultramapper Low Priority Interrupt Request (Active-Low).
Drain
O1
Open Automatic Protection Switch (APS) Interrupt Request
Drain (Active-Low).
O1
I/O
* O1 indicates external pull-up recommended (unused or system required),
I/O2 indicates external pull-down recommended (unused or system required),
ID; I/OD indicate internal pull-down,
IU indicates internal pull-up.
40
Agere Systems Inc.
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin
Symbol
Type
I/O*
Description
General Purpose Interface (13)
AP22
RSTN
—
IU
Chip Reset (Active-Low).
AM21
PMRST
—
I/OD
AN22
TCK
—
I
JTAG Test Clock. This signal provides timing for test operations.
AK21
TDI
—
IU
JTAG Test Data In. JTAG test data input signal, sampled on
the rising edge of TCK.
AP23
TMS
—
IU
JTAG Test Mode Select. Controls test operations. TMS is
sampled on the rising edge of TCK.
AJ21
TRST
—
IU
JTAG Test Reset (Active-Low). This signal provides an
asynchronous reset.
AN23
TDO
—
O
JTAG Test Data Out. JTAG test data output signal is updated
on the falling edge of TCK. The TDO output is 3-stated
except when scanning out test data.
AP24
IC3STATEN
—
IU
Disable Output Capability of all Bidirectional and 3-State
Output Buffers (Active-Low).
AM23
SCK1
—
ID
(Test Only.) Scan Clock 1.
D
Performance Monitor Reset.
AJ22
SCK2
—
I
(Test Only.) Scan Clock 2.
AN24
SCAN_EN
—
ID
(Test Only.) Scan Enable (Active-High).
—
D
(Test Only.) Serial Scan Input for Testing (Active-High).
D
(Test Only.) IDDQ Input (Active-High).
AP25
SCANMODE
I
AM24
IDDQ
—
I
AJ15
BYPASS
—
ID
(Test Only.) Enables functional bypassing of the clock synthesis with a test clock. Active-high.
AJ14
TSTPHASE
—
ID
(Test Only.) Controls bypass of 32 PLL-generated phases
with 32 low-speed phases, generated by test logic. Activehigh.
AM15
ECSEL
—
ID
(Test Only.) Enables external test control of 155 MHz clock
phase selection through ETOGGLE and EXDNUP inputs.
Active-high.
AJ16
ETOGGLE
—
ID
(Test Only.) Moves 155 MHz clock selection one phase per
positive pulse > 20 ns. Active + pulse.
AL17
EXDNUP
—
ID
(Test Only.) Direction of phase change.
0 = down; 1 = up.
AK17
TSTMODE
—
ID
(Test Only.) Enables test mode for CDR and PLLs.
—
D
(Test Only.) Enables CDR test mode shift register.
CDR Interface (7)
AM14
TSTSFTLD
I
* O1 indicates external pull-up recommended (unused or system required),
I/O2 indicates external pull-down recommended (unused or system required),
ID; I/OD indicate internal pull-down,
IU indicates internal pull-up.
Agere Systems Inc.
41
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin
AK2
AK3
AG6
AL2
AM1
AJ5
AK5
E5
AK12
AK11
AJ10
AJ12
AK14
AJ11
AK33
AL34
C20
F19
B20
A20
Symbol
Type
I/O*
No Connects
NC
—
—
NC
—
—
NC
—
—
NC
—
—
NC
—
—
NC
—
—
NC
—
—
NC
—
—
Power And Ground Signals
CDR 1 & 2 Pins (4)
VSSA_CDR1
—
I
VDD15A_CDR1
—
I
VDD15A_CDR2
—
I
VSSA_CDR2
—
I
X4PLL Pins (2)
VDD15A_X4PLL
—
I
VSSA_X4PLL
—
I
Framer PLL Pins (2)
VDD33A_SFPLL
—
I
VSSA_SFPLL
—
I
DS3/E3 PLL Pins (4)
VDD15A_DS3PLL
—
I
VSSA_DS3PLL
—
I
VDD15A_E3PLL
—
I
VSSA_E3PLL
—
I
Description
No connect.
No connect.
No connect.
No connect.
No connect.
No connect.
No connect.
No connect.
Analog VSS for CDR 1.
1.5 V analog VDD for CDR 1.
1.5 V analog VDD for CDR 2.
Analog VSS for CDR 2.
1.5 V analog VDD for the times four PLL.
Analog VSS for the times four PLL.
Analog 3.3 V VDD for the Framer PLL.
Analog ground for the Framer PLL.
1.5 V analog VDD for the DS3 PLL.
Analog VSS for the DS3 PLL.
1.5 V analog VDD for the E3 PLL.
Analog VSS for the E3 PLL.
* O1 indicates external pull-up recommended (unused or system required),
I/O2 indicates external pull-down recommended (unused or system required),
ID; I/OD indicate internal pull-down,
IU indicates internal pull-up.
42
Agere Systems Inc.
Advance Data Sheet, Rev. 2
July 2001
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
3 Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin
Symbol
Type
I/O*
Description
Common VDD15 Pins (96)
VDD15
—
— Common power signals for 1.5 V VDD.
AA16, AA17, AA18, AA19, AA28, AA7,
AB16, AB17, AB18, AB19, AB28, AB7,
AC28, AC7, AD28, AD7, AE28, AE7,
AF28, AF7, AH10, AH11, AH12, AH13,
AH14, AH15, AH16, AH19, AH20,
AH21, AH22, AH23, AH24, AH25,
AH26, AH9, G10, G11, G12, G13, G14,
G15, G16, G19, G20, G21, G22, G23,
G24, G25, G26, G9, J28, J7, K28, K7,
L28, L7, M28, M7, N16, N17, N18,
N19, N28, N7, P16, P17, P18, P19,
P28, P7, R28, R7, T13, T14, T21, T22,
T28, T7, U13, U14, U21, U22, V13,
V14, V21, V22, W13, W14, W21, W28,
W7, Y28, Y7, W22
Power And Ground Signals (continued)
Common VDD33 Pins (66)
VDD33
—
— Common power signals for 3.3 V VDD.
A2, A33, AA4, AC31, AD4, AF31,
AG28, AG4, AG7, AH17, AH18, AH27,
AH8, AJ31, AK4, AL12, AL21, AL24,
AL27, AL30, AL6, AL9, AM2, AM33,
AN1, AN3, AN32, AN34, AP2, AP33,
B1, B3, B32, B34, C2, C33, D11, D14,
D17, D20, D23, D26, D29, D5, D8,
E31, F4, G17, G18, G27, G8, H28,
H31, H7, J4, L31, M4, P31, R4, U28,
U31, U7, V28, V4, V7, Y31
Common VSS Pins (90)
VSS
—
— Common ground signals.
A1, A17, A18, A34, AA13, AA14, AA21,
AA22, AA31, AB13, AB14, AB21,
AB22, AC4, AD31, AF4, AG31, AJ4,
AK31, AL11, AL20, AL23, AL26, AL29,
AL5, AL8, AM11, AM12, AM3, AM32,
AN12, AN2, AN33, AN6, AN9, AP1,
AP12, AP34, B2, B33, C3, C32, D12,
D15, D18, D21, D24, D27, D30, D6,
D9, E4, F31, H4, J31, L4, M31, N13,
N14, N21, N22, P13, P14, P21, P22,
P4, R31, T16, T17, T18, T19, U1, U16,
U17, U18, U19, U34, U4, V1, V16, V17,
V18, V19, V31, V34, W16, W17, W18,
W19, Y4
* O1 indicates external pull-up recommended (unused or system required),
I/O2 indicates external pull-down recommended (unused or system required),
ID; I/OD indicate internal pull-down,
IU indicates internal pull-up.
Agere Systems Inc.
43
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 2. Pin Assignments for 700-Pin PBGA by Pin Number Order
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA13
AA14
AA16
44
Signal Name
VSS
VDD33
LINERXDATA[30]
LINERXDATA[27]
LINERXCLK[25]
LINERXCLK[23]
LINERXDATA[21]
LINERXCLK[19]
LINERXCLK[17]
LINERXDATA[16]
LINERXDATA[14]
LINERXCLK[12]
LINERXCLK[10]
LINERXCLK[8]
LINERXCLK[6]
LINERXDATA[5]
VSS
VSS
LINERXCLK[1]
VSSA_E3PLL
DS3XCLK
LOPOHVALIDIN
LINETXDATA[30]
LINETXCLK[28]
LINETXCLK[26]
LINETXDATA[25]
LINETXDATA[23]
LINETXCLK[21]
LINETXDATA[19]
LINETXDATA[17]
LINETXCLK[15]
LINETXCLK[12]
VDD33
VSS
DS3POSDATAIN[6]
DS3NEGDATAIN[6]
DS3RXCLKOUT[1]
VDD33
DS3POSDATAOUT[2]
DS3NEGDATAOUT[2]
VDD15
VSS
VSS
VDD15
Pin
AA18
AA19
AA21
AA22
AA28
AA29
AA30
AA31
AA32
AA33
AA34
AB1
AB2
AB6
AB7
AB13
AB14
AB16
AB17
AB18
AB19
AB21
AB22
AB28
AB29
AB33
AB34
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC28
AC29
AC30
AC31
AC32
AC33
AC34
AD1
AD2
AD3
Signal Name
VDD15
VDD15
VSS
VSS
VDD15
CHITXDATA[35]
CHITXDATA[37]
VSS
CHITXDATA[39]
CHITXDATA[42]
CHITXGFS
DS3NEGDATAOUT[1]
DS3POSDATAOUT[1]
DS3RXCLKOUT[3]
VDD15
VSS
VSS
VDD15
VDD15
VDD15
VDD15
VSS
VSS
VDD15
CHITXDATA[31]
CHITXDATA[38]
CHITXDATA[40]
DS3RXCLKOUT[2]
DS3DATAOUTCLK[2]
DS3DATAOUTCLK[3]
VSS
DS3RXCLKOUT[4]
DS3NEGDATAOUT[5]
VDD15
VDD15
CHITXDATA[24]
CHITXDATA[27]
VDD33
CHITXDATA[32]
CHITXDATA[34]
CHITXDATA[36]
DS3POSDATAOUT[3]
DS3NEGDATAOUT[3]
DS3DATAOUTCLK[4]
Agere Systems Inc.
Advance Data Sheet, Rev. 2
July 2001
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
3 Pin Information (continued)
Table 2. Pin Assignments for 700-Pin PBGA by Pin Number Order (continued)
Pin
AA17
AD5
AD6
AD7
AD28
AD29
AD30
AD31
AD32
AD33
AD34
AE1
AE2
AE6
AE7
AE28
AE29
AE33
AE34
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF28
AF29
AF30
AF31
AF32
AF33
AF34
AG1
AG2
AG3
AG4
AG5
AG6
AG7
AG28
AG29
AG30
AG31
Agere Systems Inc.
Signal Name
VDD15
DS3POSDATAOUT[5]
DS3DATAOUTCLK[6]
VDD15
VDD15
CHITXDATA[18]
CHITXDATA[23]
VSS
CHITXDATA[28]
CHITXDATA[30]
CHITXDATA[33]
DS3POSDATAOUT[4]
DS3RXCLKOUT[5]
PHASEDETUP[2]
VDD15
VDD15
CHITXDATA[15]
CHITXDATA[25]
CHITXDATA[29]
DS3NEGDATAOUT[4]
DS3POSDATAOUT[6]
DS3NEGDATAOUT[6]
VSS
PHASEDETUP[3]
PHASEDETDOWN[3]
VDD15
VDD15
CHITXDATA[12]
CHITXDATA[13]
VDD33
CHITXDATA[20]
CHITXDATA[21]
CHITXDATA[26]
DS3DATAOUTCLK[5]
PHASEDETUP[1]
PHASEDETDOWN[1]
VDD33
PHASEDETDOWN[2]
NC
VDD33
VDD33
MODE0_PLL
CHITXDATA[8]
VSS
Pin
AD4
AG34
AH1
AH2
AH8
AH9
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH33
AH34
AJ1
AJ2
AJ3
AJ4
AJ5
AJ6
AJ8
AJ9
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
Signal Name
VDD33
CHITXDATA[22]
DS3RXCLKOUT[6]
PHASEDETUP[4]
VDD33
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD33
VDD33
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD33
CHITXDATA[11]
CHITXDATA[19]
PHASEDETDOWN[5]
PHASEDETUP[5]
PHASEDETDOWN[6]
VSS
NC
REF10
RESLO
CTAPTH
VDD15A_CDR2
VSSA_X4PLL
VSSA_CDR2
CTAPRL
TSTPHASE
BYPASS
ETOGGLE
RTOACDATA
RPOACDATA
TPOACDATA
45
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 2. Pin Assignments for 700-Pin PBGA by Pin Number Order (continued)
Pin
AG32
AG33
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AK1
AK2
AK3
AK4
AK5
AK6
AK8
AK9
AK11
AK12
AK14
AK15
AK17
AK18
AK20
AK21
AK23
AK24
AK26
AK27
AK29
AK30
AK31
AK32
AK33
AK34
AL1
AL2
AL5
AL6
46
Signal Name
CHITXDATA[16]
CHITXDATA[17]
SCK2
RXDATAEN[1]
NSMIRXCLK[3]
NSMITXDATA[1]
TXDATAEN[1]
CHITXDATA[1]
CHITXDATA[5]
CHITXDATA[6]
VDD33
CLKIN_PLL
CHITXDATA[9]
CHITXDATA[14]
PHASEDETDOWN[4]
NC
NC
VDD33
NC
REF14
CTAPRH
CTAPRP
VDD15A_CDR1
VSSA_CDR1
VDD15A_X4PLL
RLSCLK
TSTMODE
TTOACSYNC
DS1XCLK
TDI
NSMIRXDATA[1]
NSMIRXDATA[2]
NSMITXSYNC[1]
TXDATAEN[2]
CHITXDATA[4]
MODE2_PLL
VSS
MODE1_PLL
VDD33A_SFPLL
CHITXDATA[10]
PHASEDETUP[6]
NC
VSS
VDD33
Pin
AJ20
AJ21
AL12
AL14
AL15
AL17
AL18
AL20
AL21
AL23
AL24
AL26
AL27
AL29
AL30
AL33
AL34
AM1
AM2
AM3
AM5
AM6
AM8
AM9
AM11
AM12
AM14
AM15
AM17
AM18
AM20
AM21
AM23
AM24
AM26
AM27
AM29
AM30
AM32
AM33
AM34
AN1
AN2
AN3
Signal Name
RHSFSYNCN
TRSTN
VDD33
TLSCLK
THSSYNC
EXDNUP
TTOACCLK
VSS
VDD33
VSS
VDD33
VSS
VDD33
VSS
VDD33
CG_PLLCLKOUT
VSSA_SFPLL
NC
VDD33
VSS
RHSDP
RHSDN
RPSDP
RPSDN
VSS
VSS
TSTSFTLD
ECSEL
RTOACCLK
RTOACSYNC
TPOACSYNC
PMRST
SCK1
IDDQ
RXDATAEN[2]
RXDATAEN[3]
NSMITXCLK[3]
TXDATAEN[3]
VSS
VDD33
CHITXDATA[7]
VDD33
VSS
VDD33
Agere Systems Inc.
Advance Data Sheet, Rev. 2
July 2001
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
3 Pin Information (continued)
Table 2. Pin Assignments for 700-Pin PBGA by Pin Number Order (continued)
Pin
AL8
AL9
AL11
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
AN32
AN33
AN34
AP1
AP2
AP3
AP4
AP5
AP6
AP7
AP8
AP9
AP10
AP11
AP12
AP13
Agere Systems Inc.
Signal Name
VSS
VDD33
VSS
THSDP
THSDN
VSS
RPSCP
RPSCN
VSS
TLSDATAP[1]
TLSDATAN[1]
TLSDATAP[2]
TLSDATAN[2]
TLSDATAP[3]
TLSDATAN[3]
RPOACCLK
TPOACCLK
LOSEXT
TCK
TDO
SCAN_EN
NSMIRXSYNC[1]
NSMIRXSYNC[2]
NSMIRXSYNC[3]
NSMITXDATA[2]
NSMITXSYNC[2]
NSMITXSYNC[3]
CHITXDATA[2]
VDD33
VSS
VDD33
VSS
VDD33
RESHI
THSCOP
THSCON
THSCP
THSCN
TPSCP
TPSCN
TPSDP
TPSDN
VSS
RLSDATAP[1]
Pin
AN4
AN5
AN6
AP18
AP19
AP20
AP21
AP22
AP23
AP24
AP25
AP26
AP27
AP28
AP29
AP30
AP31
AP32
AP33
AP34
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
Signal Name
RHSCP
RHSCN
VSS
RLSDATAN[3]
TTOACDATA
RPOACSYNC
E1XCLK
RSTN
TMS
IC3STATEN
SCANMODE
NSMIRXCLK[1]
NSMIRXCLK[2]
NSMIRXDATA[3]
NSMITXCLK[1]
NSMITXCLK[2]
NSMITXDATA[3]
CHITXDATA[3]
VDD33
VSS
VDD33
VSS
VDD33
LINERXCLK[29]
LINERXDATA[28]
LINERXDATA[26]
LINERXDATA[25]
LINERXDATA[22]
LINERXDATA[20]
LINERXDATA[18]
LINERXCLK[15]
LINERXCLK[13]
LINERXCLK[11]
LINERXCLK[9]
LINERXDATA[7]
LINERXCLK[5]
LINERXCLK[3]
LINERXDATA[3]
LINERXDATA[1]
VDD15A_E3PLL
LOPOHDATAOUT
LOPOHCLKIN
LINETXDATA[29]
LINETXDATA[27]
47
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 2. Pin Assignments for 700-Pin PBGA by Pin Number Order (continued)
Pin
AP14
AP15
AP16
AP17
B29
B30
B31
B32
B33
B34
C1
C2
C3
C5
C6
C8
C9
C11
C12
C14
C15
C17
C18
C20
C21
C23
C24
C26
C27
C29
C30
C32
C33
C34
D1
D2
D5
D6
D8
D9
D11
D12
D14
D15
48
Signal Name
RLSDATAN[1]
RLSDATAP[2]
RLSDATAN[2]
RLSDATAP[3]
LINETXCLK[16]
LINETXCLK[14]
LINETXDATA[13]
VDD33
VSS
VDD33
CSN
VDD33
VSS
LINERXCLK[28]
LINERXCLK[27]
LINERXCLK[22]
LINERXCLK[20]
LINERXCLK[16]
LINERXCLK[14]
LINERXDATA[11]
LINERXDATA[8]
LINERXDATA[4]
LINERXCLK[2]
VDD15A_DS3PLL
LOPOHDATAIN
LINETXDATA[28]
LINETXDATA[26]
LINETXDATA[22]
LINETXDATA[20]
LINETXDATA[15]
LINETXDATA[14]
VSS
VDD33
LINETXDATA[10]
ADDR[2]
ADSN
VDD33
VSS
VDD33
VSS
VDD33
VSS
VDD33
VSS
Pin
B25
B26
B27
B28
D23
D24
D26
D27
D29
D30
D33
D34
E1
E2
E3
E4
E5
E6
E8
E9
E11
E12
E14
E15
E17
E18
E20
E21
E23
E24
E26
E27
E29
E30
E31
E32
E33
E34
F1
F2
F3
F4
F5
F6
Signal Name
LINETXCLK[24]
LINETXCLK[22]
LINETXCLK[20]
LINETXCLK[17]
VDD33
VSS
VDD33
VSS
VDD33
VSS
LINETXCLK[9]
LINETXDATA[7]
ADDR[5]
ADDR[0]
DSN
VSS
NC
LINERXCLK[30]
LINERXCLK[26]
LINERXDATA[24]
LINERXDATA[19]
LINERXDATA[17]
LINERXDATA[12]
LINERXDATA[9]
LINERXCLK[4]
LINERXDATA[2]
LOPOHVALIDOUT
LINETXCLK[30]
LINETXCLK[25]
LINETXCLK[23]
LINETXCLK[18]
LINETXDATA[16]
LINETXDATA[12]
LINETXDATA[11]
VDD33
LINETXCLK[8]
LINETXDATA[8]
LINETXCLK[5]
ADDR[9]
ADDR[4]
ADDR[1]
VDD33
MPCLK
MPMODE
Agere Systems Inc.
Advance Data Sheet, Rev. 2
July 2001
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
3 Pin Information (continued)
Table 2. Pin Assignments for 700-Pin PBGA by Pin Number Order (continued)
Pin
D17
D18
D20
D21
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F29
F30
F31
F32
F33
F34
G1
G2
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
Agere Systems Inc.
Signal Name
VDD33
VSS
VDD33
VSS
LINERXCLK[18]
LINERXDATA[15]
LINERXDATA[13]
LINERXDATA[10]
LINERXCLK[7]
LINERXDATA[6]
E3XCLK
VSSA_DS3PLL
LOPOHCLKOUT
LINETXCLK[29]
LINETXCLK[27]
LINETXDATA[24]
LINETXDATA[21]
LINETXCLK[19]
LINETXDATA[18]
LINETXCLK[13]
LINETXCLK[11]
LINETXCLK[10]
VSS
LINETXCLK[7]
LINETXDATA[6]
LINETXCLK[3]
ADDR[14]
ADDR[6]
VDD33
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD33
VDD33
VDD15
VDD15
VDD15
VDD15
VDD15
Pin
F8
F9
F10
F11
G33
G34
H1
H2
H3
H4
H5
H6
H7
H28
H29
H30
H31
H32
H33
H34
J1
J2
J3
J4
J5
J6
J7
J28
J29
J30
J31
J32
J33
J34
K1
K2
K6
K7
K28
K29
K33
K34
L1
L2
Signal Name
LINERXDATA[29]
LINERXCLK[24]
LINERXDATA[23]
LINERXCLK[21]
LINETXDATA[5]
LINETXDATA[1]
ADDR[17]
ADDR[12]
ADDR[11]
VSS
ADDR[3]
RWN
VDD33
VDD33
LINETXDATA[9]
LINETXCLK[6]
VDD33
LINETXCLK[2]
LINETXDATA[2]
CHIRXDATA[40]
DATA[0]
ADDR[16]
ADDR[15]
VDD33
ADDR[8]
ADDR[7]
VDD15
VDD15
LINETXCLK[4]
LINETXDATA[4]
VSS
CHIRXDATA[42]
CHIRXDATA[41]
CHIRXDATA[36]
DATA[3]
ADDR[20]
ADDR[10]
VDD15
VDD15
LINETXDATA[3]
CHIRXDATA[37]
CHIRXDATA[33]
DATA[7]
DATA[4]
49
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 2. Pin Assignments for 700-Pin PBGA by Pin Number Order (continued)
Pin
G24
G25
G26
G27
L7
L28
L29
L30
L31
L32
L33
L34
M1
M2
M3
M4
M5
M6
M7
M28
M29
M30
M31
M32
M33
M34
N1
N2
N6
N7
N13
N14
N16
N17
N18
N19
N21
N22
N28
N29
N33
N34
P1
P2
50
Signal Name
VDD15
VDD15
VDD15
VDD33
VDD15
VDD15
LINETXCLK[1]
CHIRXDATA[39]
VDD33
CHIRXDATA[34]
CHIRXDATA[32]
CHIRXDATA[29]
DATA[10]
DATA[8]
DATA[6]
VDD33
DATA[1]
ADDR[19]
VDD15
VDD15
CHIRXDATA[38]
CHIRXDATA[35]
VSS
CHIRXDATA[30]
CHIRXDATA[28]
CHIRXDATA[26]
DATA[14]
DATA[12]
DATA[5]
VDD15
VSS
VSS
VDD15
VDD15
VDD15
VDD15
VSS
VSS
VDD15
CHIRXDATA[31]
CHIRXDATA[24]
CHIRXDATA[22]
DTN
PAR[0]
Pin
L3
L4
L5
L6
P13
P14
P16
P17
P18
P19
P21
P22
P28
P29
P30
P31
P32
P33
P34
R1
R2
R3
R4
R5
R6
R7
R28
R29
R30
R31
R32
R33
R34
T1
T2
T6
T7
T13
T14
T16
T17
T18
T19
T21
Signal Name
DATA[2]
VSS
ADDR[18]
ADDR[13]
VSS
VSS
VDD15
VDD15
VDD15
VDD15
VSS
VSS
VDD15
CHIRXDATA[27]
CHIRXDATA[25]
VDD33
CHIRXDATA[23]
CHIRXDATA[20]
CHIRXDATA[18]
DS2AISCLK
APS_INTN
HP_INTN
VDD33
PAR[1]
DATA[15]
VDD15
VDD15
CHIRXDATA[21]
CHIRXDATA[19]
VSS
CHIRXDATA[17]
CHIRXDATA[15]
CHIRXDATA[14]
DS3NEGDATAIN[1]
DS3POSDATAIN[1]
LP_INTN
VDD15
VDD15
VDD15
VSS
VSS
VSS
VSS
VDD15
Agere Systems Inc.
Advance Data Sheet, Rev. 2
July 2001
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
3 Pin Information (continued)
Table 2. Pin Assignments for 700-Pin PBGA by Pin Number Order (continued)
Pin
P3
P4
P5
P6
P7
U1
U2
U3
U4
U5
U6
U7
U13
U14
U16
U17
U18
U19
U21
U22
U28
U29
U30
U31
U32
U33
U34
V1
V2
V3
V4
V5
V6
V7
V13
V14
V16
V17
V18
V19
V21
V22
Agere Systems Inc.
Signal Name
DATA[13]
VSS
DATA[11]
DATA[9]
VDD15
VSS
DS3NEGDATAIN[2]
DS3POSDATAIN[2]
VSS
DS3DATAINCLK[1]
E2AISCLK
VDD33
VDD15
VDD15
VSS
VSS
VSS
VSS
VDD15
VDD15
VDD33
CHIRXDATA[13]
CHIRXDATA[10]
VDD33
CHIRXDATA[9]
CHIRXDATA[8]
VSS
VSS
DS3DATAINCLK[2]
DS3POSDATAIN[3]
VDD33
DS3NEGDATAIN[3]
DS3NEGDATAIN[4]
VDD33
VDD15
VDD15
VSS
VSS
VSS
VSS
VDD15
VDD15
Pin
T22
T28
T29
T33
T34
V28
V29
V30
V31
V32
V33
V34
W1
W2
W6
W7
W13
W14
W16
W17
W18
W19
W21
W22
W28
W29
W33
W34
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Signal Name
VDD15
VDD15
CHIRXDATA[16]
CHIRXDATA[12]
CHIRXDATA[11]
VDD33
CHIRXDATA[2]
CHIRXDATA[5]
VSS
CHIRXDATA[6]
CHIRXDATA[7]
VSS
DS3DATAINCLK[3]
DS3DATAINCLK[4]
DS3POSDATAIN[4]
VDD15
VDD15
VDD15
VSS
VSS
VSS
VSS
VDD15
VDD15
VDD15
CHIRXGCLK
CHIRXDATA[3]
CHIRXDATA[4]
DS3NEGDATAIN[5]
DS3POSDATAIN[5]
DS3DATAINCLK[5]
VSS
DS3DATAINCLK[6]
DS3DATAOUTCLK[1]
VDD15
VDD15
CHITXDATA[41]
CHITXGCLK
VDD33
CHIRXGTCLK
CHIRXGFS
CHIRXDATA[1]
51
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 3. Pin Assignments for 700-Pin PBGA by Signal Name Order
52
Signal Name
Pin
Signal Name
Pin
ADDR[0]
ADDR[1]
ADDR[2]
ADDR[3]
ADDR[4]
ADDR[5]
ADDR[6]
ADDR[7]
ADDR[8]
ADDR[9]
ADDR[10]
ADDR[11]
ADDR[12]
ADDR[13]
ADDR[14]
ADDR[15]
ADDR[16]
ADDR[17]
ADDR[18]
ADDR[19]
ADDR[20]
ADSN
APS_INTN
BYPASS
CG_PLLCLKOUT
CHIRXDATA[1]
CHIRXDATA[2]
CHIRXDATA[3]
CHIRXDATA[4]
CHIRXDATA[5]
CHIRXDATA[6]
CHIRXDATA[7]
CHIRXDATA[8]
CHIRXDATA[9]
CHIRXDATA[10]
CHIRXDATA[11]
CHIRXDATA[12]
CHIRXDATA[13]
CHIRXDATA[14]
CHIRXDATA[15]
CHIRXDATA[16]
CHIRXDATA[17]
CHIRXDATA[18]
CHIRXDATA[19]
E2
F3
D1
H5
F2
E1
G2
J6
J5
F1
K6
H3
H2
L6
G1
J3
J2
H1
L5
M6
K2
D2
R2
AJ15
AL33
Y34
V29
W33
W34
V30
V32
V33
U33
U32
U30
T34
T33
U29
R34
R33
T29
R32
P34
R30
CHIRXDATA[20]
CHIRXDATA[21]
CHIRXDATA[22]
CHIRXDATA[23]
CHIRXDATA[24]
CHIRXDATA[25]
CHIRXDATA[26]
CHIRXDATA[27]
CHIRXDATA[28]
CHIRXDATA[29]
CHIRXDATA[30]
CHIRXDATA[31]
CHIRXDATA[32]
CHIRXDATA[33]
CHIRXDATA[34]
CHIRXDATA[35]
CHIRXDATA[36]
CHIRXDATA[37]
CHIRXDATA[38]
CHIRXDATA[39]
CHIRXDATA[40]
CHIRXDATA[41]
CHIRXDATA[42]
CHIRXGCLK
CHIRXGFS
CHIRXGTCLK
CHITXDATA[1]
CHITXDATA[2]
CHITXDATA[3]
CHITXDATA[4]
CHITXDATA[5]
CHITXDATA[6]
CHITXDATA[7]
CHITXDATA[8]
CHITXDATA[9]
CHITXDATA[10]
CHITXDATA[11]
CHITXDATA[12]
CHITXDATA[13]
CHITXDATA[14]
CHITXDATA[15]
CHITXDATA[16]
CHITXDATA[17]
CHITXDATA[18]
P33
R29
N34
P32
N33
P30
M34
P29
M33
L34
M32
N29
L33
K34
L32
M30
J34
K33
M29
L30
H34
J33
J32
W29
Y33
Y32
AJ27
AN31
AP32
AK29
AJ29
AJ30
AM34
AG30
AJ33
AK34
AH33
AF29
AF30
AJ34
AE29
AG32
AG33
AD29
Agere Systems Inc.
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 3. Pin Assignments for 700-Pin PBGA by Signal Name Order (continued)
Signal Name
Pin
Signal Name
Pin
CHITXDATA[19]
CHITXDATA[20]
CHITXDATA[21]
CHITXDATA[22]
CHITXDATA[23]
CHITXDATA[24]
CHITXDATA[25]
CHITXDATA[26]
CHITXDATA[27]
CHITXDATA[28]
CHITXDATA[29]
CHITXDATA[30]
CHITXDATA[31]
CHITXDATA[32]
CHITXDATA[33]
CHITXDATA[34]
CHITXDATA[35]
CHITXDATA[36]
CHITXDATA[37]
CHITXDATA[38]
CHITXDATA[39]
CHITXDATA[40]
CHITXDATA[41]
CHITXDATA[42]
CHITXGCLK
CHITXGFS
CLKIN_PLL
CSN
CTAPRH
CTAPRL
CTAPRP
CTAPTH
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
DATA[8]
DATA[9]
DATA[10]
DATA[11]
AH34
AF32
AF33
AG34
AD30
AC29
AE33
AF34
AC30
AD32
AE34
AD33
AB29
AC32
AD34
AC33
AA29
AC34
AA30
AB33
AA32
AB34
Y29
AA33
Y30
AA34
AJ32
C1
AK8
AJ13
AK9
AJ9
J1
M5
L3
K1
L2
N6
M3
L1
M2
P6
M1
P5
DATA[12]
DATA[13]
DATA[14]
DATA[15]
DS1XCLK
DS2AISCLK
DS3DATAINCLK[1]
DS3DATAINCLK[2]
DS3DATAINCLK[3]
DS3DATAINCLK[4]
DS3DATAINCLK[5]
DS3DATAINCLK[6]
DS3DATAOUTCLK[1]
DS3DATAOUTCLK[2]
DS3DATAOUTCLK[3]
DS3DATAOUTCLK[4]
DS3DATAOUTCLK[5]
DS3DATAOUTCLK[6]
DS3NEGDATAIN[1]
DS3NEGDATAIN[2]
DS3NEGDATAIN[3]
DS3NEGDATAIN[4]
DS3NEGDATAIN[5]
DS3NEGDATAIN[6]
DS3NEGDATAOUT[1]
DS3NEGDATAOUT[2]
DS3NEGDATAOUT[3]
DS3NEGDATAOUT[4]
DS3NEGDATAOUT[5]
DS3NEGDATAOUT[6]
DS3POSDATAIN[1]
DS3POSDATAIN[2]
DS3POSDATAIN[3]
DS3POSDATAIN[4]
DS3POSDATAIN[5]
DS3POSDATAIN[6]
DS3POSDATAOUT[1]
DS3POSDATAOUT[2]
DS3POSDATAOUT[3]
DS3POSDATAOUT[4]
DS3POSDATAOUT[5]
DS3POSDATAOUT[6]
DS3RXCLKOUT[1]
DS3RXCLKOUT[2]
N2
P3
N1
R6
AK20
R1
U5
V2
W1
W2
Y3
Y5
Y6
AC2
AC3
AD3
AG1
AD6
T1
U2
V5
V6
Y1
AA2
AB1
AA6
AD2
AF1
AC6
AF3
T2
U3
V3
W6
Y2
AA1
AB2
AA5
AD1
AE1
AD5
AF2
AA3
AC1
Agere Systems Inc.
53
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 3. Pin Assignments for 700-Pin PBGA by Signal Name Order (continued)
54
Signal Name
Pin
Signal Name
Pin
DS3RXCLKOUT[3]
DS3RXCLKOUT[4]
DS3RXCLKOUT[5]
DS3RXCLKOUT[6]
DS3XCLK
DSN
DTN
E1XCLK
E2AISCLK
E3XCLK
ECSEL
ETOGGLE
EXDNUP
HP_INTN
IC3STATEN
IDDQ
LINERXCLK[1]
LINERXCLK[2]
LINERXCLK[3]
LINERXCLK[4]
LINERXCLK[5]
LINERXCLK[6]
LINERXCLK[7]
LINERXCLK[8]
LINERXCLK[9]
LINERXCLK[10]
LINERXCLK[11]
LINERXCLK[12]
LINERXCLK[13]
LINERXCLK[14]
LINERXCLK[15]
LINERXCLK[16]
LINERXCLK[17]
LINERXCLK[18]
LINERXCLK[19]
LINERXCLK[20]
LINERXCLK[21]
LINERXCLK[22]
LINERXCLK[23]
LINERXCLK[24]
LINERXCLK[25]
LINERXCLK[26]
LINERXCLK[27]
AB6
AC5
AE2
AH1
A21
E3
P1
AP21
U6
F18
AM15
AJ16
AL17
R3
AP24
AM24
A19
C18
B17
E17
B16
A15
F16
A14
B14
A13
B13
A12
B12
C12
B11
C11
A9
F12
A8
C9
F11
C8
A6
F9
A5
E8
C6
LINERXCLK[29]
LINERXCLK[30]
LINERXDATA[1]
LINERXDATA[2]
LINERXDATA[3]
LINERXDATA[4]
LINERXDATA[5]
LINERXDATA[6]
LINERXDATA[7]
LINERXDATA[8]
LINERXDATA[9]
LINERXDATA[10]
LINERXDATA[11]
LINERXDATA[12]
LINERXDATA[13]
LINERXDATA[14]
LINERXDATA[15]
LINERXDATA[16]
LINERXDATA[17]
LINERXDATA[18]
LINERXDATA[19]
LINERXDATA[20]
LINERXDATA[21]
LINERXDATA[22]
LINERXDATA[23]
LINERXDATA[24]
LINERXDATA[25]
LINERXDATA[26]
LINERXDATA[27]
LINERXDATA[28]
LINERXDATA[29]
LINERXDATA[30]
LINETXCLK[1]
LINETXCLK[2]
LINETXCLK[3]
LINETXCLK[4]
LINETXCLK[5]
LINETXCLK[6]
LINETXCLK[7]
LINETXCLK[8]
LINETXCLK[9]
LINETXCLK[10]
LINETXCLK[11]
B4
E6
B19
E18
B18
C17
A16
F17
B15
C15
E15
F15
C14
E14
F14
A11
F13
A10
E12
B10
E11
B9
A7
B8
F10
E9
B7
B6
A4
B5
F8
A3
L29
H32
F34
J29
E34
H30
F32
E32
D33
F30
F29
Agere Systems Inc.
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 3. Pin Assignments for 700-Pin PBGA by Signal Name Order (continued)
Signal Name
Pin
Signal Name
Pin
LINERXCLK[28]
LINETXCLK[13]
LINETXCLK[14]
LINETXCLK[15]
LINETXCLK[16]
LINETXCLK[17]
LINETXCLK[18]
LINETXCLK[19]
LINETXCLK[20]
LINETXCLK[21]
LINETXCLK[22]
LINETXCLK[23]
LINETXCLK[24]
LINETXCLK[25]
LINETXCLK[26]
LINETXCLK[27]
LINETXCLK[28]
LINETXCLK[29]
LINETXCLK[30]
LINETXDATA[1]
LINETXDATA[2]
LINETXDATA[3]
LINETXDATA[4]
LINETXDATA[5]
LINETXDATA[6]
LINETXDATA[7]
LINETXDATA[8]
LINETXDATA[9]
LINETXDATA[10]
LINETXDATA[11]
LINETXDATA[12]
LINETXDATA[13]
LINETXDATA[14]
LINETXDATA[15]
LINETXDATA[16]
LINETXDATA[17]
LINETXDATA[18]
LINETXDATA[19]
LINETXDATA[20]
LINETXDATA[21]
LINETXDATA[22]
LINETXDATA[23]
LINETXDATA[24]
LINETXDATA[25]
C5
F27
B30
A31
B29
B28
E26
F25
B27
A28
B26
E24
B25
E23
A25
F22
A24
F21
E21
G34
H33
K29
J30
G33
F33
D34
E33
H29
C34
E30
E29
B31
C30
C29
E27
A30
F26
A29
C27
F24
C26
A27
F23
A26
LINETXCLK[12]
LINETXDATA[27]
LINETXDATA[28]
LINETXDATA[29]
LINETXDATA[30]
LOPOHCLKIN
LOPOHCLKOUT
LOPOHDATAIN
LOPOHDATAOUT
LOPOHVALIDIN
LOPOHVALIDOUT
LOSEXT
LP_INTN
MODE0_PLL
MODE1_PLL
MODE2_PLL
MPCLK
MPMODE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NSMIRXCLK[1]
NSMIRXCLK[2]
NSMIRXCLK[3]
NSMIRXDATA[1]
NSMIRXDATA[2]
NSMIRXDATA[3]
NSMIRXSYNC[1]
NSMIRXSYNC[2]
NSMIRXSYNC[3]
NSMITXCLK[1]
NSMITXCLK[2]
NSMITXCLK[3]
NSMITXDATA[1]
NSMITXDATA[2]
NSMITXDATA[3]
NSMITXSYNC[1]
NSMITXSYNC[2]
A32
B24
C23
B23
A23
B22
F20
C21
B21
A22
E20
AN21
T6
AG29
AK32
AK30
F5
F6
AK2
AK3
AG6
AL2
AM1
AJ5
AK5
AK30
E5
AP26
AP27
AJ24
AK23
AK24
AP28
AN25
AN26
AN27
AP29
AP30
AM29
AJ25
AN28
AP31
AK26
AN29
Agere Systems Inc.
55
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 3. Pin Assignments for 700-Pin PBGA by Signal Name Order (continued)
56
Signal Name
Pin
Signal Name
Pin
LINETXDATA[26]
PAR[0]
PAR[1]
PHASEDETDOWN[1]
PHASEDETDOWN[2]
PHASEDETDOWN[3]
PHASEDETDOWN[4]
PHASEDETDOWN[5]
PHASEDETDOWN[6]
PHASEDETUP[1]
PHASEDETUP[2]
PHASEDETUP[3]
PHASEDETUP[4]
PHASEDETUP[5]
PHASEDETUP[6]
PMRST
REF10
REF14
RESHI
RESLO
RHSCN
RHSCP
RHSDN
RHSDP
RHSFSYNCN
RLSCLK
RLSDATAN[1]
RLSDATAN[2]
RLSDATAN[3]
RLSDATAP[1]
RLSDATAP[2]
RLSDATAP[3]
RPOACCLK
RPOACDATA
RPOACSYNC
RPSCN
RPSCP
RPSDN
RPSDP
RSTN
RTOACCLK
RTOACDATA
RTOACSYNC
C24
P2
R5
AG3
AG5
AF6
AK1
AJ1
AJ3
AG2
AE6
AF5
AH2
AJ2
AL1
AM21
AJ6
AK6
AP3
AJ8
AN5
AN4
AM6
AM5
AJ20
AK15
AP14
AP16
AP18
AP13
AP15
AP17
AN19
AJ18
AP20
AN11
AN10
AM9
AM8
AP22
AM17
AJ17
AM18
NSMITXSYNC[3]
RXDATAEN[2]
RXDATAEN[3]
SCAN_EN
SCANMODE
SCK1
SCK2
TCK
TDI
TDO
THSCN
THSCON
THSCOP
THSCP
THSDN
THSDP
THSSYNC
TLSCLK
TLSDATAN[1]
TLSDATAN[2]
TLSDATAN[3]
TLSDATAP[1]
TLSDATAP[2]
TLSDATAP[3]
TMS
TPOACCLK
TPOACDATA
TPOACSYNC
TPSCN
TPSCP
TPSDN
TPSDP
TRSTN
TSTMODE
TSTPHASE
TSTSFTLD
TTOACCLK
TTOACDATA
TTOACSYNC
TXDATAEN[1]
TXDATAEN[2]
TXDATAEN[3]
VDD15
AN30
AM26
AM27
AN24
AP25
AM23
AJ22
AN22
AK21
AN23
AP7
AP5
AP4
AP6
AN8
AN7
AL15
AL14
AN14
AN16
AN18
AN13
AN15
AN17
AP23
AN20
AJ19
AM20
AP9
AP8
AP11
AP10
AJ21
AK17
AJ14
AM14
AL18
AP19
AK18
AJ26
AK27
AM30
AA16
Agere Systems Inc.
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 3. Pin Assignments for 700-Pin PBGA by Signal Name Order (continued)
Signal Name
Pin
Signal Name
Pin
RWN
RXDATAEN[1]
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
H6
AJ23
AA19
AA28
AA7
AB16
AB17
AB18
AB19
AB28
AB7
AC28
AC7
AD28
AD7
AE28
AE7
AF28
AF7
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH9
G10
G11
G12
G13
G14
G15
G16
G19
G20
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
AA17
AA18
G23
G24
G25
G26
G9
J28
J7
K28
K7
L28
L7
M28
M7
N16
N17
N18
N19
N28
N7
P16
P17
P18
P19
P28
P7
R28
R7
T13
T14
T21
T22
T28
T7
U13
U14
U21
U22
V13
V14
V21
V22
W13
Agere Systems Inc.
57
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 3. Pin Assignments for 700-Pin PBGA by Signal Name Order (continued)
58
Signal Name
Pin
Signal Name
Pin
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15A_CDR1
VDD15A_CDR2
VDD15A_DS3PLL
VDD15A_E3PLL
VDD15A_X4PLL
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
G21
G22
W28
W7
Y28
Y7
W22
AK11
AJ10
C20
B20
AK14
A2
A33
AA4
AC31
AD4
AF31
AG28
AG4
AG7
AH17
AH18
AH27
AH8
AJ31
AK4
AL12
AL21
AL24
AL27
AL30
AL6
AL9
AM2
AM33
AN1
AN3
AN32
AN34
AP2
AP33
B1
VDD15
VDD15
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33A_SFPLL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
W14
W21
C2
C33
D11
D14
D17
D20
D23
D26
D29
D5
D8
E31
F4
G17
G18
G27
G8
H28
H31
H7
J4
L31
M4
P31
R4
U28
U31
U7
V28
V4
V7
Y31
AK33
A1
A17
A18
A34
AA13
AA14
AA21
AA22
Agere Systems Inc.
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 3. Pin Assignments for 700-Pin PBGA by Signal Name Order (continued)
Signal Name
Pin
Signal Name
Pin
VDD33
VDD33
VDD33
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B3
B32
B34
AB21
AB22
AC4
AD31
AF4
AG31
AJ4
AK31
AL11
AL20
AL23
AL26
AL29
AL5
AL8
AM11
AM12
AM3
AM32
AN12
AN2
AN33
AN6
AN9
AP1
AP12
AP34
B2
B33
C3
C32
D12
D15
D18
D21
D24
D27
D30
D6
D9
E4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA_CDR1
VSSA_CDR2
VSSA_DS3PLL
VSSA_E3PLL
VSSA_SFPLL
AA31
AB13
AB14
J31
L4
M31
N13
N14
N21
N22
P13
P14
P21
P22
P4
R31
T16
T17
T18
T19
U1
U16
U17
U18
U19
U34
U4
V1
V16
V17
V18
V19
V31
V34
W16
W17
W18
W19
Y4
AK12
AJ12
F19
A20
AL34
Agere Systems Inc.
59
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
3 Pin Information (continued)
Table 3. Pin Assignments for 700-Pin PBGA by Signal Name Order (continued)
60
Signal Name
Pin
Signal Name
Pin
VSS
VSS
F31
H4
VSSA_X4PLL
—
AJ11
—
Agere Systems Inc.
Advance Data Sheet, Rev. 2
July 2001
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Notes
Agere Systems Inc.
61
For additional information, contact your Agere Systems Account Manager or the following:
http://www.agere.com
INTERNET:
[email protected]
E-MAIL:
N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256
Tel. (65) 778 8833, FAX (65) 777 7495
CHINA:
Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC
Tel. (86) 21 50471212, FAX (86) 21 50472266
JAPAN:
Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
EUROPE:
Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148
Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),
FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki),
ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. ORCA is
a registered trademark of Agere Systems Inc. Foundry is a trademark of Xilinx, Inc.
Copyright © 2001 Agere Systems Inc.
All Rights Reserved
Printed in U.S.A.
July 2001
DS01-245BBAC (Replaces DS01-207BBAC)