TI CD74AC257E

CD74AC257, CD74ACT257,
CD74ACT258
Data sheet acquired from Harris Semiconductor
SCHS248
Quad 2-Input Multiplexer
with Three-State Outputs
August 1998
Features
Description
• CD74AC257, CD74ACT257 . . . . Non-Inverting Outputs
The CD74AC257, CD74ACT257 and CD74ACT258 are
quad 2-input multiplexers with three-state outputs that utilize
the Harris Advanced CMOS Logic technology. Each of these
devices selects four bits of data from two sources under the
control of a common Select input (S). The Output Enable
(OE) is active LOW. When OE is HIGH, all of the outputs (Y
or Y) are in the high-impedance state regardless of all other
input conditions.
• CD74ACT258 . . . . . . . . . . . . . . . . . . . Inverting Outputs
• Buffered Inputs
• Typical Propagation Delay
- 4.4ns at VCC = 5V, TA = 25oC, CL = 50pF
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
Moving data from two groups of registers to four common
output buses is a common use of the CD74AC257,
CD74ACT257 and CD74ACT258. The state of the Select
input determines the particular register from which the data
comes. The CD74AC257, CD74ACT257 and CD74ACT258
can also be used as function generators.
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
• Balanced Propagation Delays
Ordering Information
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
PART
NUMBER
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
CD74AC257, CD74ACT257, CD74ACT258
(PDIP, SOIC)
0 to 70oC, -40 to 85, 16 Ld PDIP
-55 to 125
E16.3
CD74ACT257E
0 to 70oC, -40 to 85, 16 Ld PDIP
-55 to 125
E16.3
CD74ACT258E
0 to 70oC, -40 to 85, 16 Ld PDIP
-55 to 125
E16.3
CD74AC257M
0 to 70oC, -40 to 85, 16 Ld SOIC
-55 to 125
M16.15
CD74ACT257M
0 to 70oC, -40 to 85, 16 Ld SOIC
-55 to 125
M16.15
CD74ACT258M
0 to 70oC, -40 to 85, 16 Ld SOIC
-55 to 125
M16.15
TOP VIEW
ACT258
S
AC/ACT257
S 1
AC/ACT257
16 VCC
ACT258
VCC
1I0
1I0 2
15 OE
OE
1I1
1I1 3
14 4I0
4I0
1Y
1Y 4
13 4I1
4I1
2I0
2I0 5
12 4Y
4Y
2I1
2I1 6
11 3I0
3I0
2Y
2Y 7
10 3I1
3I1
GND
GND 8
9 3Y
3Y
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris
customer service for ordering information.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © Harris Corporation 1998
PKG.
NO.
PACKAGE
CD74AC257E
Drives 50Ω Transmission Lines
Pinout
TEMP.
RANGE (oC)
1
File Number
1955.1
CD74AC257, CD74ACT257, CD74ACT258
Functional Diagram
AC/ACT AC/ACT
257
258
1I0
2I0
3I0
4I0
1I1
2I1
3I1
4I1
2
4
5
1Y
1Y
2Y
2Y
3Y
3Y
4Y
4Y
11
7
14
3
9
6
10
12
13
1
15
S
OE
TRUTH TABLE
OUTPUT
ENABLE
SELECT
INPUT
257
OUTPUTS
258
OUTPUTS
OE
S
I0
I1
Y
Y
H
X
X
X
Z
Z
L
L
L
X
L
H
L
L
H
X
H
L
L
H
X
L
L
H
L
H
X
H
H
L
DATA INPUTS
H = High level voltage, L = Low level voltage, Z = High impedance (off) state, X = Don’t Care
2
CD74AC257, CD74ACT257, CD74ACT258
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA
Thermal Resistance (Typical, Note 5)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
___
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
___
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC (Note 4)
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
-40oC TO
85oC
25oC
-55oC TO
125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
VIH
-
-
1.5
1.2
-
1.2
-
1.2
-
V
3
2.1
-
2.1
-
2.1
-
V
AC TYPES
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
VIL
VOH
-
VIH or VIL
5.5
3.85
-
3.85
-
3.85
-
V
1.5
-
0.3
-
0.3
-
0.3
V
3
-
0.9
-
0.9
-
0.9
V
5.5
-
1.65
-
1.65
-
1.65
V
-0.05
1.5
1.4
-
1.4
-
1.4
-
V
-0.05
3
2.9
-
2.9
-
2.9
-
V
-0.05
4.5
4.4
-
4.4
-
4.4
-
V
-4
3
2.58
-
2.48
-
2.4
-
V
-24
4.5
3.94
-
3.8
-
3.7
-
V
-75
(Note 6, 7)
5.5
-
-
3.85
-
-
-
V
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
-
3
CD74AC257, CD74ACT257, CD74ACT258
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
Low Level Output Voltage
-40oC TO
85oC
25oC
-55oC TO
125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
VOL
VIH or VIL
0.05
1.5
-
0.1
-
0.1
-
0.1
V
0.05
3
-
0.1
-
0.1
-
0.1
V
0.05
4.5
-
0.1
-
0.1
-
0.1
V
12
3
-
0.36
-
0.44
-
0.5
V
24
4.5
-
0.36
-
0.44
-
0.5
V
75
(Note 6, 7)
5.5
-
-
-
1.65
-
-
V
50
(Note 6, 7)
5.5
-
-
-
-
-
1.65
V
Input Leakage Current
II
VCC or
GND
-
5.5
-
±0.1
-
±1
-
±1
µA
Three-State Leakage
Current
IOZ
VIH or VIL
VO = VCC
or GND
-
5.5
-
±0.5
-
±5
-
±10
µA
Quiescent Supply Current
MSI
ICC
VCC or
GND
0
5.5
-
8
-
80
-
160
µA
High Level Input Voltage
VIH
-
-
4.5 to
5.5
2
-
2
-
2
-
V
Low Level Input Voltage
VIL
-
-
4.5 to
5.5
-
0.8
-
0.8
-
0.8
V
High Level Output Voltage
VOH
VIH or VIL
-0.05
4.5
4.4
-
4.4
-
4.4
-
V
-24
4.5
3.94
-
3.8
-
3.7
-
V
-75
(Note 6, 7)
5.5
-
-
3.85
-
-
-
V
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
ACT TYPES
Low Level Output Voltage
VOL
VIH or VIL
0.05
4.5
-
0.1
-
0.1
-
0.1
V
24
4.5
-
0.36
-
0.44
-
0.5
V
75
(Note 6, 7)
5.5
-
-
-
1.65
-
-
V
50
(Note 6, 7)
5.5
-
-
-
-
-
1.65
V
II
VCC or
GND
-
5.5
-
±0.1
-
±1
-
±1
µA
Three-State or Leakage
Current
IOZ
VIH or VIL
VO = VCC
or GND
-
5.5
-
±0.5
-
±5
-
±10
µA
Quiescent Supply Current
MSI
ICC
VCC or
GND
0
5.5
-
8
-
80
-
160
µA
∆ICC
VCC
-2.1
-
4.5 to
5.5
-
2.4
-
2.8
-
3
mA
Input Leakage Current
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC.
4
CD74AC257, CD74ACT257, CD74ACT258
ACT Input Load Table
INPUT
UNIT LOAD
Data
0.83
S
1.27
OE
1.27
NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.
Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case)
-40oC TO 85oC
PARAMETER
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
tPLH, tPHL
1.5
-
-
106
-
-
117
ns
3.3
(Note 9)
3.3
-
11.8
3.3
-
13
ns
5
(Note 10)
2.4
-
8.5
2.3
-
9.3
ns
1.5
-
-
153
-
-
168
ns
3.3
4.8
-
17.1
4.7
-
18.8
ns
5
3.5
-
12.2
3.4
-
13.4
ns
1.5
-
-
167
-
-
184
ns
3.3
5.3
-
18.7
5.2
-
20.6
ns
5
3.8
-
13.4
3.7
-
14.7
ns
1.5
-
-
91
-
-
100
ns
3.3
2.9
-
10.2
2.8
-
11.2
ns
5
2.1
-
7.3
2
-
8
ns
1.5
-
-
153
-
-
168
ns
3.3
4.8
-
17.1
4.7
-
18.8
ns
5
3.5
-
12.2
3.4
-
13.4
ns
1.5
-
-
167
-
-
184
ns
3.3
5.3
-
18.7
5.2
-
20.6
ns
5
3.8
-
13.4
3.7
-
14.7
ns
AC TYPES
Propagation Delay,
In to Y
CD74AC/ACT257
Propagation Delay,
S to Y
CD74AC/ACT257
Propagation Delay,
OE to Y
CD74AC/ACT257
Propagation Delay,
In to Y
CD74AC/ACT258
Propagation Delay,
S to Y
CD74AC/ACT258
Propagation Delay,
OE to Y
CD74AC/ACT258
tPLH, tPHL
tPLZ, tPHZ,
tPZL, tPZH
tPLH, tPHL
tPLH, tPHL
tPLZ, tPHZ,
tPZL, tPZH
Three-State Output
Capacitance
CO
-
-
-
15
-
-
15
pF
Input Capacitance
CI
-
-
-
10
-
-
10
pF
CPD
(Note 11)
-
-
130
-
-
130
-
pF
Propagation Delay,
In to Y
CD74AC/ACT257
tPLH, tPHL
5
(Note 10)
2.8
-
9.7
2.7
-
10.7
ns
Propagation Delay,
S to Y
CD74AC/ACT257
tPLH, tPHL
5
4
-
14
3.9
-
15.4
ns
Power Dissipation Capacitance
ACT TYPES
5
CD74AC257, CD74ACT257, CD74ACT258
Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case)
(Continued)
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Propagation Delay,
OE to Y
CD74AC/ACT257
tPLZ, tPHZ,
tPZL, tPZH
5
4.1
-
14.6
4
-
16.1
ns
Propagation Delay,
In to Y
CD74AC/ACT258
tPLH, tPHL
5
2.4
-
8.5
2.3
-
9.3
ns
Propagation Delay,
S to Y
CD74AC/ACT258
tPLH, tPHL
5
4
-
14
3.9
-
15.4
ns
Propagation Delay,
OE to Y
CD74AC/ACT258
tPLZ, tPHZ,
tPZL, tPZH
5
4.1
-
14.6
4
-
16.1
ns
Three-State Output
Capacitance
CO
-
-
-
15
-
-
15
pF
Input Capacitance
CI
-
-
-
10
-
-
10
pF
CPD
(Note 11)
-
-
130
-
-
130
-
pF
PARAMETER
Power Dissipation Capacitance
NOTES:
8. Limits tested 100%.
9. 3.3V Min is at 3.6V, Max is at 3V.
10. 5V Min is at 5.5V, Max is at 4.5V.
11. CPD is used to determine the dynamic power consumption per multiplexer.
AC: PD = CPD VCC2 fi + ∑ (CL VCC2 fo)
ACT: PD = CPD VCC2 fi + ∑ (CL VCC2 fo) + VCC ∆ICC where fi = input frequency, fo = output frequency, CL = output load capacitance,
VCC = supply voltage.
tr = 3ns
tf = 3ns
INPUT LEVEL
90%
OUTPUT
DISABLE
VS
10%
GND
tPZL
tPLZ
VS
0.2VCC
OUTPUT: LOW
TO OFF TO LOW
tPHZ
tPZH
0.8 VCC
VS
OUTPUT: HIGH
TO OFF TO HIGH
OUTPUTS
ENABLED
OTHER
INPUTS
(TIED HIGH
OR LOW)
OUTPUT
DISABLE
OUTPUTS
DISABLED
500Ω†
RL
DUT
WITH
THREESTATE
OUTPUT
CL
50pF
VOL (≠GND)
VOH (≠VCC)
OUTPUTS
ENABLED
GND (tPHZ, tPZH)
OPEN (tPHL, tPLH)
2 VCC (tPLZ, tPZL)
(OPEN DRAIN)
OUT
500Ω†
RL
†FOR AC SERIES ONLY: WHEN VCC = 1.5V, RL = 1kΩ
FIGURE 1. THREE-STATE PROPAGATION DELAY TIMES AND TEST CIRCUIT
6
CD74AC257, CD74ACT257, CD74ACT258
tr = 3ns
tf = 3ns
INPUT
LEVEL
nI0, nI1, S
VS
VS
S
10%
tPLH
tPHL
tPLH
INPUT LEVEL
90%
GND
Y
tPHL
VS
VS
Y
FIGURE 2. INPUTS OR SELECT TO OUTPUT PROPAGATION
DELAYS (AC/ACT257)
FIGURE 3. SELECT TO OUTPUT PROPAGATION DELAYS
(ACT258)
OUTPUT
RL (NOTE)
500Ω
DUT
OUTPUT
LOAD
CL
50pF
NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.
CD74AC
CD74ACT
VCC
3V
Input Switching Voltage, VS
0.5 VCC
1.5V
Output Switching Voltage, VS
0.5 VCC
0.5 VCC
Input Level
FIGURE 4. PROPAGATION DELAY TIMES
7
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