CD74AC280, CD74ACT280 Data sheet acquired from Harris Semiconductor SCHS250 9-Bit Odd/Even Parity Generator/Checker August 1998 Features Description • Buffered Inputs The CD74AC280 and CD74ACT280 9-bit odd/even parity generator/checkers that utilize the Harris Advanced CMOS Logic technology. Bothe even and odd parity outputs are available for checking or generating parity for words up to nine bits long. Even parity is indicated (∑Eoutput is HIGH) when an even number of data inputs is HIGH. Odd parity is indicated (∑O output is HIGH) when an odd number of data inputs is HIGH. Parity checking for words larger than nine bits can be accomplished by tying the ∑E output to any input of an additional AC/ACT280 parity checker. • Typical Propagation Delay - 10ns at VCC = 5V, TA = 25oC, CL = 50pF • Exceeds 2kV ESD Protection MIL-STD-883, Method 3015 • SCR-Latchup-Resistant CMOS Process and Circuit Design • Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption Ordering Information • Balanced Propagation Delays • AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply PART NUMBER • ±24mA Output Drive Current - Fanout to 15 FAST™ ICs - Drives 50Ω Transmission Lines PKG. NO. PACKAGE CD74AC280E 0 to 70oC, -40 to 85, 14 Ld PDIP -55 to 125 E14.3 CD74ACT280E 0 to 70oC, -40 to 85, 14 Ld PDIP -55 to 125 E14.3 CD74AC280M 0 to 70oC, -40 to 85, 14 Ld SOIC -55 to 125 M14.15 CD74ACT280M 0 to 70oC, -40 to 85, 14 Ld SOIC -55 to 125 M14.15 Pinout CD74AC280, CD74ACT280 (PDIP, SOIC) TOP VIEW TEMP. RANGE (oC) NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. I6 1 14 VCC I7 2 13 I5 NC 3 12 I4 I8 4 11 I3 ∑E 5 10 I2 ∑O 6 9 I1 GND 7 8 I0 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. Functional Diagram I0 I1 I2 I3 8 9 10 5 11 ∑ EVEN 12 I4 I5 I6 I7 I8 6 13 1 2 4 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST™ is a Trademark of Fairchild Semiconductor. Copyright © Harris Corporation 1998 1 ∑ ODD GND = 7 VCC = 14 NC = 3 File Number 1957.1 CD74AC280, CD74ACT280 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA Thermal Resistance (Typical, Note 5) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___ SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___ Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC (Note 4) AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Slew Rate, dt/dv AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max) AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max) ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. For up to 4 outputs per device, add ±25mA for each additional output. 4. Unless otherwise specified, all voltages are referenced to ground. 5. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN MAX MIN MAX MIN MAX UNITS VIH - - 1.5 1.2 - 1.2 - 1.2 - V AC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIL VOH - VIH or VIL 3 2.1 - 2.1 - 2.1 - V 5.5 3.85 - 3.85 - 3.85 - V 1.5 - 0.3 - 0.3 - 0.3 V 3 - 0.9 - 0.9 - 0.9 V 5.5 - 1.65 - 1.65 - 1.65 V -0.05 1.5 1.4 - 1.4 - 1.4 - V -0.05 3 2.9 - 2.9 - 2.9 - V -0.05 4.5 4.4 - 4.4 - 4.4 - V -4 3 2.58 - 2.48 - 2.4 - V -24 4.5 3.94 - 3.8 - 3.7 - V -75 (Note 6, 7) 5.5 - - 3.85 - - - V -50 (Note 6, 7) 5.5 - - - - 3.85 - V - 2 CD74AC280, CD74ACT280 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Low Level Output Voltage -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN MAX MIN MAX MIN MAX UNITS VOL VIH or VIL 0.05 1.5 - 0.1 - 0.1 - 0.1 V 0.05 3 - 0.1 - 0.1 - 0.1 V 0.05 4.5 - 0.1 - 0.1 - 0.1 V 12 3 - 0.36 - 0.44 - 0.5 V 24 4.5 - 0.36 - 0.44 - 0.5 V 75 (Note 6, 7) 5.5 - - - 1.65 - - V 50 (Note 6, 7) 5.5 - - - - - 1.65 V II VCC or GND - 5.5 - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - 8 - 80 - 160 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - 0.8 - 0.8 - 0.8 V High Level Output Voltage VOH VIH or VIL -0.05 4.5 4.4 - 4.4 - 4.4 - V -24 4.5 3.94 - 3.8 - 3.7 - V -75 (Note 6, 7) 5.5 - - 3.85 - - - V -50 (Note 6, 7) 5.5 - - - - 3.85 - V Input Leakage Current Quiescent Supply Current MSI ACT TYPES Low Level Output Voltage Input Leakage Current Quiescent Supply Current MSI Additional Supply Current per Input Pin TTL Inputs High 1 Unit Load VOL VIH or VIL 0.05 4.5 - 0.1 - 0.1 - 0.1 V 24 4.5 - 0.36 - 0.44 - 0.5 V 75 (Note 6, 7) 5.5 - - - 1.65 - - V 50 (Note 6, 7) 5.5 - - - - - 1.65 V II VCC or GND - 5.5 - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - 8 - 80 - 160 µA ∆ICC VCC -2.1 - 4.5 to 5.5 - 2.4 - 2.8 - 3 mA NOTES: 6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize power dissipation. 7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC. ACT Input Load Table INPUT UNIT LOAD All 1.43 NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications Table, e.g., 2.4mA max at 25oC. 3 CD74AC280, CD74ACT280 Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case) -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX UNITS tPLH, tPHL 1.5 - - 239 - - 263 ns 3.3 (Note 9) 7.5 - 26 7.3 - 29 ns 5 (Note 10) 5.4 - 19.1 5.3 - 21 ns 1.5 - - 227 - - 250 ns 3.3 7.2 - 25 7 - 28 ns 5 5.2 - 18.2 5 - 20 ns CI - - - 10 - - 10 pF CPD (Note 11) - - 115 - - 115 - pF Propagation Delay, Any Input to ∑O tPLH, tPHL 5 (Note 10) 5.6 - 19.6 5.4 - 21.6 ns Propagation Delay, Any Input to ∑E tPLH, tPHL 5 5.6 - 19.6 5.4 - 21.6 ns Input Capacitance CI - - - 10 - - 10 pF CPD (Note 11) - - 115 - - 115 - pF PARAMETER AC TYPES Propagation Delay, Any Input to ∑O Propagation Delay, Any Input to ∑E tPLH, tPHL Input Capacitance Power Dissipation Capacitance ACT TYPES Power Dissipation Capacitance NOTES: 8. Limits tested 100%. 9. 3.3V Min is at 3.6V, Max is at 3V. 10. 5V Min is at 5.5V, Max is at 4.5V. 11. CPD is used to determine the dynamic power consumption per package. AC: PD = VCC2 fi (CPD + CL) ACT: PD = VCC2 fi (CPD + CL) + VCC ∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage. tr = 3ns OUTPUT tf = 3ns RL (NOTE) 500Ω INPUT LEVEL In 0V VS VS 10% DUT 10% tPHL ΣO OUTPUT LOAD tPLH NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ. VS VS CL 50pF 0V tPLH ΣE VS tPHL CD74AC CD74ACT VCC 3V Input Switching Voltage, VS 0.5 VCC 1.5V Output Switching Voltage, VS 0.5 VCC 0.5 VCC Input Level VS 0V FIGURE 1. FIGURE 2. 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