ASAHI KASEI
[AK4516A]
AK4516A
3V 16bit ADC&DAC with built-in PGA
FEATURE
1 . Resolution: 16 bits
2 . Recording Function
• Analog Input PGA (Programmable Gain Amp)
• Peak-Meter Output
• Overflow Flag Output
• Auto Limitter Circuit
• Auto Recovery Circuit
• HPF(fc=3.4Hz) for offset cancel
3 . Playback Function
• Digital De-emphasis Filter(tc=50/15us, fs=32kHz, 44.1kHz, 48kHz)
4 . Analog-Through Mode
5 . Power Management
6 . ADC Input (Including the PGA)
• Single-ended Input
• Input Level: 1.7Vpp (=0.57×VA, VA=3V)
• THD+N: -85dB
• DR,S/N: 90dB
7 . DAC Output
• Single-ended Output
• Output Level: 1.8Vpp (=0.6×VA, VA=3V, RL≥ 10kΩ )
• Frequency Response: ±0.5dB(∼20kHz)
• THD+N: -86dB
• DR,S/N: 90dB
8 . Master Clock: 256fs/384fs
9 . Audio Data Format
• ADC: 16bit, MSB first,
MSB justified, IIS, LSB justified(only BICK=64fs correspondent)
• DAC: 16bit, MSB first,
MSB justified, IIS, MSB justified
10 . Ta: -20∼85°C
11 . Power Supply: 2.5∼3.6V
12 . Power Dissipation: 18mA
13 . 24pinVSOP (0.65mm Pitch)
M0026-E-00
-1-
ASAHI KASEI
[AK4516A]
M0026-E-00
1998/08
-2-
ASAHI KASEI
[AK4516A]
Ordering Guide
AK4516AVF
AKD4516A
-20∼ +85°C
Evaluation Board
24pin VSOP(0.65mm Pitch)
Pin Layout
M0026-E-00
1998/08
-3-
ASAHI KASEI
[AK4516A]
PIN/FUNCTION
No.
Pin Name
AGND
VA
RIN1
LIN1
RIN2
LIN2
I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
CCLK
CDTO
CDTI
DZF
LOUT
ROUT
VCML
I
I
I
I
I
I
I
I
O
I
I
I
O
I
O
O
O
O
23
VCMR
O
24
VCOM
O
PD
MCLK
LRCK
BCLK
SDTO
SDTI
DGND
VD
CS
Function
Analog Ground pin
Analog Power Supply Pin, +3V
Rch #1 input pin
Lch #1 input pin
Rch #2 input pin
Lch #2 input pin
Reset & Power down Pin
Master Clock Input Pin
Input/Output Channel Clock Pin
Audio Serial Data Clock Pin
Audio Serial Data Output Pin
Audio Serial Data Input Pin
Digital Ground Pin
Digital Power Supply Pin, +3V
Chip Select Pin
Control Clock Input Pin
Control Data Output Pin
Control Data Input Pin
Zero Detect Pin
Lch analog output pin
Rch analog output pin
Lch Common Voltage Output Pin, 0.5 x VA
Don't be connected with external circuit.
Rch Common Voltage Output Pin, 0.5 x VA
Don't be connected with external circuit.
Common Voltage Output Pin, 0.5 x VA
Don't be connected with external circuit.
M0026-E-00
1998/08
-4-
ASAHI KASEI
[AK4516A]
ABSOLUTE MAXIMUM RATING
(AGND,DGND=0V; Note 1 )
Parameter
Power Supplies: Analog
Digital
VD-VA
Input Current (Any pin except supplies.)
Analog Input Voltage
LIN1,LIN2,RIN1,RIN2
Digital Input Voltage
Ambient Temperature
Storage Temperature
Symbol
min
max
Units
VA
VD
∆ VDA
IIN
VINA
-0.3
-0.3
-0.3
6.0
6.0
0.3
±10
VA+0.3
V
V
V
mA
V
VIND
Ta
Tstg
-0.3
-20
-65
VA+0.3
85
150
V
°C
°C
Note 1 . All Voltage with respect to ground.
RECOMMENDED OPERATING CONDITIONS
(AGND,DGND=0V; Note1 )
Parameter
Power Supplies
Note
Analog
Digital
Symbol
min
typ
max
Units
VA
VD
2.5
2.5
3.0
3.0
3.6
VA
V
V
1 . All Voltage with respect to ground
M0026-E-00
1998/08
-5-
ASAHI KASEI
[AK4516A]
ANALOG CHARACTERISTICS
(Ta=25°C ; VA,VD=3.0V; fs=44.1kHz; Signal Frequency=1kHz; Measurement Frequency=10Hz ∼ 20kHz ;
S/(N+D), DR, S/N are specification toward full scale.signal; Unless otherwise specified)
Parameter
min
typ
max
units
1.53
25
1.7
40
1.87
60
Vpp
kΩ
0.1
0.1
0.1
0.1
0.5
1
2
4
Input PGA(IPGA) Characteristics:
Input Voltage(LIN1,LIN2,RIN1,RIN2=0.57xVA)(Note2 )
Input Resistance
Step Size
MIC
LINE
+8.0dB∼ -28dB
+28dB∼ -8dB
-8dB∼ -32dB
-28dB∼ -52dB
-32dB∼ -40dB
-52dB∼ -60dB
-40dB∼ -52dB
-60dB∼ -72dB
dB
dB
dB
dB
ADC Analog Input Characteristics : (Note 3 )
Resolution
S/(N+D)
(-2dB Input)
DR (-60dB Input, A-Weighted)
S/N
(A-Weighted)
Interchannel Isolation
Interchannel Gain Mismatch
16
75
84
84
80
85
90
90
90
0.2
0.5
Bits
dB
dB
dB
dB
dB
DAC Analog Output Characteristics:(Note 4 )
Resolution
S/(N+D)
DR (-60dB Output, A-Weighted)
S/N
(A-Weighted)
Interchannel Isolation
Interchannel Gain Mismatch
Output Voltage (AOUT=0.6 x VA) (Note 2 )
Load Resistance
16
75
84
84
90
1.62
10
86
90
90
100
0.1
1.8
0.3
1.98
Bits
dB
dB
dB
dB
dB
Vpp
kΩ
Power Supply
Power supply: VA+VD
Normal Operation (PD="H")
mA
27
18
AD+DA (PM0=1,PM1=1,PM2=1,PM3=0)
mA
17
11
AD (PM0=1,PM1=1,PM2=0,PM3=0)
mA
14
9
DA (PM0=0,PM1=0,PM2=1,PM3=0)
uA
100
10
Power-down-mode(PD="L") (Note 5 )
Note 2 . Analog Input and Output voltage (Full-Scale voltage:0dB) scale with VA.
IPGA: 0.57 x VA(typ.), DAC : 0.6 x VA(typ).
3 . ADC is input from LIN1/RIN1 or LIN2/RIN2 and it measures included in IPGL/IPGR. The value of
IPGL/IPGR is set 0dB.
Internal HPF removes offset in the ADC, IPGL/IPGR.
4 . Measured by AD725C(SHIBASOKU), RMS mode.
5 . In case of the power-down mode, all digital input pins including clock(MCLK, BCLK, LRCK) pins are
held VD or DGND.
M0026-E-00
1998/08
-6-
ASAHI KASEI
[AK4516A]
FILTER CHARACTERISTICS
(Ta=25°C ; VA,VD=2.5∼ 3.6V; fs=44.1kHz; DEM bit="0")
Parameter
Symbol
min
PB
0
typ
max
Units
16.5
16.1
0
kHz
kHz
kHz
kHz
dB
dB
1/fs
us
3.4
10
22
Hz
Hz
Hz
ADC Digital Filter (LPF):
Passband
(Note 6 )
±0.1dB
-0.55dB
-1.2dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 7 )
Group Delay Distortion
19.0
20.0
SB
PR
SA
GD
∆ GD
26.0
±0.1
68
ADC Digital Filter (HPF):
Frequency Response (Note 6 )
-3.0dB
-0.5dB
-0.1dB
FR
±0.1dB
-6.0dB
PB
DAC Digital Filter:
Passband
(Note 6 )
0
20.0
14.7
kHz
kHz
kHz
dB
dB
1/fs
±0.5
dB
22.05
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 7 )
SB
PR
SA
GD
DAC Digital Filter + Analog Filter
Frequency Response 0∼ 20.0kHz
FR
24.1
±0.06
43
Note 6 .The passband and stopband frequencies scale with fs (system sampling rate).
For example, ADC is PB=0.431*fs(@-0.55dB), DAC is PB=0.454*fs(@-0.1dB).
7 .The calculating delay time which occurred by digital filtering. This time is from the input of analog signal to
setting the 16 bit data of both channels to the output register for ADC.
For DAC, this time is from setting the 16 bit data of both channels on input register to the output of analog
signal.
M0026-E-00
1998/08
-7-
ASAHI KASEI
[AK4516A]
DC CHARACTERISTICS
(Ta=25°C ; VA,VD=2.5∼ 3.6V)
Parameter
Symbol
min
typ
max
units
VIH
VIL
VOH
VOL
Iin
70%VD
VD-0.4
-
-
30%VD
0.4
±10
V
V
V
V
uA
min
typ
max
Units
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fs
7.68
28
28
11.52
23
23
30
45
11.2896
12.8
16.9344
19.2
44.1
50
50
55
MHz
ns
ns
MHz
ns
ns
kHz
%
tBLK
tBLKL
tBLKH
tLRB
tBLR
tLRM
tBSD
tSDH
tSDS
312.5
130
130
50
50
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200
80
80
50
50
150
50
50
tPDW
tPDV
150
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage (Iout=-400uA)
Low-Level Output Voltage (Iout=400uA)
Input Leakage Current
SWITCHING CHARACTERISTICS
(Ta=25°C ; VA,VD=2.5∼ 3.6V; CL=20pF)
Parameter
Control Clock Frequency
Master Clock (MCLK) 256fs:
Pulse Width Low
Pulse Width High
384fs:
Pulse Width Low
Pulse Width High
Channel Select Clock(LRCK) Frequency
Duty
Audio Interface Timing
BCLK period
BCLK Pulse Width Low
Pulse Width High
LRCK Edge to BCLK "↑ "
BCLK "↑ " to LRCK Edge
LRCK to SDTO(MSB) Delay Time
BCLK "↓ " to SDTO Delay Time
SDTI Latch Hold Time
SDTI Latch Set up Time
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDATA Latch Set Up Time
CDATA Latch Hold Time
CS High Level Time
CS "↓ " to CCLK "↑ "
CCLK "↑ " to CS "↑ "
CDTO Output Delay Time
CS "↑ "to CDTO(Hi-Z)Time (Note 8 )
Reset Timing
PD Pulse Width
PD "↑ " to SDTO Delay Time
Symbol
80
80
50
50
70
70
8224
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
Note 8 .RL=1kΩ /10% Change (Pull-up operates for VD)
M0026-E-00
1998/08
-8-
ASAHI KASEI
[AK4516A]
Timing Diagram
Data Input Timing in WRITE
M0026-E-00
1998/08
-9-
ASAHI KASEI
[AK4516A]
Reset Timing
M0026-E-00
1998/08
- 10 -
ASAHI KASEI
[AK4516A]
OPERATION OVERVIEW
System Clock
The clocks which are required to operate are MCLK(256fs/384fs), LRCK(fs), BCLK(32fs∼ ). The master clock
(MCLK) should be synchronized with LRCK but the phase is free of care.
The MCLK can be input 256fs or 384fs. When 384fs is input, the internal master clock is divided into 2/3
automatically. *fs is sampling frequency.
All external clocks (MCLK, BCLK, LRCK) should always be present whenever IPGA or ADC or DAC is in operation.
If these clocks are not provided, the AK4516A may draw excess current and it is not possible to operate properly
because utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4516A should be in
the power-down mode. (Please refer to the "Mode Control 1" section.)
System Reset
AK4516A should be reset once by bringing PD pin "L" upon power-up. The internal timing starts clocking by LRCK
"↑ " after exiting reset by MCLK. After the system reset operation, the all internal AK4516A registers are initial value.
Zero detection
When the input data at both channels are continuously zeros for 8192 LRCK cycles, DZF goes to "H". DZF
immediately goes to "L", if the input data are not zero. When the DAC is power-down, DZF becomes to "L".
Digital High Pass Filter(HPF)
The ADC has HPF for the DC offset cancel. The cut-off frequency of HPF is 3.4Hz(@fs=44.1kHz) and it is -0.1dB at
22Hz. It also scales with the sampling frequency(fs).
M0026-E-00
1998/08
- 11 -
ASAHI KASEI
[AK4516A]
Audio Serial Interface Format
Data is shifted in/out the SDTI/SDTO pins using BCLK and LRCK inputs. Four serial data are selected by the DIF0
and DIF1 pins as shown in Table 1 . In all modes, the serial data is MSB-first, 2's compliment format and it is latched
by "↑ " of BCLK.
When DIF1="0" and DIF0="1", only BCLK=64fs is acceptable.
No.
DIF1
DIF0
0
1
2
3
0
0
1
1
0
1
0
1
SDTO(ADC)
SDTI(DAC)
MSB justified
LSB justified
LSB justified
LSB justified
MSB justified
MSB justified
2
2
I S compatible
I S compatible
Table 1 . Audio Data Format
BCLK
Figure
≥ 32fs
Figure 1
Figure 2
Figure 3
Figure 4
= 64fs
≥ 32fs
≥ 32fs
RESET
Figure 2. Audio Data Timing (No.1)
M0026-E-00
1998/08
- 12 -
ASAHI KASEI
[AK4516A]
Figure 4. Audio Data Timing (No.3)
M0026-E-00
1998/08
- 13 -
ASAHI KASEI
[AK4516A]
Control Register R/W Timing
The data on the 4 wires serial interface consists of op-code(3bit), address(LSB-first, 5bit) and control data
(LSB-first, 8bit). The transmitting data is output to each bit by " ↓" of CCLK, the receiving data is latched by "↑"
of CCLK. Writing data becomes effective by "↑" of CS. Reading data becomes Hi-Z(floating) by "↑" of CS.
CS should be held to "H" at no access. In case of connecting between CDTI and CDTO, the I/F can be also
controlled by 3-wires.
CCLK always needs 16 edges of "↑ " during CS ="L". Reading/Writing of the address except 00H∼ 0DH are
inhibited.
Reading/Writing of the control registers by except op0=op1="1" are invalid.
op0- op2: Op- code (111:WRITE, 110:READ)
A0- A4:
Address
D0- D7:
Control Data
Figure 5 . Control Data Timing
M0026-E-00
1998/08
- 14 -
ASAHI KASEI
• INIT:
[AK4516A]
Initializing. At this time, ZFIPL and ZFIPR are "0". When these flags becomes "1", INIT
process has completed.
• PD:
Power-down state. ADC is output "0", analog output of DAC goes floating.
• INIT-1:
Initializing all registers.
• INIT-2:
Initializing read only registers in control registers.
• Inhibit-1: Inhibits writing and reading to all control registers.
• Inhibit-2: Enable writing to control registers except "Mode Control 1 (01H)" register.
• Inhibit-3: Enable reading from control registers.
• Inhibit-4: Enable writing to only "Mode Control 1 (01H)" register of the control registers.
Note: Please refer to "explanation of register" about the condition of each register.
1
{
Digital output corresponding to analog input and analog output corresponding to digital input have the
{
group delay(GD).
If the analog signal does not be input, the digital outputs have the offset to the op-amp of input and some
{
offset error of the internal ADC.
A few noise occurs at the "↓↑ " of PD signal.
{
Please mute the analog output externally if the noise influences the system application.
When the external clocks are stopped, the AK4516A should be in the power-down mode.
2
3
4
Figure 6 .Power-up/Power-down Timing Example
M0026-E-00
1998/08
- 15 -
ASAHI KASEI
[AK4516A]
Operation mode explanation
The AK4516A can perform the limitter operation and the recovery operation automatically. There are three operation
modes.
1. Manual Mode
The manual mode is used when the AK4516A mode is changed (for example, when the input pin or the Deemphasis etc setting is changed) or the recording level is adjusted from uP writing operation by manual. In case of
the semi-auto or the full-auto modes, it is impossible to set up a part of the register.
(Refer to "Semi-auto mode", "Full-auto mode" section).
M0026-E-00
1998/08
- 16 -
ASAHI KASEI
[AK4516A]
2. Semi-auto Mode
The semi-auto mode is the mode that uses the AK4516A auto limitter function, and the recovery operation is
processed by uP or DSP etc.
During the semi-auto mode, writing to the following registers from uP is inhibited.
• LRGA, LTM1-0, ZELM, LMTH1-0, LMAT2-0
Figure 7 . Control example of semi-auto mode operation(LMAT = 1 step, ZENM=ZELM="1")
1
{
Setting up the registers for the semi-auto mode operation.
{
(LTM1-0, ZELM, LMTH1-0, LMAT2-0, IPGL, IPGR, LRGA="1", GSEL)
WR(LMTE="1", RCVE="0"): After the registers concerned in the auto limitter operation is set up and
2
3
{
4
{
5
{
6
{
7
{
8
{
9
{
confirming the zero crossing flags(ZFIPL,ZFIPR)="1", LMTE is set "1".
As the input signal of ADC exceeds LMTH, the auto limitter operation starts.
WR(IPGA="31H"):As the auto limitter is in operation, writing by uP is ignored.
After the zero crossing operation of both Lch and Rch is completed, the next operation starts.
RD(LCDET&IPGA):Confirm to complete auto limitter operation and reads the IPGA present value.
WR(IPGA="2FH"):Update IPGA value.
WR(LMTE="0")
In Figure 7 , since "0" is written to LMTE during ATT operation, the operation changes to manual mode
after completing ATT operation. After confirming LCDET="1", it is possible to change the each register
set-up. If LMTE is set "0" during the auto limitter operation or the update of the IPGA value by uP,
LCDET becomes "1" after the max "1" ATT/GAIN operation is completed by internal state.
10 In this case, the input signal of ADC exceeds LMTH, the auto limitter does not operate because of
{
LMTE="0".
M0026-E-00
1998/08
- 17 -
ASAHI KASEI
[AK4516A]
Figure 8 Register set-up sequence at Semi-auto mode
M0026-E-00
1998/08
- 18 -
ASAHI KASEI
[AK4516A]
3. Full-auto Mode
The full-auto mode is done automatically by the auto limitter and the auto recovery function of the AK4516A.
However, writing to the register is needed to enable these functions.
During the full-auto mode, writing to the following registers from uP is inhibited.
• LRGA, LTM1-0, ZELM, LMTH1-0, LMAT2-0, WTM1-0, NRTM1-0, RATT1-0, ZENM, REF6-0, IPGL, IPGR
Figure 9 . Control example of full-auto mode operation (LMAT=RATT: 1 step, ZENM=ZELM="1")
1
{
Set-up the registers of full-auto mode
2
{
(LTM1-0, ZELM, LMTH1-0, LMAT2-0, WTM1-0, RATT1-0, NRTM1-0, ZENM, REF6-0, GSEL, IPGL,
IPGR, LRGA="1")
WR(LMTE=RCVE="1"): After the registers concerned in the auto limitter operation is set up and
3
{
4
{
5
{
{
7
{
6
8
{
{
9
confirming the zero crossing flags(ZFIPL, ZFIPR)="1", LMTH and RCVE are set "1".
WR(IPGA="31H"):As the operation is full-auto mode, writing by uP is ignored.
The ready of recovery starts.
As the input signal of ADC exceeds LMTH, the recovery operation (in the figure, recovery ready) is
discontinued and the limitter operation starts.
WR(LMTE=RCVE="0"):The full-auto mode operation is completed.
In Figure 9 , since "0" is written to LMTE& RCVE during the ATT operation, the operation changes to the
manual mode after completing ATT operation. After confirming LCDET="1", it is possible to change the
each register set-up. If LMTE&RCVE are set "0" during the full-auto mode operation, LCDET becomes
"1" after the max "1" ATT/GAIN operation is completed by internal state.
In this case, the input signal of ADC exceeds LMTH, the auto limitter does not operate because of
LMTE=RCVE="0".
After the limitter operation is completed, the AK4516A waits for the time set by WTM1-0. If the input
signal does not exceed (LMTH - 2dB), the recovery operation is executed. After the waiting time finishes
the next waiting time starts immediately. In recovery ready, the waiting timer is reset under the condition
of (LMTH - 2dB) ≤ Input Signal<LMTH. And the timer starts under the condition of (LMTH - 2dB)>Input
Signal.
M0026-E-00
1998/08
- 19 -
ASAHI KASEI
[AK4516A]
Figure 10 . Registers set-up sequence at Full-auto mode
M0026-E-00
1998/08
- 20 -
ASAHI KASEI
[AK4516A]
Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
Register Name
Input Select
Mode Control 1
Mode Control 2
Zero Cross & Timer Control
Peak Hold Low Byte Lch
Peak Hold High Byte Lch
Peak Hold Low Byte Rch
Peak Hold High Byte Rch
Overflow Status
Auto LMT&RCV Control
Input PGA Control Lch
Input PGA Control Rch
Auto Recovery Control 1
Auto Recovery Control 2
D7
D6
D5
D4
0
0
0
0
0
0
0
0
MONO1 MONO0 DIF1
DIF0
LRGA GSEL NRTM1 NRTM0
PLL7
PLL6
PLL5
PLL4
PUL7 PUL6 PUL5 PUL4
PLR7 PLR6 PLR5 PLR4
PUR7 PUR6 PUR5 PUR4
ZFIPR ZFIPL ROF2 ROF1
LMTE RCVE
0
LMTH1
LCDET IPGL6 IPGL5 IPGL4
LCDET IPGR6 IPGR5 IPGR4
0
0
0
0
0
REF6 REF5 REF4
Table 2 . AK4516A Register Map
D3
D2
D1
D0
RIN2
PM3
FS1
ZENM
PLL3
PUL3
PLR3
PUR3
ROF0
LMTH0
IPGL3
IPGR3
WTM1
REF3
RIN1
PM2
FS0
LTM1
PLL2
PUL2
PLR2
UR2
LOF2
LMAT2
IPGL2
IPGR2
WTM0
REF2
LIN2
PM1
DEM
LTM0
PLL1
PUL1
PLR1
PUR1
LOF1
LMAT1
IPGL1
IPGR1
RATT1
REF1
LIN1
PM0
0
ZELM
PLL0
PUL0
PLR0
PUR0
LOF0
LMAT0
IPGL0
IPGR0
RATT0
REF0
Input Select
Addr
Register Name
00H Input Select
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
RIN2
RIN1
LIN2
LIN1
R/W
R/W
RESET
0
0
0
0
0
1
0
1
LIN2-1 : Select ON/OFF of Lch input (0:OFF, 1:ON). These bits can select to ON/OFF at the same time.
RIN2-1: Select ON/OFF of Rch input (0:OFF, 1:ON). These bits can select to ON/OFF at the same time.
This register is reset at PD pin="L", then inhibits writing to this register.
M0026-E-00
1998/08
- 21 -
ASAHI KASEI
[AK4516A]
Mode Control 1
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
01H Mode Control 1
0
0
0
0
PM3
PM2
PM1
PM0
R/W
RESET
0
0
0
0
1
1
1
R/W
0
PM3-0: Power Management (0: Power Down, 1:Power Up)
PM0: Mixer, PGA input, Auto Limitter and Auto Recovery power control.
PM1: Power control of ADC
PM2: Power control of DAC
PM3: Used both as power control of analog loopback circuit and as selection of MUX.
(0: DAC, 1:Analog loopback)
PM0-3 can be partially powered-down by ON/OFF of PM0-3. When PD pin goes "L",
all the circuit in AK4516A can be powered-down regardless of PM0-3.
When PM0-3 go all "0", all the circuits in AK4516A can be also powered-down.
When PM3 goes "1", input for output-AMP is selected to analog loopback circuit from
DAC output.
Output MUX and AMP are powered-down when PD ="L" or PM2=PM3="0". Refer to
Figure 11 .
The loopback output and the MUX selecting DAC output is a MIXER with the switch in
practice. Therefore, when both PM2 and PM3 select ON, the analog loopback signal
and DAC output are mixed by Gain 1.
Except the case of PM0=PM1=PM2=PM3="0" or PD pin="L", MCLK, BCLK, LRCK
should not be stopped.
When the input PGA and MUX are powered-down by PM0-3 or PD pin, the output of
AMP becomes Hi-Z(floating).
This register is reset by the PD pin="L", then inhibits writing to this register.
M0026-E-00
1998/08
- 22 -
ASAHI KASEI
[AK4516A]
Figure 11 . Power Management
M0026-E-00
1998/08
- 23 -
ASAHI KASEI
[AK4516A]
Mode Control 2
Addr
Register Name
D7
02H Mode Control 2
D6
MONO1 MONO0
R/W
RESET
R/W
0
R/W
0
D5
D4
D3
D2
D1
D0
DIF1
DIF0
FS1
FS0
DEM
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RD
0
MONO1-0:Monaural Mixing
00: Stereo (RESET)
01: (L+R)/2
10: LL
11: RR
DIF1-0: Select Audio Serial Interface Format
The data is all 2's complement, MSB first.
No.
DIF1
DIF0
0
1
2
3
0
0
1
1
0
1
0
1
SDTO(ADC)
SDTI(DAC)
MSB justified
LSB justified
LSB justified
LSB justifed
MSB justified
MSB justified
2
2
I S compatible
I S compatible
Table 3 . Audio Serial Interface Format
BCLK
Figure
≥ 32fs
Figure 1
Figure 2
Figure 3
Figure 4
= 64fs
≥ 32fs
≥ 32fs
RESET
FS1-0:Select De-emphasis frequency
The AK4516A includes the digital de-emphasis filter(tc=50/15us) by IIR filter. The filter
corresponds to three sampling frequency (32kHz, 44.1kHz, 48kHz). The de-emphasis filter
selected by FS0 and FS1 registers are enabled for input audio data.
FS1
FS0
Mode
0
0
1
1
0
1
0
1
44.1kHz
OFF
48kHz
32kHz
RESET
Table 4 . De-empahsis frequency
DEM: Control of De-emphasis (0: Disable, 1: Enable)
FS0 and FS1 registers of the de-emphasis are enabled by setting DEM=1. FS0 and FS1 are
ignored at DEM=0.
This register is reset by the PD pin="L", then inhibits writing to this register.
M0026-E-00
1998/08
- 24 -
ASAHI KASEI
[AK4516A]
Zero Cross & Timer Control
Addr
Register Name
D7
03H Zero Cross & Timer Control
R/W
RESET
LRGA
R/W
1
D6
D5
D4
D3
GSEL NRTM1 NRTM0 ZENM
R/W
1
R/W
1
R/W
0
R/W
0
D2
D1
D0
LTM1
LTM0
ZELM
R/W
1
R/W
0
R/W
0
LRGA: Selects the method of writing to IPGA
0: Independent data can be written to IPGA and IPGR.
1: Common data can be written to IPGL and IPGR.
In this case, when a data is written to IPGL, the same data is also written to IPGR. When a
data is written to IPGR, a data is only written to IPGR. When IPGL value differs from IPGR
value, IPGL and IPGR values can be set by a common data after writing IPGL value at
LRGA="1". (RESET)
GSEL:Selects input gain (set a common Lch and Rch)
0: LINE
1: MIC (RESET)
Even if LINE and MIC are the same data value, both gain values are different.
NRTM1-0: Zero crossing timeout at writing operation by uP and auto recovery operation.
Set-up zero crossing timeout at writing operation by uP and the auto recovery operation. The
writing operation by uP and the auto recovery operation set up in common. In case of the
auto limitter operation, zero crossing operation is set by different bits(LTM1-0).
NRTM1
NRTM0
0
0
1
1
0
1
0
1
Zero crossing timeout(ZENM="1")
513/fs
1025/fs
2049/fs
4097/fs
48kHz
44.1kHz
32kHz
10.7ms
21.4ms
42.7ms
85.4ms
11.6ms
23.2ms
46.5ms
92.9ms
16.0ms
32.0ms
64.0ms
128.0ms
RESET
Table 5 . Zero crossing timeout at uP writing operation and auto recovery operation.
(NRTM1="1", NRTM0="0" at RESET)
ZENM: Enables zero crossing detection at uP WRITE operation or auto recovery operation
(0: Disable, 1: Enable)
1: When IPGA of each L/R channels do zero crossing or timeout independently, the IPGA
value is changed by uP WRITE operation or auto recovery operation.
0: IPGA is changed immediately.
M0026-E-00
1998/08
- 25 -
ASAHI KASEI
[AK4516A]
LTM1-0:Zero crossing timeout(ZELM="1") or Update period(ZELM="0") at the auto limitter mode
(LTM1="1", LTM0="0"@RESET)
LTM1
LTM0
Zero crossing timeout(ZELM="1")
48kHz
0
0
1
1
0
1
0
1
44.1kHz
Update period(ZELM="0")
32kHz
48kHz
44.1kHz
129/fs
2.7ms
2.9ms
4.0ms
1/fs
21us
23us
258/fs
5.4ms
5.9ms
8.1ms
2/fs
42us
45us
516/fs
10.8ms
11.7ms
16.1ms
4/fs
83us
91us
1032/fs
21.5ms
23.4ms
32.3ms
8/fs
167us
181us
Table 6 . Zero crossing timeout or Update period at the auto limitter mode
32kHz
31us
63us
125us
250us
ZELM: Enables zero crossing detection at the auto limitter operation (0: Disable, 1: Enable)
0: The IPGA value is changed immediately. When the IPGA value is changed continuously,
the change is done by the period specified by LTM1-0.
1: When IPGA of each L/R channel do zero crossing or timeout independently, the IPGA
value is changed by auto limitter operation.
These bits are reset by PD pin="L", then inhibits writing to these bits.
Peak Hold
Addr
04H
05H
06H
07H
Register Name
Peak Hold Low Byte Lch
Peak Hold High Byte Lch
Peak Hold Low Byte Rch
Peak Hold High Byte Rch
D7
D6
D5
D4
D3
D2
D1
D0
PLL7
PUL7
PLR7
PUR7
PLL6
PUL6
PLR6
PUR6
PLL5
PUL5
PLR5
PUR5
PLL4
PUL4
PLR4
PUR4
PLL3
PUL3
PLR3
PUR3
PLL2
PUL2
PLR2
PUR2
PLL1
PUL1
PLR1
PUR1
PLL0
PUL0
PLR0
PUR0
R/W
RESET
PLL7-0:
PUL7-0:
PLR7-0:
PUR7-0:
RD
00H
Peak hold of Lch (Absolute value), 8bit of LSB (FFH ∼ 00H)
Peak hold of Lch (Absolute value), 8bit of MSB (7FH∼ 00H)
Peak hold of Rch (Absolute value), 8bit of LSB (FFH∼ 00H)
Peak hold of Rch (Absolute value), 8bit of MSB (7FH∼ 00H)
The peak is held L/R audio data independently. These registers are reset by reading 8bit of MSB, reading 8bit
of both MSB and LSB should be continuity controlled by reading in order of 8 bit of MSB from LSB. After
reading the 8 bit of LSB the last, 8 bit of MSB is lost by reading 8 bit of LSB the last. Sign bits (PUL7, PUR7)
becomes "0" as the output value is the absolute value.
These registers are reset on the following any conditions.
• PD pin="L"
• PM1="0"
M0026-E-00
1998/08
- 26 -
ASAHI KASEI
[AK4516A]
Overflow Status
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
ZFIPR
ZFIPL
ROF2
ROF1
ROF0
LOF2
LOF1
LOF0
R/W
RD
RD
RD
RD
RD
RD
RD
RD
RESET
0
0
0
0
0
0
0
0
08H Overflow Status
ZFIPR: Rch IPGA zero crossing detection flag.
ZFIPL: Lch IPGA zero crossing detection flag.
At writing operation by uP, when ZENM is "1", this flag becomes "0" if IPGA value is set
independently for L/R. When each channel does zero crossing or timeout, and then IPGA of
each channel is changed, the flag of each channel becomes "1".
When writing to the same channel is done again under zero crossing waiting before this flag
becomes "1", the timeout counter is not reset. Therefore then, zero crossing timeout period
becomes shorter for the new writing. But if writing is done to the channel which the flag is "1"
when the flag of either Lch or Rch is "0", the timeout counter is reset. In this case, zero
crossing timeout counter restarts from the last writing.
When ZEIP is "0", ZFIPL/ZFIPR always become "1". ZFIPL/ZFIPR always become "1" during
semi-auto mode operation (LMTE="1", RCVE="0") and full-auto mode operation
(LMTE=RCVE="1").
ZFIPR/ZFIRL is "0" during initializing operation after exiting power-down by PD pin.
The completion of the initializing operation can be recognized by confirming these flags are
"1".
These bits are reset on the following any conditions.
• PD pin="L"
In case of PM0="0", these flag become "1".
ROF2-0:
Overflow Flag of Rch
Overflow flag includes 3 bit. Max value of the overflow is held. These bits are reset to
(0, 0, 0) by reading by uP.
These bits are reset on the following any conditions.
• PD pin="L"
• PM1="0"
ROF2
ROF1
ROF0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Threshold
<-12.04dB
-12.04dB≤
-8.52dB≤
-6.02dB≤
-4.08dB≤
-1.80dB≤
-0.00dB≤
Table 7 . Overflow Flag of Rch
M0026-E-00
1998/08
- 27 -
ASAHI KASEI
LOF2-0:
[AK4516A]
Overflow Flag of Lch
Overflow flag includes 3bit. Max value of overflow is held. These bits are reset to
(0, 0, 0) by reading by uP.
These bits are reset on the following any conditions.
• PD pin="L"
• PM1="0"
LOF2
0
0
0
0
1
1
1
LOF1
LOF0
Threshold
0
0
<-12.04dB
-12.04dB≤
0
1
-8.52dB≤
1
0
-6.02dB≤
1
1
-4.08dB≤
0
0
-1.80dB≤
0
1
-0.00dB≤
1
0
Table 8 . Overflow Flag of Lch
M0026-E-00
1998/08
- 28 -
ASAHI KASEI
[AK4516A]
Auto Limitter Control
During the auto limitter operation, when either Lch or Rch exceed auto limitter detection level (LMTH1-0),
IPGA value is attenuated by auto limitter ATT step (LMAT1-0) automatically. Then the IPGA value is changed
commonly for L/R channels. In this operation, either zero crossing detection with timeout or immediate
change is selected by ZELM. Timeout period and update period are set by LTM1-0 (refer to Table 6 ). The
operation for attenuation is done continuously until the input signal level becomes LMTH1-0 or less. Unless
LMTE is set "1" after finishing operation for attenuation, this operation for attenuation repeats when input
signal level exceeds LMTH1-0 again. IPGA value of register is always written to current value in this mode
automatically, the operation for attenuation always starts from current IPGA value.
When the operation for attenuation is completed after the input signal becomes LMTH1-0 or less, auto
limitter detection flag(LCDET) becomes "1". This flag become "0" when the input signal exceeds LMTH1-0
again and the AK4516A enters the auto limitter operation.
During the auto limitter operation (LCDET=0), IPGA is changed according to the value set by the auto
limitter operation. Therefore, uP writing operation is ignored.
During semi-auto mode and after completing auto limitter operation(LCDET="1"), IPGA is changed
according to the value written by uP.
Addr
Register Name
D7
D6
09H Auto LMT&RCV Control
LMTE
RCV
0
R/W
0
R/W
0
RD
0
R/W
RESET
D5
D4
D3
D2
D1
D0
LMTH1 LMTH0 LMAT2 LMAT1 LMAT0
R/W
1
R/W
1
R/W
0
R/W
0
R/W
0
LMTE: Auto Limitter Enable Flag
0: Auto limitter operation OFF (RESET)
1: Auto limitter operation ON
RCVE: Auto Recovery Enable Flag
0: Auto recovery operation OFF(RESET)
1: Auto recovery operation ON.
This bit is only available at LMTE="1". When LMTE is "0" , auto recovery operation becomes
"OFF".
The change of operation mode by LMTE and RCVE bits always needs to control via manual-mode, between
the semi-auto mode and the full-auto mode should not be changed.
IPGA value of each channel should be equal value before entering the semi-auto mode and the full-auto
mode. LRGA should be set "1" during the semi-auto mode and writing operation by uP should always write
equal value to each channel.
LMTH1-0:Auto Limitter Detection Level / Auto Recovery Waiting Counter Reset Level
LMTH1
LMTH0
0
0
1
1
0
1
0
1
Auto Limitter Detection Level
ADC Input ≥ -8.0dB
ADC Input≥ -6.0dB
ADC Input≥ -4.0dB
ADC Input≥ -2.0dB
Auto Recovery Waiting Counter Reset Level
-8.0dB>ADC Input≥ -10.0dB
-6.0dB>ADC Input≥ -8.0dB
-4.0dB>ADC Input≥ -6.0dB
-2.0dB>ADC Input≥ -4.0dB
Table 9 . Auto Limitter Detection Level / Auto Recovery waiting Counter Reset Level
(LMTJ1=LMTH0="0"@RESET)
M0026-E-00
1998/08
- 29 -
ASAHI KASEI
[AK4516A]
LMAT2-0: Auto Limitter ATT Step
During the auto limitter operation, when either Lch or Rch exceeds the auto limitter detection level set
by LMTH1-0, the number of steps attenuated from current IPGA value is set. For example, when the
current IPGA value is 68H in the state of LMAT2-0="111", it becomes IPGA=60H by the auto limitter
operation, the input signal level is attenuated by 4dB (=0.5dB x 8).
Auto limitter operation period is the constant period by setting LTM1-0 at ZELM="1", it is the different
period by the input signal at ZELM="0". (depend on zero crossing detection period)
When the attenuation value exceeds IPGA="00"(MUTE), it clips to "00".
LMAT2
LMAT1
LMAT0
ATT STEP
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
8
Table 10 . Auto Limitter ATT Step Setting
RESET
These bits are reset by PD pin="L", then inhibits writing to these bits.
Input Analog PGA Control
Addr
Register Name
0AH Input PGA Control Lch
0BH Input PGA Control Rch
R/W
RESET
D7
D6
D5
D4
D3
D2
D1
D0
LCDET IPGL6 IPGL5 IPGL4 IPGL3 IPGL2 IPGL1 IPGL0
LCDET IPGR6 IPGR5 IPGR4 IPGR3 IPGR2 IPGR1 IPGR0
RD
1
R/W
30H
LCDET: Auto Limitter and Auto Recovery detection Flag(refer to Figure 7 and Figure 9 )
0: Updating IPGA value by uP writing at the semi-auto mode and the auto limitter or the auto
recovery operation.
1: Complete the auto recovery operation or the auto limitter operation. Complete updating
IPGA value by uP writing at semi-auto mode. (RESET)
This flag(LCDET) always become "1" at manual mode(LMTE=RCVE="1"). The LCDET in
0AH and 0BH shows the same value.
This flag is "0" during initialization after exiting power-down mode by PD pin.
During the semi-auto mode operation, if LMTE is set "0" during the auto limitter operation or
the update of the IPGA value by uP, LCDET becomes "1" after the max "1" ATT/GAIN
operation is completed by internal state.
During the full-auto-mode operation, if LMTE&RCVE are set "0" during the full-auto mode
operation, LCDET becomes "1" after the max "1" ATT/GAIN operation is completed by
internal state.
In case of changing the registers relative to the semi-auto mode and the full-auto mode,
these registers should be changed after writing LMTE="0"(at the semi-auto mode) or
LMTE=RCVE="0" (at the full-auto mode) and then confirming LCDET="1".
M0026-E-00
1998/08
- 30 -
ASAHI KASEI
[AK4516A]
IPGL6-0: Lch Input Analog PGA.
105 levels.
IPGR6-0: Rch Input Analog PGA.
105 levels.
ON/OFF of zero crossing detection is controlled by ZENM/ZELM bits.
DATA
RESET
GAIN(dB)
MIC
LINE
68H
+28.0
+8.0
67H
+27.5
+7.5
66H
+27.0
+7.0
:
:
:
30H
0.0
-20.0
2FH
-0.5
-20.5
:
:
:
21H
-7.5
-27.5
20H
-8.0
-28.0
1FH
-9.0
-29.0
1EH
-10.0
-30.0
STEP
LEVEL
0.5dB
73
1dB
24
2dB
4
4dB
3
:
:
:
09H
-31.0
-51.0
08H
-32.0
-52.0
07H
-34.0
-54.0
06H
-36.0
-56.0
05H
-38.0
-58.0
04H
-40.0
-60.0
03H
-44.0
-64.0
02H
-48.0
-68.0
01H
-52.0
-72.0
00H
MUTE
MUTE
Table 11 . Input Gain Setting
1
IPGL and IPGR are read by uP current values at rising of CS pin.
These registers are reset by PD pin="L", then inhibits writing to these registers.
These registers are reset by PM0="0".
M0026-E-00
1998/08
- 31 -
ASAHI KASEI
[AK4516A]
Auto Recovery Control
Auto recovery operation starts after completing auto limitter operation (LCDET="1") at LMTE=RCVE="1".
IPGA gain increases automatically by this operation up to the set reference level(REF6-0). Then the IPGA
value is set for L/R commonly. Either zero crossing or fs(sampling frequency) period for this auto recovery
operation is decided by zero crossing detection at the auto recovery operation and the writing operation by
uP (=ZENM).
During the auto recovery operation, when either input signal level of Lch or Rch exceeds the auto limitter
detection level (LMTH1-0), the auto recovery operation changes into the auto limitter operation immediately.
(Refer to Figure 9 )
Addr
Register Name
D7
D6
D5
D4
D3
0CH Auto Recovery Control 1
0
0
0
0
WTM1
D2
D1
D0
WTM0 RATT1 RATT0
R/W
RD
RD
RD
RD
R/W
R/W
R/W
R/W
RESET
0
0
0
0
1
0
0
0
WTM1-0: Auto Recovery Waiting Time
Recovery operation is done at a period set by WTM1-0 when any limitter operation does not
occur at full-auto mode. When the input signal level exceeds auto recovery waiting counter
reset level set by LMTH1-0, the auto recovery waiting counter is reset.
The waiting timer starts when the input signal level becomes below the auto recovery waiting
counter reset level.
When the auto recovery waiting time(WTM1-0) is shorter than zero crossing timeout period
of the auto recovery operation(NRTM1-0), the auto recovery is operated by NRTM1-0.
Therefore, in this case the auto recovery operation period is not constant.
WTM1
0
0
1
1
Timeout
WTM0
48kHz
44.1kHz
32kHz
0
512/fs
10.7ms
11.6ms
16.0ms
1
1024/fs
21.3ms
23.2ms
32.0ms
0
2048/fs
42.6ms
46.4ms
64.0ms
1
4096/fs
85.2ms
92.8ms
128.0ms
Table 12 . Auto Recovery Operation Waiting Period
RESET
RATT1-0: Auto Recovery GAIN Step
During the auto recovery operation, the number of steps changed from current IPGA value is
set. For example, when the current IPGA value is 30H, RATT1="0", RATT0="1" are set, IPGA
changes to 32H by the auto limitter operation, the input signal level is gained by 1dB(=0.5dB
x 2).
The auto recovery operation period is fs period at ZENM="0", the auto recovery operation is
done after zero crossing detection or timeout in case of ZENM="1"
When the IPGA value exceeds the reference level (REF6-0), the IPGA value does not
increase.
RATT1
RATT0
GAIN STEP
0
0
1
1
0
1
0
1
1
2
3
4
RESET
Table 13 . Auto Recovery GAIN Step Setting
M0026-E-00
1998/08
- 32 -
ASAHI KASEI
[AK4516A]
Figure 12 . Auto Recovery Operation (LMAT=RATT = 1 Step, ZENM=ZELM="1")
1
{
2
{
3
{
4
{
After completing the auto limitter operation, the auto recovery operation wait for only a period set by
WTM1-0. If the auto limitter operation is not occurred during the recovery operation, the auto recovery
operation is done only once.
IPGA is changed by zero crossing in the auto recovery operation, and the count of the next recovery
waiting period is also proceeding at the same time.
When the auto limitter operation is entered in zero crossing waiting(Rch), the auto recovery operation
in progress is stopped, the auto limitter is done according to smaller value (Rch in the Figure 10) of the
IPGA value. Then, IPGL is changed from 30H to 2EH and IPGR is changed from 2FH to 2EH.
(refer to Recovery Operation 1)
When the auto recovery operation is waiting for the next operation, the limitter operation is done from
IPGA value at that time . (refer to Recovery Operation 2)
This register is reset by PD pin = "L", then inhibits writing to this register.
M0026-E-00
1998/08
- 33 -
ASAHI KASEI
Addr
[AK4516A]
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
0DH Auto Recovery Control 2
0
REF6
REF5
REF4
REF3
REF2
REF1
REF0
R/W
RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET
0
0
1
1
0
0
0
0
REF6-0: Set the Reference value at Auto Recovery Operation
During the auto recovery operation, when IPGA value becomes the reference value set by
REF6-0, the gain of the auto recovery operation does not exceed the reference value. The
reference value is set commonly as for Lch and Rch.
During the auto recovery operation, if IPGA value exceeds the setting reference value by
GAIN operation, IPGA does not become the larger than the reference value.
For example, when REF=30H, RATT=2 step, IPGA=2FH, IPGA will become 2FH + 2step =
31H by auto recovery operation, but IPGA value becomes 30H as REF value is 30H.
IPGA should be certainly set to the same value or smaller than REF value before entering
full-auto mode .
DATA
RESET
GAIN(dB)
MIC
LINE
68H
+28.0
+8.0
67H
+27.5
+7.5
66H
+27.0
+7.0
:
:
:
30H
0.0
-20.0
2FH
-0.5
-20.5
:
:
:
21H
-7.5
-27.5
20H
-8.0
-28.0
1FH
-9.0
-29.0
1EH
-10.0
-30.0
:
:
:
09H
-31.0
-51.0
08H
-32.0
-52.0
07H
-34.0
-54.0
06H
-36.0
-56.0
05H
-38.0
-58.0
04H
-40.0
-60.0
03H
-44.0
-64.0
02H
-48.0
-68.0
01H
-52.0
-72.0
STEP
LEVEL
0.5dB
73
1dB
24
2dB
4
4dB
3
00H
MUTE
MUTE
1
Table 14 . Reference Value Setting in Auto Recovery operation
These bits are reset by PD pin ="L", then inhibits writing to these bits.
M0026-E-00
1998/08
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ASAHI KASEI
[AK4516A]
SYSTEM DESIGN
Figure 13 shows the system connection example. An evaluation board [AKD4516A] is available which
demonstrates the optimum layout, power supply arrangement and measurement results.
Figure 13 . Typical Connection Diagram
NOTE:
- LRCK=fs, SCLK ≥ 32fs or 64fs, MCLK=256fs or 384fs
- Power supply lines of VA and VD should be distributed separately from the point with low
impedance of regulator or connecting to the resistor of 10 ohms.
- When LOUT(ROUT) drives some capacitive load, some resistor should be added in series
between LOUT(ROUT) and capacitive load.
- The capacitor value on VCOM depends on low frequency noise level of power supply.
M0026-E-00
1998/08
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ASAHI KASEI
[AK4516A]
1. Grounding and Power Supply Decoupling
The AK4516A requires careful attenuation to power supply and grounding arrangements. When VA and VD are
supplied separately, VA should not be the higher voltage than VD. If so not, VA is supplied from analog supply in
system and VD is supplied from VA via 10 ohms resistor.(refer to Figure 13 )
System analog ground and digital ground should be connected together near to where the supplies are brought
onto the printed circuit board. Decoupling capacitors should be as near to the AK4516A as possible, with the small
value ceramic capacitor being nearest.
2. Voltage Reference
VCOM is a signal ground of this chip. An electrolytic less than 4.7uF in parallel with a 0.1uF ceramic capacitor
attached to these pins eliminates the effects of high frequency noise. No load current maybe drawn from VCOM pin.
All signals, especially clock, should be kept away from the VA, VCML, VCMR, VCOM pins in order to avoid
unwanted coupling into the AK4516A.
3. Analog Inputs
ADC inputs are single-ended and internally biased to VCML & VCMR with 50kΩ (typ). The input signal range scales
with the supply voltage and nominally 0.57 x VA Vpp(typ). The ADC output data format is 2's compliment. The output
code is 7FFFH(@16bit) for input above a positive full scale and 8000H(@16bit) for input below a negative full scale.
Ideal code is 0000H(@16bit) with no input signal.
4. Analog Outputs
The analog outputs are also single-ended and centered around the VCOM voltage. The input signal range scales
with the supply voltage and nominally 0.6 x VA Vpp(typ). The DAC input data format is 2's compliment. The output
voltage is a positive full scale for 7FFFH(@16bit) and a negative full scale for 8000H(@16bit). The ideal output is
VCOM voltage for 0000H(@16bit). If the noise generated by the delta-sigma modulator beyond the audio band
would be the problem, the attenuation by external filter is required.
M0026-E-00
1998/08
- 36 -
ASAHI KASEI
[AK4516A]
PACKAGE
z 24pin VSOP (Unit: mm)
NOTE: Dimension “*” does not include mold flash.
Material & Lead finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder plate
M0026-E-00
1998/08
- 37 -
ASAHI KASEI
[AK4516A]
MARKING
Contents of AAXXXX
AA:
Lot#
XXXX: Date Code
M0026-E-00
1998/08
- 38 -
IMPORTANT NOTICE
zThese products and their specifications are subject to change without notice. Before
considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM)
sales office or authorized distributor concerning their current status.
zAKM assumes no liability for infringement of any patent, intellectual property, or other
right in the application or use of any information contained herein.
zAny export of these products, or devices or systems containing them, may require an
export license or other official approval under the law and regulations of the country of
export pertaining to customs and tariffs, currency exchange, or strategic materials.
zAKM products are neither intended nor authorized for use as critical components in any
safety, life support, or other hazard related device or system, and AKM assumes no
responsibility relating to any such use, except with the express written consent of the
Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or
maintenance of safety or for applications in medicine, aerospace, nuclear energy, or
other fields, in which its failure to function or perform may reasonably be expected to
result in loss of life or in significant injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be
expected to result, whether directly or indirectly, in the loss of the safety or
effectiveness of the device or system containing it, and which must therefore meet
very high standards of performance and reliability.
zIt is the responsibility of the buyer or distributor of an AKM product who distributes,
disposes of, or otherwise places the product with a third party to notify that party in
advance of the above content and conditions, and the buyer or distributor agrees to
assume any and all responsibility and liability for and hold AKM harmless from any and
all claims arising from the use of said product in the absence of such notification.