Data Sheet 26184.24C 3967 MICROSTEPPING DRIVER WITH TRANSLATOR PWM TIMER 24 PFD REF 1 RC 2 2 23 RC 1 SLEEP 3 22 RESET OUT2B 4 21 OUT1B LOAD SUPPLY2 5 GND 6 19 GND GND 7 18 GND SENSE2 8 17 SENSE1 OUT2A 9 16 OUT1A STEP 10 DIR 11 MS1 12 ÷8 VBB2 VBB1 TRANSLATOR & CONTROL LOGIC VCC LOAD 20 SUPPLY1 15 ENABLE 14 LOGIC SUPPLY 13 MS2 Dwg. PP-075-2 ABSOLUTE MAXIMUM RATINGS at TA = +25°C Load Supply Voltage, VBB ............. 30 V Output Current, IOUT Continuous ..................... ±750 mA* Peak ................................. ±850 mA Logic Supply Voltage, VCC ........... 7.0 V Logic Input Voltage Range, VIN (tw >30 ns) ............. -0.3 V to +7.0 V (tw <30 ns) ................ -1 V to +7.0 V Sense Voltage, VSENSE ............... 0.68 V Reference Voltage, VREF ................ VCC Package Power Dissipation, PD ................................. See page 8 Operating Temperature Range, TA ........................... -20°C to +85°C Junction Temperature, TJ ......... +150°C Storage Temperature Range, TS ......................... -55°C to +150°C * Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. The A3967SLB is a complete microstepping motor driver with built-in translator. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step modes, with output drive capability of 30 V and ±750 mA. The A3967SLB includes a fixed off-time current regulator that has the ability to operate in slow, fast, or mixed current-decay modes. This current-decay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. The translator is the key to the easy implementation of the A3967SLB. By simply inputting one pulse on the STEP input the motor will take one step (full, half, quarter, or eighth depending on two logic inputs). There are no phase-sequence tables, high-frequency control lines, or complex interfaces to program. The A3967SLB interface is an ideal fit for applications where a complex µP is unavailable or over-burdened. Internal circuit protection includes thermal shutdown with hysteresis, under-voltage lockout (UVLO) and crossover-current protection. Special power-up sequencing is not required. The A3967SLB is supplied in a 24-lead SOIC with copper batwing tabs. The tabs are at ground potential and need no insulation. A leadfree (100% matte tin leadframe) version is also available. FEATURES ■ ■ ■ ■ ■ ■ ■ ±750 mA, 30 V Output Rating Satlington™ Sink Drivers Automatic Current-Decay Mode Detection/Selection 3.0 V to 5.5 V Logic Supply Voltage Range Mixed, Fast, and Slow Current-Decay Modes Internal UVLO and Thermal Shutdown Circuitry Crossover-Current Protection Always order by complete part number: Part Number A3967SLB A3967SLB-T Package 24-lead batwing SOIC 24-lead batwing SOIC; Lead-free 3967 MICROSTEPPING DRIVER WITH TRANSLATOR FUNCTIONAL BLOCK DIAGRAM LOGIC SUPPLY VCC LOAD SUPPLY UVLO AND FAULT DETECT 14 REF. SUPPLY REF VBB1 20 1 ÷8 DAC SENSE + - RC1 OUT1A PWM LATCH BLANKING MIXED DECAY 23 16 OUT1B 21 PWM TIMER 3 STEP 10 MS1 12 MS2 13 SLEEP 17 CONTROL LOGIC RESET 22 SENSE1 TRANSLATOR DIR 11 3 5 VBB2 ENABLE 15 VPF OUT2A 24 PFD 9 PWM TIMER 3 OUT2B 4 PWM LATCH BLANKING MIXED DECAY 2 RC2 + - DAC 8 6 7 SENSE2 18 19 Table 1. Microstep Resolution Truth Table MS1 L H L H 2 MS2 L L H H Resolution Full step (2 phase) Half step Quarter step Eighth step 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2002, 2003 Allegro MicroSystems, Inc. Dwg. FP-050-3A 3967 MICROSTEPPING DRIVER WITH TRANSLATOR ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 30 V, VCC = 3.0 V to 5.5V (unless otherwise noted) Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units 4.75 – 30 V During sleep mode 0 – 30 V VOUT = VBB – <1.0 20 µA VOUT = 0 V – <-1.0 -20 µA Source driver, IOUT = -750 mA – 1.9 2.1 V Source driver, IOUT = -400 mA – 1.7 2.0 V Sink driver, IOUT = 750 mA – 0.65 1.3 V Sink driver, IOUT = 400 mA – 0.21 0.5 V IF = 750 mA – 1.4 1.6 V IF = 400 mA – 1.1 1.4 V Outputs enabled – – 5.0 mA RESET high – – 200 µA Sleep mode – – 20 µA 3.0 5.0 5.5 V Output Drivers Load Supply Voltage Range Output Leakage Current Output Saturation Voltage Clamp Diode Forward Voltage Motor Supply Current VBB ICEX VCE(sat) VF IBB Operating Control Logic Logic Supply Voltage Range VCC Logic Input Voltage VIN(1) 0.7VCC – – V VIN(0) – – 0.3VCC V Logic Input Current Operating IIN(1) VIN = 0.7VCC -20 <1.0 20 µA IIN(0) VIN = 0.3VCC -20 <1.0 20 µA 500* – – kHz Maximum STEP Frequency fSTEP Blank Time tBLANK Rt = 56 kΩ, Ct = 680 pF 700 950 1200 ns toff Rt = 56 kΩ, Ct = 680 pF 30 38 46 µs Fixed Off Time continued next page … www.allegromicro.com 3 3967 MICROSTEPPPING DRIVER WITH TRANSLATOR ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 30 V, VCC = 3.0 V to 5.5V (unless otherwise noted) Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units – 0.6VCC – V Control Logic (cont’d) Mixed Decay Trip Point PFDH PFDL Ref. Input Voltage Range VREF Reference Input Impedance ZREF Gain (Gm) Error EG (note 3) Thermal Shutdown Temp. Thermal Shutdown Hysteresis UVLO Enable Threshold UVLO Hysteresis Logic Supply Current Operating VREF = 2 V, Phase Current = 38.37% † – V – VCC V 120 160 200 kΩ – – ±10 % – – ±5.0 % VREF = 2 V, Phase Current = 100.00% † – – ±5.0 % – 165 – °C Increasing VCC ∆VUVLO ICC 0.21VCC VREF = 2 V, Phase Current = 70.71% † TJ ∆TJ VUVLO – 1.0 Outputs enabled – 15 – °C 2.45 2.7 2.95 V 0.05 0.10 – V – 50 65 mA Outputs off – – 9.0 mA Sleep mode – – 20 µA * Operation at a step frequency greater than the specified minimum value is possible but not warranteed. † 8 microstep/step operation. NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal. 3. EG = ([VREF/8] – VSENSE)/(VREF/8) 4 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3967 MICROSTEPPING DRIVER WITH TRANSLATOR Functional Description Device Operation. The A3967 is a complete microstepping motor driver with built in translator for easy operation with minimal control lines. It is designed to operate bipolar stepper motors in full-, half-, quarterand eighth-step modes. The current in each of the two output H-bridges is regulated with fixed off time pulsewidth modulated (PWM) control circuitry. The H-bridge current at each step is set by the value of an external current sense resistor (RS), a reference voltage (VREF), and the DAC’s output voltage controlled by the output of the translator. At power up, or reset, the translator sets the DACs and phase current polarity to initial home state (see figures for home-state conditions), and sets the current regulator for both phases to mixed-decay mode. When a step command signal occurs on the STEP input the translator automatically sequences the DACs to the next level (see table 2 for the current level sequence and current polarity). The microstep resolution is set by inputs MS1 and MS2 as shown in table 1. If the new DAC output level is lower than the previous level the decay mode for that H-bridge will be set by the PFD input (fast, slow or mixed decay). If the new DAC level is higher or equal to the previous level then the decay mode for that H-bridge will be slow decay. This automatic current-decay selection will improve microstepping performance by reducing the distortion of the current waveform due to the motor BEMF. Reset Input (RESET). The RESET input (active low) sets the translator to a predefined home state (see figures for home state conditions) and turns off all of the outputs. STEP inputs are ignored until the RESET input goes high. Step Input (STEP). A low-to-high transition on the STEP input sequences the translator and advances the motor one increment. The translator controls the input to the DACs and the direction of current flow in each winding. The size of the increment is determined by the state of inputs MS1 and MS2 (see table 1). www.allegromicro.com Microstep Select (MS1 and MS2). Input terminals MS1 and MS2 select the microstepping format per table 1. Changes to these inputs do not take effect until the STEP command (see figure). Direction Input (DIR). The state of the DIRECTION input will determine the direction of rotation of the motor. Internal PWM Current Control. Each H-bridge is controlled by a fixed off time PWM current-control circuit that limits the load current to a desired value (ITRIP). Initially, a diagonal pair of source and sink outputs are enabled and current flows through the motor winding and RS. When the voltage across the current-sense resistor equals the DAC output voltage, the current-sense comparator resets the PWM latch, which turns off the source driver (slow-decay mode) or the sink and source drivers (fast- or mixed-decay modes). The maximum value of current limiting is set by the selection of RS and the voltage at the VREF input with a transconductance function approximated by: ITRIPmax = VREF/8RS The DAC output reduces the VREF output to the current-sense comparator in precise steps (see table 2 for % ITRIPmax at each step). ITRIP = (% ITRIPmax/100) x ITRIPmax Fixed Off-Time. The internal PWM current-control circuitry uses a one shot to control the time the driver(s) remain(s) off. The one shot off-time, toff, is determined by the selection of an external resistor (RT) and capacitor (CT) connected from the RC timing terminal to ground. The off time, over a range of values of CT = 470 pF to 1500 pF and RT = 12 kΩ to 100 kΩ is approximated by: toff = RTCT 5 3967 MICROSTEPPING DRIVER WITH TRANSLATOR Functional Description (cont’d) RC Blanking. In addition to the fixed off time of the PWM control circuit, the CT component sets the comparator blanking time. This function blanks the output of the current-sense comparator when the outputs are switched by the internal current-control circuitry. The comparator output is blanked to prevent false over-current detection due to reverse recovery currents of the clamp diodes, and/ or switching transients related to the capacitance of the load. The blank time tBLANK can be approximated by: Percent Fast Decay Input (PFD). When a STEP input signal commands a lower output current from the previous step, it switches the output current decay to either slow-, fast-, or mixed-decay depending on the voltage level at the PFD input. If the voltage at the PFD input is greater than 0.6VCC then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VCC then fast-decay mode is selected. Mixed decay is between these two levels. tBLANK = 1400CT Mixed Decay Operation. If the voltage on the PFD input is between 0.6VCC and 0.21VCC, the bridge will operate in mixed-decay mode depending on the step sequence (see figures). As the trip point is reached, the device will go into fast-decay mode until the voltage on the RC terminal decays to the voltage applied to the PFD terminal. The time that the device operates in fast decay is approximated by: Shutdown. In the event of a fault (excessive junction temperature) the outputs of the device are disabled until the fault condition is removed. At power up, and in the event of low VCC, the under-voltage lockout (UVLO) circuit disables the drivers and resets the translator to the home state. Sleep Mode (SLEEP). An active-low control input used to minimize power consumption when not in use. This disables much of the internal circuitry including the outputs. A logic high allows normal operation and startup of the device in the home position. Typical output saturation voltages showing Satlington™ sink-driver operation. tFD = RTCTIn (0.6VCC/VPFD) After this fast decay portion, tFD, the device will switch to slow-decay mode for the remainder of the fixed off-time period. 2.5 OUTPUT SATURATION VOLTAGE IN VOLTS Enable Input (ENABLE). This active-low input enables all of the outputs. When logic high the outputs are disabled. Inputs to the translator (STEP, DIRECTION, MS1, MS2) are all active independent of the ENABLE input state. TA = +25°C 2.0 SOURCE DRIVER 1.5 1.0 0.5 SINK DRIVER 0 200 300 400 500 600 700 800 OUTPUT CURRENT IN MILLIAMPERES Dwg. GP-064-4 6 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3967 MICROSTEPPING DRIVER WITH TRANSLATOR Timing Requirements (TA = +25°C, VCC = 5 V, Logic Levels are VCC and Ground) STEP 50% C A D B MS1/MS2/ DIR/RESET E SLEEP Dwg. WP-042 A. Minimum Command Active Time Before Step Pulse (Data Set-Up Time) ..... 200 ns B. Minimum Command Active Time After Step Pulse (Data Hold Time) ............ 200 ns C. Minimum STEP Pulse Width ...................... 1.0 µs D. Minimum STEP Low Time ......................... 1.0 µs E. Maximum Wake-Up Time ......................... 1.0 ms www.allegromicro.com 7 3967 MICROSTEPPING DRIVER WITH TRANSLATOR Applications Information Layout. The printed wiring board should use a heavy ground plane. For optimum electrical and thermal performance, the driver should be soldered directly onto the board. The load supply terminal, VBB, should be decoupled with an electrolytic capacitor (>47 µF is recommended) placed as close to the device as possible. To avoid problems due to capacitive coupling of the high dv/dt switching transients, route the bridge-output traces away from the sensitive logic-input traces. Always drive the logic inputs with a low source impedance to increase noise immunity. Grounding. A star ground system located close to the driver is recommended. The 24-lead SOIC has the analog ground and the power ground internally bonded to the power tabs of the package (leads 6, 7, 18, and 19). Current Sensing. To minimize inaccuracies caused by ground-trace IR drops in sensing the output current level, the current-sense resistor (RS) should have an independent ground return to the star ground of the device. This path should be as short as possible. For low-value sense resistors the IR drops in the printed wiring board sense resistor’s traces can be significant and should be taken into account. The use of sockets should be avoided as they can introduce variation in RS due to their contact resistance. Allegro MicroSystems recommends a value of RS given by RS = 0.5/ITRIPmax Thermal protection. Circuitry turns off all drivers when the junction temperature reaches 165°C, typically. It is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. Thermal shutdown has a hysteresis of approximately 15°C. *RθJA = 35°C/W on JEDEC standard “High-K” four-layer board per JESD 51-7. †RθJA = 50°C/W on typical two-sided PCB with 1.3 square inches copper ground on each side. See also, Application Note 29501.5, Improving Batwing Power Dissipation. 8 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3967 MICROSTEPPPING DRIVER WITH TRANSLATOR Table 2. Step Sequencing Home State = 45º Step Angle, DIR = H Full Step Half Step ¼ Step ⅛ Step Phase 1 Current (%Itripmax) (%) 1 1 1 100.00 0.00 0.0 2 98.08 19.51 11.3 3 92.39 38.27 22.5 4 83.15 55.56 33.8 5 70.71 70.71 45.0 6 55.56 83.15 56.3 7 38.27 92.39 67.5 8 19.51 98.08 78.8 9 0.00 100.00 90.0 10 –19.51 98.08 101.3 11 –38.27 92.39 112.5 12 –55.56 83.15 123.8 13 –70.71 70.71 135.0 14 –83.15 55.56 146.3 15 –92.39 38.27 157.5 16 –98.08 19.51 168.8 17 –100.00 0.00 180.0 18 –98.08 –19.51 191.3 19 –92.39 –38.27 202.5 20 –83.15 –55.56 213.8 21 –70.71 –70.71 225.0 22 –55.56 –83.15 236.3 23 –38.27 –92.39 247.5 24 –19.51 –98.08 258.8 25 0.00 –100.00 270.0 26 19.51 –98.08 281.3 27 38.27 –92.39 292.5 28 55.56 –83.15 303.8 29 70.71 –70.71 315.0 30 83.15 –55.56 326.3 31 92.39 –38.27 337.5 32 98.08 –19.51 348.8 2 1 2 3 4 3 5 6 2 4 7 8 5 9 10 3 6 11 12 7 13 14 4 8 15 16 www.allegromicro.com Phase 2 Current (%Itripmax) (%) Step Angle (º) 9 3967 MICROSTEPPING DRIVER WITH TRANSLATOR Full Step Operation MS1 = MS2 = L, DIR = H STEP INPUT SLOW DECAY 70.7% PHASE 1 CURRENT –70.7% SLOW DECAY 70.7% PHASE 2 CURRENT –70.7% Dwg. WK-004-19 The vector addition of the output currents at any step is 100%. 10 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3967 MICROSTEPPING DRIVER WITH TRANSLATOR Half Step Operation MS1 = H, MS2 = L, DIR = H SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY STEP INPUT 100% 70.7% PHASE 1 CURRENT –70.7% –100% 100% 70.7% PHASE 2 CURRENT –70.7% –100% Dwg. WK-004-18 The mixed-decay mode is controlled by the percent fast decay voltage (VPFD). If the voltage at the PFD input is greater than 0.6VCC then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VCC then fast-decay mode is selected. Mixed decay is between these two levels. www.allegromicro.com 11 3967 MICROSTEPPING DRIVER WITH TRANSLATOR Quarter Step Operation MS1 = L, MS2 = H, DIR = H STEP INPUT SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY 100% 70.7% 38.3% PHASE 1 CURRENT –38.3% –70.7% –100% 100% 70.7% 38.3% PHASE 2 CURRENT –38.3% –70.7% –100% Dwg. WK-004-17 The mixed-decay mode is controlled by the percent fast decay voltage (VPFD). If the voltage at the PFD input is greater than 0.6VCC then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VCC then fast-decay mode is selected. Mixed decay is between these two levels. 12 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3967 MICROSTEPPING DRIVER WITH TRANSLATOR 8 Microstep/Step Operation MS1 = MS2 = H, DIR = H STEP INPUT SLOW DECAY MIXED DECAY SLOW DECAY MIXED DECAY MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY 100% 70.7% 38.3% PHASE 1 CURRENT –38.3% –70.7% –100% 100% 70.7% 38.3% PHASE 2 CURRENT –38.3% –70.7% –100% Dwg. WK-004-16 The mixed-decay mode is controlled by the percent fast decay voltage (VPFD). If the voltage at the PFD input is greater than 0.6VCC then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VCC then fast-decay mode is selected. Mixed decay is between these two levels. www.allegromicro.com 13 3967 MICROSTEPPING DRIVER WITH TRANSLATOR Terminal List Terminal Name REF RC2 SLEEP OUT2B LOAD SUPPLY2 GND SENSE2 OUT2A STEP DIR MS1 MS2 LOGIC SUPPLY ENABLE OUT1A SENSE1 GND LOAD SUPPLY1 OUT1B RESET RC1 PFD 14 Terminal Description Gm reference input Analog input for fixed offtime – bridge 2 Logic input H bridge 2 output B VBB2, the load supply for bridge 2 Analog and power ground Sense resistor for bridge 2 H bridge 2 output A Logic input Logic Input Logic input Logic input VCC, the logic supply voltage Logic input H bridge 1 output A Sense resistor for bridge 1 Analog and power ground VBB1, the load supply for bridge 1 H bridge 1 output B Logic input Analog Input for fixed offtime – bridge 1 Mixed decay setting Terminal Number 1 2 3 4 5 6, 7 8 9 10 11 12 13 14 15 16 17 18, 19 20 21 22 23 24 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3967 MICROSTEPPING DRIVER WITH TRANSLATOR 24 13 0.0125 0.0091 0.419 0.394 0.2992 0.2914 0.050 0.016 0.020 0.013 1 2 3 0.6141 0.5985 0.050 BSC Dimensions in Inches (for reference only) 0° TO 8° NOTE 1 NOTE 3 0.0926 0.1043 0.0040 MIN. Dwg. MA-008-25A in 24 0.32 0.23 10.65 10.00 7.60 7.40 1.27 0.40 0.51 0.33 1 2 3 15.60 15.20 1.27 BSC 0° TO 8° Dimensions in Millimeters (controlling dimensions) NOTE 1 NOTE 3 2.65 2.35 0.10 MIN. NOTES: 1. 2. 3. 4. Dwg. MA-008-25A mm Exact body and lead configuration at vendor’s option within limits shown. Lead spacing tolerance is non-cumulative. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece. Supplied in standard sticks/tubes of 31 devices or add “TR” to part number for tape and reel. www.allegromicro.com 15 3967 MICROSTEPPING DRIVER WITH TRANSLATOR The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. 16 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000