SCDS087G − APRIL 1999 − REVISED APRIL 2005 D Member of the Texas Instruments D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus Family Designed to Be Used in Voltage-Limiting Applications 6.5-Ω On-State Connection Between Ports A and B Flow-Through Pinout for Ease of Printed Circuit Board Trace Routing Direct Interface With GTL+ Levels ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) GND A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 description/ordering information The SN74TVC16222A provides 23 parallel NMOS pass transistors with a common gate. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The device can be used as a 22-bit switch, with the gates cascaded together to a reference transistor. The low-voltage side of each pass transistor is limited to a voltage set by the reference transistor. This is done to protect components with inputs that are sensitive to high-state voltage-level overshoots. (See Application Information in this data sheet.) 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 GATE B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 All of the transistors in the TVC array have the same electrical characteristics; therefore, any one of them can be used as the reference transistor. Because, within the device, the characteristics from transistor to transistor are equal, the maximum output high-state voltage (VOH) is approximately the reference voltage (VREF), with minimal deviation from one output to another. This is a benefit of the TVC solution over discrete devices. Because the fabrication of the transistors is symmetrical, either port connection of each bit can be used as the low-voltage side, and the I/O signals are bidirectional through each FET. ORDERING INFORMATION TOP-SIDE MARKING Tube SN74TVC16222DL Tape and reel SN74TVC16222DLR TSSOP − DGG Tape and reel SN74TVC16222DGGR TVC16222A TVSOP − DGV Tape and reel SN74TVC16222DGVR TW222A SSOP − DL −40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA TVC16222A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and TI are trademarks of Texas Instruments. Copyright 2005, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCDS087G − APRIL 1999 − REVISED APRIL 2005 simplified schematic GATE B1 B2 B3 B4 B23 48 47 46 45 44 25 1 2 3 4 5 24 GND A1 A2 A3 A4 A23 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input/output voltage range, VI/O (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions MIN TYP MAX UNIT VI/O VGATE Input/output voltage 0 5.5 V GATE voltage 0 5.5 V IPASS TA Pass-transistor current 64 mA 85 °C 20 Operating free-air temperature −40 application operating conditions (see Figure 3) 2 VBIAS VGATE BIAS voltage VREF VDPU Reference voltage IPASS IREF Pass-transistor current TA Operating free-air temperature GATE voltage Drain pullup voltage MIN TYP MAX VREF + 0.6 VREF + 0.6 2.1 5 V 2.1 5 V 0 1.5 4.4 V 2.36 2.5 2.64 14 20 Reference-transistor current −40 • DALLAS, TEXAS 75265 V mA µA 5 POST OFFICE BOX 655303 UNIT 85 °C SCDS087G − APRIL 1999 − REVISED APRIL 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOL Ci(GATE) Cio(off) Cio(on) ron‡ TEST CONDITIONS VBIAS = 0, IREF = 5 mA, VDPU = 2.625 V, II = −18 mA VREF = 1.365 V, RDPU = 150 Ω MIN TYP† VS = 0.175 V, See Figure 2 VI = 3 V or 0 VO = 3 V or 0 MAX UNIT −1.2 V 350 mV 73 VO = 3 V or 0 IREF = 5 mA, VDPU = 2.625 V, VREF = 1.365 V, RDPU = 150 Ω pF 4 12 pF 12 25 pF 12.5 Ω VS = 0.175 V, See Figure 2 † All typical values are at TA = 25°C. ‡ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower voltage of the two (A or B) terminals. electrical characteristics from −40°C to 75°C PARAMETER ron‡ TEST CONDITIONS IREF = 5 mA, VDPU = 2.625 V, VREF = 1.552 V, RDPU = 150 Ω MIN VS = 0.175 V, See Figure 2 MAX 10 UNIT Ω ‡ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower voltage of the two (A or B) terminals. switching characteristics over recommended operating VDPU = 2.36 V to 2.64 V (unless otherwise noted) (see Figure 1) free-air PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 temperature range, MIN MAX UNIT 0 4 0 4 ns 3 SCDS087G − APRIL 1999 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VDPU 3.3 V Motherboard Interface 200 kΩ † GATE 48 RDPU = 150 Ω RDPU = 150 Ω † † RDPU = 150 Ω † RDPU = 150 Ω B1 (VBIAS) 47 B2 46 B3 45 B4 44 B23 25 2 A1 (VREF) 3 A2 (VS) 4 A3 (VS) 5 A4 (VS) 24 A23 (VS) ‡ TVC16222A 1 § § § § Open-Drain Test Interface TESTER CALIBRATION SETUP (see Note C) GATE 2.5 V Input Tester 1.25 V 1.25 V 0V tPLHREF DEFINITION Output tested Output reference Input tested SYMBOL † ‡ § tPHLREF 2.5 V Output Reference 1.25 V 1.25 V VOL tPLHDUT tPHLDUT 2.5 V Output Device Under Test 1.25 V tPLH (see Note D) 1.25 V VOL tPHL (see Note E) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. B. The outputs are measured one at a time, with one transition per measurement. C. Test procedure: tPLHREF and tPHLREF are obtained by measuring the propagation delay of a reference measuring point. tPLHDUT and tPHLDUT are obtained by measuring the propagation delay of the device under test. D. tPLH = tPLHDUT − tPLHREF E. tPHL = tPHLDUT − tPHLREF Figure 1. Tester Calibration Setup and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCDS087G − APRIL 1999 − REVISED APRIL 2005 APPLICATION INFORMATION TVC background information In personal computer (PC) architecture, there are industry-accepted bus standards. These standards define, among other things, the I/O voltage levels at which the bus communicates. Examples include the GTL+ host bus, the AGP graphics port, and the PCI local bus. In new designs, the system components must communicate with existing bus infrastructure. Providing an evolutionary upgrade path is important in the design of PC architecture, but the existing bus standards must be preserved. To achieve the ever-present need for smaller, faster, lighter devices that draw less power, yet have faster performance, most new high-performance digital integrated circuits are designed and produced with advanced submicron semiconductor process technologies. These devices have thin gate-oxide or short channel lengths and very low absolute-maximum voltages that can be tolerated at the inputs/outputs (I/Os) without causing damage. In many cases, the I/Os of these devices are not tolerant of the high-state voltage levels on the preexisting buses with which they must communicate. Therefore, it became necessary to protect the I/Os of devices by limiting the I/O voltages. The Texas Instruments (TI) translation voltage-clamp (TVC) family is designed specifically for protecting sensitive I/Os (see Figure 2). The information in this data sheet describes the I/O-protection application of the TVC family and should enable the design engineer to successfully implement an I/O-protection circuit utilizing the TI TVC solution. Low-Voltage I/O Device TVC Family Voltage-Clamp Device Standard-Voltage I/O Bus Figure 2. Thin Gate-Oxide Protection Application POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCDS087G − APRIL 1999 − REVISED APRIL 2005 APPLICATION INFORMATION TVC voltage-limiting application For the voltage-limiting configuration, the common GATE input must be connected to one side (A or B) of any one of the transistors (see Figure 3). This connection determines the VBIAS input of the reference transistor. The VBIAS input is connected through a pullup resistor (typically 200 kΩ ) to the VDD supply. A filter capacitor on VBIAS is recommended. The opposite side of the reference transistor is used as the reference voltage (VREF) connection. The VREF input must be less than VDDREF − 1 V to bias the reference transistor into conduction. The reference transistor regulates the gate voltage (VGATE) of all the pass transistors. VGATE is determined by the characteristic gate-to-source voltage difference (VGS) because VGATE = VREF + VGS. The low-voltage side of the pass transistors has a high-level voltage limited to a maximum of VGATE − VGS, or VREF. VDDREF = 3.3 V Motherboard Interface GATE† 48 VDPU 200 kΩ 150 Ω 150 Ω 150 Ω 150 Ω B1 (VBIAS)† 47 B2 46 B3 45 B4 44 B23 25 2 A1 (VREF)† 3 A2 4 A3 5 A4 24 A23 TVC16222A 1 Open-Drain CPU Interface † VREF and VBIAS can be applied to any one of the pass transistors. GATE must be connected externally to VBIAS. Figure 3. Typical Application Circuit 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCDS087G − APRIL 1999 − REVISED APRIL 2005 APPLICATION INFORMATION electrical characteristics The electrical characteristics of the NMOS transistors used in the TVC devices are illustrated by TI SPICE simulations. Figure 4 shows the test configuration for the TI SPICE simulations. The results, shown in Figures 5 and 6, show the current through a pass transistor versus the voltage at the source for different reference voltages. The plots of the dc characteristics clearly reveal that the device clamps at the desired reference voltage for the varying device environments. Figure 5 shows the V-I characteristics with low reference voltages and a reference-transistor drain-supply voltage of 3.3 V. To further investigate the spread of the V-I characteristic curves, VREF was held at 2.5 V and IREF was increased by raising VDDREF (see Figure 6). The result was a tighter grouping of the V-I curves. VDDREF GATE VDDPASS RDREF RDPASS VBIAS VDPASS VREF VSPASS Figure 4. TI SPICE-Simulation Schematic and Voltage-Node Names POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SCDS087G − APRIL 1999 − REVISED APRIL 2005 I PASS − Pass Current − mA APPLICATION INFORMATION VREF = 1 V VDDREF = 3.3 V RDREF = 200 kΩ RDPASS = 150 Ω VDDPASS = 3.3 V −2 −4 −6 −8 −10 −12 −14 −16 Weak Nominal Strong −18 −20 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 I PASS − Pass Current − mA VSPASS − Low Reference Voltage − V −2 VREF = 1.5 V VDDREF = 3.3 V RDREF = 200 kΩ RDPASS = 150 Ω VDDPASS = 3.3 V −4 −6 −8 −10 −12 −14 −16 Weak Nominal Strong −18 −20 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 I PASS − Pass Current − mA VSPASS − Low Reference Voltage − V VREF = 2 V VDDREF = 3.3 V RDREF = 200 kΩ RDPASS = 150 Ω VDDPASS = 3.3 V −2 −4 −6 −8 −10 −12 −14 −16 Weak Nominal Strong −18 −20 0.4 0.8 1.2 1.6 2.0 2.4 2.8 VSPASS − Low Reference Voltage − V Figure 5. V-I Electrical Characteristics at Low VREF Voltages 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3.2 SCDS087G − APRIL 1999 − REVISED APRIL 2005 I PASS − Pass Current − mA APPLICATION INFORMATION VREF = 2.5 V VDDREF = 3.3 V RDREF = 200 kΩ RDPASS = 150 Ω VDDPASS = 3.3 V −2 −4 −6 −8 −10 −12 −14 −16 Weak Nominal Strong −18 −20 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 I PASS − Pass Current − mA VSPASS − Low Reference Voltage − V VREF = 2.5 V VDDREF = 4 V RDREF = 200 kΩ RDPASS = 150 Ω VDDPASS = 3.3 V −2 −4 −6 −8 −10 −12 −14 −16 Weak Nominal Strong −18 −20 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 I PASS − Pass Current − mA VSPASS − Low Reference Voltage − V VREF = 2.5 V VDDREF = 5 V RDREF = 200 kΩ RDPASS = 150 Ω VDDPASS = 3.3 V −2 −4 −6 −8 −10 −12 −14 −16 Weak Nominal Strong −18 −20 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 VSPASS − Low Reference Voltage − V Figure 6. V-I Electrical Characteristics at VREF = 2.5 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SCDS087G − APRIL 1999 − REVISED APRIL 2005 APPLICATION INFORMATION features and benefits The TVC family has several features that benefit a system designer when implementing a sensitive-I/O-protection solution. Table 1 lists these features and their associated benefits. Table 1. Features and Benefits FEATURES BENEFITS Any FET can be used as the reference transistor. Ease of layout All FETs on one die, tight process control Very low spread of VO relative to VREF No active control logic (passive device) No logic power supply (VCC) required Flow-through pinout Ease of trace routing Devices offered in different bit widths and packages Optimizes design and cost effectiveness Designer flexibility with VREF input Allows migration to lower-voltage I/Os without board redesign conclusion The TI TVC family provides the designer with a solution for protection of circuits with I/Os that are sensitive to high-state voltage-level overshoots. The flexibility of TVC enables a low-voltage migration path for advanced designs to align with industry standards. frequently asked questions (FAQs) 1. Q: Can any of the transistors in the array be used as the reference transistor? A: Yes, any transistor can be used as long as its VBIAS pin is connected to the GATE pin. 2. Q: In the recommended operating conditions table of the data sheet, the typical VBIAS is 3.3 V. Should VBIAS be equal to or greater than VREF on the reference transistor? A: VBIAS is a variable that is determined by VREF. VBIAS is connected to VDD through a resistor to allow the bias voltage to be controlled by VREF. VDD can be as high as 5.5 V. VREF needs to be at least 1 V less than VDDREF on the reference transistor. 3. Q: Do both A and B ports have 5-V I/O tolerance or is 5-V I/O tolerance provided only on the low-voltage side? A: Both ports are 5-V tolerant. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74TVC16222ADGGRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74TVC16222ADGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74TVC16222ADGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74TVC16222ADGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74TVC16222ADL ACTIVE SSOP DL 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74TVC16222ADLG4 ACTIVE SSOP DL 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74TVC16222ADLR ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74TVC16222ADLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Apr-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 26-Apr-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74TVC16222ADGGR DGG 48 MLA 330 24 8.6 15.8 1.8 12 24 Q1 SN74TVC16222ADGVR DGV 48 MLA 330 24 6.8 10.1 1.6 12 24 Q1 SN74TVC16222ADLR DL 48 MLA 330 32 11.35 16.2 3.1 16 32 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74TVC16222ADGGR DGG 48 MLA 333.2 333.2 31.75 SN74TVC16222ADGVR DGV 48 MLA 333.2 333.2 31.75 SN74TVC16222ADLR DL 48 MLA 336.6 342.9 41.3 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Apr-2007 Pack Materials-Page 3 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. 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