AMICC A29DL322TG-80

A29DL32x Series
32 Megabit (4M x 8-Bit/2M x 16-Bit) CMOS 3.0 Volt-only,
Preliminary
Simultaneous Operation Flash Memory
Document Title
4M X 8 Bit / 2M X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
Revision History
Rev. No.
0.0
History
Issue Date
Remark
Initial issue
May 25, 2005
Preliminary
PRELIMINARY (May, 2005, Version 0.0)
AMIC Technology, Corp.
A29DL32x Series
32 Megabit (4M x 8-Bit/2M x 16-Bit) CMOS 3.0 Volt-only,
Preliminary
Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
Data Polling and Toggle Bits
- Provides a software method of detecting the status of
program or erase cycles
Unlock Bypass Program command
- Reduces overall programming time when issuing
multiple program command sequences
ARCHITECTURAL ADVANTAGES
Simultaneous Read/Write operations
- Data can be continuously read from one bank while
executing erase/program functions in other bank
- Zero latency between read and write operations
Multiple bank architectures
- Three devices available with different bank sizes (refer to
Table 2)
Package options
- 48-ball TFBGA
- 48-pin TSOP
Top or bottom boot block
Manufactured on 0.18 µm process technology
- Compatible with AMD AM29DL32xD device
Compatible with JEDEC standards
- Pinout and software compatible with single-power-supply
flash standard
HARDWARE FEATURES
Any combination of sectors can be erased
Ready/ Busy output (RY/ BY )
- Hardware method for detecting program or erase cycle
completion
Hardware reset pin ( RESET )
- Hardware method of resetting the internal state machine
to reading array data
WP /ACC input pin
- Write protect ( WP ) function allows protection of two
outermost boot sectors, regardless of sector protect
status
- Acceleration (ACC) function accelerates program timing
Sector protection
- Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program
or erase operation within that sector
- Temporary Sector Unprotect allows changing data in
protected sectors in-system
PERFORMANCE CHARACTERISTICS
High performance
- Access time as fast as 70ns
- Program time: 7µs/word typical utilizing Accelerate
function
Ultra low power consumption (typical values)
- 2mA active read current at 1MHz
- 10mA active read current at 5MHz
- 200nA in standby or automatic sleep mode
Minimum 1 million write cycles guaranteed per sector
20 Year data retention at 125°C
- Reliable operation for the life of the system
SOFTWARE FEATURES
Supports Common Flash Memory Interface (CFI)
Erase Suspend/Erase Resume
- Suspends erase operations to allow programming in
same bank
Software temporary sector/sector block unprotect command
Software sector protect/unprotect command
PRELIMINARY (May, 2005, Version 0.0)
1
AMIC Technology, Corp.
A29DL32x Series
GENERAL DESCRIPTION
A29DL32x Features
The A29DL32x family consists of 32 megabit, 3.0 volt-only
flash memory devices, organized as 2,097,152 words of 16
bits each or 4,194,304 bytes of 8 bits each. Word mode data
appears on I/O0–I/O15; byte mode data appears on I/O0–I/O7.
The device is designed to be programmed in-system with the
standard 3.0 volt VCC supply, and can also be programmed
in standard EPROM programmers.
The device is available with an access time of 70, 80, 90, or
120 ns. The devices are offered in 48-pin TSOP and 48-ball
Fine-pitch TFBGA. Standard control pins—chip enable ( CE ),
The device offers complete compatibility with the JEDEC
single-power-supply Flash command set standard.
Commands are written to the command register using
standard microprocessor write timings. Reading data out of
the device is similar to reading from other Flash or EPROM
devices.
The host system can detect whether a program or erase
operation is complete by using the device status bits:
RY/ BY pin, I/O7 ( Data Polling) and I/O6/I/O2 (toggle bits).
After a program or erase cycle has been completed, the
device automatically returns to reading array data.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection measures include a low VCC
detector that automatically inhibits write operations during
power transitions. The hardware sector protection feature
disables both program and erase operations in any
combination of the sectors of memory. This can be achieved
in-s y s t e m or via programming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system
can also place the device into the standby mode. Power
consumption is greatly reduced in both modes.
write enable ( WE ), and output enable ( OE )—control
normal read and write operations, and avoid bus contention
issues.
The device requires only a single 3.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
Simultaneous Read/Write Operations with Zero
Latency
The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory space into
two banks. The device can improve overall system
performance by allowing a host system to program or erase
in one bank, then immediately and simultaneously read from
the other bank, with zero latency. This releases the system
from waiting for the completion of program or erase
operations.
The A29DL32x devices use multiple bank architectures to
provide flexibility for different applications. Three devices are
available with these bank sizes:
Device
DL322
DL323
DL324
PRELIMINARY
Bank 1
4 Mb
8 Mb
16 Mb
Bank 2
28 Mb
24 Mb
16 Mb
(May, 2005, Version 0.0)
2
AMIC Technology, Corp.
A29DL32x Series
Pin Configurations
TSOP (I)
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
BYTE
VSS
I/O 15 (A-1)
I/O 7
I/O14
I/O 6
I/O13
I/O 5
I/O12
I/O 4
VCC
I/O11
I/O 3
I/O10
I/O 2
I/O 9
RY/BY
A18
A17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A7
A6
18
19
31
30
I/O 1
I/O 8
A5
A4
A3
A2
A1
20
21
22
23
24
29
28
27
26
25
I/O 0
OE
VSS
WE
RESET
NC
WP/ACC
A29DL32xV
A16
CE
A0
TFBGA
TFBGA
Top View, Balls Facing Down
A6
B6
C6
D6
E6
F6
A13
A12
A14
A15
A16
BYTE
A5
B5
C5
D5
E5
F5
G5
A9
A8
A10
A11
I/O7
I/O14
I/O13
A4
B4
C4
D4
E4
F4
G4
H4
WE
RESET
NC
A19
I/O5
I/O12
VCC
I/O4
A3
B3
C3
D3
E3
F3
G3
H3
WP/ACC
A18
A20
I/O 2
I/O10
I/O11
I/O3
A2
B2
C2
D2
E2
F2
G2
H2
A7
A17
A6
A5
I/O0
I/O 8
I/O9
I/O1
A1
B1
C1
E1
F1
G1
H1
A3
A4
A2
A0
CE
OE
VSS
RY/BY
PRELIMINARY
(May, 2005, Version 0.0)
D1
A1
3
H6
G6
I/O15(A-1)
VSS
H5
I/O6
AMIC Technology, Corp.
A29DL32x Series
Block Diagram
VCC
VSS
Upper Bank
RY/BY
I/O0-I/O15
A0-A20
Y-Decoder
Upper Bank Address
A0-A20
Latches and Control Logic
OE BYTE
X-Decoder
A0-A20
STATE
CONTROL
&
COMMAND
REGISTER
RESET
WE
CE
BYTE
WP/ACC
Status
I/O0-I/O15
Control
Lower Bank Address
A0-A20
Upper Bank
Latches and
Control Logic
Y-Decoder
X-Decoder
I/O0-I/O15
A0-A20
I/O0-I/O15
OE BYTE
Pin Descriptions
Logic Symbol
Pin No.
Description
A0 – A20
Address Inputs
I/O0 - I/O14
Data Inputs/Outputs
I/O15
I/O15 (A-1)
A-1
21
A0-A20
Data Input/Output, Word Mode
16 or 8
LSB Address Input, Byte Mode
CE
Chip Enable
WE
Write Enable
OE
Output Enable
WP /ACC
Hardware Write Protect/Acceleration Pin
RESET
Hardware Reset Pin, Active Low
I/O0-I/O15(A-1)
CE
OE
WE
WP/ACC
BYTE
Selects 8-bit or 16-bit Mode
RESET
RY/ BY
Ready/ BUSY Output
BYTE
VSS
Ground
VCC
3.0 volt-only single power supply
NC
PRELIMINARY
RY/BY
Pin Not Connected Internally
(May, 2005, Version 0.0)
4
AMIC Technology, Corp.
A29DL32x Series
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does
not occupy any addressable memory location. The register is
composed of latches that store the commands, along with
the address and data information needed to execute the
command. The contents of the register serve as inputs to the
internal state machine. The state machine outputs dictate the
function of the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe each of
these operations in further detail.
Table 1. A29DL32x Device Bus Operations
Operation
CE
OE
WE
RESET WP /ACC
A0 – A20
I/O0 - I/O7
(Note 1)
I/O8 - I/O15
BYTE =VIH
BYTE =VIL
Read
L
L
H
H
L/H
AIN
DOUT
DOUT
I/O8~I/O15=High-Z
Write
L
H
L
H
(Note 3)
AIN
DIN
DIN
I/O8~I/O14=High-Z
VCC ±
0.3 V
X
X
VCC ±
0.3 V
H
X
High-Z
High-Z
High-Z
Output Disable
L
H
H
H
L/H
X
High-Z
High-Z
High-Z
Reset
X
X
X
L
L/H
X
High-Z
High-Z
High-Z
Sector Protect
(See Note 2)
L
H
L
VID
L/H
SA, A6=L,
A1=H, A0=L
DIN
X
X
Sector Unprotect
(See Note 2)
L
H
L
VID
(Note 3)
SA, A6=H,
A1=H, A0=L
DIN
X
X
Temporary Sector
Unprotect
X
X
X
VID
(Note 3)
AIN
DIN
DIN
High-Z
I/O15=A-1
Standby
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5 -12.5V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, AIN =
Address In, DIN= Data In, DOUT = Data Out
Notes:
1. Addresses are A20:A0 in word mode ( BYTE =VIH), A20: A-1 in byte mode ( BYTE =VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the
“Sector/Sector Block Protection and Unprotection” section.
3. If WP /ACC = VIL, the two outermost boot sectors remain protected. If WP /ACC = VIH, the two outermost boot sector
protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block
Protection and Unprotection”. If WP /ACC = VHH all sectors will be unprotected.
PRELIMINARY
(May, 2005, Version 0.0)
5
AMIC Technology, Corp.
A29DL32x Series
Accelerated Program Operation
Word/Byte Configuration
The device offers accelerated program operations through
the ACC function. This is one of two functions provided by
the WP /ACC pin. This function is primarily intended to allow
faster manufacturing throughput at the factory.
If the system asserts VHH on this pin, the device automatically
enters the aforementioned Unlock Bypass mode, temporarily
unprotects any protected sectors, and uses the higher
voltage on the pin to reduce the time required for program
operations. The system would use a two-cycle program
command sequence as required by the Unlock Bypass
mode. Removing VHH from the WP /ACC pin returns the
device to normal operation. Note that the WP /ACC pin must
not be at VHH for operations other than accelerated programming, or device damage may result. In addition, the
WP /ACC pin must not be left floating or unconnected;
inconsistent behavior of the device may result.
The BYTE pin determines whether the I/O pins I/O15-I/O0
operate in the byte or word configuration. If the BYTE pin is
set at logic ”1”, the device is in word configuration, I/O15-I/O0
are active and controlled by CE and OE .
If the BYTE pin is set at logic “0”, the device is in byte
configuration, and only I/O0-I/O7 are active and controlled by
CE and OE . I/O8-I/O14 are tri-stated, and I/O15 pin is used
as an input for the LSB(A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the CE and OE pins to VIL. CE is the power control and
selects the device. OE is the output control and gates array
data to the output pins. WE should remain at VIH. The
BYTE pin determines whether the device outputs array data
in words or bytes.
The internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures that
no spurious alteration of the memory content occurs during
the power transition. No command is necessary in this mode
to obtain array data. Standard microprocessor read cycles
that assert valid addresses on the device address inputs
produce valid data on the device data outputs. Each bank
remains enabled for read access until the command register
contents are altered.
See "Requirements for Reading Array Data" for more
information. Refer to the AC Read-Only Operations table for
timing specifications and to Figure 11 for the timing
waveform, lCC1 in the DC Characteristics table represents the
active current specification for reading array data.
Autoselect Functions
If the system writes the autoselect command sequence, the
device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on I/O7-I/O0. Standard read
cycle timings apply in this mode. Refer to the Autoselect
Mode and Autoselect Command Sequence sections for more
information.
Simultaneous Read/Write Operations with Zero
Latency
This device is capable of reading data from one bank of
memory while programming or erasing in the other bank of
memory. An erase operation may also be suspended to read
from or program to another location within the same bank
(except the sector being erased). Figure 18 shows how read
and write cycles may be initiated for simultaneous operation
with zero latency. ICC6 and ICC7 in the DC Characteristics
table represent the current specifications for read-while-program and read-while-erase, respectively.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive WE and CE to VIL, and
Standby Mode
OE to VIH.
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the OE
input.
For program operations, the BYTE pin determines whether
the device accepts program data in bytes or words, Refer to
“Word/Byte Configuration” for more information.
The device features an Unlock Bypass mode to facilitate
faster programming. Once a bank enters the Unlock Bypass
mode, only two write cycles are required to program a word
or byte, instead of four. The “Word / Byte Program Command
Sequence” section has details on programming data to the
device using both standard and Unlock Bypass command
sequence.
An erase operation can erase one sector, multiple sectors, or
the entire device. The Sector Address Tables 3-4 indicate the
address range that each sector occupies. The device
address space is divided into two banks: Bank 1 contains the
boot/parameter sectors, and Bank 2 contains the larger, code
sectors of uniform size. A “bank address” is the address bits
required to uniquely select a bank. Similarly, a “sector
address” is the address bits required to uniquely select a
sector.
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
PRELIMINARY
(May, 2005, Version 0.0)
The device enters the CMOS standby mode when the CE &
RESET pins are both held at VCC ± 0.3V. (Note that this is a
more restricted voltage range than VIH.) If CE and RESET
are held at VIH, but not within VCC ± 0.3V, the device will be
in the standby mode, but the standby current will be greater.
The device requires the standard access time (tCE) for read
access when the device is in either of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
ICC3 in the DC Characteristics tables represent the standby
current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC +30ns. The automatic
6
AMIC Technology, Corp.
A29DL32x Series
The RESET pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
If RESET is asserted during a program or erase operation,
sleep mode is independent of the CE , WE and OE control
signals. Standard address access timings provide new data
when addresses are changed. While in sleep mode, output
data is latched and always available to the system. ICC4 in the
DC Characteristics table represents the automatic sleep
mode current specification.
the RY/ BY pin remains a “0” (busy) until the internal reset
operation is complete, which requires a time tREADY (during
Embedded Algorithms). The system can thus monitor
RY/ BY to determine whether the reset operation is
complete. If RESET is asserted when a program or erase
RESET : Hardware Reset Pin
The RESET pin provides a hardware method of resetting
the device to reading array data. When the system drives the
RESET pin low for at least a period of tRP, the device
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the RESET pulse. The device also resets the
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET pulse.
When RESET is held at VSS ± 0.3V, the device draws
CMOS standby current (ICC4 ). If RESET is held at VIL but not
within VSS ± 0.3V, the standby current will be greater.
operation is not executing (RY/ BY pin is “1”), the reset
operation is completed within a time of tREADY (not during
Embedded Algorithms). The system can read data tRH after
the RESET pin return to VIH.
Refer to the AC Characteristics tables for RESET
parameters and diagram.
Output Disable Mode
When the OE input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance
state.
Table 2. A29DL32x Device Bank Divisions
Device
Part Number
Bank 1
Bank 2
Megabits
Sector Sizes
Megabits
Sector Sizes
A29DL322
4 Mbit
Eight 8 Kbyte/4 Kword,
seven 64 Kbyte/32 Kword
28 Mbit
Fifty-six
64 Kbyte/32 Kword
A29DL323
8 Mbit
Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword
24 Mbit
Forty-eight
64 Kbyte/32 Kword
A29DL324
16 Mbit
Eight 8 Kbyte/4 Kword,
Thirty one 64 Kbyte/32 Kword
16 Mbit
Thirty-two
64 Kbyte/32 Kword
PRELIMINARY
(May, 2005, Version 0.0)
7
AMIC Technology, Corp.
A29DL32x Series
A29DL322T
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
Bank 2
A29DL323T
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
000000XXX
000001XXX
000010XXX
000011XXX
000100XXX
000101XXX
000110XXX
000111XXX
001000XXX
001001XXX
001010XXX
001011XXX
001100XXX
001101XXX
001110XXX
001111XXX
010000XXX
010001XXX
010010XXX
010011XXX
010100XXX
010101XXX
010110XXX
010111XXX
011000XXX
011001XXX
011010XXX
011011XXX
011100XXX
011101XXX
011110XXX
011111XXX
100000XXX
100001XXX
100010XXX
100011XXX
100100XXX
100101XXX
100110XXX
100111XXX
101000XXX
101001XXX
101010XXX
101011XXX
101100XXX
101101XXX
101110XXX
101111XXX
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
230000h-23FFFFh
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
280000h-28FFFFh
290000h-29FFFFh
2A0000h-2AFFFFh
2B0000h-2BFFFFh
2C0000h-2CFFFFh
2D0000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
000000h–007FFFh
008000h–00FFFFh
010000h–017FFFh
018000h–1FFFFFh
020000h–027FFFh
028000h–02FFFFh
030000h–037FFFh
038000h–03FFFFh
040000h–047FFFh
048000h–04FFFFh
050000h–057FFFh
058000h–05FFFFh
060000h–067FFFh
068000h–06FFFFh
070000h–077FFFh
078000h–07FFFFh
080000h–087FFFh
088000h–08FFFFh
090000h–097FFFh
098000h–09FFFFh
0A0000h–0A7FFFh
0A8000h–0AFFFFh
0B0000h–0B7FFFh
0B8000h–0BFFFFh
0C0000h–0C7FFFh
0C8000h–0CFFFFh
0D0000h–0D7FFFh
0D8000h–0DFFFFh
0E0000h–0E7FFFh
0E8000h–0EFFFFh
0F0000h–0F7FFFh
0F8000h–0FFFFFh
100000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
Bank 1
Bank 2
Bank 2
A29DL324T
Table 3 Sector Addresses for Top Boot Sector Devices
PRELIMINARY
(May, 2005, Version 0.0)
8
AMIC Technology, Corp.
A29DL32x Series
A29DL322T
Bank 1
Bank 1
Bank 1
Bank 2
A29DL323T
A29DL324T
Table 3 Sector Addresses for Top Boot Sector Devices
Sector
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
110000XXX
110001XXX
110010XXX
110011XXX
110100XXX
110101XXX
110110XXX
110111XXX
111000XXX
111001XXX
111010XXX
111011XXX
111100XXX
111101XXX
111110XXX
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3FFFFFh
3F2000h-3F3FFFh
3F4000h-3F5FFFh
3F6000h-3F7FFFh
3F8000h-3F9FFFh
3FA000h-3FBFFFh
3FC000h-3FDFFFh
3FE000h-3FFFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1F8FFFh
1F9000h–1F9FFFh
1FA000h–1FAFFFh
1FB000h–1FBFFFh
1FC000h–1FCFFFh
1FD000h–1FDFFFh
1FE000h–1FEFFFh
1FF000h–1FFFFFh
The address range is A20: A-1in byte mode ( BYTE =VIL) or A20:A0 in word mode ( BYTE =VIH). The bank address bits are A20A18 for A29DL322T, A20 and A19 for A29DL323T, and A20 for A29DL324T.
PRELIMINARY
(May, 2005, Version 0.0)
9
AMIC Technology, Corp.
A29DL32x Series
A29DL322U
Bank 2
Bank 2
Bank 2
Bank 2
Bank 1
Bank 1
A29DL323U
A29DL324U
Table 4. Sector Addresses for Bottom Boot Sector Devices
PRELIMINARY
Sector
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
000000000
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001XXX
000010XXX
000011XXX
000100XXX
000101XXX
000110XXX
000111XXX
001000XXX
001001XXX
001010XXX
001011XXX
001100XXX
001101XXX
001110XXX
001111XXX
010000XXX
010001XXX
010010XXX
010011XXX
010100XXX
010101XXX
010110XXX
010111XXX
011000XXX
011001XXX
011010XXX
011011XXX
011100XXX
011101XXX
011110XXX
011111XXX
100000XXX
100001XXX
100010XXX
100011XXX
100100XXX
100101XXX
100110XXX
100111XXX
101000XXX
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000h-001FFFh
002000h-003FFFh
004000h-005FFFh
006000h-007FFFh
008000h-009FFFh
00A000h-00BFFFh
00C000h-00DFFFh
00E000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
230000h-23FFFFh
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
280000h-28FFFFh
000000h-000FFFh
001000h-001FFFh
002000h-002FFFh
003000h-003FFFh
004000h-004FFFh
005000h-005FFFh
006000h-006FFFh
007000h-007FFFh
008000h-00FFFFh
010000h-017FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
100000h-107FFFh
108000h-10FFFFh
110000h-117FFFh
118000h-11FFFFh
120000h-127FFFh
128000h-12FFFFh
130000h-137FFFh
138000h-13FFFFh
140000h-147FFFh
(May, 2005, Version 0.0)
10
AMIC Technology, Corp.
A29DL322U
Sector
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
Bank 2
A29DL323U
Bank 2
Bank 2
A29DL324U
A29DL32x Series
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
101001XXX
101010XXX
101011XXX
101100XXX
101101XXX
101110XXX
101111XXX
110000XXX
110001XXX
110010XXX
110011XXX
110100XXX
110101XXX
110110XXX
110111XXX
111000XXX
111001XXX
111010XXX
111011XXX
111100XXX
111101XXX
111110XXX
111111XXX
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
290000h-29FFFFh
2A0000h-2AFFFFh
2B0000h-2BFFFFh
2C0000h-2CFFFFh
2D0000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3FFFFFh
148000h-14FFFFh
150000h-157FFFh
158000h-15FFFFh
160000h-167FFFh
168000h-16FFFFh
170000h-177FFFh
178000h-17FFFFh
180000h-187FFFh
188000h-18FFFFh
190000h-197FFFh
198000h-19FFFFh
1A0000h-1A7FFFh
1A8000h-1AFFFFh
1B0000h-1B7FFFh
1B8000h-1BFFFFh
1C0000h-1C7FFFh
1C8000h-1CFFFFh
1D0000h-1D7FFFh
1D8000h-1DFFFFh
1E0000h-1E7FFFh
1E8000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1FFFFFh
Note:
The address range is A20: A-1in byte mode ( BYTE =VIL) or A20:A0 in word mode ( BYTE =VIH). The bank address bits are A20A18 for A29DL322U, A20 and A19 for A29DL323U, and A20 for A29DL324U.
PRELIMINARY
(May, 2005, Version 0.0)
11
AMIC Technology, Corp.
A29DL32x Series
Autoselect Mode
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O7 - I/O0. This mode is primarily
intended for programming equipment to automatically match
a device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can
also be accessed in-system through the command register.
When using programming equipment, the autoselect mode
requires VID (8.5V to 12.5 V) on address pin A9. Address
pins A6, A1, and A0 must be as shown in Table 5. In
addition, when verifying sector protection, the sector address
must appear on the appropriate highest order address bits.
(see Table 3-4). Table 5 shows the remaining address bits
that are don't care. When all necessary bits have been set as
required, the programming equipment may then read the
corresponding identifier code on I/O7 - I/O0.
To access the autoselect codes in-system, the host system
can issue the autoselect command via the command
register, as shown in Table 12. This method does not require
VID. Refer to the Autoselect Command Sequence section for
more information.
Table 5. A29DL32x Autoselect Codes (High Voltage Method)
CE
Description
OE
WE
A20
to
A12
A11
to
A10
A9
A8
to
A7
A6
I/O8 to I/O15
A5
to
A4
A3
A2
A1
A0
BYTE BYTE
= VIH
= VIL
I/O7
to
I/O0
Manufacturer ID:
AMIC
L
L
H
BA
X
VID
X
L
X
L
L
L
L
X
X
37h
Device ID: A29DL322
L
L
H
BA
X
VID
X
L
X
X
X
L
H
22h
X
55h (T), 56h (U)
Device ID: A29DL323
L
L
H
BA
X
VID
X
L
X
X
X
L
H
22h
X
50h (T), 53h (U)
Device ID: A29DL324
L
L
H
BA
X
VID
X
L
X
X
X
L
H
22h
X
5Ch (T), 5Fh (U)
Continuation ID
L
L
H
X
X
VID
X
L
X
X
X
H
H
X
X
7Fh
Read Sector Status
L
L
H
SA
X
VID
X
L
X
L
L
H
L
X
X
01h (protected),
00h (unprotected)
L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care, BA=Bank Address
Note: The autoselect codes may also be accessed in-system via command sequences.
PRELIMINARY
(May, 2005, Version 0.0)
12
AMIC Technology, Corp.
A29DL32x Series
Table 7. Bottom Boot Sector/Sector Block Addresses for
Protection/Unprotection
Sector/Sector Block Protection and Unprotection
(Note: For the following discussion, the term “sector” applies
to both sectors and sector blocks. A sector block consists of
two or more adjacent sectors that are protected or
unprotected at the same time (see Tables 6 and 7).
Sector /
Sector Block
SA1-SA3
A20–A12
000000XXX
000001XXX,
000010XXX,
000011XXX
64 Kbytes
192 (3x64) Kbytes
0001XXXXX
256 (4x64) Kbytes
SA8-SA11
0010XXXXX
256 (4x64) Kbytes
SA12-SA15
0011XXXXX
256 (4x64) Kbytes
SA16-SA19
0100XXXXX
256 (4x64) Kbytes
SA20-SA23
0101XXXXX
256 (4x64) Kbytes
SA24-SA27
0110XXXXX
SA28-SA31
0111XXXXX
SA32-SA35
1000XXXXX
SA36-SA39
1001XXXXX
64 Kbytes
SA66- SA63
111111XXXX
111110XXX,
111101XXX,
111100XXX
1110XXXXX
256 (4x64) Kbytes
SA62- SA59
1101XXXXX
256 (4x64) Kbytes
SA58- SA55
1100XXXXX
256 (4x64) Kbytes
SA54- SA51
1011XXXXX
256 (4x64) Kbytes
SA50- SA47
1010XXXXX
256 (4x64) Kbytes
SA46-SA43
1001XXXXX
256 (4x64) Kbytes
SA42-SA39
1000XXXXX
256 (4x64) Kbytes
SA38-SA35
0111XXXXX
256 (4x64) Kbytes
SA34-SA31
0110XXXXX
256 (4x64) Kbytes
SA30-SA27
0101XXXXX
256 (4x64) Kbytes
SA26-SA23
0100XXXXX
256 (4x64) Kbytes
SA22-SA19
0011XXXXX
256 (4x64) Kbytes
SA18-SA15
0010XXXXX
256 (4x64) Kbytes
SA14-SA11
0001XXXXX
256 (4x64) Kbytes
SA69- SA67
Sector / Sector Block Size
SA4-SA7
Sector / Sector Block Size
SA70
Table 6. Top Boot Sector/Sector Block Addresses for
Protection/Unprotection
Sector /
Sector Block
SA0
A20–A12
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
192 (3x64) Kbytes
SA40-SA43
1010XXXXX
256 (4x64) Kbytes
SA44-SA47
1011XXXXX
256 (4x64) Kbytes
SA48-SA51
1100XXXXX
256 (4x64) Kbytes
SA7
000001XXX,
000010XXX,
000011XXX
000000111
256 (4x64) Kbytes
SA6
000000110
8 Kbytes
256 (4x64) Kbytes
000000101
8 Kbytes
SA63
1110XXXXX
111100XXX,
111101XXX,
111110XXX
111111000
SA5
SA64
SA65
SA52-SA55
SA56-SA59
1101XXXXX
SA10-SA8
192 (3x64) Kbytes
8 Kbytes
SA4
000000100
8 Kbytes
192 (3x64) Kbytes
SA3
000000011
8 Kbytes
8 Kbytes
SA2
000000010
8 Kbytes
111111001
8 Kbytes
SA1
000000001
8 Kbytes
111111010
8 Kbytes
SA0
000000000
8 Kbytes
SA66
111111011
8 Kbytes
SA67
111111100
8 Kbytes
SA68
111111101
8 Kbytes
SA69
111111110
8 Kbytes
SA70
111111111
8 Kbytes
SA60-SA62
PRELIMINARY
(May, 2005, Version 0.0)
13
AMIC Technology, Corp.
A29DL32x Series
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors. Sector
protection and unprotection can be implemented via two
methods.
The primary method requires VID on the RESET pin only,
and can be implemented either in-system or via
programming equipment. Figure 2 shows the algorithms and
Figure 23 shows the timing diagram. This method uses
standard microprocessor bus cycle timing. For sector
unprotect, all unprotected sectors must first be protected
prior to the first sector unprotect write cycle.
The sector unprotect algorithm unprotects all sectors in
parallel. All previously protected sectors must be individually
re-protected. To change data in protected sectors efficiently,
the temporary sector unprotect function is available. See
“Temporary Sector/Sector Block Unprotect”.
The alternate method for protection and unprotection is by
software sector /sector block protect unprotect command.
See Figure 2 for Command Flow.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See the Autoselect Mode section for details.
“Sector/Sector Block Protection and Unprotection”. The two
outermost 8 Kbyte boot sectors are the two sectors
containing the lowest addresses in a bottom-boot-configured
device, or the two sectors containing the highest addresses
in a top-boot-configured device.
If the system asserts VIH on the WP /ACC pin, the device
reverts to whether the two outermost 8 Kbyte boot sectors
were last set to be protected or unprotected. That is, sector
protection or unprotection for these two sectors depends on
whether they were last protected or unprotected using the
method described in “Sector/Sector Block Protection and
Unprotection”.
Note that the WP /ACC pin must not be left floating or
unconnected; inconsistent behavior of the device may result.
Temporary Sector/Sector Block Unprotect
(Note: For the following discussion, the term “sector” applies
to both sectors and sector blocks. A sector block consists of
two or more adjacent sectors that are protected or
unprotected at the same time (see Tables 6 and 7).
This feature allows temporary unprotection of previously
protected sectors to change data in-system. The Sector
Unprotect mode is activated by setting the RESET pin to VID
(8.5V-12.5V). During this mode, formerly protected sectors
can be programmed or erased by selecting the sector
addresses. Once VID is removed from the RESET pin, all the
previously protected sectors are protected again. Figure 1
shows the algorithm, and Figure 22 shows the timing
diagrams, for this feature.
Write Protect ( WP )
The Write Protect function provides a hardware method of
protecting certain boot sectors without using VID. This
function is one of two provided by the WP /ACC pin.
If the system asserts VIL on the WP /ACC pin, the device
disables program and erase functions in the two “outermost”
8 Kbyte boot sectors independently of whether those sectors
were protected or unprotected using the method described in
PRELIMINARY
(May, 2005, Version 0.0)
14
AMIC Technology, Corp.
A29DL32x Series
START
START
555/AA + 2AA/55 + 555/77
RESET = VID
(Note 1)
(Note 1)
Perform Erase or
Program Operations
Perform Erase or
Program Operations
XXX/F0
(Reset Command)
RESET = VIH
Soft-ware Temporary
Sector Unprotect
Completed
(Note 2)
Temporary Sector
Unprotect
Completed (Note 2)
Notes:
1. All protected sectors unprotected (If WP/ACC=VIL,
outermost boot sectors will remain protected).
2. All previously protected sectors are protected once again.
Notes:
1. All protected sectors unprotected (If WP/ACC=VIL,
outermost boot sectors will remain protected).
2. All previously protected sectors are protected once again.
Figure 1-2. Temporary Sector Unprotect Operation by Software Mode
Figure 1-1. Temporary Sector Unprotect Operation by RESET Mode
PRELIMINARY (May, 2005, Version 0.0)
15
AMIC Technology, Corp.
A29DL32x Series
START
START
Protect all sectors:
The indicated portion of
the sector protect
algorithm must be
performed for all
unprotected sectors prior
to issuing the first sector
unprotect address
PLSCNT=1
RESET=VID
Wait 1 us
No
Temporary Sector
Unprotect Mode
PLSCNT=1
RESET=VID
Wait 1 us
No
First Write
Cycle=60h?
Temporary Sector
Unprotect Mode
All sectors
protected?
Sector Protect:
Write 60h to sector
address with A6=0,
A1=1, A0=0
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with A6=1,
A1=1, A0=0
Wait 150 us
Increment
PLSCNT
No
Yes
Yes
Set up sector
address
Verify Sector
Protect: Write 40h
to sector address
with A6=0, A1=1,
A0=0
First Write
Cycle=60h?
Reset
PLSCNT=1
Wait 15 ms
Read from
sector address
with A6=0,
A1=1, A0=0
Verify Sector
Unprotect : Write
40h to sector
address with A6=1,
A1=1, A0=0
Increment
PLSCNT
No
PLSCNT
=25?
No
Read from sector
address with A6=1,
A1=1, A0=0
Data=01h?**
No
Set up
next sector
address
Yes
Yes
Protect another
sector?
Device failed
PLSCNT=
1000?
Yes
No
Yes
No
Remove VID
from RESET
Device failed
Write reset
command
Sector Protect
Algorithm
Sector Protect
complete
Data=00h?**
Yes
Last sector
verified?
No
Yes
Remove VID
from RESET
Sector Unprotect
Algorithm
Note: The term “sector” in the figure applies to both sectors and sector blocks
* No other command is allowed during this process
** Read access time is 200ns-300ns
Write reset
Command
Sector Unprotect
complete
Figure 2-1. High Voltage Sector/Sector Block Protection and Unprotection Algorithms
PRELIMINARY
(May, 2005, Version 0.0)
16
AMIC Technology, Corp.
A29DL32x Series
START
START
PLSCNT=1
555/AA + 2AA/55 +
555/77
Wait 1 us
No
Temporary Sector
Unprotect Mode
PLSCNT=1
Protect all sectors:
The indicated portion of
the sector protect
algorithm must be
performed for all
unprotected sectors prior
to issuing the first sector
unprotect address
555/AA + 2AA/55 +
555/77
Wait 1 us
No
First Write
Cycle=60h?
Yes
Temporary Sector
Unprotect Mode
All sectors
protected?
Sector Protect:
Write 60h to sector
address with A6=0,
A1=1, A0=0
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with A6=1,
A1=1, A0=0
Wait 150 us
Increment
PLSCNT
No
Yes
Set up sector
address
Verify Sector
Protect: Write 40h
to sector address
with A6=0, A1=1,
A0=0
First Write
Cycle=60h?
Reset
PLSCNT=1
Wait 15 ms
Read from
sector address
with A6=0,
A1=1, A0=0
Verify Sector
Unprotect : Write
40h to sector
address with A6=1,
A1=1, A0=0
Increment
PLSCNT
No
PLSCNT
=25?
No
Read from sector
address with A6=1,
A1=1, A0=0
Data=01h?**
No
Set up
next sector
address
Yes
Yes
Protect another
sector?
Device failed
PLSCNT=
1000?
Yes
Yes
No
Write reset
command
Sector Protect
Algorithm
No
Device failed
Sector Protect
complete
Data=00h?**
Yes
Last sector
verified?
No
Yes
Sector Unprotect
Algorithm
Write reset
Command
Sector Unprotect
complete
Note: The term “sector” in the figure applies to both sectors and sector blocks
* No other command is allowed during this process
** Read access time is 200ns-300ns
Figure 2-2. Software Sector/Sector Block Protection and Unprotection Algorithms
PRELIMINARY
(May, 2005, Version 0.0)
17
AMIC Technology, Corp.
A29DL32x Series
Hardware Data Protection
Power-Up Write Inhibit
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against
inadvertent writes (refer to Table 12 for command definitions).
In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
VCC power-up and power-down transitions, or from system
noise.
If WE = CE = VIL and OE = VIH during power up, the
device does not accept commands on the rising edge of WE .
The internal state machine is automatically reset to reading
array data on power-up.
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification outlines
device and host system software interrogation handshake,
which allows specific vendor-specified software algorithms to
be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and
forward- and backward-compatible for the specified flash
device families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the system
writes the CFI Query command, 98h, to address 55h in word
mode (or address AAh in byte mode), any time the device is
ready to read array data. The system can read CFI
information at the addresses given in Tables 8-11. To
terminate reading CFI data, the system must write the reset
command.
The system can also write the CFI query command when the
device is in the autoselect mode. The device enters the CFI
query mode, and the system can read CFI data at the
addresses given in Tables 8-11. The system must write the
reset command to return the device to the autoselect mode.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any
write cycles. This protects data during VCC power-up and
power-down. The command register and all internal
program/erase circuits are disabled, and the device resets to
reading array data. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the proper
signals to the control pins to prevent unintentional writes
when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5ns (typical) on OE , CE or WE
do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE = VIL,
CE = VIH or WE = VIH. To initiate a write cycle, CE and
WE must be a logical zero while OE is a logical one.
Table 8. CFI Query Identification String
Addresses
Addresses
(Word Mode)
(Byte Mode)
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
Data
0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
PRELIMINARY (May, 2005, Version 0.0)
Description
Query Unique ASCII string “QRY”
Primary OEM Command Set
Address for Primary Extended Table
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
18
AMIC Technology, Corp.
A29DL32x Series
Table 9. System Interface String
Addresses
Addresses
(Word Mode)
(Byte Mode)
1Bh
36h
0027h
1Ch
38h
0036h
Data
Description
VCC Min. (write/erase)
I/O7- I/O4 : volt, I/O3- I/O0: 100 millivolt
VCC Max. (write/erase)
I/O7- I/O4: volt, I/O3- I/O0: 100 millivolt
1Dh
3Ah
0000h
Vpp Min. voltage (00h = no Vpp pin present)
1Eh
3Ch
0000h
Vpp Max. voltage (00h = no Vpp pin present)
1Fh
3Eh
0003h
Typical timeout per single byte/word write 2N µs
20h
40h
0000h
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h
42h
0009h
Typical timeout per individual block erase 2N ms
22h
44h
0000h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
46h
0005h
Max. timeout for byte/word write 2N times typical
24h
48h
0000h
Max. timeout for buffer write 2N times typical
25h
4Ah
0004h
Max. timeout per individual block erase 2N times typical
26h
4Ch
0000h
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 10 Device Geometry Definition
Addresses
Addresses
(Word Mode)
(Byte Mode)
27h
4Eh
0016h
28h
50h
0002h
29h
52h
0000h
2Ah
54h
0000h
Data
Description
N
Device Size = 2 byte
Flash Device Interface description
N
2Bh
56h
0000h
Max. number of byte in multi-byte write = 2
(00h = not supported)
2Ch
58h
0002h
Number of Erase Block Regions within device
2Dh
5Ah
0007h
2Eh
5Ch
0000h
2Fh
5Eh
0020h
30h
60h
0000h
31h
62h
003Eh
32h
64h
0000h
33h
66h
0000h
34h
68h
0001h
35h
6Ah
0000h
36h
6Ch
0000h
37h
6Eh
0000h
38h
70h
0000h
39h
72h
0000h
3Ah
74h
0000h
3Bh
76h
0000h
3Ch
78h
0000h
PRELIMINARY
(May, 2005, Version 0.0)
Erase Block Region 1 Information
(refer to the CFI specification)
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
19
AMIC Technology, Corp.
A29DL32x Series
Table 11. Primary Vendor-Specific Extended Query
Addresses
Addresses
(Word Mode)
(Byte Mode)
40h
80h
0050h
41h
82h
0052h
42h
84h
0049h
43h
86h
0031h
Major version number, ASCII
44h
88h
0033h
Minor version number, ASCII
45h
8Ah
0000h
Address Sensitive Unlock
Data
Description
Query-unique ASCII string “PRI”
0 = Required, 1 = Not Required
46h
8Ch
0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
8Eh
0001h
48h
90h
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
92h
0004h
Sector Protect/Unprotect scheme
04 = A29L800 mode
4Ah
94h
00XXh
Number of Sectors (Excluding Bank 1)
XX = 38 (A29DL322)
XX = 30 (A29DL323)
XX = 20 (A29DL324)
4Bh
96h
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
98h
0000h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt,
4Dh
9Ah
0085h
4Eh
9Ch
0095h
ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt,
D3-D0: 100 mV
4Fh
9Eh
000Xh
Top/Bottom Boot Sector Flag 02h = Bottom Boot Device, 03h = Top Boot
Device
50h
A0h
0000h
57h
AEh
0002h
D3-D0: 100 mV
Program Suspend
0 = Not Supported, 1 = Supported
Bank Organization
X = 2 (2 banks, all models)
Bank 1 Region Information – Number of Sectors on Bank 1
58h
B0h
00XXh
XX = 0F (A29DL322)
XX = 17 (A29DL323)
XX = 27 (A29DL324)
Bank 2 Region Information – Number of Sectors in Bank 2
59h
B2h
00XXh
XX = 38 (A29DL322)
XX = 30 (A29DL323)
XX = 20 (A29DL324)
5Ah
B4h
0000
Bank 3 Region Information – Number of Sector in Bank 3
5Bh
B6h
0000
Bank 4 Region Information – Number of Sector in Bank 4
PRELIMINARY
(May, 2005, Version 0.0)
20
AMIC Technology, Corp.
A29DL32x Series
(or erase-suspend-read mode if that bank was in Erase
Suspend).
COMMAND DEFINITIONS
Writing specific address and data commands or sequences
into the command register initiates device operations. Table
12 defines the valid register command sequences. Writing
incorrect address and data values or writing them in the
improper sequence may place the device in an unknown
state. A reset command is then required to return the device
to reading array data.
All addresses are latched on the falling edge of WE or CE ,
whichever happens later. All data is latched on the rising
edge of WE or CE , whichever happens first. Refer to the
AC Characteristics section for timing diagrams.
Autoselect Command Sequence
The autoselect command sequence allows the host system
to access the manufacturer and device codes, and determine
whether or not a sector is protected. Table 12 shows the
address and data requirements. This method is an
alternative to that shown in Table 5, which is intended for
PROM programmers and requires VID on address pin A9.
The autoselect command sequence may be written to an
address wit h in a bank that is either in t he read or erasesuspend-read mode. The autoselect command may not be
written while the device is actively programming or erasing in
the other bank.
The autoselect command sequence is initiated by first writing
two unlock cycles. This is followed by a third write cycle that
contains the bank address and the autoselect command. T he
bank then enter s the autoselect mode. The system may read
at any address within the same bank any number of times
without initiating another autoselect command sequence:
A read cycle at address (BA)XX00h (where BA is the bank
address) returns the manufacturer code.
A read cycle at address (BA)XX01h in word mode (or
(BA)XX02h in byte mode) returns the device code.
A read cycle to an address containing a sector address
(SA) within the same bank, and the address 02h on A7-A0
in word mode (or the address 04h on A6-A-1 in byte mode)
returns 01h if the sector is protected, or 00h if it is
unprotected. (Refer to Tables 3-4 for valid sector
addresses).
The system must write the reset command to return to
reading array data (or erase-suspend-read mode if the bank
was previously in Erase Suspend).
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve
data. The device is also ready to read array data after
completing an Embedded Program or Embedded Erase
algorithm.
After the device accepts an Erase Suspend command, the
corresponding bank enters the erase-suspend-read mode,
after which the system can read data from any non-erasesuspended sector within the same bank. After completing a
programming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See the Erase Suspend/Erase Resume
Commands section for more information.
The system must issue the reset command to return a bank
to the read (or erase-suspend-read) mode if I/O5 goes high
during an active program or erase operation, or if the bank is
in the autoselect mode. See the next section, Reset
Command, for more information.
See also Requirements for Reading Array Data in the Device
Bus Operations section for more information. The Read-Only
Operations table provides the read parameters, and Figure
11 shows the timing diagram.
Byte/Word Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE pin. Programming is a
four-bus-cycle operation. The program command sequence
is initiated by writing two unlock write cycles, followed by the
program set-up command. The program address and data
are written next, which in turn initiate the Embedded Program
algorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Table 12 shows the address and
data requirements for the byte program command sequence.
When the Embedded Program algorithm is complete, that
bank then returns to reading array data and addresses are
no longer latched. The system can determine the status of
the program operation by using I/O7, I/O6, or RY/ BY . Refer
to the Write Operation Status section for information on these
status bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. Note that a hardware reset
immediately terminates the program operation. The program
command sequence should be reinitiated once that bank has
returned to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from “0” back to a
“1.” Attempting to do so may cause that bank to set I/O5 = 1,
or cause the I/O7 and I/O6 status bits to indicate the operation
was successful. However, a succeeding read will show that
the data is still “0.” Only erase operations can convert a “0” to
a “1.”
Reset Command
Writing the reset command resets the banks to the read or
erase-suspend-read mode. Address bits are don’t cares for
this command.
The reset command may be written between the sequence
cycles in an erase command sequence before erasing
begins. This resets the bank to which the system was writing
to reading array data. Once erasure begins, however, the
device ignores reset commands until the operation is
complete.
The reset command may be written between the sequence
cycles in a program command sequence before
programming begins. This resets the bank to which the
system was writing to reading array data. If the program
command sequence is written to a bank that is in the Erase
Suspend mode, writing the reset command returns that bank
to the erase-suspend-read mode. Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to
return to reading array data. If a bank entered the autoselect
mode while in the Erase Suspend mode, writing the reset
command returns that bank to the erase-suspend-read mode.
If I/O5 goes high during a program or erase operation, writing
the reset command returns the banks to reading array data
PRELIMINARY (May, 2005, Version 0.0)
21
AMIC Technology, Corp.
A29DL32x Series
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program
bytes or words to a bank faster than using the standard
program command sequence. The unlock bypass command
sequence is initiated by first writing two unlock cycles. This is
followed by a third write cycle containing the unlock bypass
command, 20h. The device then enters the unlock bypass
mode. A two-cycle unlock bypass program command
sequence is all that is required to program in this mode. The
first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program
address and data. Additional data is programmed in the
same manner. This mode dispenses with the initial two
unlock cycles required in the standard program command
sequence, resulting in faster total programming time. Table
12 shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands are valid. To
exit the unlock bypass mode, the system must issue the twocycle unlock bypass reset command sequence. The device
then returns to reading array data.
The device offers accelerated program operations through
the WP /ACC pin. When the system asserts VHH on the
WP /ACC pin, the device automatically enters the Unlock
Bypass mode. The system may then write the two-cycle
Unlock Bypass program command sequence. The device
uses the higher voltage on the WP /ACC pin to accelerate
the operation. Note that the WP /ACC pin must not be at VHH
any operation other than accelerated programming, or device
damage may result. In addition, the WP /ACC pin must not
be left floating or unconnected; inconsistent behavior of the
device may result.
Figure 3 illustrates the algorithm for the program operation.
Refer to the Erase and Program Operations table in the AC
Characteristics section for parameters, and Figure 15 for
timing diagrams.
START
Write Program
Command
Sequence
Data Poll
from System
Embedded
Program
algorithm in
progress
Verify Data ?
No
Yes
Increment Address
No
Last Address ?
Yes
Programming
Completed
Note : See Table 14 for program command sequnce.
Figure 3. Program Operation
PRELIMINARY
(May, 2005, Version 0.0)
22
AMIC Technology, Corp.
A29DL32x Series
When the Embedded Erase algorithm is complete, the bank
returns to reading array data and addresses are no longer
latched. Note that while the Embedded Erase operation is in
progress, the system can read data from the non-erasing
bank. The system can determine the status of the erase
operation by reading I/O7, I/O6, I/O2, or RY/ BY in the erasing
bank.
Refer to the Write Operation Status section for information on
these status bits.
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are ignored.
However, note that a hardware reset immediately terminates
the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once that bank has
returned to reading array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase operation.
Refer to the Erase and Program Operations tables in the AC
Characteristics section for parameters, and Figure 17 section
for timing diagrams
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does not require the system to preprogram prior to erase.
The Embedded Erase algorithm automatically preprograms
and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide
any controls or timings during these operations. Table 12
shows the address and data requirements for the chip erase
command sequence.
When the Embedded Erase algorithm is complete, that bank
returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using I/O7, I/O6, I/O2, or RY/ BY . Refer to the
Write Operation Status section for information on these
status bits.
Any commands written during the chip erase operation are
ignored. However, note that a hardware reset immediately
terminates the erase operation. If that occurs, the chip erase
command sequence should be reinitiated once that bank has
returned to reading array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase operation.
Refer to the Erase and Program Operations tables in the AC
Characteristics section for parameters, and Figure 17 section
for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to
interrupt a sector erase operation and then read data from, or
program data to, any sector not selected for erasure. This
command is valid only during the sector erase operation,
including the 50 µs time-out period during the sector erase
command sequence. The Erase Suspend command is
ignored if written during the chip erase operation or
Embedded Program algorithm.
When the Erase Suspend command is written during the
sector erase operation, the device requires a maximum of 20
µs to suspend the erase operation. However, when the Erase
Suspend command is written during the sector erase timeout, the device immediately terminates the time-out period
and suspends the erase operation.
After the erase operation has been suspended, the bank
enters the erase-suspend-read mode. The system can read
data from or program data to any sector not selected for
erasure. (The device “erase suspends” all sectors selected
for erasure.) Reading at any address within erase-suspended
sectors produces status information on I/O7–I/O0. The system
can use I/O7, or I/O6 and I/O2 together, to determine if a
sector is actively erasing or is erase-suspended. Refer to the
Write Operation Status section for information on these
status bits.
After an erase-suspended program operation is complete,
the bank returns to the erase-suspend-read mode. The
system can determine the status of the program operation
using the I/O7 or I/O6 status bits, just as in the standard Byte
Program operation. Refer to the Write Operation Status
section for more information.
In the erase-suspend-read mode, the system can also issue
the autoselect command sequence. Refer to the Autoselect
Mode and Autoselect Command Sequence sections for
details.
To resume the sector erase operation, the system must write
the Erase Resume command. The bank address of the
erase-suspended bank is ignored when writing this command.
Further writes of the Resume command are ignored. Another
Erase Suspend command can be written after the chip has
resumed erasing.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock cycles
are written, and are then followed by the address of the
sector to be erased, and the sector erase command. Table
12 shows the address and data requirements for the sector
erase command sequence.
The device does not require the system to preprogram prior
to erase. The Embedded Erase algorithm automatically
programs and verifies the entire memory for an all zero data
pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase timeout of 50 µs occurs. During the time-out period, additional
sector addresses and sector erase commands within the
bank may be written. Loading the sector erase buffer may be
done in any sequence, and the number of sectors may be
from one sector to all sectors. The time between these
additional cycles must be less than 50µs, otherwise erasure
may begin. Any sector erase address and command
following the exceeded time-out may or may not be accepted.
It is recommended that processor interrupts be disabled
during this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. Any command other than Sector Erase
or Erase Suspend during the time-out period resets that bank
to reading array data. The system must rewrite the command
sequence and any additional addresses and commands.
The system can monitor I/O3 to determine if the sector erase
timer has timed out (See the section on I/O3: Sector Erase
Timer.). The time-out begins from the rising edge of the final
WE pulse in the command sequence.
PRELIMINARY
(May, 2005, Version 0.0)
23
AMIC Technology, Corp.
A29DL32x Series
START
Write Erase
Command Sequence
(Notes 1,2)
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm in
progress
No
Data = FFh ?
Yes
Erasure Completed
Note :
1. See Table 14 for erase command sequence.
2. See the section on I/O3 for information on the sector
erase timer.
Figure 4. Erase Operation
PRELIMINARY
(May, 2005, Version 0.0)
24
AMIC Technology, Corp.
A29DL32x Series
Command Definitions
Table 12. A29DL32x Command Definitions
Cycle
Command
Sequence
(Note 1)
First
Addr Data
1
RA
RD
Reset (Note 7)
1
XXX
F0
Autoselect (Note 8)
Read (Note 6)
Manufacturer ID
Device ID
Word
Byte
Word
Byte
Word
Byte
Continuation ID
Sector Protect Verify
(Note 9)
Command Temporary
Sector Unprotect (Note15)
Program
Word
Byte
Word
Byte
Word
Byte
Word
Unlock Bypass
Byte
4
4
4
4
3
4
3
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
AA
AA
AA
AA
AA
AA
AA
Second
Addr Data
2AA
555
2AA
555
2AA
555
2AA
555
2AA
555
2AA
555
2AA
555
55
55
55
55
55
55
55
Unlock Bypass Program (Note 10)
2
XXX
A0
PA
PD
Unlock Bypass Reset (Note 11)
2
XXX
90
XXX
00
Word
Chip Erase
Byte
Word
Byte
Sector Erase
6
6
555
AAA
555
AAA
AA
AA
Erase Suspend (Note 12)
1
XXX
B0
Erase Resume (Note 13)
1
XXX
30
1
55
AA
98
CFI Query (Note 14)
Word
Byte
2AA
555
2AA
55
55
555
Bus Cycles (Notes 2–5)
Third
Fourth
Addr
Data
Addr
Data
(BA)555
(BA)AAA
(BA)555
(BA)AAA
555
AAA
(BA)555
(BA)AAA
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
90
90
90
90
(BA)X00
37
(BA)X01
(see
Fifth
Addr
Data
Sixth
Addr Data
(BA)X02 Table5)
X03
X06
(SA)
(SA)X04
7F
00/01
77
A0
PA
PD
20
80
80
555
AA A
555
AAA
AA
AA
2AA
555
2AA
555
55
55
555
AAA
SA
10
30
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE or CE pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20 - A12 select a unique sector.
BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased.
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles.
4. Data bits I/O15-I/O8 are don’t care in command sequences. Except for RD and PD.
5. Unless otherwise noted, address bits A20-A11 are don’t cares.
6. No unlock or command cycles required when bank is reading array data.
7. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if I/O5 goes high (while the bank is providing status information).
8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain
the manufacture ID, or device ID information. Data bits I/O15-I/O8 are don’t care. See the Autoselect Command Sequence
section for more information.
9. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block.
10. The Unlock Bypass command is required prior to the Unlock Bypass Program Command.
11. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode.
12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase operation, and require the bank address.
13. The Erase Resume command is valid only during the Erase.
14. Command is valid when device is ready to read array data or when device is in autoselect mode.
15. Once a reset command is applied, software temporary unprotect is exit to return to read array data. But under erase
suspend condition, this command is still effective even a reset command has been applied. The reset command which can
deactivate the software temporary unprotect command is useful only after the erase command is complete.
PRELIMINARY
(May, 2005, Version 0.0)
25
AMIC Technology, Corp.
A29DL32x Series
WRITE OPERATION STATUS
The device provides several bits to determine the status of a
program or erase operation: I/O2, I/O3, I/O5, I/O6, and I/O7.
Table 13 and the following subsections describe the function
of these bits. I/O7 and I/O6 each offer a method for
determining whether a program or erase operation is
complete or in progress. The device also provides a
hardware-based output signal, RY/ BY , to determine whether
an Embedded Program or Erase operation is in progress or
has been completed.
START
Read I/O7-I/O0
Address = VA
I/O7: Data Polling
Yes
The Data Polling bit, I/O7, indicates to the host system
whether an Embedded Algorithm is in progress or completed,
or whether the device is in Erase Suspend. Data Polling is
I/O7 = Data ?
valid after the rising edge of the final WE pulse in the
program or erase command sequence.
During the Embedded Program algorithm, the device outputs
on I/O7 the complement of the datum programmed to I/O7.
This I/O7 status also applies to programming during Erase
Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to I/O7.
The system must provide the program address to read valid
status information on I/O7. If a program address falls within a
protected sector, Data Polling on I/O7 is active for
approximately 1µs, then the device returns to reading array
data.
During the Embedded Erase algorithm, Data Polling
produces a "0" on I/O7. When the Embedded Erase algorithm
is complete, or if the device enters the Erase Suspend mode,
Data Polling produces a "1" on I/O7. The system must
provide an address within any of the sectors selected for
erasure to read valid status information on I/O7.
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data Polling on I/O7 is
active for approximately 100µs, then the bank returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
However, if the system reads I/O7 at an address within a
protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or
Erase operation, I/O7 may change asynchronously with I/O0–
I/O6 while Output Enable ( OE ) is asserted low. That is, the
device may change from providing status information to valid
data on I/O7. Depending on when the system samples the
I/O7 output, it may read the status or valid data. Even if the
device has completed the program or erase operation and
I/O7 has valid data, the data outputs on I/O0-I/O6 may be still
invalid. Valid data on I/O0-I/O7 will appear on successive read
cycles.
Table 13 shows the outputs for Data Polling on I/O7. Figure
No
No
I/O5 = 1?
Yes
Read I/O7 - I/O0
Address = VA
Yes
I/O7 = Data ?
No
FAIL
PASS
Note :
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. I/O7 should be rechecked even if I/O5 = "1" because
I/O7 may change simultaneously with I/O5.
Figure 5. Data Polling Algorithm
5 shows the Data Polling algorithm. Figure 19 in the AC
Characteristics section shows the Data Polling timing
diagram.
PRELIMINARY (May, 2005, Version 0.0)
26
AMIC Technology, Corp.
A29DL32x Series
RY/ BY : Read/ Busy
The RY/ BY is a dedicated, open-drain output pin that
indicates whether an Embedded algorithm is in progress or
complete. The RY/ BY status is valid after the rising edge of
the final WE pulse in the command sequence. Since RY/ BY
is an open-drain output, several RY/ BY pins can be tied
together in parallel with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device is
ready to read array data (including during the Erase Suspend
mode), or is in the standby mode.
Table 13 shows the outputs for RY/ BY .
START
Read I/O7-I/O0
Read I/O7-I/O0
(Note 1)
I/O6: Toggle Bit I
Toggle Bit I on I/O6 indicates whether an Embedded Program
or Erase algorithm is in progress or complete, or whether the
device has entered the Erase Suspend mode. Toggle Bit I
may be read at any address, and is valid after the rising edge
of the final WE pulse in the command sequence (prior to the
program or erase operation), and during the sector erase
time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause I/O6 to toggle.
The system may use either OE or CE to control the read
cycles. When the operation is complete, I/O6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O6 toggles for
approximately 100µs, then returns to reading array data. If not
all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use I/O6 and I/O2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O6 toggles. When the device
enters the Erase Suspend mode, I/O6 stops toggling.
However, the system must also use I/O2 to determine which
sectors are erasing or erase-suspended. Alternatively, the
system can use I/O7 (see the subsection on " I/O7: Data
Polling").
If a program address falls within a protected sector, I/O6
toggles for approximately 1µs after the program command
sequence is written, then returns to reading array data.
I/O6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm is
complete.
Table 13 shows the outputs for Toggle Bit I on I/O6. Figure 6
shows the toggle bit algorithm. Figure 20 in the “AC
Characteristics” section shows the toggle bit timing diagrams.
Figure 23 shows the differences between I/O2 and I/O6 in
graphical form. See also the subsection on I/O2: Toggle Bit II.
PRELIMINARY (May, 2005, Version 0.0)
27
Toggle Bit
= Toggle ?
No
Yes
No
I/O5 = 1?
Yes
Read I/O7 - I/O0
Twice
Toggle Bit
= Toggle ?
(Notes 1,2)
No
Yes
Program/Erase
Operation Not
Commplete, Write
Reset Command
Program/Erase
Operation Complete
Note:
The system should recheck the toggle bit even if I/O5=”1"
because the toggle bit may stop toggling as I/O5 changes to
“1”. See the subsections on I/O6 and I/O2 for more information.
Figure 6. Toggle Bit Algorithm
AMIC Technology, Corp.
A29DL32x Series
I/O2: Toggle Bit II
The "Toggle Bit II" on I/O2, when used with I/O6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the final WE pulse in the command sequence.
I/O2 toggles when the system reads at addresses within those
sectors that have been selected for erasure. (The system may
use either OE or CE to control the read cycles.) But I/O2
cannot distinguish whether the sector is actively erasing or is
erase-suspended. I/O6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information.
Refer to Table 8 to compare outputs for I/O2 and I/O6.
Figure 6 shows the toggle bit algorithm in flowchart form, and
the section " I/O2: Toggle Bit II" explains the algorithm. See
also the " I/O6: Toggle Bit I" subsection. Figure 20 shows the
toggle bit timing diagram. Figure 21 shows the differences
between I/O2 and I/O6 in graphical form.
Reading Toggle Bits I/O6, I/O2
Refer to Figure 6 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
I/O7-I/O0 at least twice in a row to determine whether a toggle
bit is toggling. Typically, a system would note and store the
value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle
bit with the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can
read array data on I/O7-I/O0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O5 is high (see the section
on I/O5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as I/O5 went high. If the toggle bit
is no longer toggling, the device has successfully completed
the program or erase operation. If it is still toggling, the device
did not complete the operation successfully, and the system
must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and I/O5 has not gone high. The
system may continue to monitor the toggle bit and I/O5
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when it
PRELIMINARY
(May, 2005, Version 0.0)
28
returns to determine the status of the operation (top of Figure
6).
I/O5: Exceeded Timing Limits
I/O5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions I/O5 produces a "1." This is a failure condition that
indicates the program or erase cycle was not successfully
completed.
The device may output a “1” on I/O5 if the system tries to
program a “1” to a location that was previously programmed
to “0.” Only an erase operation can change a “0” back to a
“1.” Under this condition, the device halts the operation, and
when the timing limit has been exceeded, I/O5 produces a
“1.” .
Under both these conditions, the system must write the reset
command to return to reading array data (or to the erasesuspend-read mode if a bank was previously in the erasesuspend-program mode).
I/O3: Sector Erase Timer
After writing a sector erase command sequence, the system
may read I/O3 to determine whether or not an erase
operation has begun. (The sector erase timer does not apply
to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies after
each additional sector erase command. When the time-out is
complete, I/O3 switches from "0" to "1." The system may
ignore I/O3 if the system can guarantee that the time
between additional sector erase commands will always be
less than 50µs. See also the "Sector Erase Command
Sequence" section.
After the sector erase command sequence is written, the
system should read the status on I/O7 ( Data Polling) or I/O6
(Toggle Bit 1) to ensure the device has accepted the
command sequence, and then read I/O3. If I/O3 is "1", the
internally controlled erase cycle has begun; all further
commands (Except Erase Suspend) are ignored until the
erase operation is complete. If I/O3 is "0", the device will
accept additional sector erase commands. To ensure the
command has been accepted, the system software should
check the status of I/O3 prior to and following each
subsequent sector erase command. If I/O3 is high on the
second status check, the last command might not have been
accepted.
Table 13 shows the status of I/O3 relative to the other status
bits.
AMIC Technology, Corp.
A29DL32x Series
Table 13. Write Operation Status
Status
I/O7
I/O6
(Note 2)
Standard Embedded Program Algorithm
Mode
Embedded Erase Algorithm
Erase
Erase
Suspend Erase-Suspend- Suspended Sector
Mode
Read
Non-Erase
Suspend Sector
Erase-Suspend-Program
I/O5
I/O3
(Note 1)
I/O2
RY/ BY
(Note 2)
I/O7
Toggle
0
N/A
No toggle
0
0
Toggle
0
1
Toggle
0
1
No toggle
0
N/A
Toggle
1
Data
Data
Data
Data
Data
1
I/O7
Toggle
0
N/A
N/A
0
Notes:
1. I/O5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on I/O5 for more information.
2. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm
is in progress. The device outputs array data if the system addresses a non-busy bank.
PRELIMINARY
(May, 2005, Version 0.0)
29
AMIC Technology, Corp.
A29DL32x Series
ABSOLUTE MAXIMUM RATINGS*
*Comments
Storage Temperature Plastic Packages. . . -65°C to + 150°C
Ambient Temperature with Power Applied. -65°C to + 125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . . . . ……. . -0.5V to +4.0V
A9, OE & RESET (Note 2) . . . . . . . . . . . . -0.5V to +12.5V
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
WP /ACC . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +10.5V
All other pins (Note 1) . . . . . . . . . . …. . -0.5V to VCC + 0.5V
Output Short Circuit Current (Note 3) . . . . . . . …. . 200mA
OPERATING RANGES
Notes:
Industrial (I) Devices
1. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, input or I/O pins may undershoot VSS
to -2.0V for periods of up to 20ns. Maximum DC voltage
on input and I/O pins is VCC +0.5V. See Figure 7. During
voltage transitions, input or I/O pins may overshoot to
VCC +2.0V for periods up to 20ns. See Figure 8.
2. Minimum DC input voltage on A9, OE , RESET and
Ambient Temperature (TA) . . . . . . . . . . . . . . -40°C to +85°C
VCC Supply Voltages
VCC for all devices . . . . . . . . . . . . . . . . . …...+2.7V to +3.6V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
WP /ACC is -0.5V. During voltage transitions, A9, OE ,
WP /ACC and RESET may overshoot VSS to -2.0V for
periods of up to 20ns. See Figure 7. Maximum DC input
voltage on A9 is +12.5V which may overshoot to 14.0V
for periods up to 20ns. Maximum DC input voltage on
WP /ACC is +9.5V which may overshoot to +12.0V for
period up to 20ns.
3. No more than one output is shorted to ground at a time.
Duration of the short circuit should not be greater than
one second.
Figure 7. Maximum Negative Overshoot Waveform
20ns
20ns
+0.8V
-0.5V
-2.0V
20ns
Figure 8. Maximum Positive Overshoot Waveform
20ns
VCC+2.0V
VCC+0.5V
2.0V
20ns
PRELIMINARY
(May, 2005, Version 0.0)
20ns
30
AMIC Technology, Corp.
A29DL32x Series
DC CHARACTERISTICS
CMOS Compatible
Parameter
Parameter Description
Symbol
ILI
Input Load Current
ILIT
ILO
A9 Input Load Current
Output Leakage Current
Test Description
Min.
Max.
Unit
VCC = VCC Max, A9 =12.5V
±1.0
35
µA
VOUT = VSS to VCC. VCC = VCC Max
±1.0
µA
VIN = VSS to VCC. VCC = VCC Max
10
16
1 MHz
2
4
CE = VIL, OE = VIH
5 MHz
10
16
Word Mode
1 MHz
2
4
CE = VIL, OE =VIH
20
30
mA
CE = VIH, RESET = VCC ± 0.3V
0.2
5
µA
Byte Mode
ICC1
µA
5 MHz
CE = VIL, OE = VIH
VCC Active Read Current
(Notes 1, 2)
Typ.
mA
ICC3
VCC Active Write Current
(Notes 2, 3)
VCC Standby Current (Note 2)
ICC4
VCC Reset Current (Note 2)
RESET = VSS ± 0.3V
0.2
5
µA
ICC5
Automatic Sleep Mode
(Note 2, 4)
VIH = VCC ± 0.3V; VIL = VSS ± 0.3V
0.2
5
µA
VCC Active Read-While-Program
Current (Notes 1, 2)
CE = VIL, OE = VIH
Byte
21
45
Word
21
45
VCC Active Read-While-Erase
Current (Notes 1, 2)
CE = VIL, OE = VIH
Byte
21
45
Word
21
45
ICC8
VCC Active
Program-While-Erase-Suspended
Current (Notes 2, 5)
CE = VIL, OE = VIH
17
35
IACC
ACC Accelerated Program Current,
Word or Byte
CE = VIL, OE = VIH
ACC pin
5
10
VCC pin
15
30
ICC2
ICC6
ICC7
mA
mA
mA
mA
VIL
Input Low Level
-0.5
0.8
V
VIH
Input High Level
0.7 x VCC
VCC + 0.3
V
VHH
Voltage for WP /ACC Sector
Protect/Unprotect and Program
Acceleration
VCC = 3.0 V ± 10%
8.5
9.5
V
VCC = 3.0 V ± 10%
8.5
12.5
V
0.45
V
VID
VOL
Voltage for Autoselect and
Temporary Unprotect Sector
Output Low Voltage
VOH1
VOH2
Output High Voltage
VLKO
Low VCC Lock-Out Voltage (Note 5)
IOL = 4.0mA, VCC = VCC Min
IOH = -2.0 mA, VCC = VCC Min
IOH = -100 µA, VCC = VCC Min
0.85 x VCC
VCC - 0.4
2.3
V
V
2.5
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE at VIH.
2. Maximum ICC specifications are tested with VCC = VCC max.
3. ICC active while Embedded Algorithm (program or erase) is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30ns. Typical sleep mode current
is 200nA.
5. Not 100% tested.
PRELIMINARY
(May, 2005, Version 0.0)
31
AMIC Technology, Corp.
A29DL32x Series
TEST CONDITIONS
Table 14. Test Specifications
Test Condition
-70, -80
Output Load
-90, -120
Unit
1 TTL gate
Output Load Capacitance, CL(including jig capacitance)
30
100
pF
Input Rise and Fall Times
5
5
ns
Input Pulse Levels
0.0 - 3.0
0.0 - 3.0
V
Input timing measurement reference levels
1.5
1.5
V
Output timing measurement reference levels
1.5
1.5
V
Figure 9. Test Setup
3.3 V
2.7 KΩ
Device
Under
Test
CL
6.2 KΩ
Diodes = IN3064 or Equivalent
Figure 10. Input Waveforms and Measurement Levels
3.0V
Input
1.5V
Measurement Level
1.5V
Output
0.0V
PRELIMINARY
(May, 2005, Version 0.0)
32
AMIC Technology, Corp.
A29DL32x Series
AC CHARACTERISTICS
Read Only Operations
Parameter
Description
JEDEC
Std
tAVAV
tRC
Read Cycle Time (Note 1)
tAVQV
tACC
Address to Output Delay
tELQV
tCE
Chip Enable to Output Delay
tGLQV
tOE
tEHQZ
Test Setup
Unit
Speed
-70
-80
-90
-120
Min.
70
80
90
120
ns
CE = VIL
OE = VIL
Max.
70
80
90
120
ns
OE = VIL
Max.
70
80
90
120
ns
Output Enable to Output Delay
Max.
30
30
40
50
ns
tDF
Chip Enable to Output High Z
(Notes 1,3)
Max.
16
16
16
16
ns
tGHQZ
tDF
Output Enable to Output High Z
(Notes 1,3)
Max.
16
16
16
16
ns
tAXQX
tOH
Output Hold Time from Addresses,
CE or OE , Whichever Occurs First
Min.
0
ns
Min.
0
ns
Min.
10
ns
tOEH
Output Enable Hold
Time (Note 1)
Read
Toggle and
Data Polling
Notes:
1. Not 100% tested.
2. See Figure 9 and Table 14 for test specifications.
3. Measurements performed by placing a 50-ohm termination on the data pin with a bias of VCC/2. The time from OE high to
the data bus driven to VCC/2 is taken as tDF.
Figure 11. Read Operation Timings
tRC
Addresses
Addresses Stable
tACC
CE
tRH
tRH
tDF
tOE
OE
tOEH
WE
tCE
tOH
High-Z
Output
Output Valid
High-Z
RESET
RY/BY
0V
PRELIMINARY
(May, 2005, Version 0.0)
33
AMIC Technology, Corp.
A29DL32x Series
AC CHARACTERISTICS
Hardware Reset ( RESET )
Parameter
JEDEC
Std
Description
Test Setup
All Speed Options
Unit
tREADY
RESET Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
Max
20
µs
tREADY
RESET Pin Low (Not During Embedded
Algorithms) to Read or Write (See Note)
Max
500
ns
tRP
RESET Pulse Width
Min
500
ns
tRH
RESET High Time Before Read (See Note)
Min
50
ns
tRB
RY/ BY Recovery Time
Min
0
ns
tRPD
RESET Low to Standby Mode
Min
20
µs
Note: Not 100% tested.
Figure 12. RESET Timings
RY/BY
0V
CE, OE
tRH
RESET
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
~
~ ~
~
tReady
RY/BY
tRB
CE, OE
~
~
RESET
tRP
PRELIMINARY
(May, 2005, Version 0.0)
34
AMIC Technology, Corp.
A29DL32x Series
AC CHARACTERISTICS
Word/Byte Configuration ( BYTE )
Parameter
JEDEC
Description
Std
-70
tELFL/tELFH
Unit
All Speed Options
-80
-90
-120
CE to BYTE Switching Low or High
Max
5
ns
tFLQZ
BYTE Switching Low to Output High-Z
Max
25
25
30
30
ns
tHQV
BYTE Switching High to Output Active
Min
70
80
90
120
ns
Figure 13. BYTE Timings for Read Operations
CE
OE
BYTE
tELFL
BYTE
Switching
from word to
byte mode
Data Output
(I/O0-I/O14)
I/O0-I/O14
Data Output
(I/O0-I/O7)
I/O15
Output
I/O15 (A-1)
Address Input
tFLQZ
tELFH
BYTE
BYTE
Switching
from byte to
word mode
I/O0-I/O14
Data Output
(I/O0-I/O7)
I/O15 (A-1)
Address Input
Data Output
(I/O0-I/O14)
I/O15
Output
tFHQV
Figure 14. BYTE Timings for Write Operations
CE
The falling edge of the last WE signal
WE
BYTE
tSET
(tAS)
tHOLD(tAH)
Note:
Refer to the Erase/Program Operations table for tAS and tAH specifications.
PRELIMINARY
(May, 2005, Version 0.0)
35
AMIC Technology, Corp.
A29DL32x Series
AC CHARACTERISTICS
Erase and Program Operations
Description
Parameter
JEDEC
Std
tAVAV
tWC
Write Cycle Time (Note 1)
Min.
tAVWL
tAS
Address Setup Time
Min.
tASO
Address Setup Time to OE low during toggle bit
polling
tAH
Address Hold Time
tAHT
Address Hold Time From CE or OE high during
toggle bit polling
tDVWH
tDS
Data Setup Time
Min.
tWHDX
tDH
Data Hold Time
Min.
Output Enable High during toggle bit polling
Min.
Read Recover Time Before Write
Min.
tWLAX
tOEPH
tGHWL
tGHWL
Unit
Speed
Min.
-70
-80
-90
-120
70
80
90
120
0
ns
ns
15
15
15
15
ns
45
45
45
50
ns
0
35
35
ns
45
50
0
20
20
ns
20
20
ns
ns
0
( OE high to WE low)
ns
tELWL
tCS
CE Setup Time
Min.
0
ns
tWHEH
tCH
CE Hold Time
Min.
0
ns
tWLWH
tWP
Write Pulse Width
Min.
30
30
35
50
ns
tWHDL
tWPH
Write Pulse Width High
Min.
30
30
30
30
ns
tSR/W
Latency Between Read and Write Operations
Min.
0
Byte
Typ.
5
Word
Typ.
7
Typ.
4
sec
Sector Erase Operation (Note 2)
Typ.
0.7
sec
tvcs
VCC Set Up Time (Note 1)
Min.
50
µs
tRB
Recovery Time from RY/ BY
Min
0
ns
Program/Erase Valid to RY/ BY Delay
Min
90
ns
tWHWH1
tWHWH1
tWHWH1
tWHWH1
Byte Programming Operation
(Note 2)
µs
Accelerated Programming Operation,
Word or Byte (Note 2)
tWHWH2
tWHWH2
tBUSY
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
PRELIMINARY
(May, 2005, Version 0.0)
36
AMIC Technology, Corp.
A29DL32x Series
AC CHARACTERISTICS
Figure 15. Program Operation Timings
Read Status Data (last two cycles)
Program Command Sequence (last two cycles)
PA
555h
PA
PA
~
~ ~
~
Addresses
tAS
~
~
tWC
tAH
CE
~
~
tCH
OE
tWP
~
~
tWHWH1
WE
tCS
tWPH
tDH
A0h
Data
PD
~
~
tDS
tBUSY
Status
DOUT
tRB
~
~ ~
~
RY/BY
tVCS
VCC
Note :
1. PA = program address, PD = program data, Dout is the true data at the program address.
2. Illustration shows device in word mode.
Figure 16. Accelerated Program Timing Diagram
WP/ACC
~
~
VHH
VIL or VIH
VIL or VIH
tVHH
PRELIMINARY
(May, 2005, Version 0.0)
tVHH
37
AMIC Technology, Corp.
A29DL32x Series
AC CHARACTERISTICS
Figure 17. Chip/Sector Erase Operation Timings
Read Status Data
Erase Command Sequence (last two cycles)
tAS
~
~
tWC
VA
555h for chip erase
tAH
VA
~
~ ~
~
SA
2AAh
Addresses
~
~
CE
OE
tCH
~
~
tWP
WE
tWPH
tWHWH2
tCS
Data
tDH
55h
30h
~
~
tDS
10h for chip erase
tBUSY
In
Progress
Complete
tRB
~
~
RY/BY
~
~
tVCS
VCC
Note :
1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").
2. Illustration shows device in word mode.
PRELIMINARY
(May, 2005, Version 0.0)
38
AMIC Technology, Corp.
A29DL32x Series
AC CHARACTERISTICS
Figure 18. Back-to-back Read/Write Cycle Timings
Addresses
tWC
tRC
Valid PA
Valid RA
tAH
tWC
tWC
Valid PA
tACC
Valid PA
tCPH
tCE
CE
tCP
tOE
OE
tGHWL
tOEH
tWP
WE
tDF
tWPH
tDS
tOH
tDH
Valid
In
Data
Valid
Out
Valid
In
Valid
In
tSR/W
WE Controlled Write Cycle
Read Cycle
CE Controlled Write Cycles
Figure 19. Data Polling Timings (During Embedded Algorithms)
~
~
tRC
Addresses
VA
tACC
CE
VA
~
~ ~
~
VA
tCE
tCH
~
~
tOE
OE
tDF
~
~
tOEH
WE
tOH
Status Data
~
~
Complement
Complement
True
Valid Data
~
~
High-Z
I/O7
Status Data
True
Valid Data
High-Z
I/O0 - I/O6
High-Z
tBUSY
~
~
RY/BY
Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
PRELIMINARY
(May, 2005, Version 0.0)
39
AMIC Technology, Corp.
A29DL32x Series
AC CHARACTERISTICS
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
tAS
~
~
tAHT
~
~
Addresses
tAHT
tASO
tCEPH
CE
~
~
tOEH
tOEPH
WE
~
~
OE
I/O6 , I/O2
tOE
Valid Status
Valid Status
Valid Status
(first read)
(second read)
~
~
tDH
Valid Status
Valid Data
(stop togging)
~
~
RY/BY
Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
Figure 21. I/O2 vs. I/O6
~
~
~
~
Erase
Complete
~
~
~
~
~
~
~
~
~
~
Erase
~
~
Erase Suspend
Read
~
~
~
~
~
~
I/O2
~
~
I/O6
Erase
Resume
Erase
Suspend
Program
Erase Suspend
Read
~
~
Erase
Enter Erase
Suspend Program
~
~
WE
Erase
Suspend
~
~
Enter
Embedded
Erasing
I/O2 and I/O6 toggle with OE and CE
Note : Both I/O6 and I/O2 toggle with OE or CE. See the text on I/O6 and I/O2 in the section "Write Operation Status" for
more information.
PRELIMINARY
(May, 2005, Version 0.0)
40
AMIC Technology, Corp.
A29DL32x Series
AC CHARACTERISTICS
Temporary Sector/Sector Block Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
500
ns
tVHH
VHH Rise and Fall Time (See Note)
Min
250
µs
tRSP
RESET Setup Time for Temporary
Min
4
µs
Min
4
µs
Sector/Sector Block Unprotect
RESET Hold Time from RY/ BY High for
Temporary Sector/Sector Block Unprotect
tRRB
Note: Not 100% tested.
Figure 22. Temporary Sector/Sector Block Unprotect Timing Diagram
VID
~
~
VID
VSS, VIL,
or VIH
VSS, VIL,
or VIH
RESET
tVIDR
tVIDR
Program or Erase Command Sequence
CE
~
~
WE
RY/BY
~ ~
~
~
tRSP
tRRB
Program/Erase Command Sequence
CE
~
~
WE
555
2AA
555
AA
55
77
XXX
~
~
~ ~
Address
FQ
~
~
I/O0 - I/O7
RY/BY
PRELIMINARY
(May, 2005, Version 0.0)
41
AMIC Technology, Corp.
A29DL32x Series
AC CHARACTERISTICS
VID
VIH
~
~
RESET
SA, A6,
A1, A0
Valid*
Valid*
~
~
Valid*
Verify
~
~
Sector Protect/Unprotect
60h
60h
40h
Status
~
~
Data
1us
CE
Sector Protect:150us
Sector Unprotect:15ms
WE
OE
Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0
200ns-300ns
Figure 23. Sector/Sector Block Protect and Unprotect Timing Diagram
PRELIMINARY
(May, 2005, Version 0.0)
42
AMIC Technology, Corp.
A29DL32x Series
AC CHARACTERISTICS
Alternate CE Controlled Erase and Program Operations
Parameter
Description
Unit
Speed
JEDEC
Std
tAVAV
tWC
Write Cycle Time (Note 1)
Min.
tAVEL
tAS
Address Setup Time
Min.
tELAX
tAH
Address Hold Time
Min.
45
45
45
50
ns
tDVEH
tDS
Data Setup Time
Min.
35
35
45
50
ns
tEHDX
tDH
Data Hold Time
Min.
0
ns
tGHEL
tGHEL
Min.
0
ns
Read Recover Time Before Write
-70
-80
-90
-120
70
80
90
120
0
ns
ns
( OE High to WE Low)
tWLEL
tWS
WE Setup Time
Min.
0
ns
tEHWH
tWH
WE Hold Time
Min.
0
ns
tELEH
tCP
CE Pulse Width
Min.
30
30
45
50
ns
tEHEL
tCPH
CE Pulse Width High
Min.
30
30
30
30
ns
tWHWH1
tWHWH1
tWHWH1
tWHWH1
tWHWH2
tWHWH2
µs
Programming Operation
Byte
Typ.
5
(Note 2)
Word
Typ.
7
Typ.
4
µs
Typ.
0.7
sec
Accelerated Programming Operation,
Word or Byte (Note 2)
Sector Erase Operation (Note 2)
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
PRELIMINARY
(May, 2005, Version 0.0)
43
AMIC Technology, Corp.
A29DL32x Series
AC CHARACTERISTICS
Figure 24. Alternate CE Controlled Write (Erase/Program) Operation Timings
PA for program
SA for sector erase
555 for chip erase
Data Polling
~
~
555 for program
2AA for erase
PA
~
~
Addresses
tAS
tWH
tAH
~
~
tWC
WE
OE
~
~
tGHEL
tCP
~
~
tWHWH1 or 2
tCPH
CE
tBUSY
tWS
tDS
Data
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
DOUT
I/O7
~
~
~
~
tDH
RESET
~
~
RY/BY
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. I/O7 is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.
PRELIMINARY
(May, 2005, Version 0.0)
44
AMIC Technology, Corp.
A29DL32x Series
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ. (Note 1)
Max. (Note 2)
Unit
Sector Erase Time
0.7
15
sec
Chip Erase Time
27
Byte Programming Time
5
150
µs
Word Programming Time
7
210
µs
Accelerated Word/Byte Programming Time
4
120
µs
Chip Programming Time
Byte Mode
9
27
sec
(Note 3)
Word Mode
6
18
sec
Comments
Excludes 00h programming
prior to erasure (Note 4)
sec
Excludes system-level
overhead (Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC, 10,000 cycles. Additionally, programming
typically assumes checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 12
for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 10,000 cycles.
LATCH-UP CHARACTERISTICS
Description
Min.
Max.
-1.0V
VCC+1.0V
-100 mA
+100 mA
-1.0V
12.5V
Input Voltage with respect to VSS on all I/O pins
VCC Current
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE and RESET )
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at time.
PACKAGE AND PIN CAPACITANCE
Parameter Symbol
CIN
Parameter Description
Input Capacitance
COUT
Output Capacitance
CIN2
Control Pin Capacitance
Test Setup
VIN=0
VOUT=0
VIN=0
Typ.
Max.
Unit
TSOP
6
7.5
pF
TF BGA
4.2
5
pF
TSOP
8.5
12
pF
TF BGA
5.4
6.5
pF
TSOP
7.5
9
pF
TF BGA
3.9
4.7
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0MHz
DATA RETENTION
Parameter
Minimum Pattern Data Retention Time
PRELIMINARY
(May, 2005, Version 0.0)
45
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
AMIC Technology, Corp.
A29DL32x Series
Ordering Information
Top Boot Sector Flash
Part No.
Access Time
(ns)
Active Read
Current
Typ. (mA)
Program/Erase
Current
Typ. (mA)
Standby Current
Typ. (µA)
70
10
20
0.2
A29DL322TV-70
48 pin TSOP
A29DL322TG-70
48 ball TFBGA
A29DL322TV-80
48 pin TSOP
80
10
20
0.2
A29DL322TG-80
48 ball TFBGA
A29DL322TV-90
48 pin TSOP
90
10
20
0.2
A29DL322TG-90
48 ball TFBGA
A29DL322TV-120
48 pin TSOP
120
10
20
0.2
A29DL322TG-120
48 ball TFBGA
A29DL323TV-70
48 pin TSOP
70
10
20
0.2
A29DL323TG-70
48 ball TFBGA
A29DL323TV-80
48 pin TSOP
80
10
20
0.2
A29DL323TG-80
48 ball TFBGA
A29DL323TV-90
48 pin TSOP
90
10
20
0.2
A29DL323TG-90
48 ball TFBGA
A29DL323TV-120
48 pin TSOP
120
10
20
0.2
A29DL323TG-120
48 ball TFBGA
A29DL324TV-70
48 pin TSOP
70
10
20
0.2
A29DL324TG-70
48 ball TFBGA
A29DL324TV-80
48 pin TSOP
80
10
20
0.2
A29DL324TG-80
48 ball TFBGA
A29DL324TV-90
48 pin TSOP
90
10
20
0.2
A29DL324TG-90
48 ball TFBGA
A29DL324TV-120
48 pin TSOP
120
10
20
A29DL324TG-120
PRELIMINARY
Package
(May, 2005, Version 0.0)
0.2
48 ball TFBGA
46
AMIC Technology, Corp.
A29DL32x Series
Ordering Information (continued)
Bottom Boot Sector Flash
Part No.
Access Time
(ns)
Active Read
Current
Typ. (mA)
Program/Erase
Current
Typ. (mA)
Standby Current
Typ. (µA)
70
10
20
0.2
A29DL322UV-70
48 pin TSOP
A29DL322UG-70
48 ball TFBGA
A29DL322UV-80
48 pin TSOP
80
10
20
0.2
A29DL322UG-80
48 ball TFBGA
A29DL322UV-90
48 pin TSOP
90
10
20
0.2
A29DL322UG-90
48 ball TFBGA
A29DL322UV-120
48 pin TSOP
120
10
20
0.2
A29DL322UG-120
48 ball TFBGA
A29DL323UV-70
48 pin TSOP
70
10
20
0.2
A29DL323UG-70
48 ball TFBGA
A29DL323UV-80
48 pin TSOP
80
10
20
0.2
A29DL323UG-80
48 ball TFBGA
A29DL323UV-90
48 pin TSOP
90
10
20
0.2
A29DL323UG-90
48 ball TFBGA
A29DL323UV-120
48 pin TSOP
120
10
20
0.2
A29DL323UG-120
48 ball TFBGA
A29DL324UV-70
48 pin TSOP
70
10
20
0.2
A29DL324UG-70
48 ball TFBGA
A29DL324UV-80
48 pin TSOP
80
10
20
0.2
A29DL324UG-80
48 ball TFBGA
A29DL324UV-90
48 pin TSOP
90
10
20
0.2
A29DL324UG-90
48 ball TFBGA
A29DL324UV-120
48 pin TSOP
120
10
20
A29DL324UG-120
PRELIMINARY
Package
(May, 2005, Version 0.0)
0.2
48 ball TFBGA
47
AMIC Technology, Corp.
A29DL32x Series
Package Information
TSOP 48L (Type I) Outline Dimensions
unit: inches/mm
1
48
24
25
y
D1
A1
A2 A
D
0.25
c
S
e
E
b
D
Detail "A"
L
θ
Detail "A"
Symbol
Dimensions in inches
Dimensions in mm
Min
Nom
Max
Min
Nom
Max
A
-
-
0.047
-
-
1.20
A1
0.002
-
0.006
0.05
-
0.15
A2
0.037
0.039
0.042
0.94
1.00
1.06
b
0.007
0.009
0.011
0.18
0.22
0.27
c
0.004
-
0.008
0.12
-
0.20
D
0.779
0.787
0.795
19.80
20.00
20.20
D1
0.720
0.724
0.728
18.30
18.40
18.50
E
-
0.472
0.476
-
12.00
12.10
e
L
0.020 BASIC
0.016
S
0.020
0.50 BASIC
0.024
0.40
0.011 Typ.
0.50
0.60
0.28 Typ.
y
-
-
0.004
-
-
0.10
θ
0°
-
8°
0°
-
8°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
PRELIMINARY
(May, 2005, Version 0.0)
48
AMIC Technology, Corp.
A29DL32x Series
Package Information
48LD CSP (6 x 8 mm) Outline Dimensions
unit: mm
(48TFBGA)
BOTTOM VIEW
TOP VIEW
b
3
2
1
1
H
H
G
G
F
F
E
E
D
D
C
C
B
B
A
A
2
3
4
5
6
E
4
E1
5
e
6
e
D1
Ball*A1 CORNER
D
A
SIDE VIEW
SEATING PLANE
A1
C
0.10 C
Symbol
A
A1
b
D
D1
e
E
E1
PRELIMINARY
(May, 2005, Version 0.0)
Dimensions in mm
Min.
0.20
0.30
5.90
Nom.
0.25
6.00
4.00 BSC
0.80
7.90
8.00
5.60 BSC
49
Max.
1.20
0.30
0.40
6.10
8.10
AMIC Technology, Corp.