A83516 Series Preliminary 8 Bit Microcontroller Document Title 8 Bit Microcontroller Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue November 25, 1998 Preliminary (November, 1998, Version 0.0) AMIC Technology, Inc. A83516 Series Preliminary 8 Bit Microcontroller Features n Four 8-bit bidirectional ports n Three 16-bit Timers/Counters (Timer 2 with up/down counter feature) n One full duplex serial port n Boolean processor n Six interrupt sources, two priority levels n Available in 40-pin P-DIP and 44-pin PLCC packages n 8-bit CMOS microcontroller n Fully static design with power saving idle mode and power down mode n Low standby current at full supply voltage n Versions for 12/24/40MHZ operating frequency n On chip 256B RAM n On chip 64KB X 8 MASK-ROM program memory n 64K bytes external data memory space General Description The AMIC A83516 is a high-performance 8-bit microcontroller. It is compatible with the industry standard 80C52 microcontroller series. The A83516 contains a 256B RAM, 64KB X 8 ROM, four 8-bit bidirectional parallel ports, three 16-bit timer/counters, a serial port and six interrupt sources with two priority levels. The A83516 has two power reduction modes, idle mode and power-down mode. It supports 64KB external data memory. Pin Configurations PRELIMINARY (November, 1998, Version 0.0) 1 P1.4 P1.3 P1.2 P1.1,T2EX P1.0,T2 NC VCC P0.0,AD0 P0.1,AD1 P0.2,AD2 P0.3,AD3 5 4 3 2 1 44 43 42 41 40 7 39 P0.4,AD4 P1.6 8 38 P0.5,AD5 P1.7 9 37 P0.6,AD6 RST 10 36 P0.7,AD7 RXD,P3.0 11 35 EA NC 12 34 NC TXD,P3.1 13 14 33 ALE INT0, P3.2 32 PSEN INT1,P3.3 15 31 P2.7,A15 T0,P3.4 16 30 P2.6,A14 T1,P3.5 17 29 P2.5,A13 23 24 25 26 27 28 P2.0,A8 P2.1,A9 P2.2,A10 P2.3,A11 P2.4,A12 22 21 XTAL1 GND NC 20 A83516L 19 P2.6,A14 P2.5,A13 P2.4,A12 P2.3,A11 P2.2,A10 P2.1,A9 P2.0,A8 P1.5 18 22 21 VCC P0.0,AD0 P0.1,AD1 P0.2,AD2 P0.3,AD3 P0.4,AD4 P0.5,AD5 P0.6,AD6 P0.7,AD7 EA ALE PSEN P2.7,A15 RD,P3.7 XTAL2 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 WR,P3.6 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A83516 T2,P1.0 T2EX,P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RXD,P3.0 TXD,P3.1 INT0,P3.2 INT1,P3.3 T0,P3.4 T1,P3.5 WR,P3.6 RD,P3.7 XTAL2 n PLCC 6 n P-DIP AMIC Technology, Inc. A83516 Series Block Diagram PSEN 64K BYTE ROM ALE EA RST XTAL1 TIMING AND CONTROL XTAL2 P0.0-P0.7 (AD0-AD7) P2.0-P2.7 A8-A15 PORT 0 ADDRESS PORT 2 ADDRESS OSCILLATOR SFR CPU CORE TIMER 2 INTERRUPT SERIAL PORT TIMER 0.1 256B RAM PORT 1 PORT 3 P1.0-P1.7 PRELIMINARY (November, 1998, Version 0.0) P3.0-P3.7 2 AMIC Technology, Inc. A83516 Series Pin Description Pin No. P-DIP PLCC 1-8 2-9 Symbol Type P1.0 - P1.7 I/O Port1. Port1 is a bidirectional I/O port with internal pull-ups. Pin P1.0 and P1.1 also provide alternate functions as follows: I/O P1.0 T2 Timer/Counter2 external input/clock out I P1.1 T2EX Timer/Counter2 capture/reload input Reset input, active high. It must be kept high for at least two machine cycles to be recognized by the processor 9 10 RST I 10 - 17 11, P3.0 - P3.7 I/O 13 - 19 Description Port3. Port3 is a bidirectional I/O port with internal pull-ups. Port3 pins also serve alternate functions as follows: I P3.0 RXD Serial receive port O P3.1 TXD Serial transmit port I P3.2 INT0 External interrupt 0 I P3.3 INT1 External interrupt 1 I P3.4 T0 Timer/Counter 0 input I P3.5 T1 Timer/Counter 1 input O P3.6 WR External data memory write strobe O P3.7 RD External data memory read strobe 18 20 XTAL2 O Crystal2. This is the output of crystal oscillator. It is the inversion of XTAL1 19 21 XTAL1 I Crystal1. This is the input of crystal oscillator. It can be driven by an external clock 20 22 GND I Ground 21 - 28 24 - 31 P2.0 - P2.7 I/O Port2. Port2 is a bidirectional I/O port with internal pull-ups. Port2 is also the multiplexed upper-order address bus during accesses to external data memory 29 32 PSEN O Program Store Enable : active low. The read strobe to external program memory. PSEN is activated in each machine cycle when fetching external program memory 30 33 ALE O Address Latch Enable : active high. ALE is used to enable the address latch that separates the data on Port 0 31 35 EA I External Access Enable : active low. It is held low to enable the device to fetch code from external program memory 32 - 39 36 - 43 P0.7 - P0.0 I/O 40 44 VCC I PRELIMINARY (November, 1998, Version 0.0) Port0. Port0 is an open drain, bidirectional I/O port. Port0 is also the multiplexed low-order address bus during accesses to external data memory Power supply 3 AMIC Technology, Inc. A83516 Series Functional Description The A83516 is a high speed 8-bit microcontroller. The architecture consists of a core controller, four general purposes I/O ports, 256 bytes RAM internal register, 64K bytes ROM and a serial port. This microcontroller supports 111 opcodes and executes instructions in 12 clock/machine cycle. It can reference both a 64K program address space and a 64K data storage space. Timer/Counter 0, 1 and 2 Timer 0,1 and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0. TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TMOD and TCON registers support control function for Timer 0 and Timer 1. The T2CON register provides control function for Timer 2. When operating reload/capture mode, RCAP2H and RCAP2L will be used. N/C XTAL 2 EXTERNAL OSCILLATOR SIGNAL XTAL 1 VSS Interrupt The A83516 provides 6 interrupt modes. These consist of 2 external interrupts, 3 internal interrupts and a serial port interrupt. The enable/disable interrupt is controlled by IE register in SFR. The priority of interrupts is controlled by IP register in SFR. Figure 2. External Clock Drive configuration Power Reduce Mode IDLE Mode It is executed by IDLE bit of PCON register in SFR. In idle mode, the clock to microcontroller core is stopped. The status in microcontroller core and I/O data are kept. The microcontroller will stop idle status when either a reset or an interrupt occurs. Serial Port Transfer The A83516 provides a full duplex serial transfer function. This function is controlled by SCON register in SFR. And the data is storaged in SBUF register during transmitting and receiving. POWER-DOWN Mode It is executed by PD bit of PCON register in SFR. In power-down mode, the oscillator clock will stop. The data in RAM and status in SFR will be kept. The only way to exit power-down mode is to reset this chip. Oscillator Characteristics The oscillator connections are shown as Figure 1. And Figure 2. When quartz crystal is used, C1 and C2 are 30pF shown in Figure 1. When external clock is used, the internal clock will be gotten through a divide-by-two flip-flop. When starting up, the input loading for XTAL1 pin is 100pF. This is due to interaction between the amplifier and its feedback capacitance interaction. After the external signal meets the VIL and VIH specification the capacitance will not exceed 20pF. RESET The external reset signal must be held high for at least two machine cycles during the oscillator running. After reset, the ports are held high, SP register to 07H, all of the other SFR registers except SBUF to 00H, and SBUF is not reset. C2 XTAL 2 C1 XTAL 1 VSS C1,C2 = 30pF ± 10pF for Crystals Figure 1. Oscillator Connections PRELIMINARY (November, 1998, Version 0.0) 4 AMIC Technology, Inc. A83516 Series Recommended DC Operating Conditions (TA = -25°C to + 85°C) Symbol Parameter VCC Supply Voltage GND Ground Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V VIH* Input High Voltage 2.4 - VCC+0.2 V VIL Input Low Voltage 0 - 0.8 V * XTAL1 is a CMOS input. RESET is a Schmit trigger input. The min. of VIH is 3.5 Volts for these two pins. Absolute Maximum Ratings* *Comments VCC to GND . . . . . . . . . . . . . . . . . . . . . –0.3V to +7.0V IN, IN/OUT Volt to GND . . . . . . . . . -0.5V to VCC + 0.5V Operating Temperature, Topr . . . . . . . -25°C to + 85°C Storage Temperature, Tstg . . . . . . . . . -55°C to + 125°C 1* Power Dissipation , Pr . . . . . . . . . . . . . . . . . . . . . . 1W Soldering Temperature & Time . . . . . . . . . 260°C, 10sec Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. 1* : Operating frequency is 40MHZ DC Electrical Characteristics (TA = -25°C to + 85°C, VCC = 5V ± 10%) Symbol Parameter Min. Max. Unit Conditions ILI Input Leakage Current - 10 µA VIN = GND to VCC ILO Output Leakage Current - 10 µA VI/O = GND to VCC ICC Operating Current - 50 mA foper = 40MHZ External oscillator is on XTAL1 pin No load IIDLE IDLE Mode Current - 6 mA foper = 40MHZ VRST = GND, V EA = GND VPORT0 = VCC IPD POWER-DOWN Mode Current - 20 µA No crystal oscillator input VRST = GND, V EA = GND VPORT0 = VCC VOL1 Output Low Voltage (PORT1, PORT2 and PORT3) - 0.45 V IOL = 2mA VOL2 Output Low Voltage - 0.45 V IOL = 4mA VOH1 (ALE, PSEN and PORT0) Output High Voltage (PORT1, PORT2 and PORT3) 2.4 - V IOH = -100µA VOH2 Output High Voltage 2.4 - V IOH = -400µA - 10 pF 1MHZ , 25°C 1 (ALE, PSEN and PORT0) C1 Input Pin Capacitance 1. For RESET pin, the ILI max. is 300 µA, since it has an internal pull-low of approx. 30KΩ resistor. PRELIMINARY (November, 1998, Version 0.0) 5 AMIC Technology, Inc. A83516 Series AC Characteristics (TA = -25°C to + 85°C, VCC = 5V ± 10%) Symbol Parameter Min. Max. Unit 2tck – 201 - ns - ns - ns - ns 1tck - ns Program Memory Cycle tAP ALE Pulse Width tALS Address Valid to ALE Low 1tck tALH Address Hold from ALE Low 1tck top PSEN Pulse Width tAO ALE Low to PSEN Low 2 3tck - 20 1 tOI PSEN Low to Valid Instruction in - 2tck ns tIDO Input Instruction Hold after PSEN High - 1tck ns tIFO Input Instruction Float after PSEN High - 1tck ns Clock Frequency 0 40 MHZ Clock Period 25 - ns Clock High Time 10 - ns Clock Low Time 10 - ns 6tck - 201 - ns External Clock fOPER tCK 3 tCKH 4 tCKL4 Data Memory Cycle tPR RD Pulse Width tPD RD Low to Valid Data in - 4tck ns tDHR Data Hold from RD High 0 2tck ns tDFR Data Float from RD High 0 2tck tAR tWP WR Pulse Width tDS Valid Data to WR Low Data Hold from WR High tDHW tAW 3tck ALE Low to RD Low 6tck - 20 3tck + 20 1 ns 1 ns - ns 1tck - ns 1tck - ns 1 ALE Low to WR Low 3tck 3tck + 20 ns Serial Port Clock 12tck - ns Serial Port Cycle tSCK 1. 2. 3. 4. tKI Clock Rising Edge to Valid Input Data - 11tck ns tIKH Input Data to Serial Clock Rising Clock Hold Time 0 - ns tOKS Output Data to Serial Clock Rising Edge Setup Time 11tck - ns tOKH Output Data to Serial Clock Rising Edge Hold Time 1tck - ns This 20 ns is due to buffer driving delay and wire loading. Instruction cycle time is 12 tck. tck = 1/ foper There are no duty cycle requirements on the XTAL1 input. PRELIMINARY (November, 1998, Version 0.0) 6 AMIC Technology, Inc. A83516 Series Timing Waveforms Program Memory Cycle S1 S2 S3 S4 S5 S6 S1 XTAL 1 tAP ALE tAO PSEN tOP tALS A8 - A15 PORT 2 tALH A8 - A15 tIFO tOI tIHO A0 - A7 PORT 0 A0 - A7 INSTRUCTION IN INSTRUCTION IN Clock Input Waveform tCKH XTAL 1 tCKL tCK PRELIMINARY (November, 1998, Version 0.0) 7 AMIC Technology, Inc. A83516 Series Timing Waveforms (continued) Data Memory Read Cycle S4 S5 S6 S1 S2 S4 S3 S5 S6 XTAL 1 ALE PSEN A8-A15 PORT 2 PORT 0 A0-A7 tAR DATA IN tRD A0-A7 tDHR RD tDFR tRP Data Memory Write Cycle S4 S5 S6 S1 S2 S4 S3 S5 S6 XTAL 1 ALE PSEN A8-A15 PORT 2 A0-A7 PORT 0 DATA OUT tDS tDHW WR tAW tWP Serial Port Timing – Shift Register Mode INSTRUCTION 0 1 2 5 4 3 6 7 8 ALE tSCK CLOCK tOKH tOKS OUTPUT DATA 0 1 2 tKI 3 4 5 6 7 tIKH SET TI INPUT DATA VALID VALID VALID VALID VALID VALID VALID VALID SET RI PRELIMINARY (November, 1998, Version 0.0) 8 AMIC Technology, Inc. A83516 Series Ordering Information Part No. RAM ROM FREQ (MHZ) Package A83516-12 256 Byte 64K Byte 12 40L P-DIP A83516L-12 256 Byte 64K Byte 12 44L PLCC A83516-24 256 Byte 64K Byte 24 40L P-DIP A83516L-24 256 Byte 64K Byte 24 44L PLCC A83516-40 256 Byte 64K Byte 40 40L P-DIP A83516L-40 256 Byte 64K Byte 40 44L PLCC PRELIMINARY (November, 1998, Version 0.0) 9 AMIC Technology, Inc. A83516 Series Package Information P-DIP 40L Outline Dimensions unit: inches/mm D 21 1 20 E1 40 A1 A2 Base Plane Seating Plane L A C E B eA e1 B1 θ 0º/15º Symbol Dimensions in inches Dimensions in mm Min Nom Max Min Nom Max A - - 0.210 - - 5.344 A1 0.015 - - 0.381 - - A2 0.150 0.155 0.160 3.810 3.937 4.064 B 0.018 TYP 0.457 TYP B1 0.050 TYP 1.270 TYP C - 0.010 - - 0.254 - D 2.049 2.054 2.059 52.045 52.172 52.299 E 0.590 0.600 0.610 14.986 15.240 15.494 E1 0.542 0.547 0.552 13.767 13.894 14.021 e1 0.100 TYP 2.540 TYP L 0.120 0.130 0.140 3.048 3.302 3.556 eA 0.622 0.642 0.662 15.799 16.307 16.815 Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. PRELIMINARY (November, 1998, Version 0.0) 10 AMIC Technology, Inc. A83516 Series Package Information PLCC 44L Outline Dimension unit: inches/mm HD D 1 44 40 39 17 29 E HE GE 7 18 0.630/0.590 6 28 b 0.022/0.016 b1 0.032/0.026 Seating Plane A A2 A1 D 0.020 MIN e 0.050 REF 0.150 REF L 0.014/0.0008 C 0.004 y GD 0.630/0.590 Dimensions in inches Symbol Min Nom Max Dimensions in mm Min Nom Max A - - 0.185 - - 4.70 D 0.648 0.653 0.658 16.46 16.59 16.71 E 0.648 0.653 0.658 16.46 16.59 16.71 HD 0.680 0.690 0.700 17.27 17.53 17.78 HE 0.680 0.690 0.700 17.27 17.53 17.78 L 0.090 0.100 0.110 2.29 2.54 2.79 θ 0° - 10° 0° - 10° Notes: 1. Dimensions D and E do not include resin fins. 2. Dimensions GD & GE are for PC Board surface mount pad pitch design reference only. PRELIMINARY (November, 1998, Version 0.0) 11 AMIC Technology, Inc.