AMICC LP61L1008S-15

LP61L1008 Series
128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
Document Title
128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
Revision History
Rev. No.
2.0
History
Issue Date
Add Product Family and 32-pin sTSOP (Type I) package
June 11, 2002
(June, 2002, Version 2.0)
Remark
AMIC Technology, Inc.
LP61L1008 Series
128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
Features
General Description
n Single 3.3V ± 10% power supply
n Access times: 12/15 ns (max.)
n Current: Operating: 180mA (max.)
Standby:
5mA (max.)
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL compatible
n Center Power/Ground Pin Configuration
n Common I/O using three-state output
n Output enable and two chip enable inputs for easy
application
n Data retention voltage: 2.0V (min.)
n Available in 32-pin SOJ 300 mil and 32-pin sTSOP
packages
The LP61L1008 is a high speed 1,048,576-bit static
random access memory organized as 131,072
words by 8 bits and operates on a single 3.3V power
supply.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
The chip enable input is provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2.0V.
Product Family
Power Dissipation
Product
Family
Operating
Temperature
VCC
Range
Speed
Data Retention
(ICCDR, Typ.)
Standby
(ISB1, Typ.)
Operating
(ICC2, Typ.)
LP61L1008
0°C~70°C
3.0V~3.6V
12/15 ns
10µA
20µA
66mA
Package
Type
32L SOJ
32L sTSOP
1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
Pin Configuration
A0
1
32
A16
A1
2
31
A15
A2
3
30
A14
4
29
A13
CE
5
28
OE
I/O1
6
27
I/O8
I/O2
7
26
I/O7
VCC
8
25
GND
GND
9
24
VCC
I/O3
10
23
I/O6
I/O4
11
22
I/O5
WE
12
21
A12
A4
13
20
A11
A5
14
19
A10
A6
15
18
A9
A7
16
17
A8
(June, 2002, Version 2.0)
LP61L1008S
A3
A0
A1
A2
A3
CE
I/O0
I/O1
VCC
VSS
I/O2
I/O3
WE
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
~
n sTSOP
LP61L1008X
~
~
n SOJ
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O7
I/O6
VSS
VCC
I/O5
I/O4
A12
A11
A10
A9
A8
AMIC Technology, Inc.
LP61L1008 Series
Block Diagram
VCC
GND
A0
256 X 4096
DECODER
MEMORY ARRAY
INPUT
DATA
CIRCUIT
COLUMN I/O
A14
A15
A16
I/O1
I/O8
CE
OE
WE
CONTROL
CIRCUIT
Pin Description
Pin No.
Symbol
1 - 4, 13 - 21,
29- 32
A0 - A16
12
WE
Write Enable
28
OE
Output Enable
5
CE
Chip Enable
6 –7, 10 - 11,
22 – 23, 26 - 27
I/O1 - I/O8
8, 24
VCC
Power Supply
9, 25
GND
Ground
(June, 2001, Version 2.0)
Description
Address Inputs
Data Input/Outputs
2
AMIC Technology, Inc.
LP61L1008 Series
Recommended DC Operating Conditions
(TA = 0°C to + 70°C)
Symbol
Parameter
VCC
Supply Voltage
GND
Ground
Min.
Typ.
Max.
Unit
3.0
3.3
3.6
V
0
0
0
V
VIH
Input High Voltage
2.2
-
VCC + 0.3
V
VIL
Input Low Voltage
-0.3
0
+0.8
V
CL
Output Load
-
-
30
pF
TTL
Output Load
-
-
1
-
Absolute Maximum Ratings*
*Comments
VCC to GND .............................................. -0.5V to +4.6V
IN, IN/OUT Volt to GND .....................-0.5V to VCC +0.5V
Operating Temperature, Topr ...................... 0°C to +70°C
Storage Temperature, Tstg..................... -55°C to +125°C
Temperature Under Bias, Tbias................ -10°C to +85°C
Power Dissipation, Pt................................................1.0W
Soldering Temp. & Time .............................260°C, 10 sec
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
DC Electrical Characteristics
(TA = 0°C to + 70°C, VCC = 3.3V ± 10%, GND = 0V)
LP61L1008-12/15
Symbol
Parameter
Unit
Min.
Max.
ILI
Input Leakage Current
-
2
µA
ILO
Output Leakage Current
-
2
µA
-12
-
180
-15
-
170
-
Conditions
VIN = GND to VCC
CE = VIH or
ICC1 (1)
Dynamic Operating
Current
ISB
OE = VIH or WE = VIL
VI/O = GND to VCC
mA
CE = VIL
II/O = 0 mA
20
mA
CE = VIH
CE ≥ VCC - 0.2V,
VIN ≤ 0.2V or VIN ≥ VCC - 0.2V
ISB1
Standby Power
Supply Current
-
5
mA
VOL
Output Low Voltage
-
0.4
V
IOL = 8 mA
VOH
Output High Voltage
2.4
-
V
IOH = -4 mA
Note: 1. ICC1 is dependent on output loading, cycle rates, and Read / Write patterns.
(June, 2001, Version 2.0)
3
AMIC Technology, Inc.
LP61L1008 Series
Truth Table
Mode
I/O Operation
Supply Current
CE
OE
WE
Standby
H
X
X
High Z
ISB, ISB1
Output Disable
L
H
H
High Z
ICC1
Read
L
L
H
DOUT
ICC1
Write
L
X
L
DIN
ICC1
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
Parameter
Min.
Max.
Unit
Conditions
CIN*
Input Capacitance
8
pF
VIN = 0V
CI/O*
Input/Output Capacitance
10
pF
VI/O = 0V
* These parameters are sampled and not 100% tested.
AC Characteristics (TA = 0°C to +70°C, VCC = 3.3V ± 10%, GND = 0V)
Symbol
LP61L1008-12
Parameter
LP61L1008-15
Unit
Min.
Max.
Min.
Max.
12
-
15
-
ns
-
12
-
15
ns
-
12
-
15
ns
-
7
-
9
ns
3
-
5
-
ns
2
-
2
-
ns
-
7
-
10
ns
Read Cycle
tRC
Read Cycle Time
tAA
Address Access Time
tACE
Chip Enable Access Time
tOE
Output Enable to Output Valid
tCLZ
Chip Enable to Output in Low Z
tOLZ
Output Enable to Output in Low Z
tCHZ
Chip Disable to Output in High Z
tOHZ
Output Disable to Output in High Z
2
7
2
9
ns
tOH
Output Hold from Address Change
2
-
5
-
ns
(June, 2001, Version 2.0)
CE
CE
CE
4
AMIC Technology, Inc.
LP61L1008 Series
AC Characteristics (continued)
Symbol
LP61L1008-12
Parameter
LP61L1008-15
Min.
Max.
Min.
Max.
Unit
Write Cycle
tWC
Write Cycle Time
12
-
15
-
ns
tCW
Chip Enable to End of Write
10
-
12
-
ns
tAS
Address Setup Time of Write
0
-
0
-
ns
tAW
Address Valid to End of Write
10
-
12
-
ns
tWP
Write Pulse Width
8
-
10
-
ns
tWR
Write Recovery Time
0
-
0
-
ns
tWHZ
Write to Output in High Z
0
7
0
8
ns
tDW
Data to Write Time Overlap
8
-
10
-
ns
tDH
Data Hold from Write Time
0
-
0
-
ns
tOW
Output Active from End of Write
5
-
5
-
ns
Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
Timing Waveforms
(1, 2, 4)
Read Cycle 1
tRC
Address
tAA
tOH
tOH
DOUT
(June, 2001, Version 2.0)
5
AMIC Technology, Inc.
LP61L1008 Series
Read Cycle 2
(1, 3, 4, 6)
CE
tACE
tCLZ5
tCHZ5
DOUT
Read Cycle 3
(1)
tRC
Address
tAA
OE
tOE
tOH
tOLZ5
CE
tACE
tCHZ5
DOUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE = VI.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
(June, 2001, Version 2.0)
6
AMIC Technology, Inc.
LP61L1008 Series
Timing Waveforms (continued)
(6)
Write Cycle 1
(Write Enable Controlled)
tWC
Address
tAW
tWR3
tCW5
CE
(4)
tAS1
tWP2
WE
tDW
tDH
DIN
tWHZ
tOW
DOUT
(June, 2001, Version 2.0)
7
AMIC Technology, Inc.
LP61L1008 Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
tWR3
tAW
tCW5
CE
tAS1
(4)
tCW5
tWP2
WE
tDW
tDH
DIN
tWHZ7
DOUT
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE and a low WE .
3. tWR is measured from the earliest of CE or WE going high to the end of the Write cycle.
4. If the CE low transition with the WE low transition or after the WE transition, outputs remain in a high
impedance state.
5. tCW is measured from the later of CE going low to the end of Write.
6. OE is continuously low. ( OE = VIL)
7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
(June, 2001, Version 2.0)
8
AMIC Technology, Inc.
LP61L1008 Series
AC Test Conditions
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Time
3 ns
Input and Output Timing Reference Levels
1.5V
Output Load
See Figures 1 and 2
+3.3V
320Ω
Output
I/O
RL=50Ω
ZO=50Ω
350Ω
VT=1.5V
5pF*
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ,
tOHZ, tOLZ, tCHZ, tWHZ,
and tOW
Data Retention Characteristics (TA = 0°C to 70°C)
Symbol
VDR1
Parameter
VCC for Data Retention
Min.
Max.
Unit
2
3.6
V
Conditions
CE ≥ VCC - 0.2V
VCC = 3.0V
ICCDR1
Data Retention Current
-
5
mA
tCDR
Chip Disable to Data Retention Time
0
-
ns
CE ≥ VCC - 0.2V
VIN ≥ VCC - 0.2V or
VIN ≤ 0.2V
See Retention Waveform
tR
Operation Recovery Time
(June, 2001, Version 2.0)
5
-
9
ms
AMIC Technology, Inc.
LP61L1008 Series
Low VCC Data Retention Waveform ( CE Controlled)
DATA RETENTION MODE
VCC
3.0V
3.0V
tCDR
tR
VDR ≥ 2V
VIH
CE
VIH
CE ≥ VDR - 0.2V
Ordering Information
Access Time (ns)
Operating Current
Max. (mA)
Standby Current
Max. (mA)
LP61L1008S-12
12
180
5
32L SOJ (300 mil)
LP61L1008X-12
12
180
5
32L sTSOP (Type I)
LP61L1008S-15
15
170
5
32L SOJ (300 mil)
LP61L1008X-15
15
170
5
32L sTSOP (Type I)
Part No.
(June, 2001, Version 2.0)
10
Package
AMIC Technology, Inc.
LP61L1008 Series
Package Information
SOJ 32/32LD (300mil BODY) Outline Dimensions
unit: inches/mm
b
D
17
c
32
E
F
F
BASE METAL
WITH PLATING
DETAIL "A"
SECTION F-F
1
16
DETAIL "A"
HE
s
b
e
D
SEATING PLANE
Symbol
A1
y
MIN
0.026"
y
A
A2
b1
e1
0.004 y
Dimensions in inches
Dimensions in mm
Min.
Nom.
Max.
Min.
Nom.
Max.
A
0128
0.132
0.140
3.25
3.35
3.56
A1
0.052
-
-
2.08
-
-
A2
0.095
0.100
0.105
2.41
2.54
2.67
b
0.016
0.018
0.020
0.41
0.46
0.51
b1
0.026
0.028
0.032
0.66
0.71
0.81
c
0.006
0.008
0.012
0.15
0.20
0.30
D
0.820
0.825
0.830
20.83
20.96
21.08
HE
0.330
0.335
0.340
8.39
8.51
8.63
E
0.295
0.300
0.305
7.49
7.62
7.75
e1
0.260
0.267
0.274
6.61
6.78
6.96
e
-
0.050
-
-
1.27
-
s
-
-
0.048
-
-
1.22
y
-
-
0.004
-
-
0.10
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E doesn't include resin fins.
3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
(June, 2001, Version 2.0)
11
AMIC Technology, Inc.
LP61L1008 Series
Package Information
sTSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions
A
A1
c
E
A2
e
unit: inches/mm
θ
L
LE
D1
D
Detail "A"
D
Detail "A"
0.076MM
S
b
SEATING PLANE
Dimensions in inches
Symbol
Dimensions in mm
Min
Nom
Max
Min
Nom
Max
A
-
-
0.049
-
-
1.25
A1
0.002
-
-
0.05
-
-
A2
0.037
0.039
0.041
0.95
1.00
1.05
b
0.007
0.008
0.009
0.17
0.20
0.23
c
0.0056
0.0059
0.0062
0.142
0.150
0.158
E
0.311
0.315
0.319
7.90
8.00
8.10
e
0.020 TYP
0.50 TYP
D
0.520
0.528
0.535
13.20
13.40
13.60
D1
0.461
0.465
0.469
11.70
11.80
11.90
L
0.012
0.020
0.028
0.30
0.50
0.70
LE
0.0275
0.0315
0.0355
0.700
0.800
0.900
S
θ
0.0109 TYP
0°
3°
0.278 TYP
5°
0°
3°
5°
Notes:
1. The maximum value of dimension D1 includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
(June, 2001, Version 2.0)
12
AMIC Technology, Inc.