A62S6316 Series Preliminary 64K X 16 BIT LOW VOLTAGE CMOS SRAM Document Title 64K X 16 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue October 8, 1998 Preliminary 0.1 Change access times from 70/100 ns to 55/70 ns(max.) February 12, 1999 Change dynamic operating current from 80/70mA to 40mA Modify TSOP 44L (Type II) outline drawing 0.2 PRELIMINARY Modify truth table (June, 1999, Version 0.2) June 9, 1999 AMIC Technology, Inc. A62S6316 Series Preliminary 64K X 16 BIT LOW VOLTAGE CMOS SRAM Features n Operating voltage: 2.7V to 3.3V n Access times: 55/70 ns (max.) n Current: A62S6316-S series: Operating: Standby: A62S6316-SI series: Operating: Standby: n Extended operating temperature range : -25°C to 85°C for -SI series n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Data retention voltage: 2V (min.) n Available in 44-pin TSOP and 48-ball Mini BGA (6X8) packages. 40mA (max.) 15µA (max.) 40mA (max.) 30µA (max.) General Description The A62S6316 is a low operating current 1,048,576-bit static random access memory organized as 65,536 words by 16 bits and operates on low power supply voltage from 2.7V to 3.3V. It is built using AMIC’s high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The chip enable input is provided for POWER-DOWN, device enable. Two byte enable inputs and an output enable input are included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2V. Pin Configuration n TSOP (Type II) n Mini BGA (6X8) Top View 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A62S6316V A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC PRELIMINARY 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE HB LB I/O 15 I/O 14 I/O 13 I/O 12 GND VCC I/O 11 I/O 10 I/O 9 I/O 8 NC A8 A9 A10 A11 NC (June, 1999, Version 0.2) 2 3 4 5 6 LB OE A0 A1 A2 NC B I/O8 HB A3 A4 CS I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D VSS I/O11 NC A7 I/O3 VCC E VCC I/O12 NC NC I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC A A62S6316G 1 AMIC Technology, Inc. A62S6316 Series Block Diagram VCC A0 GND 512 X 2048 DECODER MEMORY ARRAY A14 A15 I/O 0 I/O 8 INPUT COLUMN I/O INPUT DATA CIRCUIT DATA CIRCUIT I/O 15 I/O 7 CE LB HB OE WE PRELIMINARY CONTROL CIRCUIT (June, 1999, Version 0.2) 2 AMIC Technology, Inc. A62S6316 Series Pin Description - TSOP Pin No. Symbol Description 1 - 5, 18 - 21, 24 - 27,42 - 44 A0 - A15 6 CE Chip Enable Input 7 - 10, 13 - 16, 29 - 32, 35 - 38 I/O0 - I/O15 Data Input/Outputs 17 WE Write Enable Input 39 LB Byte Enable Input (I/O0 to I/O7) 40 HB Byte Enable Input (I/O8 to I/O15) 41 OE Output Enable Input 11, 33 VCC Power 12, 34 GND Ground 22 , 23, 28 NC Address Inputs No Connection Recommended DC Operating Conditions (TA = 0°C to + 70°C or -25°C to 85°C) Symbol Parameter Min. Typ. Max. Unit 2.7 3.0 3.3 V 0 0 0 V VCC Supply Voltage GND Ground VIH Input High Voltage 2.2 - VCC + 0.3 V VIL Input Low Voltage -0.3 - +0.6 V CL Output Load - - 30 pF TTL Output Load - - 1 - PRELIMINARY (June, 1999, Version 0.2) 3 AMIC Technology, Inc. A62S6316 Series Absolute Maximum Ratings* *Comments VCC to GND . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V IN, IN/OUT Volt to GND . . . . . . . . -0.5V to VCC + 0.5V Operating Temperature, Topr . . . . . . . . -25°C to +85°C Storage Temperature, Tstg . . . . . . . . . -55°C to +125°C Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . 0.7W Soldering Temp. & Time . . . . . . . . . . . . 260°C, 10 sec Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (TA = 0°C to + 70°C or -25°C to 85°C, VCC = 2.7V to 3.3V, GND = 0V) Symbol Parameter A62S6316-55S/70S A62S6316-55SI/70SI Min. Max. Min. Max. Unit Conditions ILI Input Leakage Current - 1 - 1 µA ILO Output Leakage Current - 1 - 1 µA ICC Active Power Supply Current - 5 - 5 mA CE = VIL, II/O = 0mA - 40 - 40 mA Min. Cycle, Duty = 100% CE = VIL, II/O = 0mA - 20 - 20 mA CE = VIL, VIH = VCC, VIL = 0V, f = 1MHz, II/O = 0 mA - 0.5 - 0.5 mA CE = VIH - 15 - 30 µA CE ≥ VCC - 0.2V VIN ≥ 0V ICC1 ICC2 Dynamic Operating Current ISB ISB1 Standby Power Supply Current VIN = GND to VCC CE = VIH or LB = VIH or HB = VIH or OE = VIH or WE = VIH VI/O = GND to VCC VOL Output Low Voltage - 0.4 - 0.4 V IOL = 2.1mA VOH Output High Voltage 2.2 - 2.2 - V IOH = -1.0mA PRELIMINARY (June, 1999, Version 0.2) 4 AMIC Technology, Inc. A62S6316 Series Truth Table I/O0 to I/O7 Mode I/O8 to I/O15 Mode VCC Current CE OE WE LB HB H X X X X Not selected Not selected ISB1, ISB L L Read Read ICC1, ICC2, ICC L H Read High - Z ICC1, ICC2, ICC H L High - Z Read ICC1, ICC2, ICC L L Write Write ICC1, ICC2, ICC L H Write Not Write/Hi - Z ICC1, ICC2, ICC H L Not Write/Hi - Z Write ICC1, ICC2, ICC L X High - Z High - Z ICC1, ICC2, ICC X L High - Z High - Z ICC1, ICC2, ICC H H Not selected L L L X L X H X H L H X Not selected ISB1, ISB Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance - 6 pF VIN = 0V CI/O* Input/Output Capacitance - 8 pF VI/O = 0V * These parameters are sampled and not 100% tested. PRELIMINARY (June, 1999, Version 0.2) 5 AMIC Technology, Inc. A62S6316 Series AC Characteristics (TA = 0°C to +70°C or -25°C to 85°C, VCC = 2.7V to 3.3V) Symbol Parameter A62S6316-55S/SI A62S6316-70S/SI Min. Max. Min. Max. 55 - 70 - ns Unit Read Cycle tRC Read Cycle Time tAA Address Access Time - 55 - 70 ns tACE Chip Enable Access Time - 55 - 70 ns tBE Byte Enable Access Time - 55 - 70 ns tOE Output Enable to Output Valid - 30 - 35 ns tCLZ Chip Enable to Output in Low Z 10 - 10 - ns tBLZ Byte Enable to Output in Low Z 5 - 5 - ns tOLZ Output Enable to Output in Low Z 5 - 5 - ns tCHZ Chip Disable to Output in High Z - 20 - 25 ns tBHZ Byte Disable to Output in High Z - 20 - 25 ns tOHZ Output Disable to Output in High Z - 20 - 25 ns tOH Output Hold from Address Change 5 - 10 - ns tWC Write Cycle Time 55 - 70 - ns tCW Chip Enable to End of Write 50 - 60 - ns tBW Byte Enable to End of Write 50 - 60 - ns tAS Address Setup Time 0 - 0 - ns tAW Address Valid to End of Write 50 - 60 - ns tWP Write Pulse Width 40 - 50 - ns tWR Write Recovery Time 0 - 0 - ns tWHZ Write to Output in High Z - 25 - 30 ns tDW Data to Write Time Overlap 25 - 30 - ns tDH Data Hold from Write Time 0 - 0 - ns tOW Output Active from End of Write 5 - 5 - ns Write Cycle Note: tCHZ, tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. PRELIMINARY (June, 1999, Version 0.2) 6 AMIC Technology, Inc. A62S6316 Series Timing Waveforms Read Cycle 1(1, 2, 4) tRC Address tAA tOH tOH DOUT Read Cycle 2(1, 2, 3) tRC Address tAA CE tACE tCHZ 5 tCLZ 5 tBE HB, LB tBLZ5 tBHZ5 OE tOE tOHZ5 tOLZ 5 DOUT Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled CE = VIL, HB = VIH and, or LB = VIL. 3. Address valid prior to or coincident with CE and ( HB and, or LB ) transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (June, 1999, Version 0.2) 7 AMIC Technology, Inc. A62S6316 Series Timing Waveforms (continued) Write Cycle 1 (Write Enable Controlled) tWC Address tWR3 tAW tCW CE tBW HB, LB tAS1 tWP2 WE tDW tDH DATA IN tWHZ4 tOW DATA OUT PRELIMINARY (June, 1999, Version 0.2) 8 AMIC Technology, Inc. A62S6316 Series Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC Address tAW tAS 1 tWR3 tCW2 CE tBW HB, LB tWP WE tDW tDH DATA IN tWHZ4 tOW DATA OUT PRELIMINARY (June, 1999, Version 0.2) 9 AMIC Technology, Inc. A62S6316 Series Timing Waveforms (continued) Write Cycle 3 (Byte Enable Controlled) tWC Address tAW tCW CE tAS1 tWR3 tBW2 HB, LB tWP WE tDH tDW DATA IN tWHZ4 tOW DATA OUT Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and ( HB and, or LB ). 3. tWR is measured from the earliest of CE or WE or ( HB and, or LB ) going high to the end of the Write cycle. 4. OE level is high or low. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (June, 1999, Version 0.2) 10 AMIC Technology, Inc. A62S6316 Series AC Test Conditions Input Pulse Levels 0V to 2.4V Input Rise And Fall Time 5 ns Input and Output Timing Reference Levels 1.5V Output Load See Figures 1 and 2 TTL TTL CL CL 5pF 30pF * Including scope and jig. * Including scope and jig. Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW Data Retention Characteristics (TA = 0°C to 70°C or -25°C to 85°C) Symbol VDR Parameter VCC for Data Retention ICCDR S-Version Min. Max. Unit 2.0 3.3 V CE ≥ VCC - 0.2V - 10* µA VCC = 2.0V, CE ≥ VCC - 0.2V VIN ≥ 0V Data Retention Current SI-Version tCDR tR tVR Chip Disable to Data Retention Time Operation Recovery Time VCC Rise Time from Data Retention Voltage to Operating Voltage * A62S6316-55S/70S ** A62S6316-55SI/70SI PRELIMINARY ICCDR: max. ICCDR: max. (June, 1999, Version 0.2) - 20** 0 - ns TRC - ns 5 - ms Conditions See Retention Waveform 3µA at TA = 0°C to + 40°C 3µA at TA = 0°C to + 40°C 11 AMIC Technology, Inc. A62S6316 Series Low VCC Data Retention Waveform DATA RETENTION MODE VCC 2.7V 2.7V tCDR tR VDR ≥ 2V tVR VIH CE VIH CE ≥ VDR - 0.2V Ordering Information Operating Current Max. (mA) Standby Current Max. (µ µA) Package 40 15 44L TSOP 40 30 44L TSOP A62S6316G-55S 40 15 48B Mini BGA A62S6316G-55SI 40 30 48B Mini BGA A62S6316V-70S 40 15 44L TSOP 40 30 44L TSOP A62S6316G-70S 40 15 48B Mini BGA A62S6316G-70SI 40 30 48B Mini BGA Part No. Access Time (ns) A62S6316V-55S A62S6316V-55SI 55 A62S6316V-70SI 70 PRELIMINARY (June, 1999, Version 0.2) 12 AMIC Technology, Inc. A62S6316 Series Package Information TSOP 44L (Type II) Outline Dimensions unit: inches/mm E HE 44 θ L L1 1 A2 A1 B e D S A c D L Dimensions in inches Symbol L1 y Min Nom Max Dimensions in mm Min Nom Max A - - 0.047 - - 1.20 A1 0.002 - 0.006 0.05 - 0.15 A2 0.037 0.039 0.041 0.95 1.00 1.05 B 0.013 0.015 0.017 0.32 0.37 0.42 c 0.003 0.005 0.009 0.08 0.13 0.23 D 0.720 0.725 0.730 18.28 18.41 18.54 E 0.395 0.400 0.405 10.03 10.16 10.29 e 0.031 BSC 0.80 BSC HE 0.455 0.463 0.471 11.56 11.76 11.96 0.60 L 0.016 0.020 0.024 0.40 0.50 L1 - 0.031 - - 0.80 - S - - 0.035 - - 0.90 y - - 0.004 - - 0.10 θ 1° 3° 5° 1° 3° 5° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. PRELIMINARY (June, 1999, Version 0.2) 13 AMIC Technology, Inc. A62S6316 Series Package Information Mini BGA 6X8 (48 BALLS) Outline Dimensions unit : millimeter(mm) Bottom View Top View Pin A1 Index Pin A1 Index 6 5 4 3 2 1 C C1 A B C D A E F G H A B Diameter D Solder Ball B1 D E2 0.10 E1 E PRELIMINARY Symbol Min Typ Max A - 0.75 - B 5.90 6.00 6.10 B1 - 3.75 - C 7.90 8.00 8.10 C1 - 5.25 - D 0.30 0.35 0.40 E 1.00 1.10 1.20 E1 - 0.36 - E2 - 0.22 - (June, 1999, Version 0.2) 14 AMIC Technology, Inc.