LP62S16256E-I Series 256K X 16 BIT LOW VOLTAGE CMOS SRAM Document Title 256K X 16 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 2.0 History Issue Date Change VCCmax from 3.3V to 3.6V January 25, 2002 Remark Add product family and 55ns specification (January, 2002, Version 2.0) AMIC Technology, Inc. LP62S16256E-I Series 256K X 16 BIT LOW VOLTAGE CMOS SRAM Features General Description n Operating voltage: 2.7V to 3.6V n Access times: 55ns / 70ns (max.) n Current: Very low power version: Operating: 40mA (max.) Standby: 10µA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Data retention voltage: 2.0V (min.) n Available in 44-pin TSOP and 48-ball CSP (6 × 8mm) packages The LP62S16256E-I is a low operating current 4,194,304-bit static random access memory organized as 262,144 words by 16 bits and operates on low power voltage from 2.7V to 3.3V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The chip enable input is provided for POWER-DOWN, device enable. Two byte enable inputs and an output enable input are included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2.0V. Product Family Power Dissipation Data Retention Standby Operating (ICCDR, Typ.) (ISB1, Typ.) (ICC2, Typ.) Product Family Operating Temperature VCC Range Speed LP62S16256E-I -40°C ~ +85°C 2.7V~3.6V 55ns / 70ns 0.08µA 5mA 0.3µA Package Type 44L TSOP 48B CSP 1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested. 2. Data retention current VCC = 2.0V. Pin Configurations n TSOP n CSP (Chip Size Package) 48-pin Top View A4 1 44 A5 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE 5 6 7 I/O2 8 I/O3 9 I/O4 10 VCC 11 GND 12 I/O5 13 I/O6 14 I/O7 15 I/O8 16 WE 17 A17 18 A16 19 A15 LP62S16256EV-I A0 CE I/O1 40 HB 39 LB 38 I/O16 37 I/O15 36 I/O14 35 I/O13 34 GND 33 VCC 32 I/O12 31 I/O11 30 I/O10 29 I/O9 28 NC 27 A8 26 A9 20 25 A10 A14 21 24 A11 A13 22 23 A12 (January, 2002, Version 2.0) A 1 1 2 3 4 5 6 LB OE A0 A1 A2 NC B I/O9 HB A3 A4 CE I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D GND I/O12 A17 A7 I/O4 VCC E VCC I/O13 NC A16 I/O5 GND F I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 NC A12 A13 WE I/O8 H NC A8 A9 A10 A11 NC AMIC Technology, Inc. LP62S16256E-I Series Block Diagram VCC A0 GND 512 X 8192 DECODER A16 MEMORY ARRAY A17 I/O9 I/O1 COLUMN I/O INPUT INPUT DATA CIRCUIT DATA CIRCUIT I/O16 I/O8 CE LB HB OE WE CONTROL CIRCUIT Pin Descriptions -- TSOP Pin No. Symbol 1 - 5, 18 - 27, 42 - 44 A0 - A17 6 CE 7 - 10, 13 - 16, 29 - 32, 35 - 38 I/O1 - I/O16 17 WE Write Enable Input 39 LB Lower Byte Enable Input (I/O1 to I/O8) 40 HB Higher Byte Enable Input (I/O9 to I/O16) 41 OE Output Enable Input 11, 33 VCC Power 12, 34 GND Ground 28 NC (January, 2002, Version 2.0) Description Address Inputs Chip Enable Input Data Inputs/Outputs No Connection 2 AMIC Technology, Inc. LP62S16256E-I Series Pin Description - CSP Symbol Symbol Description Address Inputs HB Higher Byte Enable Input (I/O9 - I/O16) Chip Enable OE Output Enable I/O1 - I/O16 Data Input/Output VCC Power Supply WE Write Enable Input GND Ground LB Byte Enable Input (I/O1 - I/O8) NC A0 - A17 CE Description No Connection Recommended DC Operating Conditions (TA = -40°C to + 85°C) Symbol Parameter Min. Typ. Max. Unit 2.7 3 3.6 V 0 0 0 V VCC Supply Voltage GND Ground VIH Input High Voltage 2.2 - VCC + 0.3 V VIL Input Low Voltage -0.3 - +0.6 V CL Output Load - - 30 pF TTL Output Load - - 1 - (January, 2002, Version 2.0) 3 AMIC Technology, Inc. LP62S16256E-I Series Absolute Maximum Ratings* *Comments VCC to GND ..............................................-0.5V to +4.0V IN, IN/OUT Volt to GND ................... -0.5V to VCC + 0.5V Operating Temperature, Topr ...................-40°C to +85°C Storage Temperature, Tstg.....................-55°C to +125°C Power Dissipation, PT ...................................................................... 0.7W Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (TA = -40°C to + 85°C, VCC = 2.7V to 3.6V, GND = 0V) Symbol Parameter LP62S16256E-55LLI / 70LLI Unit Min. Typ. Max. - - 1 µA 1 µA Conditions ILI Input Leakage Current ILO Output Leakage Current - Active Power Supply Current - - 5 mA CE = VIL, II/O = 0mA - 25 40 mA Min. Cycle, Duty = 100% ICC ICC1 - VIN = GND to VCC CE = VIH HB = VIH or OE = VIH or WE = VIH VI/O = GND to VCC CE = VI, II/O = 0mA Dynamic Operating Current CE = VIL, VIH = VCC, VIL = 0V, f = 1MHz, II/O = 0 mA ICC2 - 5 15 mA ISB - - 1 mA CE = VIH VCC ≤ 3.3V - 0.3 10 µA CE ≥ VCC - 0.2V, VCC ≤ 3.3V VIN ≥ 0V ISB1 Standby Current VOL Output Low Voltage - - 0.4 V IOL = 2.1 mA VOH Output High Voltage 2.2 - - V IOH = -1.0 mA (January, 2002, Version 2.0) 4 AMIC Technology, Inc. LP62S16256E-I Series Truth Table I/O1 to I/O8 Mode I/O9 to I/O16 Mode VCC Current CE OE WE LB HB H X X X X Not selected Not selected ISB1, ISB X X X H H High - Z High - Z ISB1, ISB L L Read Read ICC1, ICC2, ICC L H Read High - Z ICC1, ICC2, ICC H L High - Z Read ICC1, ICC2, ICC L L Write Write ICC1, ICC2, ICC L H Write High - Z ICC1, ICC2, ICC H L High - Z Write ICC1, ICC2, ICC L L L X H L L H H L X High - Z High - Z ICC1, ICC2, ICC L H H X L High - Z High - Z ICC1, ICC2, ICC Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance 6 pF VIN = 0V CI/O* Input/Output Capacitance 8 pF VI/O = 0V * These parameters are sampled and not 100% tested. (January, 2002, Version 2.0) 5 AMIC Technology, Inc. LP62S16256E-I Series AC Characteristics (TA = -40°C to +85°C, VCC = 2.7V to 3.6V) Symbol Parameter LP62S16256E-55LLI LP62S16256E-70LLI Unit Min. Max. Min. Max. 55 - 70 - ns Read Cycle tRC Read Cycle Time tAA Address Access Time - 55 - 70 ns tACE Chip Enable Access Time - 55 - 70 ns tBE Byte Enable Access Time - 55 - 70 ns tOE Output Enable to Output Valid - 30 - 35 ns tCLZ Chip Enable to Output in Low Z 10 - 10 - ns tBLZ Byte Enable to Output in Low Z 10 - 10 - ns tOLZ Output Enable to Output in Low Z 5 - 5 - ns tCHZ Chip Disable to Output in High Z - 20 - 25 ns tBHZ Byte Disable to Output in High Z - 20 - 25 ns tOHZ Output Disable to Output in High Z - 20 - 25 ns tOH Output Hold from Address Change 5 - 5 - ns tWC Write Cycle Time 55 - 70 - ns tCW Chip Enable to End of Write 50 - 60 - ns tBW Byte Enable to End of Write 50 - 60 - ns tAS Address Setup Time 0 - 0 - ns tAW Address Valid to End of Write 50 - 60 - ns tWP Write Pulse Width 40 - 50 - ns tWR Write Recovery Time 0 - 0 - ns tWHZ Write to Output in High Z - 25 - 25 ns tDW Data to Write Time Overlap 25 - 30 - ns tDH Data Hold from Write Time 0 - 0 - ns tOW Output Active from End of Write 5 - 5 - ns Write Cycle Note: tCHZ, tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. (January, 2002, Version 2.0) 6 AMIC Technology, Inc. LP62S16256E-I Series Timing Waveforms (1, 2, 4) Read Cycle 1 tRC Address tAA tOH tOH DOUT (1, 2, 3) Read Cycle 2 tRC Address tAA CE tACE tCHZ 5 tCLZ 5 tBE HB, LB tBLZ 5 tBHZ 5 OE tOHZ 5 tOE tOLZ 5 DOUT Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled CE = VIL, HB = VIL and, or LB = VIL. 3. Address valid prior to or coincident with CE and ( HB and, or LB ) transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. (January, 2002, Version 2.0) 7 AMIC Technology, Inc. LP62S16256E-I Series Timing Waveforms (continued) Write Cycle 1 (Write Enable Controlled) tWC Address tWR3 tAW tCW CE tBW HB, LB tAS1 tWP2 WE tDW tDH DATA IN tWHZ 4 tOW DATA OUT (January, 2002, Version 2.0) 8 AMIC Technology, Inc. LP62S16256E-I Series Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC Address tAW tAS1 tWR3 tCW2 CE tBW HB, LB tWP WE tDW tDH DATA IN tWHZ 4 tOW DATA OUT (January, 2002, Version 2.0) 9 AMIC Technology, Inc. LP62S16256E-I Series Timing Waveforms (continued) Write Cycle 3 (Byte Enable Controlled) tWC Address tAW tCW CE tAS1 tWR3 tBW2 HB, LB tWP WE tDH tDW DATA IN tWHZ 4 tOW DATA OUT Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and ( HB and , or LB ). 3. tWR is measured from the earliest of CE or WE or ( HB and , or LB ) going high to the end of the Write cycle. 4. OE level is high or low. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. (January, 2002, Version 2.0) 10 AMIC Technology, Inc. LP62S16256E-I Series AC Test Conditions Input Pulse Levels 0.4V to 2.4V Input Rise And Fall Time 5 ns Input and Output Timing Reference Levels 1.5V Output Load See Figures 1 and 2 TTL TTL CL CL 5pF 30pF * Including scope and jig. * Including scope and jig. Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW Data Retention Characteristics (TA = -40°C to 85°C) Symbol Parameter Min. Typ. Max. Unit VDR VCC for Data Retention 2.0 - 3.6 V ICCDR Data Retention Current - 0.08 3* µA tCDR Chip Disable to Data Retention Time 0 - - ns tRC - - ns 5 - - ms tR Operation Recovery Time tVR VCC Rising Time from Data Retention Voltage to Operating Voltage * LP62S16256E-55LLI / 70LLI (January, 2002, Version 2.0) ICCDR: max. Conditions CE ≥ VCC - 0.2V VCC = 2.0V, CE ≥ VCC - 0.2V VIN ≥ 0V See Retention Waveform 1µA at TA = 0°C to + 40°C 11 AMIC Technology, Inc. LP62S16256E-I Series Low VCC Data Retention Waveform DATA RETENTION MODE 2.7V 2.7V VCC tCDR tR VDR ≥ 2.0V tVR VIH CE VIH CE ≥ VDR - 0.2V Ordering Information Part No. Access Time (ns) LP62S16256EV-55LLI Operating Current Max. (mA) Standby Current Max. (µ µA) Package 40 10 44L TSOP 40 10 48L CSP 40 10 44L TSOP 40 10 48L CSP 55 LP62S16256EU-55LLI LP62S16256EV-70LLI 70 LP62S16256EU-70LLI (January, 2002, Version 2.0) 12 AMIC Technology, Inc. LP62S16256E-I Series Package Information TSOP 44L TYPE II Outline Dimensions unit: inches/mm HE 0.254 23 E 44 L L1 1 22 B e D S Symbol y A L1 L A1 A2 c D Dimension in inch Min. Nom. Max. Dimension in mm Min. Nom. Max. A - - 0.047 - - 1.20 A1 0.002 - - 0.05 - - A2 0.037 0.039 0.041 0.95 1.00 1.05 B 0.010 0.014 0.018 0.25 0.35 0.45 c - 0.006 - - 0.15 - D 0.721 0.725 0.729 18.31 18.41 18.51 E 0.396 0.400 0.404 10.06 10.16 10.26 e - 0.031 - - 0.80 - HE 0.455 0.463 0.471 11.56 11.76 11.96 L 0.016 0.020 0.024 0.40 0.50 0.60 L1 - 0.031 - - 0.80 - S - - 0.036 - - 0.93 y - - 0.004 - - 0.10 0° - 0° - 5° θ 5° Notes: 1. Dimension D&E do not include interlead flash. 2. Dimension B does not include dambar protrusion/intrusion. 3. Dimension S includes end flash. (January, 2002, Version 2.0) 13 AMIC Technology, Inc. LP62S16256E-I Series Package Information 48LD CSP ( 6 x 8 mm ) Outline Dimensions unit: mm (48TFBGA) BOTTOM VIEW TOP VIEW Ball#A1 CORNER 0.10 S C 0.25 S C A B Ball*A1 CORNER b (48X) 6 5 4 3 2 1 1 2 3 4 5 6 A B A C D E1 E e B C D E E F F G G H H B e D1 A 0.10 C A2 SEATING PLANE A1 (0.36) C D 0.20(4X) Symbol A A1 A2 D E D1 E1 e b A // 0.25 C SIDE VIEW Dimensions in mm MIN. NOM. MAX. 1.04 0.20 0.48 5.90 7.90 ------0.30 1.14 0.25 0.53 6.00 8.00 3.75 5.25 0.75 0.35 1.24 0.30 0.58 6.10 8.10 ------0.40 Note: 1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY). 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE. 4. BALL PAD OPENING OF SUBSTRATE IS Φ 0.3mm (SMD) SUGGEST TO DESIGN THE PCB LAND SIZE AS Φ 0.3mm (NSMD) (January, 2002, Version 2.0) 14 AMIC Technology, Inc.