A ARA05050S12 CATV Reverse Amplifier w/ Step Attenuator Advanced product information Rev. 6 FEATURES • Integrated monolithic GaAs amplifier and step attenuator. • Compatible with all digital and analog modulation types. • Frequency range: 5 - 100 MHz. • Gain: 0 - 30 dB, variable in 2 dB steps. • 5 Volt operation. • Low noise figure. • Low distortion. • Amplifier shutdown capability. • Low cost. • High reliability. • Low signal to noise ratio at all gain levels. DESCRIPTION The ARA05050 is a GaAs IC designed to perform the reverse path amplification and output level control functions in a CATV Set-Top Box or Cable Modem. It incorporates a digitally controlled precision step attenuator that is preceded by an ultra low noise amplifier stage, and followed by an ultra-linear output driver amplifier. It is capable of meeting the MCNS/DOCSIS harmonic distortion specifications while only requiring a single polarity +5V supply. This part is a single ended design that does not require an output balun to achieve -55 dBc 2nd harmonic performance at +58 dBmV output S12C 28 Pin SSOP w/ Heat Slug levels. Both the input and output are matched to 75 ohms. The precision attenuator provides up to 30 dB of attenuation in 2 dB increments. The ARA05050 is supplied in a 28-pin SSOP package featuring a thermal heat slug on the bottom of the package. Soldering this heat slug to the ground plane of the PC board ensures the lowest possible thermal resistance for the device resulting in a long MTF. Tx Enable/Disable Gain Control Switch PA ATTN 2/4/8/16 dB PA LPF Upstream QPSK/ 16-QAM Modulator Balun ARA05050 Reverse Amp Clock Data 5-42 MHz Coax Connector Microcontroller w/Enet MAC MAC Diplex Filter Clock RAM ROM Data 45 MHz IF 54-860 MHz Double Conversion Tuner SAW QAM Receiver w/FEC 10Base-T Tranceiver RJ45 Connector Figure 1. Cable Modem or Interactive Set-Top Box Block Diagram *See ANADIGICS ACU50751 and ACD0900 ARA05050S12 Advanced Product Information - Rev. 6 ELECTRICAL CHARACTERISTICS (TYPICAL) (VDD=5 VDC, TC=25 °C) Parameter Min Typ Max Unit 30 32 33 dB At 0dB attenuation setting - 0.75 1.5 dB 5 to 100 MHz 1.6 3.8 8.0 16.0 1.85 4.0 8.3 16.6 2.2 4.2 8.5 17.0 dB 5 to 42 MHz 5 MHz 25 MHz - -60 -63 -55 -55 dBc 5 MHz 25 MHz - -63 -63 -60 -60 dBc 78 - - dBmV 1dB Gain Compression Point - 70 - dBmV Noise Figure - 1.7 2.5 dB Output Noise Power Active/No Signal/Min Attn. Setting Active/No Signal/Max Attn. Setting - - -24.6 -41.6 dBmV Any 3200 KHz bandwidth from 5 to 42 MHz - 30 53.5 - dB Difference in output signal level between active and standby - 75 - ohm - -20 -15 dB Gain 1 Gain Flatness 1 Attenuation Steps Comments 1 2 4 8 16 dB dB dB dB 3 2 nd Harmonic Distortion Level 2 3 rd Harmonic Distortion Level 2 3 rd Order Output Intercept Point On/Off Isolation Shut Off Stage 2 Shut Off Stages 1 & 2 Input Impedance1 1 Input Return Loss 1 Output Impedance - 75 - ohm Ouput Return Loss1 - -20 -15 dB V DD1, VDD2 - 5 7 V V DD Digital - 5 - V -2 - -1.5 V IDD1 - 75 95 mA IDD2 - 100 130 mA IDD Digital - 8 - mA Power Consumption - 1 1.2 W - 5K - ohm 0.5 6.5 Volts V Shutdown Attenuator Control Impedance Attenuator Control Logic 4 VIL VIH 0 2.8 - Notes: 1. As measured in ANADIGICS test fixture 2. At +58 dBmV output level into 75 ohm load 3. For higher frequencies see figures 3 & 4. 4. With 470 ohm chip resistor from pin 2 to gnd (see test circuit). A 2 ARA05050S12 Advanced Product Information - Rev. 6 ABSOLUTE MAXIMUM RATINGS Parameter Absolute Maximum Unit VDD (Pins 4,12, 18) 9 VDC VRFIN (Pins 10, 24) 0 to -3 VDC ATTIN (Pin 3) ATTOUT (Pin 26) 5 VDC VISET (Pins 11, 25) 2 VDC +60 dBmV -55 to +200 °C 260 °C 5 Sec -40 to +85 °C RF Input Voltage (Pins 10, 24)* Storage Temperature Soldering Temperature Soldering Time Operating Case Temperature * Blocking capacitors required RFOUT1 Shutdown ATTOUT ATTIN RFIN2 Shutdown 30 dB 2 dB step digital attenuator section RFIN AMP AMP ISET1 16 dB 8 dB 4 dB 2 dB RFOUT ISET2 Figure 2 A 3 ARA05050S12 Advanced Product Information - Rev. 6 Figure 3 Figure 5 Figure 7 A Figure 4 Figure 6 Figure 8 4 ARA05050S12 Advanced Product Information - Rev. 6 Figure 9 Figure 10. Attenuator Switching Speed 16 dB Step Figure 11. Switching Speed of Output Disconnect Switch A 5 ARA05050S12 Advanced Product Information - Rev. 6 TEST CIRCUIT 1 28 2 27 3 26 4 25 5 24 6 23 ANADIGICS 8 ARA05050 22 9 20 * V DD1 0.1 uF 0.01 uF 1 uF 10 uH 3.3K 0.1 uF 0.1 uF 20 Ω 1000 pF 1.8K 1 uF 0.01 uF 1pF Shutdown #1 0.01 uF 5K Shutdown #2 5K 0.01 uF 7 620 Ω 5K 0.1 uF 5K 1 uF 0.01 uF 620 Ω 21 1 uF 3.3K VDD2 10uH 1 uF RF IN 0.1 uF 10 19 11 18 20 Ω 0.1 uF 0.1 uF 1 uF 3.9 Ω 1 uF 0.01 uF 12 17 13 16 14 15 RFOUT 1.8K 5V digital * = 470Ω resistor for 3V attn. control 4 3 2 1 DIP SWITCH LOGIC TABLE Attn (dB) 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 SW 1 X O X O X O X O X O X O X O X SW 2 O X X O O X X O O X X O O X X SW 3 O O O X X X X O O O O X X X X SW4 O O O O O O O X X X X X X X X O = Open X = Closed A 6 ARA05050S12 Advanced Product Information - Rev. 6 PIN DESCRIPTION PIN FUNCTION 1 NC 2 Bypass Internal bypass. This pin must be externally ac decoupled (0.1uf cap) 3 ATTIN Attenuator Input 4 RFOUT1+VDD1 5 VREF1 6,7,8,9 AC_GND 10 RF IN RF Input to 1 Amplifier Stage 11 ISET1 Resistor set current for 1 Amplifier 12 5V digital 13 16 dB 16 dB Attenuator Control Parallel data input 14 8 dB 8 dB Attenuator Control Parallel data input 15 4 dB 4 dB Attenuator Control Parallel data input 16 2 dB 2 dB Attenuator Control Parallel data input 17 Dig GND 18 RF OUT+VDD2 RF Output and +VDD2 V Supply for 2 19 VREF2 Reference voltage for 2 Amplifier 20,21,22,23 AC_GND 24 RF IN2 RF Input to 2 25 ISET2 Resistor set current for 2 Amplifier (ground for max performance) 26 ATTOUT 27 NC No Connection 28 NC No Connection A DESCRIPTION No Connection RF Output and +5v Supply for 1st Amplifier Stage Reference voltage for 1 st Amplifier AC Ground. These pins must be externally ac decoupled (1uF and 0.01uF cap) st st 5 volts digital supply voltage Digital Ground nd Amplifier Stage nd AC Ground. These pins must be externally ac decoupled (1uF and 0.01uF cap) nd nd Amplifier Stage and Shutdown pin for 2 Amplifier nd Attenuator Output 7 PACKAGE OUTLINE Application Note LAYOUT CONSIDERATIONS There are two issues that must be taken into consideration when doing the PCB layout. The first is thermal management, and the second is RF related. THERMAL LAYOUT CONSIDERATIONS The ARA05050 will typically dissipate 0.9W, and as high as 1.2W. Since the interior of most set-top boxes, and cable modems as well typically are at +70° C, consideration must be given to providing an adequate heat sink for the die to obtain the maximum MTF possible. To this end the ARA05050 incorporates a heat slug in the bottom of the package. This provides a low thermal resistance path from the die to the outside of the package. The typical thermal rise from the heat slug to the junction is 35° C/W. However, this is only half of the equation. Adequate heat sinking must be applied to the heat slug for thermal dissipation. Providing a metalized pad with via holes under the package will do this (see Figure 14). The via holes should connect to the ground plane of the PCB. The part is then soldered to this pad during assembly. EXTERNAL CIRCUITRY Output Disconnect Switch: For MCNS/DOCSIS applications an external switch to disconnect the output of the ARA05050 from the diplexer is required. This switch is needed because of the output noise requirement between bursts, and because of the requirement that any shutdown transient not exceed 7mV. The switch shown in Figure 12 meets these conditions because it does not switch any current, or voltage, on the output line. The series FET provides 35 dB of isolation, while the shunt FET insures that the diplexer remains terminated into a 75 ohm impedance. Since the switch does not draw any current, it may be driven directly from a low power CMOS logic inverter; however the control voltages must be +5V. When the switch is in the open state, it is good general practice to set the programmable attenuator to its maximum attenuation setting. This will increase the isolation between the cm output and upstream modulator, and provide the first stage amplifier with a 75 ohm termination. Shutdown of the ARA05050: In some applications it may be desirable to shut the ARA05050 down for power saving. This can be done by applying a negative voltage to pin 10 to shut down the input stage, and to pin 24 to shut down output stage (see Figure 13). Shutting down both amplifier stages will reduce the current drawn from the +5V supply to typically 10 mA. If only one stage is shutdown, it is recommended that the programmable attenuator be set to a minimum of 16 dB to provide a good impedance match to the remaining stage. RF LAYOUT CONSIDERATIONS The ARA05050 is a power amplifier designed for driving a 75ohm load. Since this part connects the transmitter to the cable system, typically via a diplexer, it is an analog device operating at RF frequencies. This means that the layout of the PCB will have an effect on the system performance. The first consideration in RF layout are the connections to ground. These must be low impedance, and as short as possible. The best way to do this is to use as large a via hole as possible, located as close as possible to connect to the ground plane. Specifically, care should be given to the layout of the following connections (the traces leading from the following pins to their respective components should be as low as impedance as is practical.): Pins 5 & 19: the 20 ohm chip resistor should be as close as possible to the pins and the 1 uF capacitor should be kept close to the 20 ohm resistor. ARA05050S12 Advanced Product Information - Rev. 6 Application Note Pins 6–9 & 20–23: the capacitors should be kept close to the pins. Pin 11: the 1uF bypass capacitor should be kept close to the pin. Pin 12: the bypass capacitor at this node should be reasonably close ot the pin. The path leading between pins 4–10, and the path between pins 18–24, should be kept as short as possible. A The bypass capacitors on the Vdd lines should be located as close as possible to the 10 uH inductors. The traces leading to the RF input, and leading away from the RF output, should be 75 ohms. Care should be taken to keep other traces, which may have clock signals on them, as far away as is practical to prevent unwanted coupling onto the signal line. 10 ARA05050S12 Advanced Product Information - Rev. 6 +5V +5V .1uF .1uF 10KΩ .1uF .1uF Q1 Input (from rev. amp) 27Ω Output (to diplexer) 75Ω Insertion Loss @ 45 MHz: 0.1dB 10KΩ Q2 Switch Control 10KΩ 3.3KΩ Q1/Q2 are AF002C4 (Alpha) +5V 3.3KΩ .1uF .1uF Isolation @ 45 MHz: 38dB 2nd Harmonic @ +58 dBmV > 70dBc Logic output levels of 0 to +5V Figure 12. Output Disconnect Switch +3.3V Pin 10/24 1st or 2nd stage of Reverse Amplifier Output 5KΩ VCONT (0/3.3) 500Ω Q1 Q2 3KΩ 5KΩ 2.5KΩ Set IQ2 for ~ -2V at gate of second stage of rev amp -5V Q1: 2N3906 Q2: 2N3904 Figure 13 A 11 ARA05050S12 Advanced Product Information - Rev. 6 ANADIGICS, Inc. 35 Technology Drive Warren, New Jersey 07059 Tel: (908) 668-5000 / Fax: (908) 668-5132 Email: [email protected] www.anadigics.com IMPORTANT NOTICE ANADIGICS, Inc. reserves the right to make changes to its products or discontinue any product at any time without notice. The Advanced Product data sheets and product specifications contained in this data sheet are subject to change prior to a products formal introduction. The information in this data sheet has been carefully checked and is assumed to be reliable. However, ANADIGICS assumes no responsibility for inaccuracies. ANADIGICS strongly urges customers to verify that the information they are using is current before placing orders. WARNING ANADIGICS products are not intended for use in life support appliances, device, or systems. Use of an ANADIGICS product in any such application without written consent is prohibited. A 12