OPA653 OP A6 53 www.ti.com........................................................................................................................................................................................... SBOS348 – DECEMBER 2008 Wideband, Fixed Gain, JFET-Input AMPLIFIER FEATURES DESCRIPTION 1 • • • • • • • • • • 2 • HIGH BANDWIDTH: 500 MHz (G = +2 V/V) HIGH SLEW RATE: 2675 V/µs (4-V Step) EXCELLENT THD: –71dBc at 10 MHz LOW INPUT VOLTAGE NOISE: 6.1 nV/√Hz FAST OVERDRIVE RECOVERY: 8 ns FAST SETTLING TIME (1% 4-V Step): 7.9 ns LOW INPUT OFFSET VOLTAGE: ±1 mV LOW INPUT BIAS CURRENT: ±10 pA HIGH INPUT IMPEDANCE: 1012 Ω||2.5 pF INTERNAL GAIN SETTING RESISTORS: G = +2 V/V or G = –1 V/V HIGH OUTPUT CURRENT: 70 mA APPLICATIONS • • • • • TEST AND MEASUREMENT FRONT-END HIGH-INPUT IMPEDANCE PROBES DATA ACQUISITION CARDS OSCILLOSCOPE INPUT ADC INPUT AMPLIFIER The OPA653 combines a very wideband voltage-feedback operational amplifier with a JFET-input stage with internal gain setting resistors to achieve an ultra-high, dynamic-range amplifier for fixed gain of +2-V/V or –1-V/V applications. The 500-MHz wide gain of +2-V/V bandwidth is complemented by a very high 2675-V/µs slew rate and fast settling time that make it ideal for time-domain and pulse-oriented applications. Excellent –72-dBc THD distortion performance at 10 MHz makes the OPA653 an excellent choice for frequency-domain and FFT analysis applications. Additionally, with the low 6.1-nV/√Hz voltage noise, low bias current, and high impedance JFET input, it supports very low noise, wideband, high input impedance applications. Examples include high-impedance probes, data acquisition cards, and oscilloscope front-ends. RELATED OPERATIONAL AMPLIFIER PRODUCTS NONINVERTING GAIN OF +2 V/V 50-W TEST ENVIRONMENT +6 V 0.1 mF 10 mF SLEW RATE (V/µs) VOLTAGE NOISE (nV/√Hz) DEVICE VS (V) BW (MHz) OPA356 +5 200 300 5.80 Unity-Gain Stable CMOS OPA656 ±5 500 290 7 Unity-Gain Stable JFET-Input OPA657 ±5 350 700 4.8 Gain of +7 Stable JFET-Input OPA659 ±6 650 2550 8.9 Unity-Gain Stable JFET-Input THS4631 ±15 105 900 7 Unity-Gain Stable JFET-Input VS+ 50-W Source VIN+ VOUT OPA653 49.9 W VIN- 49.9 W 50-W Load 160 W 160 W VS0.1 mF 10 mF AMPLIFIER DESCRIPTION -6 V SMALL-SIGNAL FREQUENCY RESPONSE 6 3 Signal Gain (dB) 0 -3 -6 -9 -12 -15 VO = 200 mVPP -18 100 k 1M 10 M 100 M 1G Frequency (Hz) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated OPA653 SBOS348 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR OPA653 SOT23-5 DBV –40°C to +85°C BZW OPA653 VSON-8 DRB –40°C to +85°C OBEI (1) ORDERING NUMBER TRANSPORT MEDIA, QUANTITY OPA653IDBVT Tape and Reel, 250 OPA653IDBVR Tape and Reel, 3000 OPA653IDRBT Tape and Reel, 250 OPA653IDRBR Tape and Reel, 3000 For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range (unless otherwise noted). OPA653 UNIT Power Supply Voltage VS+ to VS– ±6.5 V Input Voltage ±VS V Input Current 100 mA 100 mA Output Current Continuous Power Dissipation See Thermal Characteristics Operating Free Air Temperature Range, TA –40 to +85 °C Storage Temperature Range –65 to +150 °C Lead Temperature (soldering, 10s) +260 °C Maximum Junction Temperature, TJ +150 °C Maximum Junction Temperature, TJ (continuous operation for long term reliability) +125 °C Human Body Model (HBM) 4000 V Charge Device Model (CDM) 1000 V Machine Model 200 V ESD Rating: DRB PACKAGE VSON-8 (TOP VIEW) Note: 2 DRV PACKAGE SOT23-5 (TOP VIEW) NC 1 8 NC VIN- 2 7 VS+ VIN+ 3 6 VOUT VS- 4 5 NC VOUT 1 -VS 2 VIN+ 3 5 VS+ 4 VIN- NC: No connection. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): OPA653 OPA653 www.ti.com........................................................................................................................................................................................... SBOS348 – DECEMBER 2008 ELECTRICAL CHARACTERISTICS: VS = ±6 V At G = +2 V/V, RL = 100 Ω, and TA = +25°C, unless otherwise noted. OPA653 PARAMETER CONDITIONS MIN TYP MAX UNIT TEST LEVEL (1) AC PERFORMANCE Small-Signal Bandwidth VO = 200 mVPP 500 MHz C Bandwidth for 0.1-dB Flatness VO = 2 VPP 75 MHz C Large-Signal Bandwidth VO = 2 VPP 475 MHz B Slew Rate VO = 4-V Step 2675 V/µs B Rise and Fall Time VO = 4-V Step 1.3 ns C Settling Time to 1% VO = 4-V Step 7.9 ns C Pulse Response Overshoot VO = 4-V Step 14 % C 2nd harmonic –72 dBc C 3rd harmonic –90 dBc C Second-order Intermodulation –75 dBc C Third-order Intermodulation –96 dBc C Harmonic Distortion Intermodulation Distortion f = 10 MHz, VO = 2 VPP VO = 2-VPP envelope (each tone 1 VPP), f1 = 10 MHz, f2 = 11 MHz Input Voltage Noise f > 100 kHz 6.1 nV/√Hz C Input Current Noise f > 100 kHz 1.8 fA/√Hz C TA = +25°C ±0.5 ±1.25 % A TA = –40° C to +85°C ±0.6 ±1.35 % B 160 180 Ω A dB C DC PERFORMANCE Gain Error Internal RF and RG 140 Open-Loop Voltage Gain (AOL) (2) Input Offset Voltage Average input offset voltage drift Input Bias Current, Noninverting input Average input bias current drift, noninverting input 62 TA = +25°C, VCM = 0 V ±1 ±5 mV A TA = –40°C to +85°C, VCM = 0 V ±3 ±7 mV B TA = –40°C to +85°C, VCM = 0 V ±15 ±30 µV/°C B TA = +25°C, VCM = 0 V ±10 ±50 pA A TA = 0°C to + 70°C, VCM = 0 V ±240 ±1200 pA B TA = –40°C to +85°C, VCM = 0 V ±640 ±3200 pA B TA = 0°C to +70°C, VCM = 0 V ±5 ±26 pA/°C B TA = –40°C to +85°C, VCM = 0 V ±7 ±34 pA/°C B V C INPUT Input Voltage Range VIN+ = VIN– ±3.5 1012 Noninverting Input Impedance 2.5 Ω pF C OUTPUT Output Voltage Swing Output Voltage Swing Output Current, Sourcing, Sinking Closed-Loop Output Impedance (1) (2) TA = +25°C, No load ±4.35 ±4.45 V A TA = +25°C, RL = 100 Ω ±3.2 ±3.6 V A TA = –40°C to +85°C, No load ±4.2 ±4.3 V B TA = –40°C to +85°C, RL = 100 Ω ±3.07 ±3.2 V B TA = +25°C ±60 ±70 mA A TA = –40°C to +85°C ±56 ±66 mA B 0.16 Ω C f = 100 kHz Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Open loop gain is for informational use only. Open loop gain is from simulation and not measured in a closed-loop amplifier. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): OPA653 3 OPA653 SBOS348 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: VS = ±6 V (continued) At G = +2 V/V, RL = 100 Ω, and TA = +25°C, unless otherwise noted. OPA653 PARAMETER UNIT TEST LEVEL (1) ±6.5 V B 33.5 mA A 35.7 mA B 66 dB A 64 dB B °C C CONDITIONS MIN TYP MAX TA = –40°C to +85°C ±3.5 ±6 TA = +25°C 30.5 32 TA = –40°C to +85°C 28.3 TA = +25°C, ±VS = 5.5 V to 6.5 V 62 TA = –40°C to +85°C, ±VS = 5.5 V to 6.5 V 60 POWER SUPPLY Specified Operating Voltage Quiescent Current Power-Supply Rejection Ratio THERMAL CHARACTERISTICS Specified Operating Range DBV and DRB Packages –40 Thermal Resistance, θJA +85 Junction-to-ambient DBV SOT23-5 105 °C/W C DRB VSON-8 55 °C/W C TYPICAL CHARACTERISTICS Table of Graphs TITLE FIGURE Small-Signal Frequency Response VO = 200 mVPP Figure 1 Noninverting Large-Signal Frequency Response Gain = +2 V/V Figure 2 Inverting Large-Signal Frequency Response Gain = –1 V/V Figure 3 Input-Referred Voltage and Current Noise Spectral Density Figure 4 Noninverting Transient Response 0.5-V Step Inverting Transient Response 0.5-V Step Harmonic Distortion vs Frequency Figure 5 Figure 6 Figure 7, Figure 8 Harmonic Distortion vs Load Figure 9 Harmonic Distortion vs Output Voltage Figure 10 Harmonic Distortion vs ±Supply Voltage Figure 11 Two-Tone, Second- and Third-Order Intermodulation Distortion vs Frequency Figure 12 Noninverting Overdrive Recovery Gain = +2 V/V Figure 13 Inverting Overdrive Recovery Gain = –1 V/V Figure 14 Power-Supply Rejection Ratio vs Frequency Figure 15 Frequency Response vs Capacitive Load Figure 16 Recommended RISO vs Capacitive Load Figure 17 Closed-Loop Output Impedance vs Frequency Figure 18 Slew Rate vs VOUT Step Figure 19 Output Voltage Swing vs RLOAD Figure 20 4 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): OPA653 OPA653 www.ti.com........................................................................................................................................................................................... SBOS348 – DECEMBER 2008 TYPICAL CHARACTERISTICS: VS = ±6 V At G = +2 V/V, RL = 100 Ω, and TA = +25°C, unless otherwise noted. SMALL-SIGNAL FREQUENCY RESPONSE (VO = 200 mVPP) NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE 8 G = -1 V/V 3 VO = 1.0 VPP 7 0 6 Signal Gain (dB) Normalized Signal Gain (dB) 6 G = +2 V/V -3 -6 -9 VO = 0.5 VPP 5 3 -12 2 -15 1 -18 100 k 10 M 1M 100 M VO = 4.0 VPP 4 VO = 2.0 VPP VO = 6.0 VPP G = +2 V/V 0 100 k 1M 1G 10 M Frequency (Hz) INVERTING LARGE-SIGNAL FREQUENCY RESPONSE INPUT-REFERRED VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY VO = 2.0 VPP Input-Referred Voltage Noise (nV/ÖHz) Input-Referred Current Noise (fA/ÖHz) Figure 2. 2 VO = 1.0 VPP 0 VO = 6.0 VPP -2 VO = 4.0 VPP -4 VO = 0.5 VPP -6 -8 G = -1 V/V -10 100 k 1M 1k Input-Referred Voltage Noise 100 10 Input-Referred Current Noise 1 10 M 100 M 1G 10 100 10 M 1M Figure 4. NONINVERTING TRANSIENT RESPONSE INVERTING TRANSIENT RESPONSE 3 G = +2 V/V 100 k Frequency (Hz) Figure 3. 3 10 k 1k Frequency (Hz) G = -1 V/V 4-V Step 2 4-V Step 2 2-V Step 2-V Step 1 0 VOUT (V) 1 VOUT (V) 1G Figure 1. 4 Signal Gain (dB) 100 M Frequency (Hz) 0.5-V Step 0 -1 -1 -2 -2 -3 0.5-V Step -3 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 Time (ns) Time (ns) Figure 5. Figure 6. 35 40 45 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): OPA653 50 5 OPA653 SBOS348 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: VS = ±6 V (continued) At G = +2 V/V, RL = 100 Ω, and TA = +25°C, unless otherwise noted. NONINVERTING HARMONIC DISTORTION vs FREQUENCY -40 VS = ±6 V RL = 100 W VO = 2 VPP Gain = +2 V/V -50 -60 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -40 INVERTING HARMONIC DISTORTION vs FREQUENCY Second Harmonic -70 -80 Third Harmonic -90 -100 -50 Second Harmonic -70 Third Harmonic -80 -90 100 M -60 -65 10 M 100 M Frequency (Hz) Figure 7. Figure 8. HARMONIC DISTORTION vs LOAD HARMONIC DISTORTION vs OUTPUT VOLTAGE -50 VS = ±6 V RL = 100 W f = 10 MHz Gain = +2 V/V -55 -70 -75 1M Frequency (Hz) Harmonic Distortion (dBc) Harmonic Distortion (dBc) 10 M VS = ±6 V f = 10 MHz VO = 2 VPP Gain = +2 V/V -55 Second Harmonic -80 -85 -90 -95 -60 -65 Second Harmonic -70 -75 -80 -85 Third Harmonic -90 -95 Third Harmonic -100 -100 100 200 300 400 500 600 700 800 900 1k 1 6 Figure 10. HARMONIC DISTORTION vs ±VSUPPLY VOLTAGE TWO-TONE INTERMODULATION DISTORTION vs FREQUENCY -40 Intermodulation Distortion (dBc) Second Harmonic -85 Third Harmonic -90 f = 10 MHz RL = 100 W VOUT = 2 VPP Gain = +2 V/V 4.0 5 Figure 9. -80 -100 4 VOUT (VPP) -75 -95 3 2 Load (W) -70 Harmonic Distortion (dBc) -60 -100 1M 6 VS = ±6 V RL = 100 W VO = 2 VPP Gain = -1 V/V -50 4.5 VS = ±6 V RL = 100 W VOUT = 2-VPP Envelope Gain = +2 V/V -50 -60 Second Intermodulation -70 -80 Third Intermodulation -90 -100 ±Supply Voltage (V) 50 M 100 M Frequency (Hz) Figure 11. Figure 12. 5.0 5.5 6.0 0 Submit Documentation Feedback 150 M Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): OPA653 OPA653 www.ti.com........................................................................................................................................................................................... SBOS348 – DECEMBER 2008 TYPICAL CHARACTERISTICS: VS = ±6 V (continued) At G = +2 V/V, RL = 100 Ω, and TA = +25°C, unless otherwise noted. INVERTING OVERDRIVE RECOVERY (GAIN = –1V/V) 2 4 1 2 0 0 VOUT Right Scale VIN Left Scale -1 -2 -2 -4 -3 -6 0 20 40 60 4 4 3 2 1 1 0 0 -1 -1 -2 -2 -3 -3 -4 -4 0 80 100 120 140 160 180 200 220 240 20 40 60 80 100 120 140 160 180 200 Time (ns) Time (ns) Figure 13. Figure 14. POWER-SUPPLY REJECTION RATIO vs FREQUENCY FREQUENCY RESPONSE vs CLOAD (RLOAD = 1 kΩ) 5 80 70 CL = 10 pF RISO = 46.4 W 0 Normalized Gain (dB) 60 PSRR (dB) 3 VOUT Right Scale VIN Left Scale 2 Input Voltage (V) 6 50 +PSRR -PSRR 40 30 20 -50 CL = 100 pF RISO = 10.7 W -10 CL = 47 pF RISO = 15.0 W -15 CL = 22 pF RISO = 23.7 W -20 10 0 100 k Output Voltage (V) 3 Output Voltage (V) Input Voltage (V) NONINVERTING OVERDRIVE RECOVERY (GAIN = +2V/V) 10 M 1M -25 10 M 100 M 100 M Frequency (Hz) 1G Frequency (Hz) Figure 15. Figure 16. RISO vs CLOAD (RLOAD = 1 kΩ) CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY 100 RISO (W) Closed-Loop Output Impedance (W) 100 10 10 100 10 1 0.1 100 k 1M 10 M CLOAD (pF) Frequency (Hz) Figure 17. Figure 18. 100 M Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): OPA653 1G 7 OPA653 SBOS348 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: VS = ±6 V (continued) At G = +2 V/V, RL = 100 Ω, and TA = +25°C, unless otherwise noted. SLEW RATE vs VOUT STEP OUTPUT VOLTAGE SWING vs RLOAD 4000 5 4 Falling 3 2 Rising VOUT (V) Slew Rate (V/ms) 3000 2000 1 VOUT High 0 VOUT Low -1 -2 1000 -3 -4 0 -5 1 2 3 4 5 6 0 VOUT Step (V) 1k RLOAD (W) Figure 19. 8 100 200 300 400 500 600 700 800 900 Figure 20. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): OPA653 OPA653 www.ti.com........................................................................................................................................................................................... SBOS348 – DECEMBER 2008 APPLICATION INFORMATION Wideband, Noninverting, and Inverting Operation The OPA653 is a very broadband, voltage-feedback amplifier with internal gain-setting resistors that set a fixed gain of +2 V/V or -1 V/V and a high-impedance JFET-input stage. Its very high bandwidth of 500 MHz can be used to either deliver high signal bandwidths at a gain of +2 V/V or, if driven from a low-impedance source, a gain of –1 V/V . The OPA653 is designed to provide very low noise and accurate pulse response with low overshoot and ringing. To achieve the full performance of the OPA653, careful attention to printed circuit board (PCB) layout and component selection is required as discussed in the remaining sections of this data sheet. Figure 21 shows the noninverting gain of +2-V/V circuit that is used as the basis for the Typical Characteristics. Most of the curves were characterized using signal sources with 50-Ω driving impedance, and with measurement equipment that presents a 50-Ω load impedance. In Figure 21, the 49.9-Ω shunt resistor to ground at the VIN+ input is used to match the source impedance of the test generator and cable, while the 49.9-Ω series output resistor VOUT provides matching impedance for the measurement equipment load and cable. Data sheet voltage swing specifications are taken at the noninverting input pin, VIN+, or the output pin, VOUT, unless otherwise noted. +6 V 0.1 mF 50-W Source 10 mF VS+ VIN+ VOUT 49.9 W 50-W Load OPA653 49.9 W VIN- 160 W 160 W VS0.1 mF 10 mF -6 V Figure 22 shows the OPA653 in a noninverting gain of –1 V/V configuration in a 50-Ω test environment as was used for testing the Typical Characteristics. The circuit operation is essentially the same as Figure 21 except that a 72.3-Ω termination resistor is now used between the VIN– input and ground, so that together with the gain-setting resistor (RG = 160 Ω), the input impedance is approximately 50 Ω. The VIN+ input is terminated to ground using a 49.9-Ω resistor as a precaution to avoid single transistor oscillations at the input; the value is not critical, but attention should be paid to avoid large values because of the noise contribution as noted below. +6 V 0.1 mF 10 mF VS+ 49.9 W VIN+ VOUT 50-W Source 49.9 W 50-W Load OPA653 VIN- 160 W 160 W 72.3 W VS- 0.1 mF 10 mF -6 V Figure 22. Noninverting Gain of –1 V/V in 50-Ω Test Environment Note that the 72.3-Ω input termination resistor and the 50-Ω source impedance of the test equipment modify the noise gain to +1.84 V/V and the amplifier is compensated for optimal performance with a noise gain of +2 V/V. This compensation reduces the phase margin and results in more peaking in the frequency response and more overshoot/ringing in the pulse response. This effect can be seen by comparing the inverting and noninverting frequency and pulse response graphs in the characteristic data. The amplifier phase margin can be restored in an application that uses an inverting configuration if it is driven from a very low impedance source such as an op amp. Figure 21. Noninverting Gain of +2 V/V in 50-Ω Test Environment space Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): OPA653 9 OPA653 SBOS348 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com OPERATING SUGGESTIONS Setting Resistor Values to Minimize Noise The OPA653 provides a low input noise voltage. Figure 23 shows the op amp noise analysis model with all the noise terms included. In this model, all the noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. eN OPA653 However, attention should be paid to the value of RT or other source impedance on the noninverting input. High-value resistive impedance on the noninverting input can add significant noise; for example, 2.4 kΩ adds a Johnson voltage noise term equal to the amplifier itself (6.2 nV/√Hz). So while the JFET input of the OPA653 is ideal for high source impedance applications in the noninverting configuration of Figure 21, the overall bandwidth and noise are limited by high source impedances. VIN+ VOUT RT IBN Driving Capacitive Loads eO 4kTRT RF = 160 W IBI 4kTRF 4kT RG RG = 160 W VIN- Figure 23. Noise Analysis Circuit The total output spot noise voltage can be computed as the square root of the squared contributing terms to the output noise voltage. This calculation adds all the contributing noise powers at the output by superposition, then takes the square root to return to a spot noise voltage. Equation 1 shows the general form for this output noise voltage using the terms shown in Figure 23. 2 eO = [4kTR ] 2 2 1+ T + (IBNRT) + eN RF RF + (IBIRF)2 + 4kTRF 1 + RG RG (1) Dividing this expression by the noise gain = 1 + RF/RG gives the equivalent input-referred spot noise voltage at the noninverting input as shown in Equation 2 One of the most demanding and yet very common load conditions for an op amp is capacitive loading. The OPA653 is very robust, but care should be taken with light loading scenarios so output capacitance does not lead to decreased stability, increased frequency response peaking, overshoot, and ringing. When the amplifier output resistance is considered, capacitive loading introduces an additional pole in the signal path that reduces the phase margin. Several external solutions to this problem have been suggested for standard op amps. Because the OPA653 has internal gain-setting resistors, the only real option is to use a series output resistor. This option is a good solution because when the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, a series output resistor is the simplest and most effective technique. The idea is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor, RISO, between the amplifier output and the capacitive load as shown in Figure 24 below. In effect, this configuration isolates the phase shift from the loop gain of the amplifier, thus restoring the phase margin and improving stability. OPA653 VIN+ VOUT RISO 160 W VLOAD CLOAD VIN- RLOAD 160 W 2 eNI = 2 4kTRT + (IBNRT) + eN 2 I R + BI F 2 + 4kTRF 2 Figure 24. Adding Series Ouput Resistance to Isolate Capacitive Loads (2) Putting high resistor values into Equation 2 can quickly dominate the total equivalent input-referred noise. Because the gain-setting resistors, RF and RG, are internal to the device, the user cannot change this noise contribution, and the noise gain is equal to +2 V/V. 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): OPA653 OPA653 www.ti.com........................................................................................................................................................................................... SBOS348 – DECEMBER 2008 The Typical Characteristics show the recommended RISO versus Capacitive Load performance (see Figure 17) and the resulting frequency response with a 1-kΩ load. Note that larger RISO values are required for lower capacitive loading. In this case, a design target of a maximally-flat frequency response was used. Lower values of RISO may be used if some peaking can be tolerated. Long PCB traces, unmatched cables, and connections to multiple devices can easily degrade the performance of the OPA653. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA653 output pin (see the Board Layout section). With heavier loads (for example, the 100-Ω load presented in the test circuits used for testing the Typical Characteristics), the OPA653 is very robust; RISO can be as low as 10 Ω with capacitive loads less than 5 pF and continue to show a flat frequency response. Board Layout Distortion Performance b) Minimize the distance (less than 0.25 in, or 6,35 mm) from the power-supply pins to the high-frequency, 0.1-µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Use a single point ground, located away from the input pins, for the positive and negative supply high-frequency, 0.1-µF decoupling capacitors. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors. Larger (2.2-µF to 10-µF) decoupling capacitors, effective at lower frequencies, should also be used on the supply pins. These larger capacitors may be placed somewhat farther from the device and may be shared among several devices in the same area of the PCB. The OPA653 is capable of delivering low distortion at high frequencies. The distortion plots in the Typical Characteristics show the typical distortion under a wide variety of conditions. Generally, the best distortion performance can be achieved using higher power-supply voltage (±6 V is recommended), lower output voltage swings, and lower loads. The total load includes the feedback network—in the noninverting configuration, this value is the sum of RF + RG = 320 Ω, while in the inverting configuration the total load is only RF = 160 Ω (see Figure 22). Power-supply decoupling is critical for harmonic distortion performance. In particular, for optimal second-harmonic performance, the high-frequency, 0.1-µF, power-supply decoupling capacitors should be as close as posible to the positive and negative supply pins and should be brought to a single point ground away from the input pins. Pulse and Transient Response To achieve optimum pulse and transient response, the OPA653 should be used in a noise gain of +2 V/V configuration, with minimal capacitance at the output, and high-frequency, 0.1-µF, power-supply decoupling capacitors as close the power pins as possible. Note: Noise gain of +2 V/V is achieved by tying VIN– to a 0-Ω point. In noninverting gain of +2 V/V applications, VIN– should be grounded, and in inverting gain of –1 V/V applications, VIN– should be driven from a near-0-Ω source such as an op amp. Achieving optimum performance with a high-frequency amplifier such as the OPA653 requires careful attention to PCB layout parasitics and external component types. Recommendations that can optimize device performance include the following. a) Minimize parasitic capacitance to any ac ground for all of the signal input/output (I/O) pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional band-limiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. c) Careful selection and placement of external components preserves the high-frequency performance of the OPA653. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film and carbon composition, axially-leaded resistors can also provide good high-frequency performance. Again, keep the leads and PCB trace length as short as possible. Never use wirewound-type resistors in a high-frequency application. The inverting input pin is the most sensitive to parasitic capacitance; consequently, always position the feedback resistor as close to the negative input as possible. The output is also sensitive to parasitic capacitance; therefore, position a series output resistor (in this case, RISO) as close to the output pin as possible. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): OPA653 11 OPA653 SBOS348 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com Other network components, such as noninverting input termination resistors, should also be placed close to the package. Even with a low parasitic capacitance, excessively high resistor values can create significant time constants that can degrade device performance. Good axial metal film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For resistor values greater than 1.5 kΩ, this parasitic capacitance can add a pole and/or zero below 500 MHz that can affect circuit operation. Keep resistor values as low as possible. Using values less than 500 Ω automatically holds the resistor noise terms low, and minimizes the effects of parasitic capacitance. d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils, or 1,27 cm to 2,54 cm) should be used. Estimate the total capacitive load and set RISO from the plot of Recommended RISO vs Capacitive Load (Figure 17). Low parasitic capacitive loads (less than 5 pF) may not need an RISO because the OPA653 is nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an RISO are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50-Ω environment is normally not necessary onboard, and in fact a higher impedance environment improves distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA653 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. If the 6-dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this 12 case, and set the series resistor value as shown in the plot of RISO vs Capacitive Load (Figure 17). This configuration does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation as a result of the voltage divider formed by the series output into the terminating impedance. e) Socketing a high-speed part such as the OPA653 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network that can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA653 directly onto the board. Input and ESD Protection The OPA653 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies, as Figure 25 shows. +VCC External Pin Internal Circuitry -VCC Figure 25. Internal ESD Protection These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30-mA continuous current. Where higher currents are possible (for example, in systems with ±12-V supply parts driving into the OPA653), current limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible because high values degrade both noise performance and frequency response. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): OPA653 OPA653 www.ti.com........................................................................................................................................................................................... SBOS348 – DECEMBER 2008 EVALUATION MODULE Schematic and PCB Layout Figure 26 is the OPA653EVM schematic. Layers 1 through 4 of the PCB are shown in Figure 27. It is recommended to follow the layout of the external components near to the amplifier, ground plane construction, and power routing as closely as possible. N/C 2 3 + 7 6 4 + + Figure 26. OPA653EVM Schematic Figure 27. OPA653EVM PCB Layers 1 through 4 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): OPA653 13 OPA653 SBOS348 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com Bill of Materials Table 1 lists the bill of materials for the OPA653EVM as supplied from TI. Table 1. OPA653EVM Parts List 14 SMD SIZE REFERENCE DESIGNATOR QUANTITY D C1, C2 2 (AVX) TAJ106K035R 0603 C3, C4 2 (AVX) 0603YC104KAT2A R1, R2 2 (ROHM) MCR03EZPJ000 0603 R4 1 0603 R3, R5 2 (ROHM) MCR03EZPFX49R9 Jack, Banana Receptance, 0.25-in dia. hole J4, J5, J8 3 (SPC) 813 7 Connector, Edge, SMA PCB jack J1, J2, J3 3 (JOHNSON) 142-0701-801 8 Test Point, Black TP1 1 (KEYSTONE) 5001 9 IC, OPA653 U1 1 (TI) OPA653DRB 10 Standoff, 4-40 Hex, 0.625-in length 4 (KEYSTONE) 1808 11 Screw, Phillips, 4-40, .250 in 4 SHR-0440-016-SN 12 Board, Printed Circuit 1 (TI) EDGE# 6506174 13 Bead, Ferrite, 3 A, 80 Ω 2 (STEWARD) HI1206N800R-00 ITEM DESCRIPTION 1 Cap, 10.0 µF, Tantalum, 10%, 35 V 2 Cap, 0.1 µF, Ceramic, X7R, 16 V 3 Resistor, 0 Ω 0603 4 Open 5 Resistor, 49.9 Ω, 1/10W, 1% 6 1206 FB1, FB2 Submit Documentation Feedback MANUFACTURER PART NUMBER Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): OPA653 OPA653 www.ti.com........................................................................................................................................................................................... SBOS348 – DECEMBER 2008 EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does not fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives. Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. This notice contains important safety information about temperatures and voltages. For additional information on TI’s environmental and/or safety programs, please contact the TI application engineer or visit www.ti.com/esh. No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or combination in which such TI products or services might be or are used. FCC Warning This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of ±3.5 V to ±6.5 V split-supply and the output voltage range of ±3.5 V to ±6.5 V power-supply voltage; do not exceed ±6.5 V power-supply voltage. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures greater than +85°C. The EVM is designed to operate properly with certain components above +85°C as long as the input and output ranges are maintained. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): OPA653 15 PACKAGE OPTION ADDENDUM www.ti.com 22-Dec-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty OPA653IDBVR PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI OPA653IDBVT PREVIEW SOT-23 DBV 5 250 TBD Call TI Call TI OPA653IDRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA653IDRBT ACTIVE SON DRB 8 250 CU NIPDAU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID RF/IF and ZigBee® Solutions amplifier.ti.com dataconverter.ti.com dsp.ti.com www.ti.com/clocks interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti-rfid.com www.ti.com/lprf Applications Audio Automotive Broadband Digital Control Medical Military Optical Networking Security Telephony Video & Imaging Wireless www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/medical www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2008, Texas Instruments Incorporated