A PLUS MAKE YOUR PRODUCTION A-PLUS ASM17012CB DATA SHEET APLUS INTEGRATED CIRCUITS INC. Address: 3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei, Taiwan 115, R.O.C. (115)台北市南港區成功路㆒段 32 號 3 樓之 10. Sales E-mail: Mr. Jason [email protected] TEL: 886-2-2782-9266 Technology E-mail: Mr. George [email protected] FAX: 886-2-2782-9255 WEBSITE : http: //www.aplusinc.com.tw ASM17012CB ASM17012CB – VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR 1.0 General Description The AM4DD1707 is very low cost voice synthesizer with 4-bit microprocessor. It has various features including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog timer(WDT), voice synthesizer, etc. It consists of 22 instructions in the device. With CMOS technology and halt function can minimize power dissipation. Its architecture is similar to RISC, with two stages of instruction pipeline. It allows all instructions to be executed in a single cycle, except for program branches and data table read instructions (which need two instruction cycles). 1.1 Feature Single power supply can operate from 2.4V through 5.5V Internal Program ROM: 4K x 10-bit 1 sets of 19-bit DPR can access up to 512K x 10 bits data memory space Data Registers: • 96 x 4-bit data RAM (00-1Fh plus 40h-7Fh) • Unbanked special function registers (SFR) range: 20h-3Fh I/O Ports: • PRA: 4-bit I/O Port A (2Bh) • PRB: 4-bit Output Port B (2Dh) • PRC: 4-bit Input Port C (2Fh) On-chip clock generator: Resistive Clock Drive(RM) Timer: 1 • Timer0: a 9-bit auto-reload timer/counter Stack: 2-level subroutine nesting HALT and Release from HALT function to reduce power consumption Watch Dog Timer (WDT) Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles Number of instruction: 22 The Voice function can be implemented by microprocessor instruction • One 8-bit COUT output for ASMxxxxx ASM17012CB FIGURE 1.1 : Block Diagram of ASM17012CB Data Bus[3:0] ROM Latch PCLATCH(8) PCL(4) Stack(12) PC[11:0] (ADDR[18:12]) =0000000b (2-Level) ADDR[18:0] 0 ROM_ADDR[18:0] Instruction Bus [9:0] 1 DPR3,2,1 Instruction Latch Program (Data) ROM DPR[18:0] Instruction Decoder Control Signal DLATCH(10) ROM_Data[9:0] Data Bus[3:0] Instruction Bus [9:0] Accumlator(4) SRAM ALU(4) Immediate(4) PRA(4) PRB(4) PRC(4) Timer0(9) (96 x 4) Instruction Bus [9:0] PCH(8) 00h-1Fh 40h-7Fh Register(4) enter test mode One-Channel ( Voice synthesizer ) Reset Chip Reset Chip Clock Generator PRASL(4) Test select Power on Reset RESET pin COUT OSC VDD/GND PRA0 P1,P2,P3,P4 weak or strong pull-low for PRA, PRB, PRC COUT 2 Rev 1.1 2002/10/29 ASM17012CB FIGURE 1.2 : External ROM Map of ASM17012CB PC[11:0] 12bit x 2 STACK 19-bit Data Pointer Reset Vector 00000h 00080h Reserved for Testing 00080h-003FFh 00400h Program and data ROM 00000h-00FFFh 00FFFh(4K) Data ROM 00000h-7FFFFh 7FFFFh(512Kx10-bits) ASM17012CB 1.2 Pin-Out ASM17012CB Pin-Out VDD3 PRC1 I I PRC0/RESET I STI Std./O.D. STI Std./O.D. PRA3-1 I/O STI Std./O.D. PRA0/RESET I/O STI Std./O.D. OSC VDD1 COUT GND1 GND2 TEST VDD2 PRB0-3 PRC2-3 I I O I I O I O I GND3 I Std./O.D. STI Std./O.D. - 1.3 Application circuit Third Power supply during operation Input port with programmable strong pull-low or weak pull-low or fix-input-floating capability Input port with programmable strong pull-low or weak pull-low or fix-input-floating capability Mask option selected as an external RESET pin with weak pull-low capability I/O port with programmable strong pull-low or weak pull-low or fix-input-floating capability Output type with standard or Open-Drain output I/O port with programmable strong pull-low or weak pull-low or fix-input-floating capability Output type with standard or Open-Drain output Mask option selected as an external RESET pin with weak pull-low capability RM mode Oscillator input First Power supply during operation Current Output of Audio First Circuit Ground Potential Second Circuit Ground Potential Enter Test Mode. ( TEST = High ) Second Power supply during operation Output type with standard or Open-Drain output Input port with programmable strong pull-low or weak pull-low or fix-input-floating capability Third Circuit Ground Potential ASM17012CB 1.4 Bonding Diagram (256K x 10 bit) x 2-B lock R O M Y= 3140 + 80 (um) ASM17012CB C H IP S IZ E : X = 3090 + 100 (um), Y= 3140 + 80 (um) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 X= 3090 + 100 (um) Substrate must be connected to GND. ASM17012CB Pad Location PAD # PAD Name 1 VDD3 2 PRC1 3 PRC0 4 PRA3 5 PRA2 6 PRA1 7 PRA0/RESET 8 OSC 9 VDD1 10 COUT 11 GND1 X -1445.96 -1325.24 -1202.92 -1080.6 -958.28 -835.96 -713.64 -591.32 -414.36 -162.24 38.72 Chip Size: X= 3090 + 100 (um) , Y= 3140 + 80 (um) Y PAD # PAD Name X Y -1456.08 12 GND2 118.72 -1450.56 -1456.08 13 TEST 319.68 -1456.08 -1456.08 14 VDD2 575.32 -1456.08 -1456.08 15 PRB0 714.48 -1456.08 -1456.08 16 PRB1 836.8 -1456.08 -1456.08 17 PRB2 959.12 -1456.08 -1456.08 18 PRB3 1081.44 -1456.08 -1456.08 19 PRC2 1203.76 -1456.08 -1456.08 20 PRC3 1326.08 -1456.08 -1456.08 21 GND3 1449.36 -1456.08 -1450.56 ASM17012CB 1.5 DC Characteristics for ASMXXXXX SYMBOL VDD PARAMETER OPERATING VOLTAGE Isb SUPPLY CURRENT Iop STANDBY OPERATING INPUT CURRENT /Internal pull low Iih Ioh OUTPUT HIGH CURRENT Iol OUTPUT LOW CURRENT DA CURRENT OUT (FULL SCALE) FREQUENCY STABILITY Cout dF/F dF/F VDD MIN. 2.4 TYP. 3 3 5 3 5 3 5 2 7 3 9 5 -5.2 3 5 3 5 3 5 -3 -8 7 20 4 5.2 Fosc VARIATION MAX. 5.0 1 1 UNIT V uA mA uA mA -10 10 % -20 20 % CONDITION depending on Freq. 4MHz, RM in HALT Mode 4MHz, RM IO Floating 4MHz, RM in HALT Mode (IO Ports with weak pull-high pull-low) 4MHz, RM (IO ports) Fosc(3v- 2.4v) Fosc (3v) VDD=3V, Rosc=780k, 4MHz FIGURE 1.3 : Frequency Range for Rosc in RM mode Resistor(k ohm) 3v Freq.(MHz) 1000 3.18 760 4.1 560 5.4 390 7.69 R osc & Freq. Freq. MHz 10 8 7.69 6 5.4 4.1 4 2 3.18 0 0 100 200 300 400 500 600 R osc k ohm 700 800 900 1000 1100