BB ADS5272

ADS5272
SBAS324 − JUNE 2004
8-Channel, 12-Bit, 65MSPS ADC
with Serial LVDS Interface
PLL
IN2P
IN2N
IN4P
IN4N
IN5P
IN5N
The ADS5272 is a high-performance, 65MSPS, 8-channel,
parallel analog-to-digital converter (ADC). Internal references
are provided, simplifying system design requirements. Low
power consumption allows for the highest of system
integration densities. Serial LVDS (low-voltage differential
signaling) outputs reduce the number of interface lines and
package size.
An integrated phase lock loop multiplies the incoming ADC
sampling clock by a factor of 12. This 12x clock is used in the
process of serializing the data output from each channel. The
12x clock is also used to generate a 1x and a 6x clock, both
of which are transmitted as LVDS clock outputs. The 6x clock
is denoted by the differential pair LCLKP and LCLKN, while the
1x clock is denoted by ADCLKP and ADCLKN. The word
output of each ADC channel can be transmitted either as MSB
IN6P
IN6N
IN7P
IN7N
IN8P
IN8N
ADCLKN
S/H
12−Bit
ADC
Serializer
S/H
12−Bit
ADC
Serializer
S/H
12−Bit
ADC
Serializer
S/H
12−Bit
ADC
Serializer
S/H
12−Bit
ADC
Serializer
S/H
12−Bit
ADC
Serializer
S/H
12−Bit
ADC
Serializer
S/H
12−Bit
ADC
Serializer
INT/EXT
OUT1N
OUT2P
OUT2N
OUT3P
OUT3N
OUT4P
OUT4N
OUT5P
OUT5N
Registers
Reference
OUT1P
OUT6P
OUT6N
OUT7P
OUT7N
OUT8P
OUT8N
Control
PD
IN1P
IN1N
IN3P
DESCRIPTION
ADCLKP
1X ADCLK
ADCLK
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.
! Copyright  2004, Texas Instruments Incorporated
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PRODUCT PREVIEW
LCLKN
IN3N
Portable Ultrasound Systems
Tape Drives
Test Equipment
Optical Networking
LCLKP
6X ADCLK
RESET
D
D
D
D
The device is available in a TQFP-80 PowerPAD package and
is specified over a −40°C to +85°C operating range.
SDATA
APPLICATIONS
The ADS5272 provides internal references, or can optionally
be driven with external references. Best performance can be
achieved through the internal reference mode.
CS
Maximum Sample Rate: 65MSPS
12-Bit Resolution
No Missing Codes
Power Dissipation: 996mW
CMOS Technology
Simultaneous Sample-and-Hold
70.5dB SNR at 10MHz IF
Internal and External References
3.3V Digital/Analog Supply
Serialized LVDS Outputs
Integrated Frame and Synch Patterns
MSB and LSB First Modes
Option to Double LVDS Clock Output Currents
Pin- and Format-Compatible Family
TQFP-80 PowerPAD Package
SCLK
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
or LSB first. The bit coinciding with the rising edge of the 1x
clock output is the first bit of the word. Data is to be latched by
the receiver on both the rising and falling edges of the 6x clock.
REFT
VCM
REFB
FEATURES
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SBAS324 − JUNE 2004
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage Range, AVDD . . . . . . . . . . . . . . . . . . −0.3V to 3.8V
Supply Voltage Range, LVDD . . . . . . . . . . . . . . . . . . −0.3V to 3.8V
Voltage Between AVSS and LVSS . . . . . . . . . . . . . . −0.3V to 0.3V
Voltage Between AVDD and LVDD . . . . . . . . . . . . . . −0.3V to 0.3V
Voltages Applied to External REF Pins . . . . . . . . . . −0.3V to 2.4V
All LVDS Data and Clock Outputs . . . . . . . . . . . . . . −0.3V to 2.4V
Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to 2.7V
Peak Total Input Current (all inputs) . . . . . . . . . . . . . . . . . . . −30mA
Operating Free-Air Temperature Range, TA . . . . . . −40°C to 85°C
Lead Temperature 1.6mm (1/16″ from case for 10s) . . . . . . 220°C
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT PREVIEW
PRODUCT
PACKAGE
DESIGNATOR
PACKAGE-LEAD
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS5272
HTQFP-80(2)
PFP
−40°C to +85°C
ADS5272IPFP
ADS5272IPFP
Tray, 96
″
″
″
″
″
ADS5272IPFPT
Tape and Reel, 250
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
(2) Thermal pad size: 4.69mm x 4.69mm (min), 6.20mm x 6.20mm (max).
RELATED PRODUCTS
MODEL
RESOLUTION (BITS)
SAMPLE RATE (MSPS)
CHANNELS
ADS5270
ADS5271
ADS5273
ADS5275
ADS5276
ADS5277
12
12
12
10
10
10
40
50
70
40
50
65
8
8
8
8
8
8
RECOMMENDED OPERATING CONDITIONS
ADS5272
SUPPLIES AND REFERENCES
Analog Supply Voltage, AVDD
Output Driver Supply Voltage, LVDD
CLOCK INPUT AND OUTPUTS
ADCLK Input Sample Rate (low-voltage TTL)
Low Level Voltage Clock Input
High Level Voltage Clock Input
ADCLKP and ADCLKN Outputs (LVDS)
LCLKP and LCLKN Outputs (LVDS)(1)
Operating Free-Air Temperature, TA
Thermal Characteristics
qJA
qJC
(1) 6 × ADCLK.
MIN
TYP
MAX
UNIT
3.0
3.0
3.3
3.3
3.6
3.6
V
V
65
0.6
MSPS
V
V
MHz
MHz
°C
20
VDD − 0.6
20
120
−40
65
390
+85
21
68
°C/W
°C/W
REFERENCE SELECTION
MODE
INT/EXT
DESCRIPTION
2.0VPP Internal Reference
1
Default with internal pull-up.
External Reference
0
Internal reference is powered down. Common mode of external reference should be within
50mV of VCM. VCM is derived from the internal bandgap voltage.
2
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SBAS324 − JUNE 2004
ELECTRICAL CHARACTERISTICS
TMIN = −40°C, and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V,
LVDD = 3.3V, −1dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5272
TEST CONDITIONS
MIN
Differential Nonlinearity
fIN = 5MHz
−0.9
Integral Nonlinearity
fIN = 5MHz
−2.0
TBD
PARAMETER
TYP
MAX
UNITS
±0.5
0.9
LSB
±0.6
2.0
LSB
±0.2
TBD
%FS
DC ACCURACY
No Missing Codes
DNL
INL
Assured
Offset Error(1)
Offset Temperature Coefficient
14
ppm/°C
Fixed Attenuation in Channel(2)
1
%FS
±0.2
Variable Attenuation in Channel(3)
Gain Error(4)
REFT − REFB
TBD
Gain Temperature Coefficient(5)
±1.0
%FS
TBD
%FS
44
ppm/°C
POWER SUPPLY
Total Supply Current
VIN = FS, FIN = 5MHz
302
mA
I(AVDD)
Analog Supply Current
VIN = FS, FIN = 5MHz
TBD
mA
I(LVDD)
Digital Output Driver Supply Current
VIN = FS, FIN = 5MHz, LVDS Into 100Ω Load
TBD
Power Dissipation
Power Down
996
Clock Running
mA
TBD
90
mW
mW
PRODUCT PREVIEW
ICC
REFERENCE VOLTAGES
VREFT
Reference Top (internal)
1.95
2.0
2.05
V
VREFB
Reference Bottom (internal)
0.95
1.0
1.05
V
Common-Mode Voltage
1.45
1.5
1.55
VCM
VCM Output Current(6)
VREFT
Reference Top (external)
VREFB
Reference Bottom (external)
±50mV Change in Voltage
±2
V
mA
1.875
V
1.125
External Reference Input Current(7)
2.0
Differential Input Capacitance
7.0
V
mA
ANALOG INPUT
Differential Input Voltage Range
Voltage Overload Recovery Time
Input Bandwidth
pF
VCM ± 0.05
Analog Input Common-Mode Range
1.5
2.02
V
VPP
Differential Input Signal at 4VPP
Recovery to Within 1% of Code
4.0
CLK Cycles
−3dBFS
300
MHz
DIGITAL DATA OUTPUTS
Data Bit Rate
340
780
MBPS
SERIAL INTERFACE
SCLK
(1)
(2)
(3)
(4)
(5)
(6)
(7)
20
MHz
VIN LOW
Serial Clock Input Frequency
Input Low Voltage
0
0.6
V
VIN HIGH
Input High Voltage
2.1
VDD
V
Input Current
±10
µA
Input Pin Capacitance
5.0
pF
Offset error is the deviation of the average code from mid-code for a zero input. Offset error is expressed in terms of % of full-scale.
Fixed attenuation in the channel arises due to a fixed attenuation of about 1% in the sample-and-hold amplifier. When the differential voltage at the analog input pins are
changed from −VREF to +VREF, the swing of the output code is expected to deviate from the full-scale code (4096LSB) by the extent of this fixed attenuation [VREF is defined
as (REFT − REFB)].
Variable attenuation in the channel refers to the attenuation of the signal in the channel over and above the fixed attenuation.
The reference voltages are trimmed at production so that (VREFT − VREFB) is within ± 25mV of the ideal value of 1V. It does not include fixed attenuation.
The gain temperature coefficient refers to the temperature coefficient of the attenuation in the channel. It does not account for the variation of the reference voltages with
temperature.
VCM provides the common-mode current for the inputs of all eight channels when the inputs are AC-coupled. The VCM output current specified is the additional drive of
the VCM buffer if loaded externally.
Average current drawn from the reference pins in the external reference mode.
3
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SBAS324 − JUNE 2004
AC CHARACTERISTICS
TMIN = −40°C, TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V,
−1dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5272
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
SFDR
HD2
HD3
PRODUCT PREVIEW
SNR
SINAD
IMD
ENOB
Spurious-Free Dynamic Range
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
2nd-Order Harmonic Distortion
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
3rd-Order Harmonic Distortion
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
Signal-to-Noise Ratio
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
Signal-to-Noise and Distortion
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
TBD
TBD
TBD
TBD
f1 = 9.5MHz at −7dBFS
f2 = 10.2MHz at −7dBFS
fIN = 5MHz
Two-Tone Intermodulation Distortion
Effective Number of Bits
Crosstalk
TBD
Signal Applied to 7 Channels;
Measurement Taken on the Channel with
No Input Signal
87
85
85
83
dBc
dBc
dBc
dBc
90
90
89
86
dBc
dBc
dBc
dBc
87
85
85
83
dBc
dBc
dBc
dBc
70.5
70.5
70.5
70.5
dBFS
dBFS
dBFS
dBFS
70
70
70
70
dBFS
dBFS
dBFS
dBFS
−85
dBFS
11.3
Bits
−90
dBc
LVDS DIGITAL DATA AND CLOCK OUTPUTS
Test conditions at IO = 3.5mA, RLOAD = 100Ω, and CLOAD = 9pF. IO refers to the current setting for the LVDS buffer. RLOAD is the differential load resistance
between the differential LVDS pair. CLOAD is the effective single-ended load capacitance between the differential LVDS pins and ground. CLOAD includes the
receiver input parasitics as well as the routing parasitics. Measurements are done with a transmission line of 100Ω differential impedance between the device and
the load. All LVDS specifications are functionally tested, but not parametrically tested.
PARAMETER
DC SPECIFICATIONS(1)
VOH
VOL
 VOD
VOS
CO
 ∆VOD
∆VOS
ISOUT
CONDITIONS
MIN
Output Voltage Low, OUTP or OUTN
RLOAD = 100Ω ± 1%; See LVDS Timing Diagram, Page 7
RLOAD = 100Ω ± 1%
900
1025
Output Differential Voltage,  OUTP − OUTN
Output Offset Voltage(2)
RLOAD = 100Ω ± 1%
RLOAD = 100Ω ± 1%; See LVDS Timing Diagram, Page 7
300
350
400
mV
1100
1200
1300
mV
25
mV
RLOAD = 100Ω ± 1%
Drivers Shorted to Ground
25
mV
40
mA
Drivers Shorted Together
12
mA
Output Voltage High, OUTP or OUTN
Output Capacitance(3)
Change in  VOD Between 0 and 1
Change Between 0 and 1
Output Short-Circuit Current
ISOUTNP Output Current
DRIVER AC SPECIFICATIONS
Clock
Clock Signal Duty Cycle
VCM = 1.5V
RLOAD = 100Ω ± 1%
6 × ADCLK
Minimum Data Setup TIme(4, 5)
Minimum Data Hold Time(4, 5)
tRISE/tFALL
(1)
(2)
(3)
(4)
(5)
4
VOD Rise Time or VOD Fall Time
TYP
MAX
UNITS
1375
1500
mV
mV
4
45
50
pF
55
%
650
ps
650
ps
IO = 2.5mA
IO = 3.5mA
400
250
ps
IO = 4.5mA
IO = 6mA
200
ps
150
ps
The DC specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1.
VOS refers to the common-mode of OUTP and OUTN.
Output capacitance inside the device, from either OUTP or OUTN to ground.
Refer to the LVDS application note (SBAA118) for a description of data setup and hold times.
Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume that the data and clock
paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as reduced timing margins.
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SBAS324 − JUNE 2004
SWITCHING CHARACTERISTICS
TMIN = −40°C, TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V,
LVDD = 3.3V, −1dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5272
PARAMETER
MIN
CONDITIONS
TYP
MAX
UNITS
50
ns
SWITCHING SPECIFICATIONS
tSAMPLE
tD(A)
25
Aperture Delay
2.5
Aperture Jitter (uncertainty)
tD(pipeline)
tPROP
Latency
Propagation Delay
ns
1
ps
6.5
cycles
5
ns
SERIAL INTERFACE TIMING
Data is shifted in MSB first.
PRODUCT PREVIEW
Outputs change on
next rising clock edge
after CS goes high.
ADCLK
Start Sequence
CS
t1
Data latched on
each rising edge of SCLK.
t2
SCLK
t3
MSB
SDATA
D6
D5
D4
D3
D2
D1
D0
t4
t5
PARAMETER
DESCRIPTION
MIN
t1
t2
t3
t4
t5
Serial CLK Period
Serial CLK High Time
Serial CLK Low Time
Minimum Data Setup Time
Minimum Data Hold Time
50
TYP
25
25
5
5
MAX
UNIT
ns
ns
ns
ns
ns
5
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SBAS324 − JUNE 2004
SERIAL INTERFACE TIMING
ADDRESS
D6
D5
D4
0
0
0
0
0
0
PRODUCT PREVIEW
DATA
D7
0
0
0
0
0
1
1
D3
D2
0
0
1
1
0
1
0
1
DESCRIPTION
D1
REMARKS
D0
0
0
1
1
0
1
0
1
0. LVDS BUFFERS
Normal ADC Output
Deskew Pattern
Sync Pattern
Custom Pattern
Output Current in LVDS = 3.5mA
Output Current in LVDS = 2.5mA
Output Current in LVDS = 4.5mA
Output Current in LVDS = 6.0mA
1. LSB/MSB MODE
Default LVDS Clock Output Current
2X LVDS Clock Output Current
LSB Mode
MSB Mode
1
D3
0
0
0
D2
X
0
1
D1
X
X
X
D0
1
X
X
D3
D2
D1
D0
X
X
X
X
D3
D2
D1
D0
X
X
X
X
D3
MSB
X
X
D2
X
X
X
D1
X
X
X
D0
X
X
LSB
0
Patterns Get Reversed in MSB First
Mode of LVDS
2. POWER-DOWN ADC CHANNELS
1
Power-Down Channels 1 to 4; D3 is
for Channel 4 and D0 for Channel 1
Example: 1010 Powers Down
Channels 4 and 2 and Keeps
Channels 1 and 3 Alive
3. POWER-DOWN ADC CHANNELS
Power-Down Channels 5 to 8; D3 is
for Channel 8 and D0 for Channel 5
CUSTOM PATTERN (registers 4-6)
0
0
0
1
1
1
0
0
1
0
1
0
Bits for Custom Pattern
TEST PATTERNS(1)
Deskew
101010101010
Sync
000000111111
Custom
Any 12-bit pattern that is defined in the custom pattern registers 4 to 6. The output comes out in the following order:
D0(4) D1(4) D2(4) D3(4) D0(5) D1(5) D2(5) D3(5) D0(6) D1(6) D2(6) D3(6)
where, for example, D0(4) refers to the D0 bit of register 4, etc.
(1) Default is LSB first. If MSB is selected the above patterns will be reversed.
6
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SBAS324 − JUNE 2004
LVDS TIMING DIAGRAM (PER ADC CHANNEL)
Sample n
Sample n+6
Input
1
tSAMPLE
ADCLK
tS
2
LCLKP
6X ADCLK
LCLKN
OUTP
SERIAL DATA
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1
PRODUCT PREVIEW
OUTN
Sample n data
ADCLKP
1X ADCLK
ADCLKN
tD(A)
tPROP
6.5 Clock Cycles
RESET TIMING
t1
+AVDD
Power
Supply
t1 > 10ms
t2 > 100ns
0V
+AVDD
RESET
0V
t2
POWER-DOWN TIMING
Device Fully
Powers Down
10µs
PD
1µs
Device Fully
Powers Up
7
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SBAS324 − JUNE 2004
PIN CONFIGURATION
PRODUCT PREVIEW
AVSS
AVSS
AVSS
ADCLK
AVDD
INT/EXT
AVSS
REFT
REFB
76
75
74
73
72
71
70
69
68
67
66
65
AVSS
AVDD
77
AVSS
CS
78
AVDD
SDA
79
ISET
SCLK
80
VCM
AVSS
TQFP
AVSS
Top View
64
63
62
61
AVDD
1
60 AVDD
IN1P
2
59 IN8N
IN1N
3
58 IN8P
AVSS
4
57 AVSS
IN2P
5
56 IN7N
IN2N
6
55 IN7P
AVDD
7
54 AVDD
AVSS
8
53 AVSS
IN3P
9
52 IN6N
51 IN6P
IN3N 10
ADS5272
AVSS 11
50 AVSS
IN4P 12
49 IN5N
IN4N 13
48 IN5P
AVDD 14
47 AVDD
LVSS 15
46 LVSS
45 RESET
PD 16
LVSS 17
44 LVSS
LVSS 18
43 LVSS
8
36
37
38
39
40
OUT8N
35
OUT8P
34
OUT7N
33
OUT7P
32
LVSS
31
LVDD
30
OUT6N
29
OUT6P
28
OUT5N
27
OUT5P
26
OUT4N
25
OUT4P
24
OUT3N
23
OUT3P
22
OUT1N
OUT1P
21
LVSS
41 ADCLKP
LVDD
LCLKN 20
OUT2N
42 ADCLKN
OUT2P
LCLKP 19
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SBAS324 − JUNE 2004
NAME
PIN #
NUMBER
OF PINS
I/O
DESCRIPTION
AVDD
AVSS
LVDD
LVSS
IN1P
IN1N
IN2P
IN2N
IN3P
IN3N
IN4P
IN4N
IN5P
IN5N
IN6P
IN6N
IN7P
IN7N
IN8P
IN8N
REFT
REFB
VCM
INT/EXT
PD
LCLKP
LCLKN
ADCLK
OUT1P
OUT1N
OUT2P
OUT2N
OUT3P
OUT3N
OUT4P
OUT4N
OUT5P
OUT5N
OUT6P
OUT6N
OUT7P
OUT7N
OUT8P
OUT8N
ADCLKP
ADCLKN
ISET
RESET
CS
SDA
SCLK
1, 7, 14, 47, 54, 60, 63, 70, 75
4, 8, 11, 50, 53, 57, 61, 62, 68, 72-74, 79, 80
25, 35
15, 17, 18, 26, 36, 43, 44, 46
2
3
5
6
9
10
12
13
48
49
51
52
55
56
58
59
67
66
65
69
16
19
20
71
21
22
23
24
27
28
29
30
31
32
33
34
37
38
39
40
41
42
64
45
76
77
78
9
14
2
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
O
I
I
O
O
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I
I
I
I
Analog Power Supply
Analog Ground
LVDS Power Supply
LVDS Ground
Channel 1 Differential Analog Input High
Channel 1 Differential Analog Input Low
Channel 2 Differential Analog Input High
Channel 2 Differential Analog Input Low
Channel 3 Differential Analog Input High
Channel 3 Differential Analog Input Low
Channel 4 Differential Analog Input High
Channel 4 Differential Analog Input Low
Channel 5 Differential Analog Input High
Channel 5 Differential Analog Input Low
Channel 6 Differential Analog Input High
Channel 6 Differential Analog Input Low
Channel 7 Differential Analog Input High
Channel 7 Differential Analog Input Low
Channel 8 Differential Analog Input High
Channel 8 Differential Analog Input Low
Reference Top Voltage (0.1µF capacitor to ground)
Reference Bottom Voltage (0.1µF capacitor to ground)
Common-Mode Output Voltage
Internal/External Reference Select; 0 = External, 1 = Internal
Power-Down; 0 = Normal, 1 = Power-Down
Positive LVDS Clock
Negative LVDS Clock
Data Converter Clock Input
Channel 1 Positive LVDS Data Output
Channel 1 Negative LVDS Data Output
Channel 2 Positive LVDS Data Output
Channel 2 Negative LVDS Data Output
Channel 3 Positive LVDS Data Output
Channel 3 Negative LVDS Data Output
Channel 4 Positive LVDS Data Output
Channel 4 Negative LVDS Data Output
Channel 5 Positive LVDS Data Output
Channel 5 Negative LVDS Data Output
Channel 6 Positive LVDS Data Output
Channel 6 Negative LVDS Data Output
Channel 7 Positive LVDS Data Output
Channel 7 Negative LVDS Data Output
Channel 8 Positive LVDS Data Output
Channel 8 Negative LVDS Data Output
Positive LVDS ADC Clock Output
Negative LVDS ADC Clock Output
Bias Current Setting Resistor of 56kΩ to Ground
Reset to Default; 0 = Reset, 1 = Normal
Chip Select; 0 = Select, 1 = No Select
Serial Data Input
Serial Data Clock
9
PRODUCT PREVIEW
PIN DESCRIPTIONS
"#$%&%
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SBAS324 − JUNE 2004
THEORY OF OPERATION
PRODUCT PREVIEW
OVERVIEW
The ADS5272 is an 8-channel, high-speed, CMOS ADC.
It consists of a high-performance sample-and-hold circuit
at the input, followed by a 12-bit ADC. The 12 bits given out
by each channel are serialized and sent out on a single pair
of pins in LVDS format. All eight channels of the ADS5272
operate from a single clock referred to as ADCLK. The
sampling clocks for each of the eight channels are
generated from the input clock using a carefully matched
clock buffer tree. The 12X clock required for the serializer
is generated internally from ADCLK using a phase lock
loop (PLL). A 6X and a 1X clock are also output in LVDS
format along with the data to enable easy data capture.
The ADS5272 operates from internally generated
reference voltages that are trimmed to ensure matching
across multiple devices on a board. This feature eliminates
the need for external routing of reference lines and also
improves matching of the gain across devices. The
nominal values of REFT and REFB are 2V and 1V,
respectively. These values imply that a differential input of
−1V corresponds to the zero code of the ADC, and a
differential input of +1V corresponds to the full-scale code
(4095 LSB). VCM (common-mode voltage of REFP and
REFN) is also made available externally through a pin, and
is nominally 1.5V.
The ADC employs a pipelined converter architecture
consisting of a combination of multi-bit and single-bit
internal stages. Each stage feeds its data into the digital
error correction logic, ensuring excellent differential
linearity and no missing codes at the 12-bit level. The
pipeline architecture results in a data latency of 6.5 clock
cycles.
The output of the ADC goes to a serializer that operates
from a 12X clock generated by the PLL. The 12 data bits
from each channel are serialized and sent LSB first. In
addition to serializing the data, the serializer also
generates a 1X clock and a 6X clock. These clocks are
generated in the same way the serialized data is
generated, so these clocks maintain perfect synchronization with the data. The data and clock outputs of the
serializer are buffered externally using LVDS buffers.
Using LVDS buffers to transmit data externally has
multiple advantages, such as reduced number of output
pins (saving routing space on the board), reduced power
consumption, and reduced effects of digital noise coupling
to the analog circuit inside the ADS5272.
10
The ADS5272 operates from two sets of supplies and
grounds. The analog supply/ground set is denoted as
AVDD/AVSS, while the digital set is denoted by
LVDD/LVSS.
DRIVING THE ANALOG INPUTS
The analog input biasing is shown in Figure 1. The
recommended method to drive the inputs is through AC
coupling. AC coupling removes the worry of setting the
common-mode of the driving circuit, since the inputs are
biased internally using two 600Ω resistors.
ADS5272
IN+
600Ω
Input
Circuitry
600Ω
IN−
CM Buffer 1
Internal
Voltage
Reference
VCM
CM Buffer 2
Figure 1. Analog Input Bias Circuitry
The sampling capacitor used to sample the inputs is 4pF.
The choice of the external AC coupling capacitor is
dictated by the attenuation at the lowest desired input
frequency of operation. The attenuation resulting from
using a 10nF AC coupling capacitor is 0.04%.
If the input is DC-coupled, then the output common-mode
voltage of the circuit driving the ADS5272 should match
the VCM (which is provided as an output pin) to within
±50mV. It is recommended that the output common-mode
of the driving circuit be derived from VCM provided by the
device.
"#$%&%
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The sampling circuit consists of a low-pass RC filter at the
input to filter out noise components that might be getting
differentially coupled on the input pins. The inputs are
sampled on two 4pF capacitors as shown in Figure 2. The
sampling on the capacitors is done with respect to an
internally generated common-mode voltage (INCM). The
switches connecting the sampling capacitors to the INCM
are opened out first (before the switches connecting them
to the analog inputs). This ensures that the charge
injection arising out of the switches opening is
independent of the input signal amplitude to a first-order of
approximation. SP refers to a sampling clock whose falling
edge comes an instant before the SAMPLE clock. The
falling edge of SP determines the sampling instant.
INCM
(internally generated voltage)
15Ω
IN+
1.5pF
Sample
4pF
SP
(defines sampling instant)
All bias currents required for the internal operation of the
device are set using an external resistor to ground at pin
ISET. Using a 56kΩ resistor on ISET generates an internal
reference current of 20µA. This current is mirrored
internally to generate the bias current for the internal
blocks. Using a larger external resistor at ISET reduces the
reference bias current and thereby scales down the device
operating power. However, it is recommended that the
external resistor be within 10% of the specified value of
56k so that the internal bias margins for the various blocks
are proper.
Buffering the internal bandgap voltage also generates a
voltage called VCM, which is set to the midlevel of REFT
and REFB, and is accessible on a pin. The internal buffer
driving VCM has a drive of ±2mA. It is meant as a reference
voltage to derive the input common-mode in case the input
is directly coupled.
When using the internal reference mode, a resistor greater
than 2Ω should be added between the reference pins
(REFT and REFB) and the decoupling capacitor, as shown
in Figure 3.
1.7pF
SP
IN−
1.5pF
ADS5272
4pF
15Ω
Sample
REFT
SP
INCM
REFB
> 2Ω
> 2Ω
Figure 2. Input Circuitry
0.1µF
2.2µF
2.2µF
0.1µF
INPUT OVER-VOLTAGE RECOVERY
The differential full-scale input peak-to-peak supported by
the ADS5272 is 2V. For a nominal value of VCM (1.5V), INP
and INN can swing from 1V to 2V. The ADS5272 is
specially designed to handle an over-voltage differential
peak-to-peak voltage of 4V (2.5V and 0.5V swings on INP
and INN). If the input common-mode is not considerably off
from VCM during overload (less than 300mV), recovery
from an over-voltage input condition is expected to be
within 4 clock cycles. All of the amplifiers in the SHA and
ADC are specially designed for excellent recovery from an
overload signal.
REFERENCE CIRCUIT DESIGN
The digital beam-forming algorithm relies heavily on gain
matching across all receiver channels. A typical system
would have about 12 octal ADCs on the board. In such a
case, it is critical to ensure that the gain is matched,
essentially requiring the reference voltages seen by all the
ADCs to be the same. Matching references within the eight
channels of a chip is done by using a single internal
reference voltage buffer. Trimming the reference voltages
on each chip during production ensures the reference
voltages are well matched across different chips.
Figure 3. Internal Refernce Mode
The device also supports the use of external reference
voltages. This mode involves forcing REFT and REFB
externally. In this mode, the internal reference buffer is
tri-stated. Since the switching current for the eight ADCs
come from the externally forced references, it is possible
for the performance to be slightly less than when the
internal references are used. It should be noted that in this
mode, VCM and ISET continue to be generated from the
internal bandgap voltage, as in the internal reference
mode. It is therefore important to ensure that the
common-mode voltage of the externally forced reference
voltages matches to within 50mV of VCM.
CLOCKING
The eight channels on the chip run off a single ADCLK
input. To ensure that the aperture delay and jitter are same
for all the channels, a clock tree network is used to
generate individual sampling clocks to each channel. The
11
PRODUCT PREVIEW
SBAS324 − JUNE 2004
"#$%&%
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SBAS324 − JUNE 2004
PRODUCT PREVIEW
clock paths for all the channels are matched from the
source point all the way to the sample-and-hold. This
ensures that the performance and timing for all the
channels are identical. The use of the clock tree for
matching introduces an aperture delay, which is defined as
the delay between the rising edge of ADCLK and the actual
instant of sampling. The aperture delays for all the
channels are matched, and vary between 2.5ns to 4.5ns
across devices. Another critical spec is the aperture jitter
that is defined as the uncertainty of the sampling instant.
The gates in the clock path are designed so as to give an
rms jitter of about 1ps.
The input ADCLK should ideally have a 50% duty cycle.
However, while routing ADCLK to different components on
board, the duty cycle of the ADCLK reaching the ADS5272
could deviate from 50%. A smaller (or larger) duty cycle
eats into the time available for sample or hold phases of
each circuit, and is therefore not optimal. For this reason,
the internal PLL is used to generate an internal clock that
has 50% duty cycle.
The use of the PLL automatically dictates the lower
frequency of operation to be about 20MHz.
LVDS BUFFERS
The LVDS buffer has two current sources, as shown in
Figure 4. OUTP and OUTN are loaded externally by a
resistive load that is ideally about 100Ω. Depending on the
data being 0 or 1, the currents are directed in one or the
other direction through the resistor. The LVDS buffer has
four current settings. The default current setting is 3.5mA,
and gives a differential drop of about ±350mV across the
100Ω resistor.
High
External
Termination
Resistor
Low
OUTP
OUTN
Low
High
data rate output by the serializer is 480 MBPS. The data
comes out LSB first, with a register programmability to
revert to MSB first. The serializer also gives out a 1X clock
and a 6X clock. The 6X clock (denoted as LCLKP/ LCLKN)
is meant to synchronize the capture of the LVDS data. The
deskew mode can be enabled as well, using a register
setting. This mode gives out a data stream of alternate 0s
and 1s and can be used determine the relative delay
between the 6X clock and the output data for optimum
capture. A 1X clock is also generated by the serializer and
transmitted by the LVDS buffer. The 1X clock (referred to
as ADCLKP/ADCLK N) is used to determine the start of the
12-bit data frame. The sync mode (enabled through a
register setting) gives out a data of six 0s followed by six
1s. Using this mode, the 1X clock can be used to determine
the start of the data frame. In addition to the deskew mode
pattern and the sync pattern, a custom pattern can be
defined by the user and output from the LVDS buffer.
NOISE COUPLING ISSUES
High-speed mixed signals are sensitive to various types of
noise coupling. One of the main sources of noise is the
switching noise from the serializer and the output buffers.
Maximum care is taken to isolate these noise sources from
the sensitive analog blocks. As a starting point, the analog
and digital domains of the chip are clearly demarcated.
AVDD and AVSS are used to denote the supplies for the
analog sections, while LVDD and LVSS are used to denote
the digital supplies. Care is taken to ensure that there is
minimal interaction between the supply sets within the
device. The extent of noise coupled and transmitted from
the digital to the analog sections depends on the following:
1.
The effective inductances of each of the supply/ground
sets.
2.
The isolation between
supply/ground sets.
the
digital
and
analog
Smaller effective inductance of the supply/ground pins
leads to better suppression of the noise. For this reason,
multiple pins are used to drive each supply/ground. It is
also critical to ensure that the impedances of the supply
and ground lines on board are kept to the minimum
possible values. Use of ground planes in the board as well
as large decoupling capacitors between the supply and
ground lines are necessary to get the best possible SNR
from the device.
It is recommended that the isolation be maintained on
board by using separate supplies to drive AVDD and
LVDD, as well as separate ground planes for AVSS and
LVSS.
Figure 4. LVDS Buffer
The LVDS buffer gets data from a serializer that takes the
output data from each channel and serializes it into a
single data stream. For a clock frequency of 40MHz, the
12
The use of LVDS buffers reduces the injected noise
considerably, compared to CMOS buffers. The current in
the LVDS buffer is independent of the direction of
switching. Also, the low output swing as well as the
differential nature of the LVDS buffer results in low-noise
coupling.
"#$%&%
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SBAS324 − JUNE 2004
The ADS5272 has a power-down pin, PD. Pulling PD high
causes the devices to enter the power-down mode. In this
mode, the reference and clock circuitry as well as all the
channels are powered down. Device power consumption
drops to less than 100mW in this mode. Individual
channels can also be selectively powered down by
programming registers.
The ADS5272 also has an internal circuit that monitors the
state of stopped clocks. If ADCLK is stopped (or if it runs
at a speed < 3MHz), this monitoring circuit generates a
logic signal that puts the device in a power-down state. As
a result, the power consumption of the device goes to less
than 100mW when ADCLK is stopped. This circuit can
also be disabled using register options.
SUPPLY SEQUENCE
The following supply sequence is recommended for
powering up the device:
1.
AVDD is powered up.
2.
LVDD is powered up.
After the supplies have stabilized, it is required to give the
device an active RESET pulse. This results in all internal
registers getting reset to their default value of 0 (inactive).
Without RESET, it is possible that some registers might be
in their non-default state on power-up. This could cause
the device to malfunction.
LAYOUT OF PCB WITH
PowerPAD THERMALLYENHANCED PACKAGES
The ADS5272 is housed in an 80-lead PowerPAD
thermally-enhanced package. To make optimum use of
the thermal efficiencies designed into the PowerPAD
package, the PCB must be designed with this technology
in mind. Please refer to SLMA004 PowerPAD brief
PowerPAD Made Easy (refer to our web site at
www.ti.com), which addresses the specific considerations
required when integrating a PowerPAD package into a
PCB design. For more detailed information, including
thermal modeling and repair procedures, please see
SLMA002 technical brief PowerPAD Thermally Enhanced
Package (www.ti.com).
13
PRODUCT PREVIEW
POWER-DOWN MODE
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ADS5272IPFP
PREVIEW
HTQFP
PFP
80
ADS5272IPFPT
PREVIEW
HTQFP
PFP
80
96
Lead/Ball Finish
MSL Peak Temp (3)
TBD
Call TI
Call TI
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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