WM8234 w 70MSPS 6-Channel AFE with Sensor Timing Generation and LVDS/CMOS Data Output DESCRIPTION FEATURES The WM8234 is a 16-bit analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors (CIS) at pixel sample rates of up to 23MSPS. 70MSPS conversion rate 16 bit ADC resolution Current consumption – 280mA 3.3V single supply operation Sample and hold /correlated double sampling Programmable offset adjust (8-bit resolution) Flexible clamp timing Pixel clamp / line clamp mode Programmable clamp voltage Programmable CIS/CCD timing generator Internally generated voltage references Compliant for Spread Spectrum Clock LVDS/CMOS output options The device has six analogue signal processing channels each of which contains Reset Level Clamping, Correlated Double Sampling (also Sample and Hold), Programmable Gain, Automatic Gain Control (AGC) and Offset adjust functions. The output from each of these channels is time multiplexed, in pairs, into two high-speed 16-bit Analogue to Digital Converters. The digital data is available in a variety of output formats via the flexible data port. The WM8234 has a user selectable LVDS or CMOS output architecture. An internal 8-bit DAC is supplied for internal reference level generation. This may be used during CDS to reference CIS signals or during Clamping to clamp CCD signals. An external reference level may also be supplied. ADC references are generated internally, ensuring optimum performance from the device. A programmable automatic Black-Level Calibration function is available to adjust the DC offset of the output data. The WM8234 features a sensor timing clock generator for both CCD and CIS sensors. The clock generator can accept a slow or fast reference clock input and also has a flexible timing adjustment function for output timing clocks to allow use of many different sensors. LVDS 5pair 490MHz 35-bit data CMOS 90MHz output maximum Complete on chip clock generator. MCLK 5MHz to 23MHz Internal timing adjustment Automatic Gain Control Automatic Black Level Calibration 56-lead QFN package 7mm x 7mm Serial control interface APPLICATIONS Digital copiers USB2.0 compatible scanners Multi-function peripherals High-speed CCD/CIS sensor interface WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews Product Brief, February 2012, Rev 3.0 Copyright 2012 Wolfson Microelectronics plc. WM8234 Product Brief w TGSYNC CLK9 CLK10 CLK11 CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 CLK1 CLK2 BLOCK DIAGRAM Product Brief, Rev 3.0, February 2012 2 Product Brief WM8234 TABLE OF CONTENTS DESCRIPTION ....................................................................................................... 1 FEATURES ............................................................................................................ 1 APPLICATIONS..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................ 2 TABLE OF CONTENTS ......................................................................................... 3 PIN CONFIGURATION .......................................................................................... 4 ORDERING INFORMATION .................................................................................. 4 PIN DESCRIPTION ................................................................................................ 5 ABSOLUTE MAXIMUM RATINGS ........................................................................ 7 RECOMMENDED OPERATING CONDITIONS ..................................................... 7 ELECTRICAL CHARACTERISTICS ..................................................................... 8 GENERAL CHARACTERISTICS ..................................................................................... 9 APPLICATIONS INFORMATION ........................................................................ 11 RECOMMENDED EXTERNAL COMPONENTS ........................................................... 11 RECOMMENDED EXTERNAL COMPONENT VALUES .............................................. 12 PACKAGE DIMENSIONS .............................................................................................. 13 IMPORTANT NOTICE ......................................................................................... 14 ADDRESS: .................................................................................................................... 14 REVISION HISTORY ........................................................................................... 15 w Product Brief, Rev 3.0, February 2012 3 WM8234 Product Brief 46 AGND3 49 48 47 CLK10 51 50 CLK9 IN3 52 CLK11 IN4 53 AGND2 IN5 54 AVDD2 IN6 55 IN1 AVDD1 56 IN2 AGND1 PIN CONFIGURATION 45 44 43 VREF2C 1 42 CLK8 VRLC/VBIAS 2 41 CLK7 VREF3C 3 40 CLK6 VREF1C 4 39 CLK5 SEN 5 38 CLK4 SDO 6 37 CLK3 SCK 7 36 CLK2 WM8234 SDI 8 35 CLK1 LDO2VDD 9 34 TGSYNC LDO2GND 10 33 LDOV1DD LDO2VOUT 11 32 LDO1GND DSLCT2 12 31 LDO1VOUT 30 MON MCLK 13 29 HZCTRL 15 16 17 18 19 20 21 22 23 24 25 26 27 28 D5N/OP10 D5P/OP9 D4N/OP8 D4P/OP7 DCLKN/OC2 DCLKP/OC1 DBGND DBVDD D3N/OP6 D3P/OP5 D2N/OP4 D2P/OP3 D1N/OP2 D1P/OP1 DSLCT1 14 ORDERING INFORMATION DEVICE TEMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE 56-lead QFN WM8234GEFL/V o -40 to 85 C (7X7x0.85mm) MSL3 260C MSL3 260C (Pb-free) 56-lead QFN WM8234GEFL/RV o -40 to 85 C (7X7x0.85mm) (Pb-free, tape and reel) Reel quantity = 2,200 w Product Brief, Rev 3.0, February 2012 4 Product Brief WM8234 PIN DESCRIPTION PIN NAME Type 1 VREF2C Analogue output DESCRIPTION Mid reference voltage. This pin must be connected to AGND via a decoupling capacitor. Reference voltage input/output 2 VRLC Analogue I/O 3 VREF3C Analogue output Lower reference voltage. This pin must be connected to AGND via a decoupling capacitor. 4 VREF1C Analogue output Upper reference voltage. This pin must be connected to AGND via a decoupling capacitor. Enables the serial interface when high. 5 SEN Digital input 6 SDO Digital output 7 SCK Digital input Serial interface clock 8 SDI Digital input Serial interface data input 9 LDO2VDD Supply Analogue supply 10 LDO2GND Supply Analogue ground 11 LDO2VOUT Supply LDO output 12 DSLCT2 Analogue input Device select 2 13 MCLK Analogue input Master clock 14 DSLCT1 Analogue input Device select 1 15 D5N/OP[9] LVDS output LVDS Data output 5 – Negative / CMOS output 11 16 D5P/OP[8] LVDS output LVDS Data output 5 – Positive / CMOS output 10 17 D4N/OP[7] LVDS output LVDS Data output 4 – Negative / CMOS output 9 18 D4P/OP[6] LVDS output LVDS Data output 4 – Positive / CMOS output 8 19 DCLKN/OC[2] LVDS output LVDS Clock Output – Negative/ CMOS clock output 2 20 DCLKP/OC[1] LVDS output LVDS Clock Output – Positive/ CMOS clock output 1 21 DBGND Supply Analogue ground 22 DBVDD Supply Analogue supply 23 D3N/OP[5] LVDS output LVDS Data output 3 – Negative / CMOS output 5 24 D3P/OP[4] LVDS output LVDS Data output 3 – Positive / CMOS output 4 25 D2N/OP[3] LVDS output LVDS Data output 2 – Negative / CMOS output 3 26 D2P/OP[2] LVDS output LVDS Data output 2 – Positive / CMOS output 2 27 D1N/OP[1] LVDS output LVDS Data output 1 – Negative / CMOS output 1 28 D1P/OP[0] LVDS output LVDS Data output 1 – Positive / CMOS output 0 29 HZCTRL Digital input Internal use only. Must be connected to AGND. 30 MON Analogue output 31 LDO1VOUT Supply Serial interface data output This pin must be connected to AGND via a decoupling capacitor. Clock monitor LDO output. This pin must be connected to AGND via a decoupling capacitor. Supply Analogue ground LDO1VDD Supply Analogue supply TGSYNC Digital input 35 CLK1 Digital output Sensor Timing Output 1 36 CLK2 Digital output Sensor Timing Output 2 37 CLK3 Digital output Sensor Timing Output 3 38 CLK4 Digital output Sensor Timing Output 4 39 CLK5 Digital output Sensor Timing Output 5 40 CLK6 Digital output Sensor Timing Output 6 41 CLK7 Digital output Sensor Timing Output 7 42 CLK8 Digital output Sensor Timing Output 8 43 AGND3 Supply 44 CLK9 Digital output Sensor Timing Output 9 45 CLK10 Digital output Sensor Timing Output 10 46 CLK11 Digital output Sensor Timing Output 11 47 AGND2 Supply 32 LDO1GND 33 34 w Sensor Timing Sync pulse from host Analogue ground Analogue ground Product Brief, Rev 3.0, February 2012 5 WM8234 Product Brief PIN NAME Type DESCRIPTION 48 AVDD2 Supply Analogue supply 49 IN1 Analogue input Analogue input 1 50 IN2 Analogue input Analogue input 2 51 IN3 Analogue input Analogue input 3 52 IN4 Analogue input Analogue input 4 53 IN5 Analogue input Analogue input 5 54 IN6 Analogue input Analogue input 6 55 AVDD1 Supply Analogue supply 56 AGND1 Supply Analogue ground w Product Brief, Rev 3.0, February 2012 6 Product Brief WM8234 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION MIN MAX Analogue supply voltage: AVDD1-2, LDO1VDD-LDO2VDD, DBVDD GND - 0.3V Analogue grounds: AGND1-3, LDO1GND-LDO2GND, DBGND GND - 0.3V GND + 0.3V Analogue inputs (IN1-6) GND - 0.3V AVDD + 0.3V Other Analogue pins GND - 0.3V AVDD + 0.3V Digital I/O pins GND - 0.3V AVDD + 0.3V GND + 5V -40C Operating temperature range: TA +85C 30C max / 85% RH max Storage temperature prior to soldering -65C Storage temperature after soldering +150C Notes: 1. 2. GND denotes the voltage of any ground pin. AGND, LDOGND and DBGND pins are intended to be operated at the same potential. Differential voltages between these pins will degrade performance. RECOMMENDED OPERATING CONDITIONS CONDITION Operating temperature range Analogue Supply voltage SYMBOL MIN TA -40 AVDD1-2 2.97 TYP 3.3 MAX UNITS 85 C 3.63 V LDO1VDDLDO2VDD DBVDD w Product Brief, Rev 3.0, February 2012 7 WM8234 Product Brief ELECTRICAL CHARACTERISTICS Test Conditions AVDD = LDOVDD = DBVDD = 3.3V , AGND = LDOGND = DBGND= 0V, TA = 25C, MCLK= 23.3MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT 23.3 MSPS Overall System Specification (including 10-bit ADC, PGA, Offset and CDS functions) Conversion rate per channel 5 Full-scale input voltage range ADCFS=0, Max Gain 0.12 Vp-p (see Note 1) ADCFS=0, Min Gain 2.0 Vp-p ADCFS=1, Max Gain 0.18 Vp-p ADCFS=1, Min Gain 3.0 Vp-p Input signal limits (see Note 2) Input capacitance VIN CIN Full-scale transition error SF_INP=0 AGND-0.3 AVDD+0.3 SF_INP=1 AGND AGND+1.2 V V Inputs to AGND 10 pF Gain = 0dB; AGAIN[4:0] = 02(hex) 20 mV 20 mV DGAIN[11:0] = 6AB(hex) Zero-scale transition error Gain = 0dB; AGAIN[4:0] = 02(hex) DGAIN[11:0] = 6AB(hex) Differential non-linearity DNL 10-bit 0.5 LSB Integral non-linearity (pk-pk/2) INL 10-bit 1 LSB Min Gain 5 % Max Gain 15 % 0.3 LSB rms +/-0.5 LSB Channel to channel gain matching Output noise Unity Gain (Unused channels grounded) Channel to channel crosstalk 10-bit Programmable Gain Amplifier Total Resolution (Ga + Gd) GT 12 bits Analogue Gain Ga 0.6 + 0.3 * AGAIN[4:0] V/V V/V Max gain, each channel (Ga) Ga MAX AGAIN[4:0] = 1F(hex) 9.9 Min gain, each channel (Ga) Ga MIN AGAIN[4:0] = 0(hex) 0.6 Digital Gain Gd DGAIN[11:0] / 2 V/V 11 V/V Max gain, each channel (Gd) Gd MAX DGAIN[11:0] = FFF(hex) Min gain, each channel (Gd) Gd MIN DGAIN[11:0] = 400 (hex) 0.5 V/V Max gain, each channel GTMAX AGAIN[4:0] = 1F(hex) 19.8 V/V 0.3 V/V (Ga + Gd) Min gain, each channel (Ga + Gd) 2 V/V DGAIN[11:0] = FFF(hex) GTMIN AGAIN[4:0] = 0(hex) DGAIN[11:0] = 400 (hex) Analogue to Digital Converter Resolution 16 Speed bits 70 MSPS Notes: 1. Full-scale input voltage denotes the differential input signal amplitude (VIN-VRLC in non-CDS mode, VIN-RESET level in CDS mode) that can be gained to match the ADC full-scale input range. 2. Input signal limits are the limits within which each input voltage and VRLC reference must lie. w Product Brief, Rev 3.0, February 2012 8 Product Brief WM8234 GENERAL CHARACTERISTICS Test Conditions AVDD = LDOVDD = DBVDD = 3.3V , AGND = LDOGND = DBGND= 0V, TA = 25C, MCLK= 23.3MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT References Upper reference voltage Lower reference voltage Input return bias voltage Diff. Reference voltage (VREF1CVREF3C) VREF1C VREF3C ADCFS=0 2.05 V ADCFS=1 2.25 V ADCFS=0 1.25 V ADCFS=1 1.05 V 1.2 V ADCFS=0 0.8 V ADCFS=1 1.2 V 1 VREF2C VREF1C3C Output resistance VREF1C, VREF3C, VREF2C VRLC/Reset-Level Clamp (RLC) RLC switching impedance 50 RLC short-circuit current 2 mA RLC output resistance 2 RLC Hi-Z leakage current VRLC = 0 to AVDD 1 RLCDAC resolution A 5 bits VRLC_TOP_SEL=0 0.09 V/step VRLCSTEP VRLC_TOP_SEL=1 0.048 V/step VRLCBOT VRLC_TOP_SEL=0, 0.2 V 0.11 V 3.0 V 1.6 V VRLC DNL +/- 0.5 LSB VRLC INL +/- 0.5 LSB RLCDAC step size RLCDAC output voltage at code 0(hex) VRLCSTEP VRLC_VSEL[4:0]=00000 VRLCBOT VRLC_TOP_SEL=1, VRLC_VSEL[4:0]=00000 RLCDAC output voltage at code 1F(hex) VRLCTOP VRLC_TOP_SEL=0, VRLC_VSEL[4:0]=11111 VRLCTOP VRLC_TOP_SEL=1, VRLC_VSEL[4:0]=11111 Offset DAC, Monotonicity Guaranteed Resolution Differential non-linearity DNL Integral non-linearity INL Step size Output voltage 8 bits 0.1 LSB 0.75 LSB 2.04 mV/step Code 00(hex) -250 mV Code FF(hex) +250 mV DIGITAL SPECIFICATIONS Digital Inputs High level input voltage VIH Low level input voltage VIL High level input current Low level input current Input capacitance CI w 0.7 AVDD V 0.2 AVDD V IIH 1 A IIL 1 A 5 pF Product Brief, Rev 3.0, February 2012 9 WM8234 Product Brief Test Conditions AVDD = LDOVDD = DBVDD = 3.3V , AGND = LDOGND = DBGND= 0V, TA = 25C, MCLK= 23.3MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN High level output voltage VOH IOH = 6mA AVDD – 0.5 Low level output voltage VOL IOL = 1mA High impedance output current IOZ TYP MAX UNIT CMOS Outputs V 0.5 V 1 A TG Outputs High level output voltage VOHTG Low level output voltage VOLTG IOL = 1mA 0.5 V High impedance output current IOZTG Grounded 1 A IOH = 1mA AVDD – 0.5 V Digital IO Pins 0.7 AVDD Applied high level input voltage VIH Applied low level input voltage VIL High level output voltage VOH IOH = 1mA Low level output voltage VOL IOL = 1mA Low level input current IIL High level input current IIH Input capacitance CI Output Impedance Ro High impedance output current IOZ V 0.2 AVDD AVDD – 0.5 V 0.5 V 1 A 1 A 5 Io = 1mA V pF 38 Ω 1 A 110 Ω 450 mV 15 mV LVDS Outputs Differential load impedance Differential steady-state output voltage magnitude 90 RL |VOD| RL=100Ω Change in the steady-state differential output voltage magnitude between opposite binary states Δ|VOD| RL=100Ω Steady-state common-mode output voltage VOC(SS) Peak-to-peak common-mode output VOC(PP) 100 280 RL=100Ω 1.25 20 V 50 mV Short-circuit output current IOS –6 6 mA High-impedance state output current IOZ –10 10 uA Supply Currents Total supply current full power down mode SF_INP=0, SF_VRLC=0 280 SF_INP=1, SF_VRLC=1 320 mA mA 1.0 mA Notes: 1. 2. Full-scale input voltage denotes the differential input signal amplitude (VIN-VRLC in non-CDS mode, VIN-RESET level in CDS mode) that can be gained to match the ADC full-scale input range. Input signal limits are the limits within which each input voltage and VRLC reference must lie. w Product Brief, Rev 3.0, February 2012 10 Product Brief WM8234 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS AVDD1 AVDD2 DBVDD LDO1VDD LDO2VDD 55 48 C1 22 C2 C3 33 9 C4 AGND1 AGND2 AVDD1 AGND3 56 47 43 AVDD2 LDO1VDD VREF1C 4 VREF2C 1 LDO2VDD VREF3C 3 DBVDD 2 C11 49 50 51 52 53 54 C6 IN1 IN2 IN3 IN4 IN5 IN6 MCLK 34 7 5 14 12 LDO2VOUT 31 C12 SDI SCK SEN DSLCT1 DSLCT2 C13 C14 AGND D1P/OP[0] D1N/OP[1] D2P/OP[2] D2N/OP[3] D3P/OP[4] D3N/OP[5] DCLKP/OC[1] DCLKN/OP[2] D4P/OP[6] D4N/OP[7] D5P/OP[8] D5N/OP[9] TGSYNC AVDD1 AVDD2 DBVDDLDO1VDD LDO2VDD 11 WM8234 13 8 LDO1VOUT VRLC/VBIAS AGND Interface Controls C7 C10 AGND AGND Timing Signals C9 C8 C5 Video Inputs AGND CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 CLK9 CLK10 CLK11 28 27 26 25 24 23 20 19 18 17 16 15 35 36 37 38 39 40 41 42 44 45 46 C15 C16 C17 C18 AGND LDO1VOUT Output Data Bus C19 LDO2VOUT C20 AGND Timing generator Outputs NOTES: 1. C1-20 should be fitted as close to device as possible. 2. AGND should be connected as close to device as possible. Figure 1 External Components Diagram w Product Brief, Rev 3.0, February 2012 11 WM8234 Product Brief RECOMMENDED EXTERNAL COMPONENT VALUES COMPONENT REFERENCE SUGGESTED VALUE DESCRIPTION C1 0.1uF C2 0.1uF De-coupling for AVDD2 C3 0.1uF De-coupling for DBVDD C4 0.1uF De-coupling for LDO1VDD C5 0.1uF De-coupling for LDO2VDD C6 0.1uF De-coupling for VREF1C C7 0.1uF De-coupling for VREF2C C8 0.1uF De-coupling for VREF3C C9 0.01uF High frequency decoupling between VREF1C and VREF3C C10 10uF Low frequency decoupling between VREF1C and VREF3C C11 1uF De-coupling for VRLC/VBIAS De-coupling for AVDD1 C12 1uF De-coupling for LDO1VOUT C13 1uF De-coupling for LDO2VOUT C14 10uF Reservoir capacitor for AVDD1 C15 10uF Reservoir capacitor for AVDD2 C16 10uF Reservoir capacitor for DBVDD C17 10uF Reservoir capacitor for LDO1VDD C18 10uF Reservoir capacitor for LDO2VDD C19 10uF Reservoir capacitor for LDOOUT C20 10uF Reservoir capacitor for LDOOUT Table 1 External Components Description w Product Brief, Rev 3.0, February 2012 12 Product Brief WM8234 PACKAGE DIMENSIONS DM092.B FL: 56 PIN QFN PLASTIC PACKAGE 7 X 7 X 0.85 mm BODY, 0.40 mm LEAD PITCH D2 eee C B A A PIN 1 D2/2 D B 56 43 L INDEX AREA (D/2 X E/2) 1 36 EXPOSED 6 GND PADDLE E2/2 E2 eee C B A 29 14 28 b e TOP VIEW bbb C A2 A A1 SEATING PLANE ccc C M Symbols aaa bbb ccc ddd eee REF aaa C 2X ddd M C A B M A A1 A2 A3 b D D2 E E2 e L aaa C 2X 15 (A3) C E MIN 0.8 0 0.15 5.10 5.10 0.35 Dimensions (mm) NOM MAX 0.85 0.9 0.05 0.035 0.65 0.67 0.203 REF 0.2 0.25 7.00 BSC 5.20 5.30 7.00 BSC 5.20 5.30 0.4 BSC 0.45 0.4 NOTE 1 Tolerances of Form and Position 0.10 0.10 0.08 0.10 0.10 JEDEC, MO-220, VARIATION VKKE NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP. 2. ALL DIMENSIONS ARE IN MILLIMETRES 3. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-002. 4. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 5. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 6. REFER TO APPLICATIONS NOTE WAN_0118 FOR FURTHER INFORMATION. w Product Brief, Rev 3.0, February 2012 13 WM8234 Product Brief IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: [email protected] w Product Brief, Rev 3.0, February 2012 14 Product Brief WM8234 REVISION HISTORY REV ORIGINATOR 22/11/10 DATE 1.0 NB CHANGES First Release 20/02/12 3.0 JMacD Current consumption updated to 280mA DAC description updated from 4-bit to 8-bit Temperature range updated to -40 Updated ADCFS characteristics Updated RLC DAC resolution Updated parameter name and register name for RLC DAC Added test condition for TG output Updated Supply currents 29/02/12 3.0 JMacD w Recommended External Component Values – C9 value updated to 0.01uF Product Brief, Rev 3.0, February 2012 15