DAC8801 SLAS403A – NOVEMBER 2004 – REVISED DECEMBER 2004 14-Bit, Serial Input Multiplying Digital-to-Analog Converter FEATURES • • • • • • • • • • • • • • • 14-Bit Monotonic ±1 LSB INL ±0.5 LSB DNL Low Noise: 12 nV/√Hz Low Power: IDD = 2 µA +2.7 V to +5.5 V Analog Power Supply 2 mA Full-Scale Current ±20% with VREF = 10 V 0.5 µs Settling Time 4-Quadrant Multiplying Reference-Input Reference Bandwidth: 10 MHz ±10 V Reference Input Reference Dynamics: -105 THD 3-Wire 50-MHz Serial Interface Tiny 8-Lead 3 x 3 mm SON and 3 x 5 mm MSOP Packages Industry-Standard Pin Configuration APPLICATIONS • • • • Automatic Test Equipment Instrumentation Digitally Controlled Calibration Industrial Control PLCs DESCRIPTION The DAC8801 multiplying digital-to-analog converter is designed to operate from a single 2.7-V to 5.5-V supply. The applied external reference input voltage VREF determines the full-scale output current. An internal feedback resistor (RFB) provides temperature tracking for the full-scale output when combined with an external I-to-V precision amplifier. A serial-data interface offers high-speed, three-wire microcontroller compatible inputs using data-in (SDI), clock (CLK), and chip select (CS). The DAC8801 is packaged in space-saving 8-lead SON and MSOP packages. DAC8801 VDD VREF D/A Converter RFB IOUT 14 CS DAC Register 14 CLK SDI Shift Register GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated DAC8801 www.ti.com SLAS403A – NOVEMBER 2004 – REVISED DECEMBER 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) PRODUCT MINIMUM RELATIVE ACCURACY (LSB) DIFFERENTIAL NONLINEARITY (LSB) PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER DAC8801 ±1 ±0.5 MSOP-8 DGK -40°C to +85°C F01 DAC8801IDGKT Tape and Reel, 250 DAC8801 ±1 ±0.5 MSOP-8 DGK -40°C to +85°C F01 DAC8801IDGKR Tape and Reel, 2500 DAC8801 ±1 ±0.5 SON-8 DRB -40°C to +85°C E01 DAC8801IDRBT Tape and Reel, 250 DAC8801 ±1 ±0.5 SON-8 DRB -40°C to +85°C E01 DAC8801IDRBR Tape and Reel, 2500 (1) TRANSPORT MEDIA, QUANTITY For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or refer to our web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) DAC8801 UNITS -0.3 to +7 V Digital Input voltage to GND -0.3 to +VDD + 0.3 V VOUT to GND -0.3 to +VDD + 0.3 V Operating temperature range -40 to +105 °C Storage temperature range -65 to +150 °C +125 °C VDD to GND Junction temperature range (TJ max) Power dissipation Thermal impedance, RΘJA (TJ max - TA) / RΘJA W +55 °C/W Lead temperature, soldering Vapor phase (60s) +215 °C Lead temperature, soldering Infrared (15s) +220 °C ESD rating, HBM 1500 V ESD rating, CDM 1000 V (1) 2 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. DAC8801 www.ti.com SLAS403A – NOVEMBER 2004 – REVISED DECEMBER 2004 ELECTRICAL CHARACTERISTICS VDD = +2.7 V to +5.5 V; IOUT = Virtual GND, GND = 0 V; VREF = 10 V; TA = Full Operating Temperature; all specifications -40°C to +85°C unless otherwise noted. DAC8801 PARAMETER CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution 14 Bits Relative accuracy Differential nonlinearity Output leakage current Data = 0000h, TA = 25°C Output leakage current Data = 0000h, TA = TMAX Full-scale gain error All ones loaded to DAC register ±1 Full-scale tempco OUTPUT ±1 LSB ±0.5 LSB 10 nA 10 nA ±4 mV ±3 ppm of FSR/°C 2 mA 50 pF CHARACTERISTICS (1) Output current Output capacitance Code dependent REFERENCE INPUT VREF Range -15 Input resistance Input capacitance LOGIC INPUTS AND 15 V 5 kΩ 5 pF OUTPUT (1) Input low voltage VIL VDD = +2.7V 0.6 V Input low voltage VIL VDD = +5V 0.8 V Input high voltage VIH VDD = +2.7V 2.1 Input high voltage VIH VDD = +5V 2.4 Input leakage current Input capacitance V V IIL 10 µA CIL 10 pF 50 MHz INTERFACE TIMING Clock input frequency fCLK Clock pulse width high 10 ns Clock pulse width low 10 ns CS to Clock setup time 0 ns Clock to CS hold time 10 ns Data setup time 5 ns Data hold time 10 ns POWER REQUIREMENTS VDD 2.7 5.5 V IDD (normal operation) Logic inputs = 0 V 5 µA VDD = +4.5V to +5.5V VIH = VDD and VIL = GND 3 5 µA VDD = +2.7V to +3.6V VIH = VDD and VIL = GND 1 2.5 µA AC CHARACTERISTICS Output voltage settling time Reference multiplying BW VREF = 5 VPP, Data = 3FFFh DAC glitch impulse VREF = 0 V, Data = 3FFFh to 2000h Feedthrough error VREF = 100 mVRMS, 100kHz, Data = 0000h Digital feedthrough Total harmonic distortion 100Hz to 20kHz Output spot noise voltage f = 1 kHz, BW = 1 Hz (1) 0.5 µs 10 MHz 2 nV/s -70 dB 2 nV/s -105 dB 12 nV/√Hz Specified by design and characterization, not production tested. 3 DAC8801 www.ti.com SLAS403A – NOVEMBER 2004 – REVISED DECEMBER 2004 PIN ASSIGNMENTS DGK PACKAGE (TOP VIEW) DRB PACKAGE (TOP VIEW) CLK 1 8 CS CLK 1 8 CS SDI 2 7 VDD SDI 2 7 RFB 3 6 GND VDD VREF 4 5 IOUT RFB 3 6 GND VREF 4 5 IOUT TERMINAL FUNCTIONS 4 PIN NAME 1 CLK Clock input, positive edge triggered clocks data into shift register DESCRIPTION 2 SDI Serial register input, data loads directly into the shift register MSB first. Extra leading bits are ignored. 3 RFB Internal matching feedback resistor. Connect to external op amp output. 4 VREF DAC reference input pin. Establishes DAC full-scale voltage. Constant input resistance versus code. 5 IOUT DAC current output. Connects to inverting terminal of external precision I to V op amp. 6 GND Analog and digital ground 7 VDD Posiitve power supply input. Specified range of operation 2.7 V to 5.5 V. 8 CS Chip select, active low digital input. Transfers shift register data to DAC register on rising edge. See Table 1 for operation. DAC8801 www.ti.com SLAS403A – NOVEMBER 2004 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS: VDD = +5 V At TA = +25°C, +VDD = +5 V, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 1.0 TA = +25 C 0.6 0.6 0.4 0.4 0.2 0 −0.2 0.2 0 −0.2 −0.4 −0.4 −0.6 −0.6 −0.8 −0.8 −1.0 −1.0 0 1.0 2048 4096 0 6144 8192 10240 12288 14336 16384 Digital Input Code 2048 4096 Figure 2. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 TA = −40C 0.8 0.6 0.4 0.4 DNL (LSB) 0.6 0.2 0 −0.2 0.2 0 −0.2 −0.4 −0.4 −0.6 −0.6 −0.8 −0.8 −1.0 −1.0 0 2048 4096 6144 8192 10240 12288 14336 16384 0 2048 4096 Digital Input Code Figure 4. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 TA = +85 C 0.8 6144 8192 10240 12288 14336 16384 Digital Input Code Figure 3. 1.0 TA = +85 C 0.8 0.6 0.6 0.4 0.4 DNL (LSB) INL (LSB) 6144 8192 10240 12288 14336 16384 Digital Input Code Figure 1. TA = −40C 0.8 INL (LSB) TA = +25 C 0.8 DNL (LSB) INL (LSB) 0.8 0.2 0 −0.2 0.2 0 −0.2 −0.4 −0.4 −0.6 −0.6 −0.8 −0.8 −1.0 −1.0 0 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Figure 5. 0 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Figure 6. 5 DAC8801 www.ti.com SLAS403A – NOVEMBER 2004 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS: VDD = +5 V (continued) At TA = +25°C, +VDD = +5 V, unless otherwise noted. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE REFERENCE BANDWIDTH 1.6 6 0 −6 −12 −18 −24 −30 −36 −42 −48 −54 −60 −66 −72 −78 −84 −90 −96 −102 −108 −114 VDD = +5.0V 1.2 Attenuation (dB) Supply Current, IDD (mA) 1.4 1.0 0.8 0.6 0.4 0.2 VDD = +2.7V 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 10 1k 10k 100k Figure 7. Figure 8. DAC SETTLING TIME DAC GLITCH Voltage Output Settling Trigger Pulse Time (0.1µs/div) Figure 9. 6 100 1M 10M Bandwidth (Hz) Output Voltage (50mV/div) Output Voltage (5V/div) Logic Input Voltage (V) Code: 3FFFh to 2000h Trigger Pulse Time (0.2µs/div) Figure 10. 100M DAC8801 www.ti.com SLAS403A – NOVEMBER 2004 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS: VDD = +2.7V At TA = +25°C, +VDD = +2.7V, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 TA = +25 C 0.8 0.6 0.6 0.4 0.4 DNL (LSB) INL (LSB) 1.0 TA = +25 C 0.8 0.2 0 −0.2 0.2 0 −0.2 −0.4 −0.4 −0.6 −0.6 −0.8 −0.8 −1.0 −1.0 0 2048 4096 6144 8192 10240 12288 14336 16384 0 2048 4096 Digital Input Code 1.0 Figure 12. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 0.6 0.6 0.4 0.4 0.2 0 −0.2 0.2 0 −0.2 −0.4 −0.4 −0.6 −0.6 −0.8 −0.8 −1.0 −1.0 0 2048 4096 0 6144 8192 10240 12288 14336 16384 Digital Input Code 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Figure 13. Figure 14. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 1.0 TA = +85 C 0.8 TA = +85 C 0.8 0.6 0.6 0.4 0.4 DNL (LSB) INL (LSB) TA = −40C 0.8 DNL (LSB) INL (LSB) Figure 11. TA = −40C 0.8 6144 8192 10240 12288 14336 16384 Digital Input Code 0.2 0 −0.2 0.2 0 −0.2 −0.4 −0.4 −0.6 −0.6 −0.8 −0.8 −1.0 −1.0 0 2048 4096 6144 8192 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Digital Input Code Figure 15. Figure 16. 7 DAC8801 www.ti.com SLAS403A – NOVEMBER 2004 – REVISED DECEMBER 2004 THEORY OF OPERATION The DAC8801 is a single channel current output, 16-bit digital-to-analog converter (DAC). The architecture, illustrated in Figure 17, is an R-2R ladder configuration with the three MSBs segmented. Each 2R leg of the ladder is either switched to GND or the IOUT terminal. The IOUT terminal of the DAC is held at a virtual GND potential by the use of an external I/V converter op amp. The R-2R ladder is connected to an external reference input VREF that determines the DAC full-scale current. The R-2R ladder presents a code independent load impedance to the external reference of 5 kΩ± 25%. The external reference voltage can vary in a range of -10 V to 10 V, thus providing bipolar IOUT current operation. By using an external I/V converter and the DAC8801 RFB resistor, output voltage ranges of -VREF to VREF can be generated. When using an external I/V converter and the DAC8801 RFB resistor, the DAC output voltage is given by Equation 1: V OUT −VREF CODE 16384 (1) R R R VREF 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R RFB IOUT GND Figure 17. Equivalent R-2R DAC Circuit Each DAC code determines the 2R leg switch position to either GND or IOUT. Because the DAC output impedance as seen looking into the IOUT terminal changes versus code, the external I/V converter noise gain will also change. Because of this, the external I/V converter op amp must have a sufficiently low offset voltage such that the amplifier offset is not modulated by the DAC IOUT terminal impedance change. External op amps with large offset voltages can produce INL errors in the transfer function of the DAC8801 due to offset modulation versus DAC code. For best linearity performance of the DAC8801, an op amp (OPA277) as shown in Figure 18 is recommended. This circuit allows VREF to swing from -10V to +10V. VDD U1 VDD VREF DAC8801 RFB U2 15 V IOUT _ V+ OPA277 GND + V− −15 V Figure 18. Voltage Output Configuration 8 VO DAC8801 www.ti.com SDI SLAS403A – NOVEMBER 2004 – REVISED DECEMBER 2004 D13 D12 D11 D10 D9 D8 D7 D6 D1 D0 CLK t(DS) t(CH) t(CL) t(DH) t(CSS) t(CSH) CS Figure 19. DAC8801 Timing Diagram Table 1. Control Logic Truth Table (1) (1) CLK CS Serial Shift Register DAC Register X H No effect Latched ↑+ L Shift register data advanced one bit Latched X H No effect Latched X ↑+ Shift register data transferred to DAC register New data loaded from serial register ↑+ Positive logic transition; X = Don't care Table 2. Serial Input Register Data Format, Data Loaded MSB First Bit B13 (MSB) B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 (LSB) Data (1) D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (1) A full 16-bit data word can be loaded into the serial register, but only the last 14 bits are transferred to the DAC register when CS goes high. 9 DAC8801 www.ti.com SLAS403A – NOVEMBER 2004 – REVISED DECEMBER 2004 APPLICATION INFORMATION Stability Circuit For a current-to-voltage design as shown in Figure 20, the DAC8801 current output (IOUT) and the connection with the inverting node of the op amp should be as short as possible and according to correct PCB layout design. For each code change there is a step function. If the GBP of the op amp is limited and parasitic capacitance is excessive at the inverting node then gain peaking is possible. Therefore, for circuit stability, a compensation capacitor C1 (4 pF to 20 pF typ) can be added to the design as shown in Figure 20. VDD VDD VREF RFB _ IOUT U1 VREF C1 U2 VOUT + GND Figure 20. Gain Peaking Prevention Circuit With Compensation Capacitor Positive Voltage Output Circuit As shown in Figure 21, in order to generate a positive voltage output, a negative reference is input to the DAC8801. This design is suggested instead of using an inverting amp to invert the output due to tolerance errors of the resistor. For a negative reference, VOUT and GND of the reference are level-shifted to a virtual ground and a -2.5 V input to the DAC8801 with an op amp. +2.5V Reference VOUT VIN GND VREF − + VDD VDD RFB DAC8801 −2.5 V OPA277 C1 IOUT OPA277 − + VOUT GND 0 VOUT +2.5 V Figure 21. Positive Voltage Output Circuit 10 DAC8801 www.ti.com SLAS403A – NOVEMBER 2004 – REVISED DECEMBER 2004 Bipolar Output Circuit The DAC8801, as a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the full-scale output IOUT is the inverse of the input reference voltage at VREF. Some applications require full 4-quadrant multiplying capabilities or bipolar output swing. As shown in Figure 22, external op amp U4 is added as a summing amp and has a gain of 2X that widens the output span to 5 V. A 4-quadrant multiplying circuit is implemented by using a 2.5-V offset of the reference voltage to bias U4. According to the circuit transfer equation given in Equation 2, input data (D) from code 0 to full scale produces output voltages of VOUT = -2.5 V to VOUT = +2.5 V. V OUT 16,D384 1 V REF (2) 10 k VDD 5 k VREF C2 − RFB VDD +2.5 V (+10 V) 10 k + C1 DAC8801 VOUT U4 OPA277 − IOUT + GND U2 OPA277 −2.5 V VOUT +2.5 V (−10 V VOUT +10 V) Figure 22. Bipolar Output Circuit Programmable Current Source Circuit A DAC8801 can be integrated into the circuit in Figure 23 to implement an improved Howland current pump for precise voltage to current conversions. Bidirectional current flow and high voltage compliance are two features of the circuit. A application of this circuit includes a 4-mA to 20-mA current transmitter with up to a 500-Ω load. With a matched resistor network, the load current of the circuit is shown in Equation 3: R2 R3 R1 IL VREF D R3 (3) R2 15 k C1 10 pF R1 150 k VDD VDD VREF VREF RFB U1 DAC8801 U2 OPA277 R3 50 − U2 OPA277 IOUT − VOUT + R1 150 k R2 15 k R3 50 + IL GND LOAD Figure 23. Programmable Bidirectional Current Source Circuit 11 DAC8801 www.ti.com SLAS403A – NOVEMBER 2004 – REVISED DECEMBER 2004 The value of R3 in the previous equation can be reduced to increase the output current drive of U3. U3 can drive ±20 mA in both directions with voltage compliance limited up to 15 V by the U3 voltage supply. Elimination of the circuit compensation capacitor C1 in the circuit is not suggested because of the change in the output impedance ZO, according to Equation 4: R1R3(R1 R2) ZO R1(R2 R3) R1(R2 R3) (4) As shown in Equation 4, with matched resistors, ZO is infinite and the circuit is optimum for use as a current source. However, if unmatched resistors are used, ZO is positive or negative with negative output impedance being a potential cause of oscillation. Therefore, by incorporating C1 into the circuit, possible oscillation problems are eliminated. The value of C1 can be determined for critical applications; however, for most applications a value of several pF is suggested. Cross-Reference The DAC8801 has an industry-standard pinout. Table 3 provides the cross-reference information. Table 3. Cross Reference PRODUCT INL (LSB) DNL (LSB) SPECIFIED TEMPERATURE RANGE PACKAGE DESCIPTION PACKAGE OPTION CROSS REFERENCE DAC8801IDGK ±1 ±1 -40°C to +85°C 8-Lead MicroSOIC MSOP-8 ADS5553CRM DAC8801IDRB ±1 ±1 -40°C to +85°C 8-Lead Small Outline SON-8 N/A 12 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty DAC8801IDGKR ACTIVE MSOP DGK 8 2000 TBD CU SNPB Level-1-220C-UNLIM DAC8801IDGKT ACTIVE MSOP DGK 8 250 TBD CU SNPB Level-1-220C-UNLIM DAC8801IDRBR ACTIVE SON DRB 8 2500 TBD CU Level-1-240C-UNLIM DAC8801IDRBT ACTIVE SON DRB 8 250 TBD CU Level-1-240C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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