ADS1244 ADS1 244 SBAS273 – DECEMBER 2002 Low-Power, 24-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● 20-BIT EFFECTIVE RESOLUTION The ADS1244 is a 24-bit, delta-sigma Analog-to-Digital (A/D) converter. It offers excellent performance and very low power in an MSOP-10 package and is well suited for demanding high-resolution measurements, especially in portable and other space- and power-constrained systems. ● CURRENT CONSUMPTION: 90µA ● ANALOG SUPPLY: 2.5V to 5.25V ● DIGITAL SUPPLY: 1.8V to 3.6V ● ±5V DIFFERENTIAL INPUT RANGE ● 0.0002% INL (TYP), 0.0008% INL (MAX) ● SIMPLE 2-WIRE SERIAL INTERFACE ● SIMULTANEOUS 50Hz AND 60Hz REJECTION ● SINGLE CONVERSIONS WITH SLEEP MODE ● SINGLE-CYCLE SETTLING ● SELF-CALIBRATION ● WELL-SUITED FOR MULTICHANNEL SYSTEMS ● EASILY CONNECTS TO THE MSP430 APPLICATIONS ● HAND-HELD INSTRUMENTATION A simple, 2-wire serial interface provides all the necessary control. Data retrieval, self-calibration, and Sleep Mode are handled with a few simple waveforms. When only single conversions are needed, the ADS1244 can be shut down (Sleep Mode) while idle between measurements to dramatically reduce the overall power dissipation. Multiple ADS1244s can be connected together to create a synchronously sampling multichannel measurement system. The ADS1244 is designed to easily connect to microcontrollers, such as the MSP430. The ADS1244 supports 2.5V to 5.25V analog supplies and 1.8V to 3.6V digital supplies. Power is typically less than 270µW in normal operation and less than 1µW during Sleep Mode. ● PORTABLE MEDICAL EQUIPMENT ● INDUSTRIAL PROCESS CONTROL ● WEIGH SCALES VREFP VREFN A 3rd-order delta-sigma modulator and digital filter form the basis of the A/D converter. The analog modulator has a ±5V differential input range. The digital filter rejects both 50Hz and 60Hz signals, completely settles in one cycle, and outputs data at 15 samples per second. AVDD DVDD CLK AINP 3rd-Order Modulator DRDY/DOUT Digital Filter AINN Serial Interface SCLK GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) AVDD to GND ....................................................................... –0.3V to +6V DVDD to GND ................................................................... –0.3V to +3.6V Input Current ............................................................... 100mA, Momentary Input Current ................................................................ 10mA, Continuous Analog Input Voltage to GND .............................. –0.5V to AVDD + 0.5V Digital Input Voltage to GND ............................... –0.3V to DVDD + 0.3V Digital Output Voltage to GND ............................. –0.3V to DVDD + 0.3V Maximum Junction Temperature ................................................... +150°C Operating Temperature Range ........................................ –40°C to +85°C Storage Temperature Range ......................................... –60°C to +150°C Lead Temperature (soldering, 10s) ............................................... +300°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. DEMO BOARD ORDERING INFORMATION PRODUCT DESCRIPTION ADS1244-EVM ADS1244 Evaluation Module PACKAGE/ORDERING INFORMATION PRODUCT ADS1244 PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING MSOP-10 DGS –40°C to +85°C BHG ADS1244IDGST Tape and Reel, 250 " " " " ADS1244IDGSR Tape and Reel, 2500 " ORDERING NUMBER TRANSPORT MEDIA, QUANTITY NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. PIN DESCRIPTIONS PIN CONFIGURATION Top View MSOP PIN NUMBER NAME 1 GND 2 VREFP Positive Reference Input 3 VREFN Negative Reference Input 4 AINN Negative Analog Input 5 AINP Positive Analog Input GND 1 10 CLK VREFP 2 9 SCLK VREFN 3 8 DRDY/DOUT 6 AVDD Analog Power Supply, 2.5V to 5.25V AINN 4 7 DVDD 7 DVDD Digital Power Supply, 1.8V to 3.6V AINP 5 6 AVDD 8 DRDY/ DOUT Dual-Purpose Output: Data Ready: Indicates valid data by going LOW. Data Output: Outputs data, MSB first, on the first rising edge of SCLK. 9 SCLK Serial Clock Input: Clocks out data on the rising edge. Used to initiate calibration and Sleep Mode, see text for more details. 10 CLK ADS1244 2 DESCRIPTION Analog and Digital Ground System Clock Input: Typically 2.4576MHz ADS1244 www.ti.com SBAS273 ELECTRICAL CHARACTERISTICS All specifications –40°C to +85°C, AVDD = 5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = 2.5V, unless otherwise specified. ADS1244 PARAMETER ANALOG INPUT Full-Scale Input Voltage Range Absolute Input Range Differential Input Impedance SYSTEM PERFORMANCE Resolution Data Rate Integral Nonlinearity (INL) Offset Error Offset Error Drift(3) Gain Error Gain Error Drift(3) Common-Mode Rejection Normal-Mode Rejection Input Referred Noise Analog Power-Supply Rejection Digital Power-Supply Rejection VOLTAGE REFERENCE INPUT Reference Input Voltage (VREF) Negative Reference Input (VREFN) Positive Reference Input (VREFP) Voltage Reference Impedance DIGITAL INPUT/OUTPUT Logic Levels VIH (CLK, SCLK) VIL (CLK, SCLK) VOH (DRDY/DOUT ) VOL (DRDY/DOUT ) Input Leakage (CLK, SCLK) CLK Frequency (fCLK) CLK Duty Cycle POWER SUPPLY AVDD DVDD AVDD Current DVDD Current Total Power Dissipation CONDITIONS MIN AINP – AINN AINP, AINN with Respect to GND fCLK = 2.4576MHz GND – 0.1 No Missing Codes fCLK = 2.4576MHz Differential Input Signal, End Point Fit at DC fCM(4) = 50 ± 1Hz, fCLK = 2.4576MHz fCM = 60 ± 1Hz, fCLK = 2.4576MHz fSIG(5) = 50 ± 1Hz, fCLK = 2.4576MHz fSIG = 60 ± 1Hz, fCLK = 2.4576MHz AVDD + 0.1 V V MΩ 24 90 100 100 60 70 15 ±0.0002 1 0.01 0.005 0.5 130 ±0.0008 10 0.02 1 105 100 0.5 GND – 0.1 VREFN + 0.5 2.5 2.1 GND 2.6 V V V MΩ 5.25 0.9 V V V V µA MHz % 0.4 ±10 6 70 2.5 1.8 0.1 85 90 0.1 1.3 4.5 270 Bits sps(1) % FSR(2) ppm of FSR ppm of FSR/°C % ppm/°C dB dB dB dB dB ppm of FSR, rms dB dB AVDD(6) VREFP – 0.5 AVDD + 0.1 1 30 Sleep Mode AVDD = 3V AVDD = 5V Sleep Mode, CLK Stopped Sleep Mode, 2.4576MHz CLK Running DVDD = 3V AVDD = DVDD = 3V UNITS 5 fCLK = 2.4576MHz IOH = 1mA IOL = 1mA 0 < (CLK, SCLK) < DVDD MAX ±2VREF at DC, ∆AVDD = 5% at DC, ∆DVDD = 5% VREF ≡ VREFP – VREFN TYP 5.25 3.6 1 150 5 10 V V µA µA µA µA µA µA µW NOTES: (1) sps = Samples Per Second. (2) FSR = Full-Scale Range = 4VREF. (3) Recalibration can reduce these errors to the level of the noise. (4) fCM is the frequency of the common-mode input. (5) fSIG is the frequency of the input signal. (6) It will not be possible to reach the digital output full-scale code when VREF > AVDD/2. ADS1244 SBAS273 www.ti.com 3 TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +2.5V, unless otherwise specified. ANALOG CURRENT vs TEMPERATURE DIGITAL CURRENT vs TEMPERATURE 110 12 105 10 AVDD = 5V, fCLK = 4.9152MHz 95 Current (µA) Current (µA) 100 90 85 DVDD = 3V, fCLK = 4.9152MHz 8 6 4 80 AVDD = 3V, fCLK = 2.4576MHz 2 75 DVDD = 1.8V, fCLK = 2.4576MHz 0 70 –45 –25 –5 15 35 55 75 95 –45 –25 –5 Temperature (°C) 15 35 55 75 95 Temperature (°C) ANALOG CURRENT vs ANALOG SUPPLY DIGITAL CURRENT vs DIGITAL SUPPLY 94 20 18 92 16 14 fCLK = 4.9152MHz Current (µA) Current (µA) 90 88 86 fCLK = 2.4576MHz 84 12 10 fCLK = 4.9152MHz 8 6 4 82 2 80 fCLK = 2.4576MHz 0 2.5 3 3.5 4.5 4 5 5.5 1.5 2 Analog Supply (V) 3 3.5 4 INTEGRAL NONLINEARITY vs VIN INTEGRAL NONLINEARITY vs VIN 3 2.5 Digital Supply (V) 3 AVDD = 3V, VREF = 1.25V AVDD = 5V, VREF = 2.5V 2 2 INL (ppm of FSR) INL (ppm of FSR) T = 25°C 1 T = –40°C 0 –1 T = –40°C 0 T = 25°C –1 –2 –2 T = 85°C T = 85°C –3 –2.5 –3 –5 –3 –1 1 3 5 –1.5 –0.5 0.5 1.5 2.5 VIN (V) VIN (V) 4 1 ADS1244 www.ti.com SBAS273 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +2.5V, unless otherwise specified. INTEGRAL NONLINEARITY vs ANALOG SUPPLY INTEGRAL NONLINEARITY vs ANALOG SUPPLY 20 18 VREF = AVDD/2 18 T = –40°C T = 85°C 16 INL (ppm of FSR) 16 INL (ppm of FSR) 20 VREF = AVDD 14 12 10 8 T = 25°C 6 4 14 T = 25°C 12 10 T = –40°C 8 6 4 2 2 T = 85°C 0 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 1.5 2 2.5 3 Analog Supply (V) 4.5 5 5.5 75 95 75 95 1.00008 1.00006 1.00004 0.5 Normalized Gain Normalized Offset (ppm of FSR) 4 GAIN vs TEMPERATURE OFFSET vs TEMPERATURE 1 0 –0.5 1.00002 1 0.99998 0.99996 0.99994 0.99992 –1 0.9999 –45 –25 –5 15 35 55 75 –45 95 –25 –5 15 35 55 Temperature (°C) Temperature (°C) NOISE vs INPUT SIGNAL NOISE vs TEMPERATURE 1.6 1.6 1.5 1.4 1.4 Noise (ppm of FSR, rms) Noise (ppm of FSR, rms) 3.5 Analog Supply (V) 1.3 1.2 1.1 1 0.9 0.8 1.2 1.0 0.8 0.6 0.4 0.2 0.7 0 0.6 –5 –3 –1 1 3 5 –45 VIN (V) –5 15 35 55 Temperature (°C) ADS1244 SBAS273 –25 www.ti.com 5 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +2.5V, unless otherwise specified. INPUT-REFERRED NOISE vs VREF HISTOGRAM OF OUTPUT DATA 14 1200 13 Input-Referred Noise (µV, rms) Number of Occurences 1000 800 600 400 200 12 11 10 9 8 7 0 6 –4 –3 –2 –1 0 1 2 3 0 4 1 2 ANALOG PSRR vs FREQUENCY 4 5 10k 100k DIGITAL PSRR vs FREQUENCY 120 120 100 100 Magnitude (dB) Magnitude (dB) 3 VREF (V) ppm of FSR 80 60 40 20 80 60 40 20 0 0 1 10 100 1k 10k 100k 1 10 100 Frequency (Hz) 1k Frequency (Hz) CMRR vs FREQUENCY 160 140 Magnitude (dB) 120 100 80 60 40 20 0 1 10 100 1k 10k 100k Frequency (Hz) 6 ADS1244 www.ti.com SBAS273 OVERVIEW ESD Protection The ADS1244 is an A/D converter comprised of a 3rd-order modulator followed by a digital filter. The modulator measures the differential input signal VIN = (AINP – AINN) against the differential reference VREF = (VREFP – VREFN). Figure 1 shows a conceptual diagram. The differential reference is scaled internally so that the full-scale input range is ±2VREF. The digital filter receives the modulator’s signal and provides a low-noise digital output. The filter also sets the frequency response of the converter and provides 50Hz and 60Hz rejection while settling in a single conversion cycle. A 2-wire serial interface indicates conversion completion and provides the user with the output data. AVDD/2 AVDD CA1 = 4pF S2 S1 AINP CB = 8pF S1 AINN S2 CA2 = 4pF AVDD AVDD/2 FIGURE 2. Simplified Input Structure. VREFP VREFN Σ tSAMPLE = 128/fCLK ON CLK VREF S1 OFF 2 ON S2 2VREF AINP AINN Σ VIN Modulator Digital Filter and Serial Interface DRDY/DOUT FIGURE 3. S1 and S2 Switch Timing for Figure 1. SCLK FIGURE 1. Conceptual Diagram of the ADS1244. ANALOG INPUTS (AINP, AINN) The input signal to be measured is applied to the input pins AINP and AINN. The ADS1244 accepts differential input signals, but can also measure unipolar signals. When measuring unipolar (or “single-ended” signals) with respect to ground, connect the negative input (AINN) to ground and connect the input signal to the positive input (AINP). Note that when the ADS1244 is used this way, only half of the converter’s full-scale range is used since only positive digital output codes will be produced. The ADS1244 measures the input signal using internal capacitors that are continuously charged and discharged. Figure 2 shows a simplified schematic of the ADS1244’s input circuitry with Figure 3 showing the ON/OFF timings of the switches. S1 switches close during the input sampling phase. With S1 closed, CA1 charges to AINP, CA2 charges to AINN, and CB charges to (AINP – AINN). For the discharge phase, S1 opens first and then S2 closes. CA1 and CA2 discharge to approximately AVDD/2 and CB discharges to 0V. This 2-phase sample/discharge cycle repeats with a frequency of fCLK/128 (19.2kHz for fCLK = 2.4576MHz). The constant charging of the input capacitors presents a load on the inputs that can be represented by effective impedances. Figure 4 shows the input circuitry with the capacitors and switches of Figure 2 replaced by their effective impedances. These impedances scale inversely with fCLK frequency. For example, if fCLK’s frequency is reduced by a factor of 2, the impedances will double. AVDD/2 ZeffA = tSAMPLE/CA1 = 13MΩ(1) AINP ZeffB = tSAMPLE/CB = 6.5MΩ(1) AINN ZeffA = tSAMPLE/CA2 = 13MΩ(1) AVDD/2 NOTE: (1) fCLK = 2.4576MHz. FIGURE 4. Effective Analog Input Impedances. ESD diodes protect the inputs. To keep these diodes from turning on, make sure the voltages on the input pins do not go below GND by more than 100mV, and likewise do not exceed AVDD by 100mV: GND – 100mV < (AINP, AINN) < AVDD + 100mV. ADS1244 SBAS273 OFF www.ti.com 7 VOLTAGE REFERENCE INPUTS (VREFP, VREFN) The voltage reference used by the modulator is generated from the voltage difference between VREFP and VREFN: VREF = VREFP – VREFN. The reference inputs use a structure similar to that of the analog inputs. A simplified diagram of the circuitry on the reference inputs is shown in Figure 5. The switches and capacitors can be modeled with an effective tSAMPLE / 25pF = 1MΩ for fCLK = 2.4576MHz. impedance = 2 VREFP AVDD S1 S1 DATA READY/DATA OUTPUT ( DRDY/DOUT) This digital output pin serves two purposes. It indicates when new data is ready by going LOW. Afterwards, on the first rising edge of SCLK, the DRDY/DOUT pin changes function and begins outputting the conversion data, MSB first. Data is shifted out on each subsequent SCLK rising edge. After all 24 bits have been retrieved, the pin can be forced HIGH with an additional SCLK. It will then stay HIGH until new data is ready. This is useful when polling on the status of DRDY/DOUT to determine when to begin data retrieval. VREFN AVDD Minimize the overshoot and undershoot on CLK for the best analog performance. A small resistor in series with CLK (10Ω to 100Ω) can often help. CLK can be generated from a number of sources including stand-alone crystal oscillators and microcontrollers. The MSP430, an ultra low power microcontroller, is especially well suited for this task. Using the MSP430’s FLL clock generator available on the 4xx family, it’s easy to produce a 2.4576MHz clock from a 32.768kHz crystal. ESD Protection 25pF SERIAL CLOCK INPUT (SCLK) S2 FIGURE 5. Simplified Reference Input Circuitry. ESD diodes protect the reference inputs. To prevent these diodes from turning on, make sure the voltages on the reference pins do not go below GND by more than 100mV, and likewise do not exceed AVDD by 100mV: GND – 100mV < (VREFP, VREFN) < AVDD + 100mV. VREF is typically AVDD/2, but it can be raised as high as AVDD. When VREF exceeds AVDD/2, it will not be possible to reach the full-scale digital output value corresponding to ±2VREF since this would require the analog inputs to exceed the power supplies. For example, if VREF = AVDD = 5V, the positive full-scale signal is 10V. The maximum positive input signal that can be supplied before the ESD diodes begin to turn on is when AINP = 5.1V and AINN = –0.1V → VIN = 5.2V. Therefore, it will not be possible to reach the positive (or negative) full-scale readings in this configuration. The digital output codes will be limited to approximately one half of the entire range. This digital input shifts serial data out with each rising edge. As with CLK, this input may be driven with 5V logic regardless of the DVDD or AVDD voltage. There is hysteresis built into this input, but care should still be taken to ensure a clean signal. Glitches or slow rising signals can cause unwanted additional shifting. For this reason, it is best to make sure the rise-and-fall times of SCLK are less than 50ns. FREQUENCY RESPONSE The ADS1244’s frequency response for fCLK = 2.4576MHz is shown in Figure 6. The frequency response repeats at multiples of 19.2kHz. The overall response is that of a low-pass filter with a –3dB cutoff frequency of 13.7Hz. As can be seen, the ADS1244 does a good job attenuating out to 19kHz. For the best resolution, limit the input bandwidth to below this value to keep higher frequency noise from affecting performance. Often a simple RC filter on the ADS1244’s analog inputs is all that is needed. FREQUENCY RESPONSE fCLK = 2.4576MHz 0 For best performance, bypass the voltage reference inputs with a 0.1µF capacitor between VREFP and VREFN. Place the capacitor as close as possible to the pins. –20 Gain (dB) –40 CLOCK INPUT (CLK) This digital input supplies the system clock to the ADS1244. The recommended CLK frequency is 2.4576MHz. This places the notches of the digital filter at 50Hz and 60Hz and sets the data rate at 15SPS. The CLK frequency can be increased to speed up the data rate, but the frequency notches will move in frequency proportionally. CLK must be left running during normal operation. It may be turned off during Sleep Mode to save power, but this is not required. The CLK input may be driven with 5V logic, regardless of the DVDD or AVDD voltage. 8 –60 –80 –100 –120 –140 0 9.6 Frequency (kHz) 19.2 FIGURE 6. Frequency Response. ADS1244 www.ti.com SBAS273 To help see the response at lower frequencies, Figure 7 illustrates the response out to 180Hz. Notice that both 50Hz and 60Hz signals are rejected. This feature is very useful for eliminating power line cycle interference during measurements. Figure 8 shows the ADS1244’s response around these frequencies. The ADS1244’s data rate and frequency response scale directly with CLK frequency. For example, if fCLK increases from 2.4576MHz to 4.9152MHz, the data rate increases from 15sps to 30sps while the notches in the response at 50Hz and 60Hz move out to 100Hz and 120Hz. SETTLING TIME FREQUENCY RESPONSE TO 180Hz fCLK = 2.4576MHz The ADS1244 has single-cycle settling. That is, the output data is fully settled after a single conversion—there is no need to wait for additional conversions before retrieving the data when there is a change on the analog inputs. 0 –20 –40 Gain (dB) –60 –80 –100 –120 –140 –160 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 –180 Frequency (Hz) FIGURE 7. Frequency Response to 180Hz. In order to realize single-cycle settling, synchronize changes on the analog inputs to the conversion beginning, which is indicated by the falling edge of DRDY/DOUT. For example, when using a multiplexer in front of the ADS1244, change the multiplexer’s inputs when DRDY/DOUT goes LOW. Increasing the time between the conversion beginning and the change on the analog inputs (tDELAY) will result in a settling error in the conversion data, as shown in Figure 9. The settling error versus delay time is shown in Figure 10. If the input change is delayed to the point where the settling error is too high, simply ignore the first data result and wait for the second conversion which will be fully-settled. FREQUENCY RESPONSE NEAR 50Hz AND 60Hz fCLK = 2.4576MHz SETTLING ERROR vs DELAY TIME fCLK = 2.4576MHz –40 10.000000 –50 1.000000 Settling Error (%) Gain (dB) –60 –70 –80 –90 0.100000 0.010000 0.001000 –100 0.000100 –110 0.000010 –120 0.000001 45 50 55 Frequency (Hz) 60 65 FIGURE 8. Frequency Response Near 50Hz and 60Hz. 0 2 4 6 8 10 12 Delay Time, tDELAY (ms) 14 16 FIGURE 10. Settling Error vs Delay Time. Begin New Conversion, Previous Conversion Data Complete Previous Conversion New Conversion Complete DRDY/DOUT tDELAY VIN FIGURE 9. Analog Input Change Timing. ADS1244 SBAS273 www.ti.com 9 POWER-UP Self-calibration is performed at power-up to minimize offset and gain errors. In order for the self-calibration at power-up to work properly, make sure that both AVDD and DVDD increase monotonically and are settled by t1, as shown in Figure 11. SCLK must be held LOW during this time. Once calibration is complete, DRDY/DOUT will go LOW indicating data is ready for retrieval. The time required before the first data is ready (t6) depends on how fast AVDD and DVDD ramp to their final value (t1). For most ramp rates, t1 + t2 ≈ 350ms (fCLK = 2.4576MHz). If the system environment is not stable during power-up (the temperature is varying or the supply voltages are moving around), it is recommended that a self-calibration be issued after everything is stable. duces an output code of 7FFFFFH and the negative full-scale input produces an output code of 800000H. The output clips at these codes for signals exceeding full-scale. Table I summarizes the ideal output codes for different input signals. INPUT SIGNAL VIN (AINP – AINN) IDEAL OUTPUT CODE(1) ≥ +2VREF 7FFFFFH +2VREF 2 23 − 1 000001H 0 000000H −2VREF 2 23 − 1 FFFFFFH 2 23 ≤ − 2VREF 23 2 − 1 800000H NOTE: (1) Excludes effects of noise, INL, offset, and gain errors. DATA FORMAT TABLE I. Ideal Output Code versus Input Signal. The ADS1244 outputs 24 bits of data in Binary Two’s Complement format. The Least Significant Bit (LSB) has a weight of (2VREF)/(223 – 1). A positive full-scale input pro- AVDD and DVDD Data ready after power-up calibration. DRDY/DOUT SCLK t1 SYMBOL t1(1) t2(1) t2 DESCRIPTION MIN AVDD and DVDD settling time. Wait time for calibration and first data conversion. 316 MAX UNITS 100 ms ms NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional to CLK period. FIGURE 11. Power-Up Timing. 10 ADS1244 www.ti.com SBAS273 DATA RETRIEVAL retrieval during the update period. DRDY/DOUT will remain at the state of the last bit shifted out until it is taken HIGH (see t7), indicating that new data is being updated. The ADS1244 continuously converts the analog input signal. To retrieve data, wait until DRDY/DOUT goes LOW, as shown in Figure 12. After this occurs, begin shifting out the data by applying SCLKs. Data is shifted out Most Significant Bit (MSB) first. It is not required to shift out all the 24 bits of data, but the data must be retrieved before the new data is updated (see t3) or else it will be overwritten. Avoid data To avoid having DRDY/DOUT remain in the state of the last bit, shift a 25th SCLK to force DRDY/DOUT HIGH, see Figure 13. This technique is useful when a host controlling the ADS1244 is polling DRDY/DOUT to determine when data is ready. Data New data is ready. Data is ready. MSB DRDY/DOUT 23 LSB 22 21 0 t5 t6 t3 t4 t7 1 SCLK 24 t4 t8 SYMBOL DESCRIPTION MIN t3 DRDY/DOUT LOW to first SCLK rising edge. t4 t5(1) t6 MAX UNITS 0 ns SCLK positive or negative pulse width. 100 ns SCLK rising edge to new data bit valid: propagation delay. 50 ns SCLK rising edge to old data bit valid: hold time. t7(2) Data updating, no read back allowed. t8(2) Conversion time (1/data rate). 0 ns 152 152 µs 66.667 66.667 ms NOTES: (1) Load on DRDY/DOUT = 20pF || 100kΩ. (2) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional to CLK period. For example, for fCLK = 4.9152MHz, t8 → 33.333ms. FIGURE 12. Data Retrieval Timing. Data New data is ready. Data is ready. DRDY/DOUT SCLK 23 22 21 1 0 24 25 25th SCLK to force DRDY/DOUT HIGH. FIGURE 13. Data Retrieval with DRDY/DOUT Forced HIGH Afterwards. ADS1244 SBAS273 www.ti.com 11 SELF-CALIBRATION When the calibration is complete, DRDY/DOUT will go LOW indicating that new data is ready. There is no need to alter the analog input signal applied to the ADS1244 during calibration, the inputs pins are disconnected within the A/D converter and the appropriate signals applied internally automatically. The first conversion after a calibration is fully settled and valid for use. The time required for a calibration depends on two independent signals: the falling edge of SCLK and an internal clock derived from CLK. Variations in the internal calibration values will change the time required for calibration (t9) within the range given by the MIN/MAX specs. t12 and t13 described in the next section are affected likewise. The user can initiate self-calibration at any time, though in many applications the ADS1244’s drift performance is good enough that the self-calibration performing automatically at power-up is all that is needed. To initiate a self-calibration, apply at least two additional SCLKs after retrieving 24 bits of data. Figure 14 shows the timing pattern. The 25th SCLK will send DRDY/DOUT HIGH. The falling edge of the 26th SCLK will begin the calibration cycle. Additional SCLK pulses may be sent after the 26th SCLK, but try to minimize activity on SCLK during calibration for best results. Data ready after cal. DRDY/DOUT 23 22 21 0 23 Cal begins. 1 SCLK 24 25 26 t9 SYMBOL t9(1) DESCRIPTION MIN MAX UNITS First data ready after calibration. 209 210 ms NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional to CLK period. FIGURE 14. Self-Calibration Timing. 12 ADS1244 www.ti.com SBAS273 SLEEP MODE Sleep Mode dramatically reduces power consumption (typically < 1µW with CLK stopped) by shutting down all of the active circuitry. To enter Sleep Mode, simply hold SCLK HIGH after DRDY/DOUT goes LOW, as shown in Figure 15. Sleep Mode can be initiated at any time during read back; it is not necessary to retrieve all 24 bits of data beforehand. Once t11 has passed with SCLK held HIGH, Sleep Mode will activate. DRDY/DOUT stays HIGH once Sleep Mode begins. SCLK must remain HIGH to stay in Sleep Mode. To exit Sleep Mode (“wakeup”), set SCLK LOW. The first data after exiting Sleep Mode is valid. It is not necessary to stop CLK during Sleep Mode, but doing so will further reduce the digital supply current. Sleep Mode With Self-Calibration Self-calibration can be set to run immediately after exiting Sleep Mode. This is useful when the ADS1244 is put in Sleep Mode for long periods of time and self-calibration is desired afterwards to compensate for temperature or supply voltage changes. To force a self-calibration with Sleep Mode, shift 25 bits out before taking SCLK HIGH to enter Sleep Mode. Self-calibration will then begin after wakeup. Figure 16 shows the appropriate timing. Note the extra time needed after wakeup for calibration before data is ready. The first data after Sleep Mode with self-calibration is fully-settled and can be used. SINGLE CONVERSIONS When only single conversions are needed, Sleep Mode can be used to start and stop the ADS1244. To make a single conversion, first enter the Sleep Mode holding SCLK HIGH. Now, when ready to start the conversion, take SCLK LOW. The ADS1244 will wake up and begin the conversion. Wait for DRDY/DOUT to go LOW, and then retrieve the data. Afterwards, take SCLK HIGH to stop the ADS1244 from converting and re-enter Sleep Mode. Continue to hold SCLK HIGH until ready to start the next conversion. Operating in this fashion greatly reduces power consumption since the ADS1244 is shut down while idle between conversions. Selfcalibrations can be performed prior to the start of the single conversions by using the waveform shown in Figure 16. Data ready after wakeup. Sleep Mode DRDY/DOUT 23 SCLK 22 21 0 1 23 Wakeup 24 t10 t11 SYMBOL t10 (1) t12 DESCRIPTION SCLK HIGH after DRDY/DOUT goes LOW to activate Sleep Mode. Sleep Mode activation Time. Data ready after wakeup. t11(1) t12(1) MIN MAX UNITS 0 63.7 ms 66.5 71 66.5 72 ms ms NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional to CLK period. FIGURE 15. Sleep Mode Timing; Can be Used for Single Conversions. Data ready after wakeup and cal. Sleep Mode DRDY/DOUT 23 22 21 0 23 Wakeup and begin cal. SCLK 1 24 25 t13 t11 SYMBOL t13(1) DESCRIPTION MIN MAX UNITS Data ready after wakeup and calibration. 210 211 ms NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional to CLK period. FIGURE 16. Sleep Mode with Self-Calibration on Wakeup Timing; Can be Used for Single Conversions. ADS1244 SBAS273 www.ti.com 13 SINGLE-SUPPLY OPERATION MULTICHANNEL SYSTEMS It is possible to operate the ADS1244 with a single supply. For a 3V supply, simply connect AVDD and DVDD together. Figure 17 shows an example of the ADS1244 running on a single 5V supply. An external resistor, R1, is used to drop 5V supply down to a desired voltage level of DVDD. For example, if the desired DVDD supply voltage is 3V and AVDD is 5V, the value of R1 should be: Multiple ADS1244s can be operated in parallel to measure multiple input signals. Figure 18 shows an example of a 2-channel system. For simplicity, the supplies and reference circuitry were not included. The same CLK signal should be applied to all devices. To be able to synchronize the ADS1244s, connect the same SCLK signal to all devices as well. When ready to synchronize, place all the devices in Sleep Mode. Afterwards, “wakeup” and all the ADS1244s will be synchronized. That is, they will sample the input signals simultaneously. R1 = (5V – 3V)/4.5µA ≈ 440kΩ where 4.5µA is a typical digital current consumption when DVDD = 3V (refer to the typical characteristic “Digital Current vs Digital Supply”). A buffer on DRDY/DOUT can provide level-shifting if required. DVDD can be set to a desired voltage by choosing a proper value of R1, but keep in mind that DVDD must be set between 1.8V and 3.6V. Note that the maximum logic HIGH output of DRDY/DOUT is equal to DVDD, but both CLK and SCLK inputs can be driven with 5V logic regardless of the DVDD or AVDD voltage. Use 0.1µF capacitors to bypass both AVDD and DVDD. The DRDY/DOUT outputs will go LOW at approximately the same time after synchronization. The falling edges indicating that new data is ready will vary with respect to each other no more than timing specification t14. This variation is due to posible differences in the ADS1244’s internal calibration settings. To account for this when using multiple devices, either wait for t14 to pass after seeing one device’s DRDY/DOUT go LOW, or wait until all DRDY/DOUTs have gone LOW before retrieving data. ADS1244 to +5V logic SN74LVCC3245A 0.1µF + from +5V logic GND 2 VREFP SCLK 9 3 VREFN DRDY/DOUT 8 4 AINN DVDD 7 5 AINP AVDD 6 1 GND 0.1µF + R1 OUT1 IN1 +5V from +5V logic CLK 10 1 ADS1244 CLK 10 10 9 8 7 6 2 VREFP SCLK 9 CLK SCLK DRDY/DOUT DVDD AVDD 3 VREFN DRDY/DOUT 8 4 AINN DVDD 7 5 AINP AVDD 6 OUT2 IN2 ADS1244 GND VREFP VREFN AINN AINP 1 2 3 4 5 CLK and SCLK Sources OUT1 t14 OUT2 SYMBOL FIGURE 17. Example of the ADS1244 Running on a Single 5V Supply. t14 DESCRIPTION Difference between DRDY/DOUT s going LOW in multichannel systems. MIN MAX UNITS ±500 µs FIGURE 18. Example of Using Multiple ADS1244s in Parallel. 14 ADS1244 www.ti.com SBAS273 WEIGH SCALE SYSTEM differential gain stage noise and reduce mechanical vibration noise from the load cell. The cutoff frequency of the low-pass filter should be as low as possible to minimize the overall system noise. The reference voltage is typically generated by dividing down the supply voltage (RVR1, RVR2). Use a bypass capacitor located as close to VREFP as possible. Figure 19 shows an example of a weigh scale system. OPA1, OPA2, RG, and RF form a differential gain stage to amplify the load cell output. The gain is equal to (1 + 2 RF/RG). Depending on the load cell, the typical gain setting is from 100 to 250. RI and CI form a single-pole low-pass filter to band-limit the 5V 1.8V ~ 3.6V EMI Filter 1µF 0.1µF 0.1µF 1µF 0.1µF RVR1 AVDD RVR2 0.1µF DVDD DVCC AVCC VREFP EMI Filter AINP OPA1(1) RI ADS1244 RF Load Cell CI RG MSP430Fx41x SCLK P1.2/TA1 XIN DRDY/ DOUT P1.0/TA0 XOUT/TCLK 32.768kHz RF EMI Filter AINN OPA2(1) RI CLK VREFN GND P1.1/TA0/MCLK AVSS DVSS EMI Filter NOTE: (1) OPA2335 or OPA2277 recommended. FIGURE 19. Weigh Scale System. ADS1244 SBAS273 www.ti.com 15 SUMMARY OF SERIAL INTERFACE WAVEFORMS DRDY/DOUT 23 22 21 0 MSB SCLK LSB 1 24 a. Data Retrieval. DRDY/DOUT 23 SCLK 22 21 0 1 24 25 b. Data Retrieval with DRDY/DOUT Forced HIGH Afterwards. Data ready after cal. DRDY/DOUT 23 22 21 0 Begin cal. SCLK 1 24 25 26 c. Self-Calibration. Data ready. Sleep Mode 23 DRDY/DOUT 22 21 0 Wakeup and start conversion. SCLK 1 24 d. Sleep Mode/Single Conversions. Data ready after wakeup and cal. Sleep Mode DRDY/DOUT 23 22 21 0 Wakeup and begin cal. SCLK 1 24 25 e. Sleep Mode/Single Conversions with Self-Calibration on Wakeup. FIGURE 20. Summary of Serial Interface Waveforms. 16 ADS1244 www.ti.com SBAS273 PACKAGE DRAWING DGS (S-PDSO-G10) PLASTIC SMALL-OUTLINE PACKAGE 0,27 0,17 0,50 10 0,08 M 6 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 0°– 6° 5 3,05 2,95 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073272/B 08/01 NOTES: A. B. C. A. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-187 ADS1244 SBAS273 www.ti.com 17 PACKAGE OPTION ADDENDUM www.ti.com 3-Oct-2003 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY ADS1244IDGSR ACTIVE VSSOP DGS 10 2500 ADS1244IDGST ACTIVE VSSOP DGS 10 250 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. 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