SBAS286A − JUNE 2003 − REVISED MARCH 2004 FEATURES D 240SPS Data Rate with 4MHz Clock D 20-Bit Effective Resolution D Input Multiplexer with Four Differential D D D D D D D D D D Channels Pin-Selectable, High-Impedance Input Buffer ±5V Differential Input Range 0.0003% INL (typ), 0.0015% INL (max) Self-Calibrating Simple 2-Wire Serial Interface On-Chip Temperature Sensor Single Conversions with Standby Mode Low Current Consumption: 300µA Analog Supply: 2.7V to 5.5V Digital Supply: 2.7V to 5.5V APPLICATIONS D Hand-Held Instrumentation D Portable Medical Equipment D Industrial Process Control D Weigh Scales DESCRIPTION The ADS1224 is a 4-channel, 24-bit, delta-sigma analog-to-digital (A/D) converter. It offers excellent performance and low power in a TSSOP-20 package. The ADS1224 is well-suited for demanding, high-resolution measurements, especially in portable systems and other space-saving and power-constrained applications. A delta-sigma modulator and digital filter form the basis of the A/D converter. The analog modulator has a ±5V differential input range. An input multiplexer (mux) is used to select between four separate differential input channels. A buffer can be selected to increase the input impedance of the measurement. A simple, 2-wire serial interface provides all the necessary control. Data retrieval, self-calibration, and Standby mode are handled with a few simple waveforms. When only single conversions are needed, the ADS1224 can be quickly shut down (Standby mode) while idle between measurements to dramatically reduce the overall power consumption. Multiple ADS1224s can be connected together to create a synchronously sampling multichannel measurement system. The ADS1224 is designed to easily connect to microcontrollers, such as the MSP430. The ADS1224 supports 2.7V to 5.5V analog supplies and 2.7V to 5.5V digital supplies. Power is typically less than 1mW in 3V operation and less than 1µW during Standby mode. TEMPEN AVDD VREFP VREFN DVDD CLK AINP1 AINN1 AINP2 AINN2 Mux Buffer AINP3 AINN3 ∆Σ Modulator Digital Filter and Serial Interface SCLK DRDY/DOUT AINP4 AINN4 MUX0 MUX1 BUFEN GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright 2003−2004, Texas Instruments Incorporated !"# " $ % & % '& ( ) (&% &$ %&& % $% " % %$% % ( ( *) (& &%% (% &%% * &( % $%) www.ti.com www.ti.com SBAS286A − JUNE 2003 − REVISED MARCH 2004 ORDERING INFORMATION PRODUCT PACKAGE−LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ADS1224 TSSOP-20 PW −40°C to +85°C ADS1224 ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS1224IPWT Tape and Reel, 250 ADS1224IPWR Tape and Reel, 2500 (1) For the most current specification and package information, refer to our web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) ADS1224 UNIT AVDD to GND −0.3 to +6 V DVDD to GND −0.3 to +6 V 100, momentary mA Input current 10, continuous mA Analog input voltage to GND −0.3 to AVDD + 0.3 V Digital input voltage to GND −0.3 to DVDD + 0.3 V +150 °C Operating Temperature Range −55 to +125 °C Storage Temperature Range −60 to +150 °C Maximum Junction Temperature Lead Temperature (soldering, 10s) +300 °C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. 2 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. www.ti.com SBAS286A − JUNE 2003 − REVISED MARCH 2004 ELECTRICAL CHARACTERISTICS All specifications at TA = −40°C to +85°C, AVDD = +5V, DVDD = +5V, fCLK = 2MHz, and VREF = +2.5V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog Input Full-scale input voltage Absolute input voltage Differential input impedance Common-mode input impedance ±2VREF AINP − AINN V Buffer off; AINP, AINN with respect to GND GND − 0.1 AVDD + 0.1 Buffer on; AINP, AINN with respect to GND GND + 0.05 AVDD − 1.5 V V Buffer off; fCLK = 2MHz 2.7 MΩ Buffer on; fCLK = 2MHz 1.2 GΩ Buffer off; fCLK = 2MHz 5.4 MΩ 120 (fCLK/2MHz) Bits SPS(1) % of FSR(2) System Performance Resolution No missing codes 24 Data rate Integral nonlinearity (INL) Offset error Offset error drift Offset error match Gain error Gain error drift Gain error match Common-mode rejection Analog power-supply rejection Digital power-supply rejection Buffer off, Differential input signal, end point fit 0.0003 Buffer on, Differential input signal, end point fit 0.0006 0.0015 % of FSR 100 µV Buffer off 20 Buffer on 20 µV Buffer off 0.2 µV/°C Buffer on 0.2 µV/°C 20 100 µV Buffer off 0.004 0.025 % Buffer on 0.008 % Buffer off 0.00003 % of FSR/°C Buffer on 0.00006 % of FSR/°C Between channels 0.0005 % Between channels Buffer off, at DC 90 110 dB Buffer on, at DC 90 110 dB Buffer off, at DC, ± 10% ∆ in AVDD 95 dB Buffer on, at DC, ± 10% ∆ in AVDD 95 dB Buffer off, at DC, DVDD = 2.7V to 5.5V 85 dB Buffer on, at DC, DVDD = 2.7V to 5.5V 85 dB 0.8 ppm of FSR, rms 106 mV 360 µV/°C Noise Temperature Sensor Temperature sensor voltage TA = 25°C Temperature sensor coefficient Voltage Reference Input AVDD(3) V GND − 0.1 VREFP − 0.5 V Buffer off VREFN + 0.5 AVDD + 0.1 V Negative reference input Buffer on GND + 0.05 VREFP − 0.5 V Positive reference input Buffer on VREFN + 0.5 AVDD − 1.5 Voltage reference impedance fCLK = 2MHz Reference input voltage Negative reference input VREF = VREFP − VREFN Buffer off Positive reference input 0.5 2.5 500 V kΩ (1) SPS = samples per second. (2) FSR = full-scale range = 4VREF. (3) It will not be possible to reach the digital output full-scale code when VREF > AVDD/2. 3 www.ti.com SBAS286A − JUNE 2003 − REVISED MARCH 2004 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = −40°C to +85°C, AVDD = +5V, DVDD = +5V, fCLK = 2MHz, and VREF = +2.5V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.8 DVDD DVDD + 0.1 V GND − 0.1 0.2 DVDD V Digital Input/Output Logic levels VIH VIL VOH VOL IOH = 1mA IOL = 1mA 0.8 DVDD V Input leakage CLK frequency (fCLK) 0.2 DVDD V ±10 µA 8 MHz 30 70 % AVDD 2.7 5.5 V DVDD 2.7 5.5 CLK duty cycle Power Supply AVDD current DVDD current Total power dissipation V Standby mode <1 µA AVDD = 5V, normal mode, buffer off 285 µA AVDD = 5V, normal mode, buffer on 405 µA AVDD = 3V, normal mode, buffer off 265 µA AVDD = 3V, normal mode, buffer on 385 µA Standby mode <1 µA DVDD = 5V, normal mode 20 µA DVDD = 3V, normal mode 10 AVDD = DVDD = 5V, buffer off 1.5 AVDD = DVDD = 3V, buffer off 0.8 µA 2.25 mW mW Temperature Range Specified −40 +85 °C Operating −55 +125 °C Storage −60 +150 °C (1) SPS = samples per second. (2) FSR = full-scale range = 4VREF. (3) It will not be possible to reach the digital output full-scale code when VREF > AVDD/2. 4 www.ti.com SBAS286A − JUNE 2003 − REVISED MARCH 2004 PIN ASSIGNMENTS PW PACKAGE TSSOP (TOP VIEW) DVDD 1 20 AVDD SCLK 2 19 VREFP CLK 3 18 VREFN DRDY/DOUT 4 17 GND MUX0 5 16 AINN1 MUX1 6 15 AINP1 TEMPEN 7 14 AINN2 BUFEN 8 13 AINP2 AINP4 9 12 AINN3 AINN4 10 11 AINP3 ADS1224 Terminal Functions TERMINAL NAME NO. I/O DVDD 1 Digital DESCRIPTION SCLK 2 Digital input Serial clock input CLK 3 Digital input System clock input DRDY/DOUT 4 Digital Ouput MUX0 5 Digital input Selects analog input of mux, bit 0 MUX1 6 Digital input Selects analog input of mux, bit 1 TEMPEN 7 Digital input Selects temperature sensor input from mux BUFEN 8 Digital input Enables input buffer AINP4 9 Analog input Analog channel 4 positive input AINN4 10 Analog input Analog channel 4 negative input AINP3 11 Analog input Analog channel 3 positive input AINN3 12 Analog input Analog channel 3 negative input AINP2 13 Analog input Analog channel 2 positive input AINN2 14 Analog input Analog channel 2 negative input AINP1 15 Analog input Analog channel 1 positive input AINN1 16 Analog input Analog channel 1 negative input GND 17 Analog/Digital Analog and digital ground VREFN 18 Analog input Negative reference input VREFP 19 Analog input Positive reference input AVDD 20 Analog Digital power supply Dual-purpose output: Data Ready: indicates valid data by going low. Data Output: outputs data, MSB first, on the rising edge of SCLK. Analog power supply 5 www.ti.com SBAS286A − JUNE 2003 − REVISED MARCH 2004 TYPICAL CHARACTERISTICS At TA = −40°C to +85°C, AVDD = +5V, DVDD = +5V, fCLK = 2MHz, and VREF = +2.5V, unless otherwise noted. ANALOG CURRENT vs TEMPERATURE ANALOG CURRENT vs TEMPERATURE 500 350 Buffer Off Buffer On fCLK = 4MHz, AVDD = 5V 325 300 Current (µA) Current (µA) fCLK = 2MHz, AVDD = 5V 450 fCLK = 2MHz, AVDD = 5V 275 fCLK = 2MHz, AVDD = 3V 250 fCLK = 4MHz, AVDD = 5V fCLK = 4MHz, AVDD = 3V 400 f CLK = 2MHz, AVDD = 3V f CLK = 4MHz, AVDD = 3V 350 225 300 200 −55 −25 5 35 65 95 −55 125 −25 5 Temperature (_C) 35 Figure 1 DIGITAL CURRENT vs TEMPERATURE 125 ANALOG CURRENT vs SUPPLY VOLTAGE 450 40 400 f CLK = 2MHz fCLK = 4MHz, AVDD = 5V Current (µA) Current (µA) 95 Figure 2 50 30 65 Temperature (_C) f CLK = 2MHz, AVDD = 5V 20 Buffer On 350 300 Buffer Off fCLK = 4MHz, AVDD = 3V 250 10 fCLK = 2MHz, AVDD = 3V 0 −55 −25 5 200 35 65 95 2.5 125 3.0 3.5 Figure 3 DIGITAL CURRENT vs SUPPLY VOLTAGE 5.0 5.5 TEMPERATURE SENSOR VOLTAGE vs TEMPERATURE Temperature Sensor Voltage (mV) 150 40 Current (µA) 4.5 Figure 4 50 30 fCLK = 4MHz 20 fCLK = 2MHz 10 0 140 130 120 110 100 90 80 70 2.5 3.0 3.5 4.0 4.5 Supply Voltage (V) Figure 5 6 4.0 Supply Voltage (V) Temperature (_ C) 5.0 5.5 −55 −25 5 35 65 Temperature (_C) Figure 6 95 125 www.ti.com SBAS286A − JUNE 2003 − REVISED MARCH 2004 TYPICAL CHARACTERISTICS (CONTINUED) At TA = −40°C to +85°C, AVDD = +5V, DVDD = +5V, fCLK = 2MHz, and VREF = +2.5V, unless otherwise noted. INTEGRAL NONLINEARITY vs INPUT VOLTAGE INTEGRAL NONLINEARITY vs INPUT VOLTAGE 0.0010 0.0006 0.0004 fCLK = 2MHz Buffer Off −40_ C 0.0008 0.0006 +25_C IN L (% o f FSR ) IN L (% o f F SR ) 0.0002 0 −0.0002 +85_ C −0.0004 −0.0006 0.0004 +25_C 0.0002 0 +85_C −0.0002 −0.0004 −0.0006 −0.0008 −0.0010 f CLK = 2MHz Buffer On −40_C −0.0008 −5 −4 −3 −2 −1 0 1 2 3 4 −0.0010 −3.5 5 −2.5 −1.5 Figure 7 INTEGRAL NONLINEARITY vs INPUT VOLTAGE fCLK = 4MHz Buffer Off −40_ C 3.5 IN L (% of F SR ) +25_ C 0.0005 +25_ C 0 +85_ C 0.0005 +85_C 0 −0.0005 −0.0010 −0.0010 −5 −4 −3 −2 −1 0 1 2 3 4 5 −0.0015 −3.5 −2.5 Figure 9 Noise (ppm of FSR, rms) Input Voltage, VIN (V) Figure 11 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 0 −2.0 2.5 3.5 fCLK = 2MHz Buffer Off 0.5 −2.5 1.5 1.5 1.0 −3.0 0.5 NOISE vs INPUT VOLTAGE fCLK = 2MHz Buffer On −3.5 −0.5 Figure 10 NOISE vs INPUT VOLTAGE 1.5 −1.5 Input Voltage, VIN (V) Input Voltage, VIN (V) Noise (ppm of FSR, rms) 2.5 f CLK = 4MHz Buffer On 0.0010 −40_C IN L (% of FS R ) 1.5 INTEGRAL NONLINEARITY vs INPUT VOLTAGE 0.0015 0.0010 −0.0015 0.5 Figure 8 0.0015 −0.0005 −0.5 Input Voltage, VIN (V) Input Voltage, VIN (V) 1.0 0.5 0 −5 −3 −1 1 3 5 Input Voltage, VIN (V) Figure 12 7 www.ti.com SBAS286A − JUNE 2003 − REVISED MARCH 2004 as shown in Table 1. The ADS1224 accepts differential input signals, but can also measure unipolar signals. When measuring unipolar (or single-ended signals) with respect to ground, connect the negative input (AINNx) to ground and connect the input signal to the positive input (AINPx). Note that when the ADS1224 is configured this way, only half of the converter full-scale range is used since only positive digital output codes are produced. An input buffer can be selected to increase the input impedance of the A/D converter with the BUFEN pin. OVERVIEW The ADS1224 is an A/D converter comprised of a delta-sigma modulator followed by a digital filter. A mux allows for one of four input channels to be selected. A buffer can also be selected to increase the input impedance. The modulator measures the differential input signal VIN = (AINP – AINN) against the differential reference VREF = (VREFP – VREFN). Figure 13 shows a conceptual diagram of the device. The differential reference is scaled internally so that the full-scale input range is ±2VREF. The digital filter receives the modulator signal and provides a low-noise digital output. A 2-wire serial interface indicates conversion completion and provides the user with the output data. Table 1. Input Channel selection with MUX0 and MUX1 DIGITAL PINS ANALOG INPUTS (AINPx, AINNx) The input signal to be measured is applied to the input pins AINPx and AINNx. The positive internal input is generalized as AINP, and the negative internal input is generalized as AINN. The signal is selected though the input mux, which is controlled by pins MUX0 and MUX1, TEMPEN MUX1 POSITIVE INPUT NEGATIVE INPUT 0 0 AINP1 AINN1 0 1 AINP2 AINN2 1 0 AINP3 AINN3 1 1 AINP4 AINN4 VREFP VREFN − + Σ Temp Sensor AINP3 AINN3 CLK VREF AINP1 AINN1 AINP2 AINN2 SELECTED ANALOG INPUTS MUX0 2 2VREF AINP Mux Buffer AINN Σ VIN ∆Σ Modulator Digital Filter and Serial Interface AINP4 AINN4 MUX0 MUX1 BUFEN Figure 13. Conceptual Diagram of the ADS1224 8 SCLK DRDY/DOUT www.ti.com SBAS286A − JUNE 2003 − REVISED MARCH 2004 Analog Input Measurement without the Input Buffer With the buffer disabled by setting the BUFEN pin low, the ADS1224 measures the input signal using internal capacitors that are continuously charged and discharged. Figure 14 shows a simplified schematic of the ADS1224 input circuitry, with Figure 15 showing the on/off timings of the switches. The S1 switches close during the input sampling phase. With S1 closed, CA1 charges to AINP, CA2 charges to AINN, and CB charges to (AINP – AINN). For the discharge phase, S1 opens first and then S2 closes. CA1 and CA2 discharge to approximately AVDD/2 and CB discharges to 0V. This two-phase sample/discharge cycle repeats with a frequency of fCLK/32 (62.5kHz for fCLK = 2MHz). ESD Protection AVDD/2 AVDD CA1 3pF AINP S1 AINPx S2 AINN S1 AINNx S2 ZeffA = tSAMPLE/CA1 = 6MΩ (1) AINPx ZeffB = tSAMPLE/CB = 3MΩ (1) AINNx ZeffA = tSAMPLE/CA2 = 6MΩ (1) AVDD/2 NOTE: (1) fCLK = 2MHz. Figure 16. Effective Analog Input Impedances with the Buffer Off ESD diodes protect the inputs. To keep these diodes from turning on, make sure the voltages on the input pins do not go below GND by more than 100mV, and likewise do not exceed AVDD by 100mV: GND – 100mV < (AINP, AINN) < AVDD + 100mV CB 6pF Mux AVDD/2 CA2 3pF AVDD AVDD/2 Figure 14. Simplified Input Structure with the Buffer Turned Off Analog Input Measurement with the Input Buffer When the buffer is enabled by setting the BUFEN pin high, a low-drift, chopper-stabilized input buffer is used to achieve very high input impedance. The buffer charges the input sampling capacitors, thus removing the load from the measurement. Because the input buffer is chopper-stabilized, the charging of parasitic capacitances causes the charge to be carried away, as if by resistance. The input impedance can be modeled by a single resistor, as shown in Figure 17. The impedance scales inversely with fCLK frequency, as in the nonbuffered case. tSAMPLE = 32/fCLK ON S1 OFF AINP ON S2 OFF Figure 15. S1 and S2 Switch Timing for Figure 14 The constant charging of the input capacitors presents a load on the inputs that can be represented by effective impedances. Figure 16 shows the input circuitry with the capacitors and switches of Figure 14 replaced by their effective impedances. These impedances scale inversely with fCLK frequency. For example, if fCLK frequency is reduced by a factor of 2, the impedances will double. 1.2GΩ (1) AINN NOTE: (1) fCLK = 2MHz. Figure 17. Effective Analog Input Impedances with the Buffer On Note that the analog inputs (listed in the Electrical Characteristics table as Absolute Input Range) must remain between GND + 0.05V to AVDD − 1.5V. Exceeding this range degrades linearity and results in performance outside the specified limits. 9 www.ti.com SBAS286A − JUNE 2003 − REVISED MARCH 2004 TEMPERATURE SENSOR On-chip diodes provide temperature-sensing capability. By setting the TEMPEN pin high, the selected analog inputs are disconnected and the inputs to the A/D converter are connected to the anodes of two diodes scaled to 1x and 64x in current and size inside the mux, as shown in Figure 18. By measuring the difference in voltage of these diodes, temperature changes can be inferred from a baseline temperature. Typically, the difference in diode voltages is 106mV at 25°C, with a temperature coefficient of 360µV/°C. A similar structure is used in the MSC1210 for temperature measurement. For more information, see TI application report SBAA100, Using the MSC121x as a High-Precision Intelligent Temperature Sensor, available for download at www.ti.com. VOLTAGE REFERENCE INPUTS (VREFP, VREFN) The voltage reference used by the modulator is generated from the voltage difference between VREFP and VREFN: VREF = VREFP – VREFN. The reference inputs use a structure similar to that of the analog inputs. A simplified diagram of the circuitry on the reference inputs is shown in Figure 19. The switches and capacitors can be modeled with an effective impedance of: ǒt 2 Ǔń16pF + 500kW sample where fCLK = 2MHz. VREFP VREFN TEMPEN AVDD 8I AVDD ESD Protection 1I Self Gain Cal 16pF AINP AINN 1X AVDD Zeff = 500kΩ(1) AINP AINN 8X (1) fCLK = 2MHz AINP1 Figure 19. Simplified Reference input Circuitry AINN1 AINP2 ESD diodes protect the reference inputs. To prevent these diodes from turning on, make sure the voltages on the reference pins do not go below GND by more than 100mV, and likewise, do not exceed AVDD by 100mV: AINN2 AINP3 AINN3 AINP4 AINN4 GND – 100mV < (VREFP, VREFN) < AVDD + 100mV MUX0 MUX1 Figure 18. Measurement of the Temperature Sensor in the Input Multiplexer 10 During self gain calibration, all the switches in the input multiplexer are opened, VREFN is internally connected to AINN, and VREFP is connected to AINP. The input buffer may be disabled or enabled during calibration. When the buffer is disabled, the reference pins will be driving the circuitry shown in Figure 9 during self gain calibration, resulting in increased loading. To prevent this additional loading from introducing gain errors, make sure the circuitry driving the reference pins has adequate drive capability. When the buffer is enabled, the loading on the reference pins will be much less, but the buffer will limit the www.ti.com SBAS286A − JUNE 2003 − REVISED MARCH 2004 For best performance, VREF should be AVDD/2, but it can be raised as high as AVDD. When VREF exceeds AVDD/2, it is not possible to reach the full-scale digital output value corresponding to ±2VREF, since this requires the analog inputs to exceed the power supplies. For example, if VREF = AVDD = 5V, the positive full-scale signal is 10V. The maximum positive input signal that can be supplied before the ESD diodes turn on is when AINP = 5.1V and AINN = –0.1V, resulting in VIN = 5.2V. Therefore, it is not possible to reach the positive (or negative) full-scale readings in this configuration. The digital output codes are limited to approximately one half of the entire range. For best performance, bypass the voltage reference inputs with a 0.1µF capacitor between VREFP and VREFN. Place the capacitor as close as possible to the pins. CLOCK INPUT (CLK) This digital input supplies the system clock to the ADS1224. The CLK frequency can be increased to speed up the data rate. CLK must be left running during normal operation. It may be turned off during Standby mode to save power, but this is not required. The CLK input may be driven with 5V logic, regardless of the DVDD or AVDD voltage. Minimize the overshoot and undershoot on CLK for the best analog performance. A small resistor in series with CLK (10Ω to 100Ω) can often help. CLK can be generated from a number of sources including standalone crystal oscillators and microcontrollers. the pin can be forced high with an additional SCLK. It will then stay high until new data is ready. This is useful when polling on the status of DRDY/DOUT to determine when to begin data retrieval. SERIAL CLOCK INPUT (SCLK) This digital input shifts serial data out with each rising edge. As with CLK, this input may be driven with 5V logic regardless of the DVDD or AVDD voltage. There is hysteresis built into this input, but care should still be taken to ensure a clean signal. Glitches or slow-rising signals can cause unwanted additional shifting. For this reason, it is best to make sure the rise-and-fall times of SCLK are less than 50ns. FREQUENCY RESPONSE The ADS1224 frequency response for fCLK = 2MHz is shown in Figure 20. The frequency response repeats at multiples of the modulator sampling frequency of 62.5kHz. The overall response is that of a low-pass filter with a −3db cutoff frequency of 31.5Hz. As shown, the ADS1224 does a good job attenuating out to 60kHz. For the best resolution, limit the input bandwidth to less than this value to keep higher frequency noise from affecting performance. Often, a simple RC filter on the ADS1224 analog inputs is all that is needed. 0 −20 Gain (dB) allowable voltage range on VREFP and VREFN during self or self gain calibration as the reference pins must remain within the specified input range of the buffer in order to establish proper gain calibration. −40 −60 DATA READY/DATA OUTPUT (DRDY/DOUT) This digital output pin serves two purposes. First, it indicates when new data is ready by going LOW. Afterwards, on the first rising edge of SCLK, the DRDY/DOUT pin changes function and begins outputting the conversion data, most significant bit (MSB) first. Data is shifted out on each subsequent SCLK rising edge. After all 24 bits have been retrieved, −80 −100 0 31250 62500 Input Frequency (Hz) Figure 20. Frequency Response 11 www.ti.com SBAS286A − JUNE 2003 − REVISED MARCH 2004 To help see the response at lower frequencies, Figure 21 illustrates the response out to 1kHz. Notice that signals at multiples of 120Hz are rejected. The ADS1224 data rate and frequency response scale directly with CLK frequency. For example, if fCLK increases from 2MHz to 4MHz, the data rate increases from 120SPS to 240SPS, while the notches increase from 120Hz to 240Hz. 0 Gain (dB) −20 −40 −60 −80 0 −100 30 Gain (dB) −20 40 50 60 70 −40 Figure 22. Frequency Response Near 50Hz and 60Hz with fCLK = 910kHz −60 SETTLING TIME −80 After changing the input multiplexer, selecting the input buffer, or using temperature sensor, the first data is fully settled. In the ADS1224, the digital filter is allowed to settle after toggling any of the MUX0, MUX1, BUFEN, or TEMPEN pins. Toggling of any of these digital pins will cause the input to switch to the proper channel, start conversions, and hold the DRDY/DOUT line high until the digital filter is fully settled. For example, if MUX0 changes from low to high, selecting a different input channel, DRDY/DOUT immediately goes high and the conversion process restarts. DRDY/DOUT goes low when fully settled data is ready for retrieval. There is no need to discard any data. Figure 23 shows the timing of the DRDY/DOUT line as the input multiplexer changes. −100 0 100 200 300 400 500 600 700 800 900 1k Input Frequency (Hz) Figure 21. Frequency Response to 1kHz Rejecting 50Hz or 60Hz noise is as simple as choosing the clock frequency. If simultaneous rejection of 50Hz and 60Hz noise is desired, fCLK = 910kHz can be chosen. The data rate becomes 54.7sps and the frequency response of the ADS1224 rejects the 50Hz and 60Hz noise to below 60dB. The frequency response of the ADS1224 near 50Hz and 60Hz with fCLK = 910kHz is shown in Figure 22. MUX0 Abrupt change in internal VIN due to status change (for example, switch channels, temp sensor, buffer enable) VIN t1 ADS1224 holds DRDY/DOUT until digital filter settles Fully settled data ready DRDY/DOUT DRDY/DOUT suppressed after status change SYMBOL t1(1) DESCRIPTION MIN MAX UNITS Settling time (DRDY/DOUT held high) after a change in any of the MUX0, MUX1, BUFEN, or TEMPEN pins 25.9 26.4 ms (1) Values given for fCLK = 2MHz. For different fCLK frequencies, scale proportional to CLK period. Figure 23. Example of Settling Time After Changing the Input Multiplexer 12 80 Input Frequency (Hz) www.ti.com SBAS286A − JUNE 2003 − REVISED MARCH 2004 The ADS1224 uses a Sinc3 digital filter to improve noise performance. Therefore, in certain instances, large changes in input will require settling time. For example, an external multiplexer in front of the ADS1224 can put large changes in input voltage by simply switching input channels. Abrupt changes in the input will require three data cycles to settle. When continuously converting, four readings may be necessary to settle the data. If the change in input occurs in the middle of the first conversion, three more full conversions of the fully settled input will be required to get fully settled data. Discard the first three readings because they will contain only partially− settled data. Figure 24 illustrates the settling time for the ADS1224 in Continuous Conversion mode. If the input is known to change abruptly, the mux can be quickly switched to an alternate channel and quickly switched back to the original channel. By toggling the mux, the ADS1224 resets the digital filter and initiates a new conversion. During this time, the DRDY/DOUT line is held high until fully-settled data is available. DATA FORMAT The ADS1224 outputs 24 bits of data in binary two’s complement format. The least significant bit (LSB) has a weight of (2VREF)/(223 – 1). The positive full-scale input produces an output code of 7FFFFFh and the negative full-scale input produces an output code of 800000h. The output clips at these codes for signals exceeding full-scale. Table 2 summarizes the ideal output codes for different input signals. Table 2. Ideal Output Code vs Input Signal INPUT SIGNAL VIN (AINP − AINN) IDEAL OUTPUT CODE(1) w +2V REF 7FFFFFh +2V REF 000001h 2 23 * 1 0 000000h −2V REF FFFFFFh 2 23 * 1 ǒ2 2 * 1 Ǔ v −2VREF 23 800000h 23 (1) Excludes effects of noise, INL, offset, and gain errors. DATA RETRIEVAL The ADS1224 continuously converts the analog input signal. To retrieve data, wait until DRDY/DOUT goes low, as shown in Figure 25. After this occurs, begin shifting out the data by applying SCLKs. Data is shifted out MSB first. It is not required to shift out all 24 bits of data, but the data must be retrieved before the new data is updated (see t2) or else it will be overwritten. Avoid data retrieval during the update period. DRDY/DOUT remain at the state of the last bit shifted out until it is taken high (see t6), indicating that new data is being updated. To avoid having DRDY/DOUT remain in the state of the last bit, shift a 25th SCLK to force DRDY/DOUT high (see Figure 26). This technique is useful when a host controlling the ADS1224 is polling DRDY/DOUT to determine when data is ready. Abrupt change in external VIN VIN Start of conversion DRDY/DOUT First Conversion; includes unsettled VIN Second Conversion; VIN settled, but digital filter unsettled Third Conversion; VIN settled, but digital filter unsettled Fourth Conversion; VIN and digital filter both settled Conversion time Figure 24. Settling Time in Continuous Conversion Mode 13 www.ti.com SBAS286A − JUNE 2003 − REVISED MARCH 2004 Data New Data Ready Data Ready MSB DRDY/DOUT 23 LSB 22 21 0 t4 t5 t2 t3 t6 1 SCLK 24 t3 t7 SYMBOL DESCRIPTION t2 t3 t4(1) t5 t6(1) t7(1) MIN DRDY/DOUT low to first SCLK rising edge SCLK positive or negative pulse width SCLK rising edge to new data bit valid: propogation delay SCLK rising edge to old data bit valid: hold time Data updating; no readback allowed Conversion time (1/data rate) MAX 0 100 50 0 48 8.32 8.32 UNITS ns ns ns ns µs ms (1) Values given for fCLK = 2MHz. For different fCLK frequencies, scale proportional to CLK period. Figure 25. Data Retrieval Timing Data Data Ready New Data Ready DRDY/DOUT SCLK 23 1 22 21 0 24 25 25th SCLK to Force DRDY/DOUT High Figure 26. Data Retrieval with DRDY/DOUT Forced High Afterwards 14 www.ti.com SBAS286A − JUNE 2003 − REVISED MARCH 2004 SELF-CALIBRATION STANDBY MODE Self-calibration can be initiated at any time, although in many applications the ADS1224 drift performance is so good that the self-calibration performed automatically at power-up is all that is needed. To initiate self-calibration, apply at least two additional SCLKs after retrieving 24 bits of data. Figure 27 shows the timing pattern. The 25th SCLK will send DRDY/DOUT high. The falling edge of the 26th SCLK will begin the calibration cycle. Additional SCLK pulses may be sent after the 26th SCLK; however, activity on SCLK should be minimized during calibration for best results. Standby mode dramatically reduces power consumption (typically < 1µW with CLK stopped) by shutting down all of the active circuitry. To enter Standby mode, simply hold SCLK high after DRDY/DOUT goes low, as shown in Figure 28. Standby mode can be initiated at any time during readback; it is not necessary to retrieve all 24 bits of data beforehand. When t11 has passed with SCLK held high, Standby mode will activate. DRDY/DOUT stays high when Standby mode begins. SCLK must remain high to stay in Standby mode. To exit Standby mode (wakeup), set SCLK low. The first data after exiting Standby mode is valid. It is not necessary to stop CLK during Standby mode, but doing so will further reduce the digital supply current. When the calibration is complete, DRDY/DOUT goes low, indicating that new data is ready. There is no need to alter the analog input signal applied to the ADS1224 during calibration; the input pins are disconnected within the A/D converter and the appropriate signals are applied internally and automatically. The first conversion after a calibration is fully settled and valid for use. The time required for a calibration depends on two independent signals: the falling edge of SCLK and an internal clock derived from CLK. Variations in the internal calibration values will change the time required for calibration (t8) within the range given by the min/max specs. t11 and t12 described in the next section are affected likewise. Standby Mode With Self-Calibration Self-calibration can be set to run immediately after exiting Standby mode. This is useful when the ADS1224 is put in Standby mode for long periods of time and self-calibration is desired afterwards to compensate for temperature or supply voltage changes. To force a self-calibration with Standby mode, shift 25 bits out before taking SCLK high to enter Standby mode. Self-calibration then begins after wakeup. Figure 29 shows the appropriate timing. Note the extra time needed after wakeup for calibration before data is ready. The first data after Standby mode with self-calibration is fully settled and can be used. Data Ready After Calibration DRDY/DOUT 23 22 21 0 23 Calibration Begins SCLK 1 24 25 26 t8 SYMBOL DESCRIPTION MIN MAX UNITS t8(1) First data ready after calibration 77.1 77.9 ms (1) Values given for fCLK = 2MHz. For different fCLK frequencies, scale proportional to CLK period. Figure 27. Self-Calibration Timing 15 www.ti.com SBAS286A − JUNE 2003 − REVISED MARCH 2004 Data Ready Standby Mode DRDY/DOUT 23 22 21 0 23 Start Conversion SCLK 1 24 t9 t10 t11 SYMBOL DESCRIPTION t9(1) t10(1) t11(1) MIN SCLK high after DRDY/DOUT goes low to activate Standby mode MAX UNITS 0 8.272 ms Standby mode activation time 8.272 8.304 ms Data ready after exiting Standby mode 27.7 28.1 ms (2) Values given for fCLK = 2MHz. For different fCLK frequencies, scale proportional to CLK period. Figure 28. Standby Mode Timing (can be used for single conversions) Data Ready After Calibration Standby Mode DRDY/DOUT SCLK 23 22 21 0 1 24 23 Begin Calibration 25 t 12 t10 SYMBOL DESCRIPTION MIN MAX UNITS t12(1) Data ready after exiting Standby mode and calibration 78.8 79.7 ms (1) Values given for fCLK = 2MHz. For different fCLK frequencies, scale proportional to CLK period. Figure 29. Standby Mode with Self-Calibration Timing (can be used for single conversions) SINGLE CONVERSIONS When only single conversions are needed, Standby mode can be used to start and stop the ADS1224. To make a single conversion, first enter the Standby mode holding SCLK high. Now, when ready to start the conversion, take SCLK low. The ADS1224 wakes up and begins the conversion. Wait for DRDY/DOUT to go low, and then retrieve the data. Afterwards, take SCLK 16 high to stop the ADS1224 from converting and re-enter Standby mode. Continue to hold SCLK high until ready to start the next conversion. Operating in this fashion greatly reduces power consumption since the ADS1224 is shut down while idle between conversions. Self-calibrations can be performed prior to the start of the single conversions by using the waveform shown in Figure 29. www.ti.com SBAS286A − JUNE 2003 − REVISED MARCH 2004 APPLICATIONS INFORMATION GENERAL RECOMMENDATIONS The ADS1224 is a high-resolution A/D converter. Achieving optimal device performance requires careful attention to the support circuitry and printed circuit board (PCB) design. Figure 30 shows the basic connections for the ADS1224. As with any precision circuit, be sure to use good supply bypassing capacitor techniques. A smaller value ceramic capacitor in parallel with a larger value tantulum capacitor works well. Place the capacitors, in particular the ceramic ones, close to the supply pins. Use a ground plane and tie the ADS1224 GND pin and bypass capacitors directly to it. Avoid ringing on the digital inputs. Small resistors (≈100Ω) in series with the digital pins can help by controlling the trace impedance. Place these resistors at the source end. Pay special attention to the reference and analog inputs. These are the most critical circuits. Bypass the voltage reference using similar techniques to the supply voltages. The quality of the reference directly affects the overall accuracy of the device. Make sure to use a low noise and low drift reference such as the REF1004. Often, only a simple RC filter is needed on the inputs. This circuits limits the higher frequency noise. Avoid low-grade dielectrics for the capacitors and place them as close as possible to the input pins. Keep the traces to the input pins short, and carefully watch how they are routed on the PCB. After the power supplies and reference voltage have stabilized, issue a self-calibration command to minimize offset and gain errors. +5V +5V 10µF 0.1µF 0.1µF 10µF 0.1µF 10µF ADS1224 1 100Ω 2 100Ω 100Ω 3 4 100Ω 100Ω 5 6 100Ω 100Ω 7 8 9 220pF 301Ω 10 DVDD AVDD SCLK VREFP CLK DRDY/DOUT VREFN GND MUX0 AINN1 MUX1 AINP1 TEMPEN AINN2 BUFEN AINP2 AINP4 AINN3 AINN4 AINP3 20 19 +2.5V Reference 18 17 16 15 14 13 Same as shown for AINP4 and AINN4. 12 11 VINP 301Ω 0.1µF VINN 220pF Figure 30. Basic Connections 17 www.ti.com SBAS286A − JUNE 2003 − REVISED MARCH 2004 MULTICHANNEL SYSTEMS Multiple ADS1224s can be operated in parallel to measure multiple input signals. Figure 31 shows an example of an eight-channel system. For simplicity, the supplies and reference circuitry are not shown. The same CLK signal should be applied to all devices. To synchronize the ADS1224s, connect the same SCLK signal to all devices. Then place all the devices in Standby mode. Afterwards, starting a conversion will synchronize all the ADS1224s; that is, they will sample the input signals simultaneously. The DRDY/DOUT outputs will go low at approximately the same time after synchronization. When reading data from the devices, the data appears in parallel on DRDY/DOUT as a result of the common SCLK connection. The falling edges of DRDY/DOUT, indicating that new data is ready, will vary with respect to each other no more than time t13. This variation is due to possible differences in the ADS1224 internal calibration settings. To account for this, when using multiple devices, either wait for t13 to pass after seeing one DRDY/DOUT go low, or wait until all DRDY/DOUTs have gone low before retrieving data. Note that changing channels (using the MUX0 and MUX1 pins), or using the input buffer (BUFEN) or the temperature sensor (TEMPEN), may require more care to settle the digital filter. For example, if the MUX0 pin is toggled on one device and not the other, the DRDY/DOUT line will be held high until the conversion settles on the first device. The latter device will continue conversions through this time. See the Settling Time section of this datasheet for further details. ADS1224 AINP1 CLK AINN1 … Inputs SCLK AINP4 AINN4 DRDY/DOUT MUX Select OUT1 MUX0 MUX1 OUT1 ADS1224 t13 AINP1 AINN1 OUT2 … Inputs CLK AINP4 SCLK AINN4 DRDY/DOUT MUX Select OUT2 MUX0 MUX1 CLK and SCLK Sources SYMBOL t13(1) DESCRIPTION MIN Difference between DRDY/DOUTs going low in multichannel systems (1) Values given for fCLK = 2MHz. For different fCLK frequencies, scale proportional to CLK period. Figure 31. Example of Using Multiple ADS1224s in Parallel 18 MAX UNITS ±0.8 ms www.ti.com SBAS286A − JUNE 2003 − REVISED MARCH 2004 VESSEL WEIGHING WITH FOUR LOAD CELLS In vessel weighing systems, four load cells are frequently employed to measure the weight of the vessel and its contents. The output of the load cells are usually combined in an external summing junction box that balances the load cells’ sensitivities for accuracy. The four differential inputs of the ADS1224 allow for direct measurement of the four load cells individually. In this way, the mechanical adjustments performed inside the summing junction box are eliminated and are replaced by digital summing of the load cells in software. Figure 32 shows an example of such a system. The reference voltage of the ADS1224 is derived by dividing down the AVDD supply voltage to 2.5V, while the load cell has a positive full-scale output of 10mV. In the figure, a low drift, dual op amp (OPA2335) provides a differential in/differential out amplifier with a gain of 499V/V (G = 1 + 2RF/RG). Gain on the load cell gives the amplifier a full-scale output of 5V. Each load cell input uses an external amplifier. The outputs of the amplifiers connect to the analog inputs of the ADS1224 through a low-pass filter. The cut-off frequency is set to 360Hz, allowing full settling in a single measurement cycle. A lower cut-off frequency can be used to reduce noise from mechanical vibrations, but at the expense of filter settling time. The internal buffer of the ADS1224 is disabled, allowing the VREFN pin to be grounded. Note that the loading from the reference inputs will change the effective reference voltage. The effective input impedance into the VREFP and VREFN pins will lower the reference voltage seen at these pins. At 2MHz, input impedance is approximately 500kΩ. For the reference circuit shown in Figure 32, this lowers the effective reference voltage by approximately 0.1%. 5V +3V 0.1 µ F 0.1 µ F 1µF 0.1 µ F R FI F ilter 1k Ω(1) AVDD DVDD VREFP 0.1 µ F 350 Ω Load Cell DVCC AVCC BUF EN 1k Ω(1) 5V Shielded Cable TEMPEN VREFN 100 Ω R FI F ilter G=1 + R FI F ilter 1/2 O PA2335 1k Ω AD S1224 MSP430F41x AINP1 2R F RG R G(1) 10 Ω R F(1) 2.49k Ω 0.22 µ F AINN 1 AINP2 R F(1) 2.49k Ω NO TE: (1) Low−drift resistors. 100 Ω R FI F ilter 1k Ω 1/2 O PA2335 C LK P1.1/TA0/M CLK AINN2 SC LK P1.2/TA1 AINP3 DRDY/DO UT P1.0/TA0 AINN3 MU X0 P1.6/C A0 AINP4 MU X1 P1.7/C A1 AINN4 G ND XIN XO UT/TCLK GND Replicate for Channels 2, 3 and 4 Figure 32. Vessel Weighing System with Four Load Cells 19 www.ti.com SBAS286A − JUNE 2003 − REVISED MARCH 2004 SUMMARY OF SERIAL INTERFACE WAVEFORMS DRDY/DOUT 23 22 21 0 MSB SCLK LSB 1 24 (a) Data Retrieval DRDY/DOUT 23 SCLK 22 21 0 1 24 25 (b) Data Retrieval with DRDY/DOUT Forced High Afterwards Data Ready After Calibration DRDY/DOUT 23 SCLK 22 21 0 1 24 Begin Calibration 25 26 (c) Self−Calibration Data Ready Standby Mode 23 DRDY/DOUT 22 21 0 Start Conversion SCLK 1 24 (d) Standby Mode/Single Conversions Data Ready After Calibration Standby Mode DRDY/DOUT 23 22 21 0 Begin Calibration SCLK 1 24 25 (e) Standby Mode/Single Conversions with Self−Calibration Figure 33. Summary of Serial Interface Waveforms 20 PACKAGE OPTION ADDENDUM www.ti.com 29-Mar-2004 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY ADS1224IPWR ACTIVE TSSOP PW 20 2500 ADS1224IPWT ACTIVE TSSOP PW 20 250 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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