BB DSD1700E

®
DSD1700
DSD
170
0
For most current data sheet and other product
information, visit www.burr-brown.com
Direct Stream Digital™ (DSD™)
Audio
DIGITAL-TO-ANALOG CONVERTER
TM
FEATURES
APPLICATIONS
● DIRECT TRANSFER OF DSD DATA
STREAM TO ANALOG OUTPUT SIGNAL
● DUAL DIFFERENTIAL ANALOG FIR FILTER
● DIRECT, CMOS LOGIC INTERFACE TO
DSDTM DECODER IC
Data Clock: 2.8224 MHz (64 • 44.1kHz)
System Clock: 11.2896 MHz (256 • 44.1kHz)
● EXCELLENT DYNAMIC PERFORMANCE
THD+N: 0.001% (typ)
Dynamic Range: 110dB (typ)
SNR: 110dB (typ)
Frequency Response (–3dB): 100kHz
● SINGLE +5V SUPPLY OPERATION
● SMALL 28-LEAD SSOP PACKAGE
● SUPER AUDIO CD (SACD™) PLAYERS
● PROFESSIONAL DSD PROCESSORS
● PROFESSIONAL DSD CONSOLES
DESCRIPTION
The DSD1700 is a unique digital-to-analog converter
designed for DSD audio applications. The DSD1700
consists of a single-channel, 8-tap analog FIR filter
constructed using a double differential circuit architecture, ensuring excellent dynamic performance and
high power- supply noise rejection. The DSD1700
also includes the necessary logic required to interface
directly to a DSD decoder IC.
The overall features and performance of the DSD1700
make it an ideal choice for high-performance Super
Audio CD players and DSD studio applications.
All trademarks are property of their respective owners.
VDD
PHASE
DATA
DSD I/F
Duty
Generator
Analog FIR
(HOT/P)
IOUTHP
Analog FIR
(HOT/N)
IOUTHN
Analog FIR
(COLD/P)
IOUTCP
Analog FIR
(COLD/N)
IOUTCN
Shift Register
(HOT)
VDD
RST
DCK
SCK
Timing
Generator
VDD
DGND
VCC
Power
Supply
Duty
Generator
AGND
Shift Register
(COLD)
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©
1999 Burr-Brown Corporation
PDS-1555A
Printed in U.S.A. December, 1999
SPECIFICATIONS
All specifications TA = +25°C, VDD = VCC = 5.0V, fS = 44.1kHz, data clock = 64fS, system clock = 256fS, unless otherwise specified. (Although the sampling frequency
of Direct Stream Digital is 2.8224MHz, for convenience, in this specification sheet, it is described that the sampling frequency (fS) is 44.1kHz and the 2.8224MHz
clock is 64fS).
DSD1700E
PARAMETER
CONDITIONS
INPUT CLOCK
Data Clock Frequency (DCK)
System Clock Frequency (SCK)
MIN
64fS
256fS
SCK AC REQUIREMENT(1)
Input Clock Duty Cycle
DIGITAL INPUT
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
MHz
MHz
50
%
0.3VDD
±10
±10
–120
with 30kHz GIC Filter
with 30kHz GIC Filter
with 30kHz GIC Filter
POWER SUPPLY REQUIREMENTS
Voltage Range
Supply Current
ICC+IDD
Power Dissipation
4.5
5
5.5
27.5
–25
–55
θJA
±10
±1
0.001
110
110
100
VCC, VDD
VCC = VDD = 5.0V
VCC = VDD = 5.0V
28-Pin SSOP
UNITS
2.8224
11.2896
4.1VCC
±4
±0.1
2
DYNAMIC PERFORMANCE(5)
THD+N, VOUT = 0dB
Dynamic Range
Signal-to-Noise Ratio
Frequency Response, –3dB
MAX
0.7VDD
VIH
VIL
IIH
IIL(2)
IIL(3)
ANALOG OUTPUT(5)
Full-Scale Voltage
Gain Error
Offset Error
Output Impedance(4)
TEMPERATURE RANGE
Operating
Storage
Thermal Resistance
TYP
100
V
V
µA
µA
µA
Vp-p
% of FSR
% of FSR
kΩ
%
dB
dB
kHz
5.5
8.0
40
VDC
mA
mW
+85
+125
°C
°C
°C/W
NOTES: (1) See description of system clock in the Functional Description section of this data sheet. (2) Pins 26, 27, 28: DATA. DCK. SCK. (3) Pins 3, 4: RST, PHASE
(with internal pull-up). (4) Pins 13, 14, 15, 16: IOUTHN, IOUTCP, IOUTCN, IOUTHP. (5) Measure DSD signal modulated fSIG = 1kHz with 50% scaling factor through
standard differential to single-ended converter (see Figure 10) using Audio Precision System II in rms mode with 20kHz LPF and 400Hz HPF.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
DSD1700
2
PIN CONFIGURATION
PIN ASSIGNMENTS
Top View
SSOP
DGND
1
28
SCK
VDD
2
27
DCK
RST
3
26
DATA
PHASE
4
25
AGND
AGND
5
24
VCC
VCC
6
23
AGND
AGND
7
22
VCC
VCC
8
21
VCC
VCC
9
20
AGND 10
PIN
NAME
I/O
DESCRIPTION
1
DGND
—
Digital Ground
2
VDD
—
Digital Power Supply: +5V
3
RST
IN
Reset Control Input, Active LOW(1)
4
PHASE
IN
Select data phase
(LOW = Normal; HIGH = Invert)
5
AGND
—
Analog Ground
6
VCC
—
Analog Power Supply: +5V
7
AGND
—
Analog Ground
8
VCC
—
Analog Power Supply: +5V
Analog Power Supply: +5V
9
VCC
—
10
AGND
—
Analog Ground
11
VCC
—
Analog Power Supply: +5V
Analog Ground
12
AGND
—
13
IOUTHN
OUT
14
IOUTCP
OUT
Analog Output from DAC (Cold Positive)
15
IOUTCN
OUT
Analog Output from DAC (Cold Negative)
AGND
16
IOUTHP
OUT
19
VCC
17
AGND
—
18
AGND
—
Analog Ground
VCC 11
18
AGND
19
VCC
—
Analog Power Supply: +5V
AGND 12
17
AGND
20
AGND
—
Analog Ground
21
VCC
—
Analog Power Supply: +5V
Analog Power Supply: +5V
DSD1700
Analog Output from DAC (Hot Negative)
Analog Output from DAC (Hot Positive)
Analog Ground
IOUTHN 13
16
IOUTHP
22
VCC
—
IOUTCP 14
15
IOUTCN
23
AGND
—
Analog Ground
24
VCC
—
Analog Power Supply: +5V
25
AGND
—
Analog Ground
26
DATA
IN
Direct Stream Digital Data Input
27
DCK
IN
Data Clock Input
28
SCK
IN
System Clock Input
NOTE: (1) With internal pull-up resistor
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
Voltage(2)
Supply
.............................................................................. +6.5V
Supply Voltage Differences(3) ........................................................... ±0.1V
Ground Voltage Differences(4) .......................................................... ±0.1V
Digital Input Voltage ................................................... –0.3V to VDD +0.3V
Input Current (any pins except supplies) ....................................... ±10mA
Operating Temperature .................................................... –25°C to +85°C
Storage Temperature ..................................................... –55°C to +125°C
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 5s) ................................................. +260°C
Package Temperature (IR reflow, peak, 10s) ............................... +235°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability. (2) VCC, VDD. (3) Among VCC, VDD . (4) Among AGND, DGND.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER
DSD1700E
28-Lead SSOP
324
0°C to +70°C
DSD1700E
"
"
"
"
"
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
DSD1700E
DSD1700E/2K
Rails
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “DSD1700E/2K” will get a single 2000-piece Tape and Reel.
®
3
DSD1700
GENERAL INFORMATION
DECODER INTERFACE
The decoder interface consists of several CMOS logic inputs. The system clock input, SCK (pin 28), operates at
11.2896MHz (256 • 44.1kHz). The data bit clock, DCK
(pin 27), operates at 2.8244 MHz (64 • 44.1kHz) and is the
64x oversampled data clock. The 1-bit, 64x oversampled
data stream is input at DATA (pin 26). DATA and DCK are
synchronized to the SCK falling edge.
The DSD1700 generates HOT and COLD data internally for
use with the double differential analog FIR filter. The
PHASE input (pin 4) is used to determine the polarity of the
HOT and COLD data (normal or inverted). The PHASE
input is synchronized to the rising edge of SCK.
The DSD1700 is designed solely for use in DSD and SACD
applications. It is not compatible with standard CD audio
transports, or DVD/MPEG-2 decoders. Burr-Brown manufacturers a wide array of products for these applications.
Please refer to our audio brochure and product data sheets,
available from our web site (www.burr-brown.com) and
local sales offices.
FUNCTIONAL DESCRIPTION
The concept of Direct Stream Digital (DSD) conversion is
simple. An analog audio input is digitized by a 1-bit, 64x
oversampled delta-sigma modulator. The 1-bit data stream is
then stored and may be transferred to a SACD disc at a later
time. For playback, the 1-bit, 64x oversampled data is then
presented to the DSD1700 directly by a DSD decoder IC.
The DSD1700 then low-pass filters the oversampled data to
reconstruct the original analog audio waveform. The recording and playback functions are illustrated in Figures 1 and 2
respectively.
To perform the digital-to-analog conversion, the DSD1700
includes both the decoder interface logic and an analog FIR
filter. The following paragraphs provide a summary of these
functions.
Analog
Input
Loop Filter
(Noise Shaping
and Integration)
1-Bit
Quantizer
∫
Q
+
–
The RST input (pin 3) is used for system reset purposes.
RST should be High for normal operation, and Low for reset
operation. When RST is held Low, the current outputs of the
analog FIR filter are set to the bipolar zero (BPZ) level. The
RST signal is synchronized to the rising edge of SCK.
TIMING
Figures 3 though 6 show the timing diagrams for the
DSD1700 interface signals. Figure 3 shows the system clock
(SCK) timing requirements. Figure 4 shows the general
timing for the data input. Figures 5 and 6 show the detailed
timing for the DSD data and control data inputs.
Interface
Logic
DSD
Input
(64fS, 1-Bit)
DSD
Output
(64fS, 1-Bit)
Low-Pass
Filter
Analog
Output
LOGIC
FIGURE 2. DSD Playback.
FIGURE 1. DSD Recording.
tSCKH
VIH
High
VIH = 0.7VDD
VIL = 0.3VDD
System Clock
VIL
Low
tSCKL
SYMBOL
tSCKH
tSCKL
1/256 fS
DESCRIPTION
MIN
System Clock Pulse Width High
System Clock Pulse Width Low
10
10
FIGURE 3. System Clock Timing.
RST
SCK (256fS)
DATA
DCK (64fS)
FIGURE 4. Input Signal Timing.
®
DSD1700
4
TYP
MAX
UNITS
ns
ns
SCK
tSCWL
tSCWH
tSCY
DCK
tDCH
tDCS
tDAH
tDAS
DATA
SYMBOL
tSCWH
tSCWL
tSCY
tDCS
tDCH
tDAS
tDAH
DESCRIPTION
MIN
SCK Pulse Width High
SCK Pulse Width Low
SCK Pulse Cycle Time
DCK Setup Time
DCK Hold Time
DATA Setup Time
DATA Hold Time
10
10
TYP
MAX
UNITS
ns
ns
sec
ns
ns
ns
ns
1/(256fS)
15
5
15
5
FIGURE 5. DSD Data Input Timing.
SCK
tSCWH
tSCWL
tSCY
PHASE
tPH
tPS
tRH
tRS
RST
SYMBOL
tSCWH
tSCWL
tSCY
tPS
tPH
tRS
tRH
DESCRIPTION
MIN
SCK Pulse Width High
SCK Pulse Width Low
SCK Pulse Cycle Time
PHASE Setup Time
PHASE Hold Time
RST Setup Time
RST Hold Time
10
10
TYP
1/(256fS)
15
5
15
5
MAX
UNITS
ns
ns
sec
ns
ns
ns
ns
FIGURE 6. Control Data Input Timing.
®
5
DSD1700
ANALOG FIR FILTER
Figure 7. Prior to the analog FIR filters, the duty cycle of the
DSD input signal is set to 75% by the DSD1700’s duty
generators.
The low-pass filter function for the DSD1700 is constructed
by using four 8-tap, analog FIR filters with current outputs.
The four filters include one each for HOT and COLD
positive, and one each for HOT and COLD negative. This is
referred to as a double differential architecture. These filters
use resistors to set the filter coefficients, as shown in
D0
D1
R0
D2
R1
D3
R2
Plots of the analog FIR filter response is shown in Figure 8.
The stop-band attenuation of the filters dictates that additional low-pass filtering is required at the output of the
external current-to-voltage converter circuit (see Figure 10).
D4
R3
D5
R4
D6
R5
D7
R6
R7
IOUT
FIGURE 7. Analog FIR Filter Structure.
FREQUENCY RESPONSE
(DC – 11.2896MHz)
FREQUENCY RESPONSE
(DC – 1.4112MHz)
0
Gain (dB)
Gain (dB)
0
–50
–50
–100
–100
0
705,600
Frequency (Hz)
0
1,411,200
FIGURE 8. Analog FIR Filter Frequency Response.
®
DSD1700
6
5,644,800
Frequency (Hz)
11,289,600
APPLICATIONS INFORMATION
CURRENT-TO-VOLTAGE (I/V)
CONVERTER CIRCUIT
TYPICAL CONNECTIONS
The DSD1700 is a current output device, and requires an
I/V conversion circuit to transform the double-differential
outputs into a usable voltage output. The circuit in Figure 10
is recommended for this purpose. Op amps are OPA134 or
equivalent.
Figure 9 shows the basic connection diagram for the
DSD1700. A significant number of power supply bypass
capacitors are required, and Burr-Brown recommends the
indicated values for optimal performance.
+5V
DSD1700
1
DGND
SCK 28
2
VDD
DCK 27
System Reset
3
RST
DATA 26
Phase Control
4
PHASE
AGND 25
5
AGND
6
VCC
7
AGND
VCC 22
8
VCC
VCC 21
9
VCC
AGND 20
System Clock
C1
Direct
Stream
Digital™
Data
C6
VCC 24
C1
AGND 23
C7
C3
C4
10 AGND
C5
C8
VCC 19
11 VCC
AGND 18
12 AGND
AGND 17
13 IOUTHN
IOUTHP 16
14 IOUTCP
IOUTCN 15
C9
=
Analog
Ground
NOTE: C1 = 0.1µF ceramic and 1-100µF. C2 - C9 = 0.1µF ceramic each and 1-100µF chemical.
FIGURE 9. Basic Connection Diagram.
+18V
0.1µF
1kΩ
100pF
1kΩ
8.2 kΩ
+18V
0.1µF
IOUTCN
220pF
IOUTHP
2
3
+5V
470pF
4.7kΩ
4.7kΩ
1
3
+18V
OPA134
4
2
3
6
OPA134
4
Analog
Out
6
1
0.1µF
7
4.7kΩ
1
8.2 kΩ
–18V
220pF
IOUTCP
1kΩ
7
2
–18V
4.7kΩ
1kΩ
6
OPA134
4
4.7kΩ
470pF
7
4.7kΩ
100pF
IOUTHN
0.1µF
=
Analog
Ground
–18V
FIGURE 10. Recommended I/V Conversion Circuit.
®
7
DSD1700
PRINTED CIRCUIT BOARD LAYOUT
Separate power supplies are recommended for the digital
and analog sections of the board. This prevents the switching
noise present on the digital supply from contaminating the
analog power supply and degrading the dynamic performance of the DSD1700.
A typical PCB floor plan for the DSD1700 is shown in
Figure 11. A ground plane is recommended, with the analog
and digital sections being isolated from one another using a
split in the plane. The DSD1700 should be oriented with the
digital I/O pins facing the ground plane split/cut, allowing
for direct connection to the DSD decoder and control signals
originating from the digital section of the board.
Digital Power
+VD
Analog Power
DGND
AGND +5VA
+VS –VS
VCC
VDD
DSD™ Decoder
and
Control Logic
DGND
DSD1700
Output
Circuits
Digital
Ground
AGND
DIGITAL SECTION
ANALOG SECTION
Return Path for Digital Signals
FIGURE 11. Recommended PCB Layout Technique.
®
DSD1700
8
Analog
Ground