® PCM1704 49% 170 4 FPO PCM 24-Bit, 96kHz BiCMOS Sign-Magnitude DIGITAL-TO-ANALOG CONVERTER TM FEATURES DESCRIPTION ● SAMPLING FREQUENCY (fS): 16kHz to 96kHz The PCM1704 is a precision, 24-bit digital-to-analog converter with exceptionally high dynamic performance. The ultra-low distortion and excellent lowlevel signal performance makes the PCM1704 an ideal candidate for high-end consumer and professional audio applications. When used with a digital interpolation filter, the PCM1704 supports 8X oversampling at 96kHz. ● 8X OVERSAMPLING AT 96kHz ● INPUT AUDIO DATA WORD: 20-, 24-Bit ● HIGH PERFORMANCE: Dynamic Range: K Grade = 112dB typ SNR: 120dB typ THD+N: K Grade = 0.0008% typ ● FAST CURRENT OUTPUT: ±1.2mA/200ns ● GLITCH-FREE OUTPUT ● PIN-PROGRAMMABLE DATA INVERSION ● POWER SUPPLY: ±5V ● SMALL 20-LEAD SO PACKAGE The PCM1704 incorporates a BiCMOS sign-magnitude architecture that eliminates glitches and other nonlinearities around bipolar zero. The PCM1704 is precision laser-trimmed at the factory to minimize differential linearity and gain errors. In addition to high performance audio systems, the PCM1704 is well-suited to waveform synthesis applications requiring very low distortion and noise. BCLK 23-Bit DAC A WCLK DATA Serial Input and Control Logic 23-Bit DAC B 20-BIT IOUT INVERT Bipolar Offset Reference and Servo Power Supply REF DC SERVO DC –VDD DGND +VDD –VCC AGND +VCC BPO DC International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1998 Burr-Brown Corporation SBAS097 PDS-1454C Printed in U.S.A. February, 1999 SPECIFICATIONS All specifications at TA = +25°C, ±VCC = ±VDD = ±5V, fS = 768kHz (96kHz • 8), and 24-bit data, unless otherwise noted. PCM1704U PARAMETER CONDITIONS MIN TYP RESOLUTION MAX 24 DATA FORMAT Audio Data Interface Format Audio Data Code Sampling Frequency (fS) Input Clock Frequency DIGITAL INPUT/OUTPUT Input Logic Level: VIH(1) VIL(1) VIH(2) VIL(2) Input Logic Current: IIH(1) IIL(1) IIH(2) IIL(2) DYNAMIC PERFORMANCE(3) THD+N VO = 0dB VO =–20dB Dynamic Range Signal-to-Noise Ratio Low Level Linearity DC ACCURACY Gain Error Bipolar Zero Error Gain Drift Bipolar Zero Error Drift ANALOG OUTPUT Output Range Output Impedance Settling Time POWER SUPPLY REQUIREMENTS Voltage Range: +VCC = +VDD –VCC = –VDD Combined Supply Current:+ICC –ICC UNITS Bits 20-, 24-Bit, MSB-First Binary Two’s Complement 16 96 25 kHz MHz +2.0 0 –3.0 –5.0 +5.0 +0.8 0 –4.2 V V V V ±10 ±10 ±10 –100 µA µA µA µA 0.0030 0.0025 0.0015 0.020 0.015 0.01 % % % % % % VIH = +VDD VIL = 0V VIH = 0V VIL = –VDD PCM1704U PCM1704U-J PCM1704U-K PCM1704U PCM1704U-J PCM1704U-K EIAJ, A-weighted PCM1704U, U-J PCM1704U-K EIAJ, A-weighted f = 1002Hz at –90dB 0.0025 0.0015 0.0008 0.008 0.007 0.006 102 106 112 110 112 120 ±0.5 0°C to 70°C 0°C to 70°C ±1.0 ±0.5 ±25 ±5 ±0.0003% of FSR, ±1.2mA Step ±1.2 1.0 200 +4.75 –4.75 +VCC = +VDD = +5.0V –VCC = –VDD = –5.0V TEMPERATURE RANGE Operation Storage –25 –55 +5.0 –5.0 5 30 dB dB dB dB ±3.0 ±1.0 % of FSR % of FSR ppm of FSR/°C ppm of FSR/°C mA kΩ ns +5.25 –5.25 8 45 VDC VDC mA mA +85 +125 °C °C NOTES: (1) BCLK, WCLK, DATA. (2) 20BIT, INVERT. (3) Dynamic performance data is tested with 5534 I/V amp with 7.5kΩ feedback resistor. THD+N data is tested by Shibasoku 725C with 30kHz external LPF, 400Hz HPF, average mode. Input signal frequency = 1.1kHz. ® PCM1704 2 PIN CONFIGURATION PIN ASSIGNMENTS TOP VIEW SOIC DATA BCLK 1 20 2 19 –VCC REF DC PIN NAME I/O 1 DATA IN FUNCTION Serial Audio Data Input. 2 BCLK IN Bit Clock Input for Serial Audio Data. 3 NC — No Connection. 4 –VDD — Digital Power, –5V. 5 DGND — Digital Ground. Digital Power, +5V. NC 3 18 NC 6 +VDD — –VDD 4 17 SERVO DC 7 WCLK IN Data Latch Enable Input. DGND 5 16 AGND 8 NC — No Connection. +VDD 6 15 AGND 9 20BIT IN Input Data Word Selection(1). 7 14 10 INVERT IN Input Data Polarity Selection(1). WCLK IOUT 11 +VCC — Analog Power, +5V. NC 8 13 NC 12 BPO DC — Bipolar Offset Decoupling Capacitor. 20BIT 9 12 BPO DC 13 NC — No Connection. INVERT 10 11 +VCC 14 IOUT OUT 15 AGND — 16 AGND — Analog Ground. 17 SERVO DC — Servo Amplifier Decoupling Capacitor. PCM1704U PACKAGE INFORMATION PRODUCT PACKAGE TEMPERATURE RANGE PCM1704U 20-Lead SOIC –25°C to +85°C PACKAGE DRAWING NUMBER(1) 248 Current Output for Audio Signal. Analog Ground. 18 NC — No Connection. 19 REF DC — Band Gap Reference Decoupling Capacitor. 20 –VCC — Analog Power, –5V. NOTE: (1) Internal pull-up resistors. Input level must be a voltage from –VDD to DGND. NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. Supply Voltage, +VDD ,+VCC ............................................................. +6.5V Supply Voltage Differences .............................................................. ±0.1V GND Voltage Differences ................................................................. ±0.1V Digital Input Voltage (BCLK, WCLK, DATA) ............................ DGND –0.3V to (+VDD + 0.3V) (20BIT, INVERT) .................................... –VDD – 0.3V to (DGND + 0.3V) Input Current (any pins except supply pins) ................................... ±10mA Power Dissipation .......................................................................... 300mW Operating Temperature Range ......................................... –25°C to +85°C Storage Temperature ...................................................... –55°C to +125°C Lead Temperature (soldering, 5s) ................................................. +260°C Package Temperature (reflow, 10s) .............................................. +235°C ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ® 3 PCM1704 SPECIFICATIONS All specifications at +25°C, ±VCC and ±VDD = ±5.0V, unless otherwise noted. THD+N vs LEVEL –90dB SIGNAL SPECTRUM 0 –80 10 –20 –90 1 –40 –60 24-Bit Data 0.10 –80 Amplitude (dB) 16-Bit Data 0.1 –100 THD+N (dB) THD+N (%) 100 –110 –120 –130 0.001 –100 0.0001 –100 –90 –140 –120 –80 –70 –60 –50 –40 –30 –20 –10 –150 20.0 2.02k 4.02k 6.01k 8.01k 10.0k 12.0k 14.0k 16.0k 18.0k 20.0k 0 Output Level (dBFS) Output Frequency (Hz) DAC OUTPUT –110dB, 24-Bit, 96kHz DAC OUTPUT –110dB, 20-Bit, 96kHz DAC OUTPUT –120dB, 24-Bit, 96kHz DAC OUTPUT –120dB, 20-Bit, 96kHz ® PCM1704 4 SPECIFICATIONS (CONT) All specifications at +25°C, ±VCC and ±VDD = ±5.0V, unless otherwise noted. POWER SUPPLY REJECTION RATIO vs FREQUENCY Power Supply Rejection Ratio (dB) –60 –70 –80 –VCC –90 –100 +VCC –110 –120 10 20 50 100 200 500 1k Frequency (Hz) ® 5 PCM1704 THEORY OF OPERATION For production testing, the output of the DAC is connected to a current-to-voltage (I/V) converter. The output of the I/V converter is then connected to a 40kHz, 3rd-order GIC low-pass filter. The filter output is then passed on to a programmable gain amplifier to provide gain for low-level test signals before being fed into an analog distortion analyzer (Shiba Soku Model 725 or equivalent). SIGN-MAGNITUDE ARCHITECTURE Digital audio systems have traditionally used laser-trimmed, current-source DACs in order to achieve sufficient accuracy. However, even the best of these suffer from potential lowlevel nonlinearity due to errors in the major carry bipolar zero transition. Current systems have turned to oversampling data converters, such as the popular delta-sigma architectures, to correct the linearity problems. This is done, however, at the expense of signal-to-noise performance, and the noise shaping techniques utilized by these converters creates a considerable amount of out-of-band noise. If the outputs are not properly filtered, dynamic performance of the overall system will be adversely effected. For the audio bandwidth, the THD+N for the PCM1704 is essentially flat for all frequencies. DYNAMIC RANGE Dynamic range in data converters is specified as the measure of THD+N at an effective output signal level of –60dBFS (conforms to EIAJ method with A-weighting applied). Resolution is commonly used as a theoretical measure of dynamic range, but it does not take into account the effects of distortion and noise at low signal levels. The sign-magnitude architecture of the PCM1704, with its ideal performance around bipolar zero, provides a more usable dynamic range (even with the strict audio definition) than any other previously available D/A converter. The PCM1704 employs an innovative architecture which combines the advantages of traditional DACs (e.g., excellent full-scale performance, high signal-to-noise ratio, and ease of use) with superior low-level performance. This architecture is referred to as sign-magnitude. Two DACs are combined in a complementary arrangement to produce an extremely linear output. The two DACs share a common reference, and a common R-2R ladder for bit current sources. The R-2R ladder utilizes dual balanced current segments to ensure ideal tracking under all conditions. By interleaving the individual bits of each DAC and employing precision laser-trimming of resistors, a highly accurate match between the two DACs is achieved. IDLE CHANNEL SIGNAL-TO-NOISE RATIO (SNR) Another important specification for a digital audio converter is idle channel signal-to-noise ratio (Idle Channel SNR). This is the ratio of the noise on the DAC output at bipolar zero compared to the full-scale range of the D/A converter. To make this measurement, the digital input is continually fed the code for bipolar zero, while the output of the DAC is band limited from 20Hz to 20kHz and A-weighting is applied. The ideal channel SNR for the PCM1704 is typically greater than 120dB, making it ideal for low noise applications. The sign-magnitude architecture, which steps away from zero with small steps in both directions, avoids any glitching or large linearity errors, and provides an absolute current output. The low-level performance of the PCM1704 is such that true 24-bit resolution can be realized around the critical bipolar zero point. OFFSET GAIN AND TEMPERATURE DRIFT DISCUSSION OF KEY SPECIFICATIONS Although the PCM1704’s primary application is in high performance digital audio systems where dynamic specifications are most important, specifications are also given for more traditional DC parameters. These include gain error, bipolar zero offset, temperature gain and offset drift. These specifications are important in test and measurement systems, which is the other main systems application for the PCM1704. TOTAL HARMONIC DISTORTION + NOISE (THD+N) This is the key specification for the PCM1704. Digital data words are read into the PCM1704 at eight times the standard DVD audio sampling frequency of 96kHz (e.g., 8 x 96kHz = 768kHz) to create a sinewave output of 1100Hz. The output of the DAC is then passed through analog signal conditioning circuitry before being input to a distortion analyzer. ® PCM1704 6 AUDIO DATA INTERFACE Maximum Bit Clock (BCLK) Rate The maximum BCLK rate is specified as 25MHz. This is derived from the 8X oversampling of the PCM1704. Given a 96kHz sampling rate, an 8X oversampling input and a 32-bit frame length, we get: BASIC OPERATION The audio interface of the PCM1704 accepts TTL-compatible input levels. The data format at the DATA input of the PCM1704 is Binary Two’s Complement, with the most significant bit (MSB) being first in the serial input bit steam. Table I shows the relationship between the audio input data and DAC output for the PCM1704. Any number of bits can precede the 24 bits to be loaded since only the last 24 bits will be transferred to the parallel DAC register after WCLK (pin 7) has gone LOW (logic 0). BINARY TWO’S COMPLEMENT INPUT DATA (Hex) DAC OUTPUT 7FFFFF 000000 FFFFFF 800000 + Full Scale Bipolar Zero Bipoar Zero – 1 LSB – Full Scale 96kHz • 8 • 32 = 24.576MHz “Stopped Clock” Operation The PCM1704 is normally operated with a continuous BCLK input. If BCLK is stopped between input data words, the last 24 bits shifted in are not actually transferred from the serial register to the parallel DAC register until WCLK goes LOW. WCLK must remain LOW until after the first BCLK cycle of the next data word to insure proper DAC operation. The specified setup and hold times for DATA and WCLK must be observed. DATA FORMAT CONTROL Data format is controlled by two pins on the PCM1704—the 20BIT and INVERT inputs. Their functions are described in the following paragraphs and tables. Input Word Length TABLE I. Digital Input/DAC Output Relationships. Audio data is supplied to the DATA (pin 1) input. The bit clock is used to shift data into the PCM1704 and is supplied to BCLK (pin 2). All DAC serial input data bits are latched into the serial input register on the rising edge of BCLK. The serial-to-parallel data transfer to the DAC occurs on the falling edge of WCLK. The change in the output of the DAC occurs at the rising edge of the 2nd BCLK after the falling edge of WCLK. Figure 1 shows the audio data input format. Figure 2 shows the input timing relationships. 20BIT (pin 9) is used to select the input data length. Table II shows the available selections. Pin 9 is internally pulled up to DGND and therefore, defaults to 24-bit data. 20BIT (Pin 9) DATA WORD LENGTH 20BIT = H (DGND) 20BIT = L (–VDD) 24-Bit Data Word 20-Bit Data Word TABLE II. Input Word Length Selection. B22 B23 B24 B1 B2 B3 DATA (24-Bit) MSB LSB DATA (20-Bit) B18 B19 B20 B1 B2 B3 LSB MSB BCK WCLK DAC Output DATA FIGURE 1. Audio Input Data Format. tWCH tWCL WCLK 1.4V tBCH tBCL tWH tWS BCLK 1.4V tBCY DATA 1.4V tDS BCLK Pulse Cycle Time tBCY 40ns (min) BCLK Pulse Width HIGH tBCH 14ns (min) BCLK Pulse Width LOW tBCL 14ns (min) BCLK Rising Edge to WCLK Falling Edge tWH 10ns (min) WCLK Falling Edge to BCLK Rising Edge tWS 10ns (min) WCLK Pulse Width HIGH t WCH > tBCY WCLK Pulse WIdth LOW tWCL > tBCY DATA Set-up Time tDS 10ns (min) DATA Hold Time tDH 10ns (min) tDH FIGURE 2. Audio Input Data Timing. ® 7 PCM1704 Input Data Inversion supply. No advantage is gained by using separate analog and digital power supplies. It is more important that the analog supplies used to drive these pins are as noise and ripple free as possible to reduce coupling of supply noise to the output. INVERT (pin 10) is used to select the phase of the input data presented to the DAC. Table III shows the two options. Pin 10 is internally pulled up to DGND, and therefore defaults to normal, or non-inverting data. INVERT (Pin 10) PHASE INVERT = H (DGND) INVERT = L (–VDD) Normal (non-inverted) Inverted Power supply decoupling capacitors should be used at each supply pin to maximize power supply rejection, as shown in Figure 3. All ground pins (AGND and DGND) should be connected to an analog ground plane as close to the PCM1704 as possible. The PCM1704 should reside entirely over the analog ground plane of the printed circuit board. TABLE III. Input Data Phase Selection. Bypass and Decoupling Capacitor Requirements Various-sized decoupling capacitors can be used, with no special tolerances being required. Figure 5 shows typical values used by Burr-Brown on our evaluation fixture, which designers can use as recommended values. All capacitors should be located as close to the appropriate pins of the PCM1704 as possible to reduce noise pickup from surrounding circuitry. Aluminum electrolytic capacitors are recommended for larger values, while metal-film or monolithic ceramic capacitors are used for smaller values. APPLICATIONS INFORMATION POWER SUPPLIES For this discussion, please refer to the internal connection diagram for the PCM1704 in Figure 3. The PCM1704 only requires a ±5V supply for operation. Both positive supplies (+VDD and +VCC) should be tied together at a single point and connected to a single +5V analog power supply. Similarly, both negative supplies (–VDD and –VCC) should be tied at a single point and connected to a single –5V analog power +5V Supply 2mA + 3mA +VDD +VCC + SERVO DC WCLK Interface Logic and Logic Bias BCLK DATA Logic Bias Reference, Servo and Bipolar Offset REF DC + + Analog Bias BPO DC BPO + 23-Bit Segment Switches + DGND IOUT 23-Bit Current Segments –VDD –VCC 20mA 10mA + AGND –5V Supply FIGURE 3. PCM1704 Internal Connection Diagram. ® PCM1704 8 TYPICAL APPLICATION EXAMPLES DF1704 or Other Digital Filter The audio interface connections for a stereo audio application is shown in Figure 4. The audio data is input to the digital filter, which then oversampleS the data by a factor of 8. The audio data is then filtered digitally and output to the PCM1704 DACs. PCM1704 DOR DATA WCKO WCLK BCKO BCLK 24-Bit 96kHz Data Figure 5 shows single channel circuit connections for a typical PCM1704 application. It shows the PCM1704 interface to the digital filter, the I/V converter, and the DAC post filter. Selection of an appropriate op amp for the I/V converter is critical for obtaining optimum dynamic performance from the PCM1704. The OPA627 is recommended for this application. Op amps with similar characteristics and faster settling times may also be used. PCM1704 DATA DOL WCLK BCLK The suggested DAC post filter is a second-order lowpass active filter, using the multiple feedback (MFB) circuit technique. The OPA2134 is an excellent choice for the op amp in this circuit, since it is designed for high performance audio applications. The post filter is used to reconstruct and band limit the DAC output signal. FIGURE 4. Audio Interface Connections for Stereo Audio Application. 100µF + DAC I/V 0.1µF Post Filter 100µF + 24-Bit 96kHz Data –5V 0.1µF PCM1704U 1 DATA –VCC 20 2 BCLK REF DC 19 + + C3 C4 +15V 2.5kΩ 8X Oversampling Interpolation Filter C1 C2 + Digital Controls C1 = 4.7µF C2 = 4.7µF C3 = 4.7µF C4 = 47µF C5 = 47µF C6 = 100µF C7 = 4.7 3 NC 4 –VDD 5 DGND AGND 16 6 +VDD AGND 15 7 WCLK 8 NC 9 20BIT 10 INVERT NC 18 SERVO DC 17 + C5 47pF 4.7µF + IOUT 14 +VCC 11 + 560pF 4.7µF + 4.7kΩ U1 NC 13 BPO DC 12 4.7kΩ 2kΩ OPA627 U2 C6 Audio Output 1/2 OPA2134 4.7µF + 2200pF C7 + 4.7µF + +5V Aluminum Electrolytics –15V 0.1µF 0.1µF 100µF + 100µF + FIGURE 5. Typical Application Circuit (one channel shown). ® 9 PCM1704 PACKAGE OPTION ADDENDUM www.ti.com 30-Nov-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) PCM1704U NRND SO NS 20 38 Pb-Free (RoHS) CU SNBI Level-2-260C-1 YEAR PCM1704U-J NRND SO NS 20 38 Pb-Free (RoHS) CU SNBI Level-2-260C-1 YEAR PCM1704U-K NRND SO NS 20 38 Pb-Free (RoHS) CU SNBI Level-2-260C-1 YEAR PCM1704U-K/2K NRND SO NS 20 2000 Pb-Free (RoHS) CU SNBI Level-2-260C-1 YEAR PCM1704U/2K NRND SO NS 20 2000 Pb-Free (RoHS) CU SNBI Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device PCM1704U-K/2K Package Package Pins Type Drawing SO NS 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 25.4 Pack Materials-Page 1 8.8 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.1 2.8 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM1704U-K/2K SO NS 20 2000 367.0 367.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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