ISO808 ® ISO8 08 Isolated 12-Bit Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● 100kHz SAMPLING RATE ● 1500Vrms ISOLATION CONTINUOUS ● 10µS CONVERSION TIME The ISO808 is a low-power isolated sampling ADC using state-of-the-art CMOS structures and high voltage capacitors. The ISO808 contains a complete 12-bit capacitor based SAR, ADC with S/H, clock, reference, µP interface, serial out and galvanic isolation. Laser-trimmed scaling resistors provide standard industrial input ranges including ±10V, ±5V, 0-5V, 0-4V. They are available in 28-pin 0.6" wide plastic DIP and are specified over the industrial temperature range of –40°C to +85°C. ● 12-BIT SERIAL OUTPUT ● SINGLE +5V SUPPLY ● 28-PIN 0.6" PLASTIC DIP APPLICATIONS ● INDUSTRIAL PROCESS CONTROL ● PC-BASED DATA ACQUISITION TEST EQUIPMENT Isolation Barrier Successive Approximation Register and Control Logic 20kΩ R/C Clock R1IN 10kΩ R2IN BUSY 5kΩ R3IN 20kΩ Serial CAP Data Data Clock Out Internal +2.5V Ref 4kΩ Serial Data REF SB/BTC International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1996 Burr-Brown Corporation PDS-1317B Printed in U.S.A. October, 1996 SPECIFICATIONS ELECTRICAL At TA = –40°C to +85°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 3, unless otherwise specified. ISO808P PARAMETER ISOLATION PARAMETERS Rated Voltage, Continuous Partial Discharge, 100% Test(8) Creepage Distance (External) DIP = “P” Package Internal Isolation Distance Barrier Impedance Leakage Current(9) CONDITIONS MIN 50Hz 1s, 5pC 1500 2500 TYP MAX UNITS 1.7 1.4 Vrms Vrms mm mm Ω II pF µArms µArms 12 Bits 16 0.10 >1013 II 15 240Vrms, 60Hz 240Vrms, 50Hz RESOLUTION ANALOG INPUT Voltage Ranges Impedance Capacitance ±10V, 0V to 5V, etc. (See Table I) See Table I 35 THROUGHPUT SPEED Conversion Time Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error Differential Linearity Error No Missing Codes Transition Noise(2) Full Scale Error(3,4) Full Scale Error Drift Full Scale Error Drift Bipolar Zero Error(3) Bipolar Zero Error Drift Unipolar Zero Error(3) Unipolar Zero Error Drift Power Supply Sensitivity (VDIG = VANA = VD) AC ACCURACY Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise+Distortion) Signal-to-Noise Full-Power Bandwidth(6) 5.7 Acquire and Convert DIGITAL INPUTS Logic Levels VIL VIH IIL IIH µs µs kHz ±0.9 ±0.9 LSB(1) LSB Guaranteed 0.1 ±7 ±2 Ext. 2.5000V Ref Bipolar Ranges Bipolar Ranges Unipolar Ranges Unipolar Ranges +4.75V < VD < +5.25V fIN fIN fIN fIN = = = = 45kHz 45kHz 45kHz 45kHz ±2 ±2 ±10V ±10V ±10V ±10V No Load ±10 ±5 ±0.5 90 –90 73 73 250 dB(5) dB dB dB kHz 40 Sufficient to meet AC specs 150 ns ns ns 2.52 V µA 2.3 2.5 2.7 V 100 µA 1.0 VD +0.3V ±10 ±10 V V µA µA Binary Two’s Complement or Straight Binary ±0.4 +4 ISINK = 1.6mA ISOURCE = 500µA LSB % ppm/°C ppm/°C mV ppm/°C mV ppm/°C LSB 2.5 1 Ext. 2.5000V Ref VIL = 0V VIH = 5V ±0.5 2.48 –0.3 VD –1.0 DIGITAL OUTPUTS Data Coding VOL VOH 8 10 100 SAMPLING DYNAMICS Aperture Delay Aperture Jitter Overvoltage Recovery(7) REFERENCE Internal Reference Voltage Internal Reference Source Current (Must use external buffer) External Reference Voltage Range for Specified Linearity External Reference Current Drain pF V V The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® ISO808 2 SPECIFICATIONS (CONT) ELECTRICAL At TA = –40°C to +85°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 3, unless otherwise specified. ISO808P PARAMETER POWER SUPPLIES Specified Performance VDIG1 VANA VDIG2 IDIG1 IANA IDIG2 Power Dissipation CONDITIONS MIN TYP MAX UNITS Must be ≤ VANA +4.75 +4.75 +4.75 +5 +5 +5.25 +5.25 +5.25 V V V mA mA mA mW +85 +150 °C °C 4.2 16 10.8 175 VANA = VDIG = 5V, fS = 100kHz TEMPERATURE RANGE Specified Performance Storage Thermal Resistance, φJA Plastic DIP –40 –65 °C/W 75 NOTES: (1) LSB means Least Significant Bit. One LSB for the ±10V input range is 4.88mV. (2) Typical rms noise at worst case transition. (3) As measured with fixed resistors shown in Figure 7b. Adjustable to zero with external potentiometer. (4) Full scale error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. (5) All specifications in dB are referred to a full-scale input. (6) Usable Bandwidth defined as Full-Scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60dB. (7) Recovers to specified performance after 2 x FS input overvoltage. (8) All devices receive a 1s test. Failure criterion is ≥ 5 pulses of ≥ 5pC. (9) Tested at 2500Vrms, 50Hz limit 10µA. ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY ........................................................................... ±25V ........................................................................... ±25V ........................................................................... ±25V .................................... VANA +0.3V to AGND2 –0.3V ........................................... Indefinite Short to AGND, Momentary Short to VANA Ground Voltage Differences: DGND and AGND ............................... ±0.3V DGND, AGND, and GNDISO ........... 1563Vrms VANA ....................................................................................................... 7V VDIG to VANA ...................................................................................... +0.3V VDIG ........................................................................................................ 7V Digital Inputs .............................................................. –0.3V to VDIG +0.3V Maximum Junction Temperature ................................................... +165°C Internal Power Dissipation ............................................................. 700mW Lead Temperature (soldering, 10s) ................................................ +300°C Analog Inputs: R1IN R2IN R3IN CAP REF Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PACKAGE INFORMATION PRODUCT ISO808P PACKAGE PACKAGE DRAWING NUMBER(1) 28-Pin Plastic DIP 215-1 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ORDERING INFORMATION PRODUCT ISO808P MAXIMUM INTEGRAL LINEARITY ERROR (LSB) TYPICAL SIGNAL-TO(NOISE + DISTORTION) RATIO (dB) SPECIFICATION TEMPERATURE RANGE (°C) PACKAGE ±0.9 70 –40°C to +85°C 28-Pin Plastic DIP ® 3 ISO808 PIN # DIGITAL I/O NAME DESCRIPTION 1 RC I 2 BUSY O Read/Convert. With BUSY high, a falling edge on R/C initiates a new conversion. 3 +5VDIG2 Isolated Digital Supply Volts. 10 +5VDIG1 Digital Supply Volts. 11 +5VANA Analog Supply Volts. 12 R1IN Analog Input. 13 R2N Analog Input. 14 R3N Analog Input. 15 CAP Reference Buffer Output. 2.2µF tantalum capacitor to ground. Reference Input/Output. 2.2µF tantalum capacitor to ground. At the start of conversion BUSY goes LOW and stays LOW until conversion is complete. 16 REF 17 AGND 18 SB/BTC 19 DGND1 26 DGND2 27 DATACLK O Data Clock Output. 28 SDATA O Serial Output Synchronized to DATACLK. Analog Ground. I Selects Straight Binary or Binary Two’s Complement for output data format. Digital Ground. Isolated Ground. TABLE I. Pin Assignments. PIN CONFIGURATION R/C 1 28 SDATA BUSY 2 27 DATACLK +5VDIG2 3 26 DGND2 ANALOG INPUT RANGE CONNECT R1IN VIA 200Ω TO ±10V ±5V ±3.33 0V to 10V 0V to 5V 0V to 4V VIN AGND VIN AGND AGND VIN CONNECT R2IN VIA 100Ω CONNECT R3IN TO TO AGND VIN VIN VIN AGND AGND IMPEDANCE CAP CAP CAP AGND VIN VIN 22.9kΩ 13.3kΩ 10.7kΩ 13.3kΩ 10.0kΩ 10.7kΩ TABLE I. Input Range Connections. See Figure 3 for complete information. ISO808 +5VDIG1 10 19 DGND1 +5VANA 11 18 SB/BTC R1IN 12 17 AGND R2IN 13 16 REF R3IN 14 15 CAP SYMBOL DESCRIPTION t1 Convert Pulse Width t2 BUSY Delay t3 BUSY LOW t4 BUSY Delay after End of Conversion MIN TYP MAX UNITS 40 4500 ns 8 µs 120 ns 220 t5 Aperture Delay 40 t6 Conversion Time 5.7 t7 Acquisition Time ns ns 8 µs 2 µs 10 µs t6 + t7 Throughput Time 9 t8 R/C LOW to DATACLK Delay 450 ns t9 DATACLK Period 440 ns t10 Data Valid to DATACLK HIGH Delay 20 75 ns t11 Data Valid after DATACLK LOW Delay 100 125 ns TABLE II. Conversion and Data Timing. TA = –40°C to +85°C. ® ISO808 4 t1 R/C t3 BUSY t2 t4 t5 MODE Acquire Convert Acquire t6 t7 FIGURE 1. Basic Conversion Timing. t8 R/C t9 1 DATACLK 2 3 11 12 Bit 9 Valid Bit 1 Valid LSB Valid t11 t10 SDATA MSB Valid Bit 10 Valid t2 t3 BUSY FIGURE 2. Serial Data Timing. SPECIFIC FUNCTION R/C BUSY DATACLK SB/BTC 0 1 Output X Initiates Conversion “n”. Data from conversion “n–1” clocked out on DATA synchronized to 12 clock pulses output on DATACLK. 1>0 1 Output X Initiates Conversion “n”. Data from conversion “n–1” clocked out on DATA synchronized to 12 clock pulses output on DATACLK. Incorrect Conversions 0 0>1 X X R/C must be HIGH or a new conversion will be initiated without time for acquisition. Selecting Output Format X X X 0 Serial Data is output in Binary Two’s Complement format. X X X 1 Serial Data is output in Straight Binary format. Initiate Conversion and Output Data OPERATION TABLE III. Control Truth Table. DIGITAL OUTPUT BINARY TWO’S COMPLEMENT (SB/BTC LOW) DESCRIPTION Full-Scale Range Least Significant Bit (LSB) +Full Scale (FS – 1LSB) Midscale One LSB Below Midscale –Full Scale HEX BINARY CODE CODE 3.99902V 0111 1111 1111 7FF 1111 1111 1111 FFF 2V 0000 0000 0000 000 1000 0000 0000 800 1.99902V 1111 1111 1111 FFF 0111 1111 1111 7FF 0V 1000 0000 0000 800 0000 0000 0000 000 ANALOG INPUT ±10 ±5 ±3.33V 4.88mV 2.44mV 1.63mV 9.99512V 4.99756V 3.33171V 0V 0V –4.88mV –2.44mV –1.63mV –10V –5V –3.333333V 0V to 5V 0V to 10V 1.22mV 2.44mV 4.99878V 9.99756V 0V 2.5V 5V 2.49878V 4.99756V 0V 0V STRAIGHT BINARY (SB/BTC HIGH) HEX BINARY CODE CODE 0V to 4V 0.98mV TABLE IV. Output Codes and Ideal Input Voltages. ® 5 ISO808 Input Range With Trim (Adjust offset first at 0V, then adjust gain) Without Trim 200Ω 200Ω R1IN R1IN 100Ω 100Ω R2IN VIN R2IN VIN 33.2kΩ 33.2kΩ R3IN 0V – 10V R3IN 2.2µF CAP +5V + CAP +5V 576kΩ + 2.2µF 50kΩ REF 2.2µF 50kΩ REF + + 2.2µF AGND AGND 200Ω 200Ω R1IN R1IN AGND AGND 100Ω 100Ω R2IN 33.2kΩ 0V – 5V R3IN VIN R2IN 33.2kΩ R3IN VIN +5V CAP CAP + +5V 2.2µF 2.2µF + 50kΩ REF 2.2µF 576kΩ REF 50kΩ + 2.2µF AGND AGND 200Ω 200Ω VIN VIN R1IN R1IN AGND AGND 100Ω 100Ω R2IN R2IN 0V – 4V R3IN R3IN 33.2kΩ 2.2µF +5V 33.2kΩ +5V CAP + 2.2µF + 576kΩ 50kΩ REF + CAP REF 50kΩ 2.2µF 2.2µF + AGND AGND FIGURE 3a. Offset/Gain Circuits for Unipolar Input Ranges. ® ISO808 + 6 Input Range With Trim (Adjust offset first at 0V, then adjust gain) Without Trim 200Ω 200Ω VIN VIN R1IN R1IN 100Ω 100Ω R2IN R2IN +5V 33.2kΩ ±10V 33.2kΩ R3IN R3IN 50kΩ +5V CAP + 2.2µF 2.2µF CAP + 576kΩ REF 2.2µF REF 50kΩ + 2.2µF + AGND AGND 200Ω 200Ω R1IN R1IN 100Ω 100Ω R2IN VIN 33.2kΩ R2IN VIN 33.2kΩ R3IN 2.2µF ±5V CAP + +5V R3IN + CAP +5V 576kΩ 2.2µF 50kΩ REF 50kΩ + 2.2µF REF + 2.2µF AGND AGND 200Ω 200Ω VIN VIN R1IN R1IN 100Ω 100Ω R2IN R2IN R3IN R3IN 33.2kΩ ±3.33V 33.2kΩ CAP 2.2µF + CAP +5V +5V 576kΩ + REF 2.2µF + 50kΩ 50kΩ REF + 2.2µF 2.2µF AGND AGND FIGURE 3b. Offset/Gain Circuits for Bipolar Input Ranges. ® 7 ISO808