® ISO807 ISO8 07 Isolated 16-Bit Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● 1500Vrms ISOLATION CONTINUOUS ● 25µS CONVERSION TIME ● 16-BIT SERIAL OUTPUT The ISO807 is a low-power isolated sampling ADC using state-of-the-art CMOS structures and high voltage capacitors. The ISO807 contains a complete 16-bit capacitor based SAR, ADC with S/H, clock, reference, µP interface, serial out and galvanic isolation. Laser-trimmed scaling resistors provide standard industrial input ranges including ±10V, ±5V, 0-5V, 0-4V. They are available in 28-pin 0.6" wide plastic DIP and are specified over the industrial temperature range of –40°C to +85°C. ● SINGLE +5V SUPPLY ● 28-PIN 0.6" PLASTIC DIP APPLICATIONS ● INDUSTRIAL PROCESS CONTROL ● PC-BASED DATA ACQUISITION TEST EQUIPMENT Isolation Barrier Successive Approximation Register and Control Logic 40kΩ R/C Clock R1IN BUSY 10kΩ R2IN 40kΩ Serial CAP Data Data Clock Out Internal +2.5V Ref 6kΩ Serial Data REF SB/BTC International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1996 Burr-Brown Corporation PDS-1320B Printed in U.S.A. August, 1997 SPECIFICATIONS ELECTRICAL At TA = –40°C to +85°C, fS = 40kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 3b, unless otherwise specified. ISO807P PARAMETER ISOLATION PARAMETERS Rated Voltage, Continuous Partial Discharge, 100% Test(8) Creepage Distance (External) DIP = “P” Package Internal Isolation Distance Barrier Impedance Leakage Current(9) CONDITIONS MIN 50Hz 1s, 5pC 1500 2500 TYP MAX UNITS 1.7 1.4 Vrms Vrms mm mm Ω II pF µArms µArms 16 Bit 16 0.10 >1013 II 15 240Vrms, 60Hz 240Vrms, 50Hz RESOLUTION ANALOG INPUT Voltage Ranges Impedance Capacitance ±10, 0 to +5, 0 to +4 (See Table II) 35 THROUGHPUT SPEED Conversion Time Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error Differential Linearity Error No Missing Codes Transition Noise(2) Full Scale Error(3,4) Full Scale Error Drift Full Scale Error Drift Bipolar Zero Error(3) Bipolar Zero Error Drift Unipolar Zero Error(3) Unipolar Zero Error Drift Power Supply Sensitivity (VDIG = VANA = VS) AC ACCURACY Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise+Distortion) Signal-to-Noise Useable Bandwidth(6) Acquire and Convert DIGITAL INPUTS Logic Levels VIL VIH IIL IIH 20 25 µs µs kHz ±3 +3, –2 LSB(1) LSB Bits LSB % ppm/°C ppm/°C mV ppm/°C mV ppm/°C LSB 15 0.8 ±7 ±0.5 Ext. 2.5000V Ref ±10V Range ±10V Range 0V to 5V, 0V to 4V Ranges 0V to 5V, 0V to 4V Ranges +4.75V < VS < +5.25V fIN fIN fIN fIN = = = = 1kHz, 1kHz, 1kHz, 1kHz, ±0.5 ±0.5 ±10V ±10V ±10V ±10V No Load 2.48 2.3 Ext. 2.5000V Ref –0.3 VD –1.0 VIL = 0V VIH = 5V DIGITAL OUTPUTS Data Coding VOL VOH pF 40 SAMPLING DYNAMICS Aperture Delay Aperture Jitter Overvoltage Recovery(7) REFERENCE Internal Reference Voltage Internal Reference Source Current (Must use external buffer.) Internal Reference Drift External Reference Voltage Range for Specified Linearity External Reference Current Drain V ±0.5 ±10 ±3 ±8 100 –100 88 88 130 dB(5) dB dB dB kHz 40 20 750 ns ps ns 2.5 1 8 2.5 2.52 2.7 ppm/°C V 100 µA 1.0 VD +0.3V ±10 ±10 V V µA µA Binary Two’s Complement or Straight Binary 0.4 +4 ISINK = 1.6mA ISOURCE = 500µA V µA V V The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® ISO807 2 SPECIFICATIONS (CONT) ELECTRICAL At TA = –40°C to +85°C, fS = 40kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 3b, unless otherwise specified. ISO807P PARAMETER POWER SUPPLIES Specified Performance VDIG1 VANA VDIG2 IDIG1 IANA IDIG2 Power Dissipation CONDITIONS MIN TYP MAX UNITS Must be ≤ VANA +4.75 +4.75 +4.75 +5 +5 +5.25 +5.25 +5.25 V V V mA mA mA mW +85 +150 °C °C 4.2 5.0 10.8 125 VANA = VDIG = 5V, FS = 40kHz TEMPERATURE RANGE Specified Performance Storage Thermal Resistance, θJA Plastic DIP –40 –65 °C/W 75 NOTES: (1) LSB means Least Significant Bit. One LSB for the ±10V input range is 3.05µV. (2) Typical rms noise at worst case transition. (3) As measured with fixed resistors shown in Figure 7b. Adjustable to zero with external potentiometer. (4) Full scale error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. (5) All specifications in dB are referred to a full-scale input. (6) Usable Bandwidth defined as Full-Scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60dB. (7) Recovers to specified performance after 2 x FS input overvoltage. (8) All devices receive a 1s test. Failure criterion is ≥ 5 pulses of ≥ 5pC. (9) Tested at 2500Vrms, 50Hz limit 10µA. ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY ........................................................................... ±25V ........................................................................... ±25V .................................... VANA +0.3V to AGND2 –0.3V ......................................... Indefinite Short to AGND2, Momentary Short to VANA Ground Voltage Differences: DGND and AGND1 ............................. ±0.3V DGND, AGND, and GNDISO ........... 1563Vrms VANA ....................................................................................................... 7V VDIG to VANA ...................................................................................... +0.3V VDIG ........................................................................................................ 7V Digital Inputs .............................................................. –0.3V to VDIG +0.3V Maximum Junction Temperature ................................................... +165°C Internal Power Dissipation ............................................................. 825mW Lead Temperature (soldering, 10s) ................................................ +300°C Analog Inputs: R1IN R2IN CAP REF Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PACKAGE INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) ISO807P Plastic DIP 215-1 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ORDERING INFORMATION PRODUCT ISO807P MAXIMUM INTEGRAL LINEARITY ERROR (LSB) TYPICAL SIGNAL-TO(NOISE + DISTORTION) RATIO (dB) SPECIFICATION TEMPERATURE RANGE PACKAGE ±3 83 –40°C to +85°C Plastic DIP ® 3 ISO807 PIN # DIGITAL I/O NAME DESCRIPTION 1 RC I 2 BUSY O Read/Convert. With BUSY high, a falling edge on R/C initiates a new conversion. 3 +5VDIG2 Isolated Digital Supply Volts. 10 +5VDIG1 Digital Supply Volts. 11 +5VANA Analog Supply Volts. 12 R1IN Analog Input. 13 NC No Connection. Leave unconnected. At the start of conversion BUSY goes LOW and stays LOW until conversion is complete. 14 R2IN Analog Input. 15 CAP Reference Buffer Output. 2.2µF tantalum capacitor to ground. 16 REF Reference Input/Output. 2.2µF tantalum capacitor to ground. 17 AGND 18 SB/BTC Analog Ground. 19 DGND1 26 DGND2 27 DATACLK O Data Clock Output. 28 SDATA O Serial Output Synchronized to DATACLK. I Selects Straight Binary or Binary Two’s Complement for Output Data Format. Digital Ground. Isolated Ground. TABLE I. Pin Assignments. PIN CONFIGURATION R/C 1 28 SDATA BUSY 2 27 DATACLK +5VDIG2 3 26 DGND2 ANALOG INPUT RANGE CONNECT R1IN VIA 200Ω TO CONNECT R2IN VIA 100Ω TO IMPEDANCE ±10V 0V to 5V 0V to 4V VIN AGND VIN CAP VIN VIN 45.7kΩ 20.0kΩ 21.4kΩ TABLE II. Input Range Connections. See also Figure 3. ISO807 +5VDIG1 10 19 DGND1 +5VANA 11 18 SB/BTC R1IN 12 17 AGND NC 13 16 REF R2IN 14 15 CAP R/C BUSY DATACLK OPERATION ↓ 1 Output 0 ↑ X New conversion initiated without acquisition of a new signal. Data will be invalid. R/C must be HIGH when BUSY goes HIGH. X 0 X New convert commands ignored. Conversion “n” in progress. Initiates conversion “n”. Valid data from conversion “n-1” clocked out on SDATA. TABLE III. Control Functions ® ISO807 4 TYPICAL PERFORMANCE CURVES At TA = +25°C, fS = 40kHz, VDIG = V ANA = +5V, using internal reference and fixed resistors shown in Figure 3b, unless otherwise specified. FREQUENCY SPECTRUM (8192 Point FFT; fIN = 15kHz, 0dB) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 Amplitude (dB) 0 5 10 Frequency (kHz) 15 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 20 100 100 90 90 80 80 70 70 60 50 15 20 0dB –20dB 60 50 40 40 30 30 20 20 –60dB 10 10 100 1k 10k 100k 0 1M 2 4 6 8 10 12 14 16 Input Signal Frequency (Hz) Input Signal Frequency (kHz) SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE (fIN = 1kHz, 0dB; fS = 10kHz to 40kHz) A.C. PARAMETERS vs TEMPERATURE (fIN = 1kHz, 0dB) 100 18 SFDR, SINAD, and SNR (dB) 110 95 10kHz SINAD (dB) 10 Frequency (kHz) SIGNAL-TO-(NOISE + DISTORTION) vs INPUT FREQUENCY AND INPUT AMPLITUDE SINAD (dB) SINAD (dB) SIGNAL-TO-(NOISE + DISTORTION) vs INPUT FREQUENCY (fIN = 0dB) 5 30kHz 20kHz 90 40kHz 85 80 20 –80 SFDR 105 –85 100 –90 95 –95 THD SNR 90 THD (dB) Amplitude (dB) FREQUENCY SPECTRUM (8192 Point FFT; fIN = 1kHz, 0dB) –100 85 –105 SINAD 80 75 –75 –50 –25 0 25 50 75 100 125 150 –75 Temperature (°C) –50 –25 0 25 50 75 100 125 –110 150 Temperature (°C) ® 5 ISO807 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, fS = 40kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 3b, unless otherwise specified. 3 2 1 0 –1 –2 –3 1 All Codes INL 0 8192 16384 24576 40960 32768 49152 57344 Linearity Degradation (LSB/LSB) 16 Bit LSBs POWER SUPPLY RIPPLE SENSITIVITY INL/DNL DEGRADATION PER LSB OF P-P RIPPLE 65535 16 Bit LSBs Decimal Code 3 2 1 0 –1 –2 –3 All Codes DNL 10–1 10–2 INL 10–3 10–4 DNL 10–5 101 102 103 104 105 106 107 Power Supply Ripple Frequency (Hz) 0 8192 16384 24576 32768 40960 49152 57344 65535 Decimal Code +FS Error 0 –0.20 –FS Error 0 –0.20 –75 –50 0.40 Percent From Ideal 0.20 Percent From Ideal BPZ Error mV From Ideal 0.20 ENDPOINT ERRORS (UNIPOLAR RANGES) 3 2 1 0 –1 –2 Percent From Ideal mV From Ideal Percent From Ideal ENDPOINT ERRORS (20V BIPOLAR RANGE) 3 2 1 0 –1 –2 –25 0 25 50 75 100 125 UPO Error +FS Error (4V Range) 0.20 0 0.40 +FS Error (5V Range) 0.20 0 –75 150 –50 –25 0 Temperature (°C) 50 25 75 100 125 Temperature (°C) CONVERSION TIME vs TEMPERATURE INTERNAL REFERENCE VOLTAGE vs TEMPERATURE 2.520 19.4 2.510 Conversion Time (µs) Internal Reference (V) 2.515 2.505 2.500 2.495 2.490 2.485 19.2 19 18.8 18.6 2.480 –75 –50 –25 0 25 50 75 100 125 –75 150 ® ISO807 –50 –25 0 25 50 Temperature (°C) Temperature (°C) 6 75 100 125 150 150 BASIC OPERATION STARTING A CONVERSION SERIAL OUTPUT Figure 1 shows a basic circuit to operate the ISO807 with a ±10V input range and serial output. Taking R/C (pin 1) LOW for 40ns (12µs max) will initiate a conversion and output valid data from the previous conversion on SDATA (pin 28) synchronized to 16 clock pulses output on DATACLK (pin 27). BUSY (pin 2) will go LOW and stay LOW until the conversion is completed and the serial data has been transmitted. Data will be output in Binary Two’s Complement format, MSB first, and will be valid on both the rising and falling edges of the data clock. BUSY going HIGH can be used to latch the data. All convert commands will be ignored while BUSY is LOW. The R/C (pin 1) LOW for a minimum of 40ns immediately puts the sample/hold of the ISO807 in the hold state and starts conversion ‘n’. BUSY (pin 2) will go LOW and stay LOW until conversion ‘n’ is completed and the internal output register has been updated. All new convert commands during BUSY LOW will be ignored. R/C must go HIGH before BUSY goes HIGH or a new conversion will be initiated without sufficient time to acquire a new signal. The ISO807 will begin tracking the input signal at the end of the conversion. Allowing 25µs between convert commands assures accurate acquisition of a new signal. R/C is level triggered. The ISO807 will begin tracking the input signal at the end of the conversion. Allowing 25µs between convert commands assures accurate acquisition of a new signal. READING DATA The ISO807 outputs serial data in Straight Binary or Binary Two’s Complement data output format. If SB/BTC (pin 18) is HIGH, the output will be in SB format, and if LOW, the output will be in BTC format. Refer to Table IV for ideal output codes. The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset and gain will be corrected in software (refer to the Calibration section). DESCRIPTION Reading the data through the serial port will shift the internal output registers one bit per data clock pulse. ANALOG INPUT ±10 305µV Full-Scale Range Least Significant Bit (LSB) 0V to 5V 76µV 0V to 4V 61µV DIGITAL OUTPUT BINARY TWO’S COMPLEMENT STRAIGHT BINARY (SB/BTC LOW) (SB/BTC HIGH) HEX +Full Scale (FS – 1LSB) HEX BINARY CODE CODE BINARY CODE CODE 9.999695V 4.999924V 3.999939V 0111 1111 1111 1111 7FFF 1111 1111 1111 1111 FFFF 0V 2.5V 2V 0000 0000 0000 0000 0000 1000 0000 0000 0000 8000 –305µV 2.499924V 1.999939V 1111 1111 1111 1111 FFFF 0111 1111 1111 1111 7FFF –10V 0V 0V 1000 0000 0000 0000 8000 0000 0000 0000 0000 0000 Midscale One LSB Below Midscale –Full Scale Table IV. Output Codes and Ideal Input Voltages. +5V 0.1µF SYMBOL DESCRIPTION 1 R/C SDATA 28 t1 Convert Pulse Width 2 BUSY DATACLK 27 t3 BUSY Delay from Start of Conversion 110 3 +5VDIG2 t4 BUSY LOW 18.8 t5 BUSY Delay after End of Conversion 90 DGND2 26 10µF ISO807 10 +5VDIG1 +5V 200Ω VIN 11 +5VANA 12 R1IN +5V MIN TYP MAX UNITS 0.04 12 t6 Aperture Delay 40 t7 Conversion Time 18.8 µs ns 20 µs ns ns 20 µs t8 Acquisition Time 5 µs t13 Start of Conversion to DATACLK Delay 1.4 µs DGND1 19 t14 DATACLK Period 1.1 µs SB/BTC 18 t15 Data Valid to DATACLK HIGH Delay 75 ns 2.2µF + – t16 Data Valid after DATACLK LOW Delay 600 ns + – t7 + t8 Throughput Time AGND 17 13 NC REF 16 14 R2IN CAP 15 2.2µF 66.5kΩ 25 µs TABLE V. Conversion and Data Timing. TA = –40°C to +85°C. 100Ω FIGURE 1. Basic ±10V Operation with Serial Output. ® 7 ISO807 SERIAL OUTPUT The serial output can not be tri-stated and is always active. The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset and gain will be corrected in software (refer to the Calibration section). INTERNAL DATA CLOCK (During A Conversion) The R/C (pin 1) LOW will initiate conversion ‘n’ and activate the internal data clock (typically 900kHz clock rate). The ISO807 will output 16 bits of valid data, MSB first, from conversion ‘n-1’ on SDATA (pin 28), synchronized to 16 clock pulses output on DATACLK (pin 27). The data will be valid on both the rising and falling edges of the internal data clock. The rising edge of BUSY (pin 2) can be used to latch the data. After the 16th clock pulse, DATACLK will remain LOW until the next conversion is initiated, SDATA will also go LOW. The input impedance, summarized in Table II, results from the combination of the internal resistor network shown on the front page of the product data sheet and the external resistors used for each input range (see Figure 4). The input resistor divider network provides inherent overvoltage protection guaranteed to at least ±25V. Analog inputs above or below the expected range will yield either positive full scale or negative full scale digital outputs respectively. There will be no wrapping or folding over for analog inputs outside the nominal range. INPUT RANGES Note: (1) Full scale error includes offset and gain errors measured at both +FS and –FS. The ISO807 offers three input ranges: standard ±10V and 0-5V, and a 0-4V range for complete, single supply systems. Figures 3a and 3b show the necessary circuit connections for implementing each input range and optional offset and gain adjust circuitry. Offset and full scale error(1) specifications are tested and guaranteed with the fixed resistors shown in Figure 3b. Adjustments for offset and gain are described in the Calibration section of this data sheet. CALIBRATION HARDWARE CALIBRATION To calibrate the offset and gain of the ISO807 in hardware, install the resistors shown in Figure 3a. Table VI lists the hardware trim ranges relative to the input for each input range. t 7 + t8 R/C t14 1 t13 DATACLK 2 3 15 16 1 2 Bit 13 Valid Bit 1 Valid LSB Valid MSB Valid Bit 14 Valid t16 t15 MSB Valid Bit 14 Valid SDATA (Results from previous conversion.) BUSY FIGURE 2. Serial Data Timing. ±10V 0-5V 0-4V 33.2kΩ 200Ω 200Ω 12 VIN 12 R1IN 12 R1IN R1IN 200Ω 33.2kΩ VIN 14 R2IN 100Ω 33.2kΩ +5V 2.2µF + 50kΩ 1MΩ 2.2µF CAP 50kΩ AGND 14 CAP 1MΩ 2.2µF 15 ® 8 16 50kΩ 17 AGND + CAP 50kΩ REF + R2IN 100Ω +5V 2.2µF 16 FIGURE 3a. Circuit Diagrams (With Hardware Trim). ISO807 + 50kΩ REF + 17 +5V 15 2.2µF 16 50kΩ R2IN 100Ω +5V 15 14 VIN 1MΩ 2.2µF REF + 17 AGND ±10V 0-5V 0-4V 33.2kΩ 200Ω 200Ω 12 VIN 12 R1IN R1IN 14 +5V R2IN 14 VIN 2.2µF + 16 2.2µF R2IN 14 15 CAP 2.2µF + REF 2.2µF REF 2.2µF + 16 AGND R2IN 100Ω + 17 AGND CAP 15 16 + 17 VIN 100Ω 100Ω 15 R1IN 200Ω 33.2kΩ 66.5kΩ 12 2.2µF CAP REF + 17 AGND FIGURE 3b. Circuit Diagrams (Without Hardware Trim). SOFTWARE CALIBRATION To calibrate the offset and gain in software, no external resistors are required. However, to get the data sheet specifications for offset and gain, the resistors shown in Figure 3b are necessary. See the No Calibration section for more details on the external resistors. Refer to Table VII for the range of offset and gain errors with and without the external resistors. laser trimmed to high relative accuracy to meet full specifications. The actual input impedance of the internal resistor network looking into pin 12 or pin 14 however, is only accurate to ±20% due to process variations. This should be taken into account when determining the effects of removing the external resistors. NO CALIBRATION See Figure 3b for circuit connections. Note that the actual voltage dropped across the external resistors is at least two orders of magnitude lower than the voltage dropped across the internal resistor divider network. This should be considered when choosing the accuracy and drift specifications of the external resistors. In most applications, 1% metal-film resistors will be sufficient. The ISO807 operates with its internal 2.5V reference. The internal reference has approximately an 8ppm/°C drift (typical) and accounts for approximately 20% of the full scale error (FSE = ±0.5%). REFERENCE The ISO807 also has an internal buffer for the reference voltage. See Figure 6 for characteristic impedances at the input and output of the buffer with all combinations of power down and reference down. The external resistors shown in Figure 3b may not be necessary in some applications. These resistors provide compensation for an internal adjustment of the offset and gain which allows calibration with a single supply. Not using the external resistors will result in offset and gain errors in addition to those listed in the electrical specifications section. Offset refers to the equivalent voltage of the digital output when converting with the input grounded. A positive gain error occurs when the equivalent output voltage of the digital output is larger than the analog input. Refer to Table VII for nominal ranges of gain and offset errors with and without the external resistors. Refer to Figure 4 for typical shifts in the transfer functions which occur when the external resistors are removed. REF REF (pin 16) is an input for an external reference or the output for the internal 2.5V reference. A 2.2µF tantalum capacitor should be connected as close as possible to the REF pin from ground. This capacitor and the output resistance of REF create a low pass filter to bandlimit noise on the reference. Using a smaller value capacitor will introduce more noise to the reference, degrading the SNR and SINAD. The REF pin should not be used to drive external AC or DC loads. See Figure 6. The range for the external reference is 2.3V to 2.7V and determines the actual LSB size. Increasing the reference voltage will increase the full scale range and the LSB size of the converter which can improve the SNR. To further analyze the effects of removing any combination of the external resistors, consider Figure 5. The combination of the external and the internal resistors form a voltage divider which reduces the input signal to a 0.3125V to 2.8125V input range at the CDAC. The internal resistors are ® 9 ISO807 CAP CAP (pin 15) is the output of the internal reference buffer. A 2.2µF tantalum capacitor should be placed as close as possible to the CAP pin from ground to provide optimum switching currents for the CDAC throughout the conversion cycle. This capacitor also provides compensation for the output of the buffer. Using a capacitor any smaller than 1µF can cause the output buffer to oscillate and may not have sufficient charge for the CDAC. Capacitor values larger than 2.2µF will have little affect on improving performance. See Figure 6. The +5V power for the A/D should be separate from the +5V used for the system’s digital logic. Connecting VDIG1 (pin 10) directly to a digital supply can reduce converter performance due to switching noise from the digital logic. For best performance, the +5V supply can be produced from whatever analog supply is used for the rest of the analog signal conditioning. If +12V or +15V supplies are present, a simple +5V regulator can be used. Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filter the supply. Either using a filtered digital supply or a regulated analog supply, both VDIG1 and VANA should be tied to the same +5V source. The output of the buffer is capable of driving up to 1mA of current to a DC load. Using an external buffer will allow the internal reference to be used for larger DC loads and AC loads. Do not attempt to directly drive an AC load with the output voltage on CAP. This will cause performance degradation of the converter. GROUNDING Two ground pins are present on the ISO807 input side. DGND1 is the digital supply ground. AGND is the analog supply ground. AGND is the ground to which all analog signals internal to the A/D are referenced. AGND is more susceptible to current induced voltage drops and must have the path of least resistance back to the power supply. LAYOUT The ground pin of the A/D should be tied to an analog ground plane, separated from the system’s digital logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to the “system” ground as near to the power supplies as possible. This helps to prevent dynamic digital ground currents from modulating the analog ground through a common impedance to power ground. POWER For optimum performance, tie the analog and digital power pins to the same +5V power supply and tie the analog and digital grounds together. As noted in the electrical specifications, the ISO807 uses 50% of its isolated power for the analog circuitry. The ISO807 front end should be considered as an analog component. OFFSET ADJUST RANGE (mV) INPUT RANGE GAIN ADJUST RANGE (mV) ±10V ±15 ±60 0 to 5V ±4 ±30 0 to 4V ±3 ±30 TABLE VI. Offset and Gain Adjust Ranges for Hardware Calibration (see Figure 3a). OFFSET ERROR INPUT RANGE W/ RESISTORS GAIN ERROR W/OUT RESISTORS W/ RESISTORS W/OUT RESISTORS (V) RANGE (mV) RANGE (mV) TYP (mV) RANGE (% FS) RANGE (% FS) TYP ±10 –10 ≤ BPZ ≤ 10 0 ≤ BPZ ≤ 35 +15 –0.4 ≤ G ≤ 0.4 0.15 ≤ G(1) ≤ 0.15 –0.3 ≤ G ≤ 0.5 –0.1 ≤ G(1) ≤ 0.2 +0.05 +0.05 0 to 5 –3 ≤ UPO ≤ 3 –12 ≤ UPO ≤ –3 –7.5 –0.4 ≤ G ≤ 0.4 0.15 ≤ G(1) ≤ 0.15 –1.0 ≤ G ≤ 0.1 –0.55 ≤ G(1) ≤ –0.05 –0.2 –0.2 0 to 4 –3 ≤ UPO ≤ 3 –10.5 ≤ UPO ≤ –1.5 –6 –0.4 ≤ G ≤ 0.4 –0.15 ≤ G(1) ≤ 0.15 –1.0 ≤ G ≤ 0.1 –0.55 ≤ G(1) ≤ –0.05 –0.2 –0.2 Note: (1) High Grade. TABLE VII. Range of Offset and Gain Errors with and without External Resistors ® ISO807 10 SIGNAL CONDITIONING The FET switches used for the sample hold on many CMOS A/D converters release a significant amount of charge injection which can cause the driving op amp to oscillate. The amount of charge injection due to the sampling FET switch on the ISO807 is approximately 5-10% of the amount on similar ADCs with the charge redistribution DAC (CDAC) architecture. There is also a resistive front end which attenuates any charge which is released. The end result is a minimal requirement for the drive capability on the signal conditioning preceding the A/D. Any op amp sufficient for the signal in an application will be sufficient to drive the ISO807. The resistive front end of the ISO807 also provides a guaranteed ±25V overvoltage protection. In most cases, this eliminates the need for external over voltage protection circuitry. (a) Bipolar (b) Unipolar Digital Output Digital Output +Full Scale +Full Scale Analog Input –Full Scale Analog Input –Full Scale Typical Transfer Functions With External Resistors Typical Transfer Functions Without External Resistors FIGURE 4. Typical Transfer Functions With and Without External Resistors. ® 11 ISO807 200Ω 39.8kΩ CDAC (High Impedance) VIN (0.3125V to 2.8125V) 20kΩ 9.9kΩ 66.5kΩ 40kΩ +5V 100Ω +2.5V +2.5V 200Ω 39.8kΩ CDAC (High Impedance) (0.3125V to 2.8125V) 33.2kΩ 40kΩ 20kΩ 9.9kΩ 100Ω VIN +2.5V 200Ω +2.5V 39.8kΩ CDAC (High Impedance) VIN (0.3125V to 2.8125V) 33.2kΩ 40kΩ 20kΩ 9.9kΩ 100Ω +2.5V +2.5V FIGURE 5. Circuit Diagrams Showing External and Internal Resistors. ZCAP CAP (Pin 15) CDAC Buffer Internal Reference REF (Pin 16) ZREF PWRD 0 REFD 0 PWRD 0 REFD 1 PWRD 1 REFD 0 PWRD 1 REFD 1 ZCAP (Ω) 1 1 200 200 ZREF (Ω) 6k 100M 6k 100M FIGURE 6. Characteristic Impedances of Internal Buffer. ® ISO807 12