MP MP C50 C50 MPC506A MPC507A 6 7 SBFS018A – JANUARY 1988 – REVISED OCTOBER 2003 Single-Ended 16-Channel/Differential 8-Channel CMOS ANALOG MULTIPLEXERS FEATURES FUNCTIONAL DIAGRAMS ● ANALOG OVERVOLTAGE PROTECTION: 70VPP ● NO CHANNEL INTERACTION DURING OVERVOLTAGE 1kΩ In 1 Out ● BREAK-BEFORE-MAKE SWITCHING 1kΩ ● ANALOG SIGNAL RANGE: ±15V In 2 ● STANDBY POWER: 7.5mW typ Decoder/ Driver 1kΩ In 16 ● TRUE SECOND SOURCE DESCRIPTION Overvoltage Clamp and Signal Isolation The MPC506A is a 16-channel single-ended analog multiplexer, and the MPC507A is an 8-channel differential multiplexer. The MPC506A and MPC507A multiplexers have input overvoltage protection. Analog input voltages may exceed either power supply voltage without damaging the device or disturbing the signal path of other channels. The protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. Analog inputs can withstand 70VPP signal levels and standard ESD tests. Signal sources are protected from short circuits should multiplexer power loss occur; each input presents a 1kΩ resistance under this condition. Digital inputs can also sustain continuous faults up to 4V greater than either supply voltage. 5V Ref Level Shift (1) (1) NOTE: (1) Digital Input Protection. MPC506A (1) (1) (1) VREF A0 A1 A2 A3 EN 1kΩ In 1A Out A 1kΩ In 8A 1kΩ In 1B Out B 1kΩ Decoder/ Driver In 8B These features make the MPC506A and MPC507A ideal for use in systems where the analog signals originate from external equipment or separately powered sources. The MPC506A and MPC507A are fabricated with BurrBrown’s dielectrically isolated CMOS technology. The multiplexers are available in plastic DIP and plastic SOIC packages. Temperature range is –40/+85°C. Overvoltage Clamp and Signal Isolation NOTE: (1) Digital Input Protection. MPC507A 5V Ref Level Shift (1) (1) (1) VREF A0 A1 A2 (1) EN Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 1988-2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTRICAL CHARACTERISTICS Supplies = +15V, –15V; VREF (Pin 13) = Open; VAH (Logic Level High) = +4.0V; VAL (Logic Level Low) = +0.8V unless otherwise specified. MPC506A/MPC507A PARAMETER ANALOG CHANNEL CHARACTERISTICS VS, Analog Signal Range RON, On Resistance(1) IS (OFF), Off Input Leakage Current ID (OFF), Off Output Leakage Current MPC506A MPC507A ID (OFF) with Input Overvoltage Applied(2) ID (ON), On Channel Leakage Current MPC506A MPC507A IDIFF Differential Off Output Leakage Current (MPC507A Only) DIGITAL INPUT CHARACTERISTICS VAL, Input Low Threshold VAH, Input High Threshold(3) VAL, MOS Drive(4) VAH, MOS Drive(4) IA, Input Leakage Current (High or Low)(5) SWITCHING CHARACTERISTICS tA, Access Time tOPEN, Break-Before-Make Delay tON (EN), Enable Delay (ON) tOFF (EN), Enable Delay (OFF) Settling Time (0.1%) (0.01%) "OFF Isolation"(6) CS (OFF), Channel Input Capacitance CD (OFF), Channel Output Capacitance: MPC506A MPC507A CA, Digital Input Capacitance CDS, (OFF), Input to Output Capacitance POWER REQUIREMENTS PD, Power Dissipation I+, Current Pin 1(7) I–, Current Pin 27(7) TEMP MIN Full +25°C Full +25°C Full +25°C Full Full +25°C +25°C Full Full –15 TYP 1.3 1.5 0.5 MAX UNITS +15 1.5 1.8 10 10 V kΩ kΩ nA nA nA nA nA µA nA nA nA 10 nA 0.8 V V V V µA 10 0.2 5 5 2 2 Full Full Full +25°C +25°C Full 4.0 0.8 6.0 1.0 +25°C Full +25°C +25°C Full +25°C Full +25°C +25°C +25°C +25°C +25°C +25°C 25°C +25°C µs µs ns ns ns ns ns µs µs dB pF pF pF pF pF 0.3 0.6 25 80 200 500 250 500 50 Full Full Full 1.2 3.5 68 5 50 25 5 0.1 7.5 0.7 5 mW mA µA 1.5 20 NOTES: (1) VOUT = ±10V, IOUT = –100µA. (2) Analog overvoltage = ±33V. (3) To drive from DTL/TTL circuits. 1kΩ pull-up resistors to +5.0V supply are recommended. (4) VREF = +10V. (5) Digital input leakage is primarily due to the clamp diodes. Typical leakage is less than 1nA at 25°C. (6) VEN = 0.8V, RL = 1kΩ, CL = 15pF, VS = 7Vrms, f = 100kHz. Worst-case isolation occurs on channel 8 due to proximity of the output pins. (7) VEN, VA = 0V or 4.0V. 2 MPC506A, MPC507A www.ti.com SBFS018A PIN CONFIGURATION Top View Top View +VSUPPLY 1 28 Out A Out B 2 27 26 In 8 NC 3 26 In 8A 4 25 In 7 In 8B 4 25 In 7A In 15 5 24 In 6 In 7B 5 24 In 6A In 14 6 23 In 5 In 6B 6 23 In 5A In 13 7 22 In 4 In 5B 7 22 In 4A In 12 8 21 In 3 In 4B 8 21 In 3A In 11 9 20 In 2 In 3B 9 20 In 2A In 10 10 19 In 1 In 2B 10 19 In 1A 18 Enable In 1B 11 18 Enable +VSUPPLY 1 28 Out NC 2 27 NC 3 In 16 In 9 11 –VSUPPLY –VSUPPLY Ground 12 17 Address A0 Ground 12 17 Address A0 VREF 13 16 Address A1 VREF 13 16 Address A1 Address A3 14 15 Address A2 NC 14 15 Address A2 MPC507A (Plastic) MPC506A (Plastic) TRUTH TABLES MPC506A MPC507A A3 A2 A1 A0 EN "ON" CHANNEL X L L L L L L L L H H H H H H H H X L L L L H H H H L L L L H H H H X L L H H L L H H L L H H L L H H X L H L H L H L H L H L H L H L H L H H H H H H H H H H H H H H H H None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 "ON" CHANNEL MPC506A, MPC507A SBFS018A www.ti.com A2 A1 A0 EN PAIR X L L L L H H H H X L L H H L L H H X L H L H L H L H L H H H H H H H H None 1 2 3 4 5 6 7 8 3 ABSOLUTE MAXIMUM RATINGS(1) PACKAGE/ORDERING INFORMATION Voltage between supply pins ............................................................... 44V VREF to ground, V+ to ground ............................................................... 22V V– to ground ........................................................................................ 25V Digital input overvoltage: VEN, VA: VSUPPLY (+) ............................................................................ +4V VSUPPLY (–) ............................................................................ –4V or 20mA, whichever occurs first. Analog input overvoltage: VS: VSUPPLY (+) .................................................................................. +20V VSUPPLY (–) .................................................................................. –20V Continuous current, S or D ............................................................... 20mA Peak current, S or D (pulsed at 1ms, 10% duty cycle max) ............................................ 40mA Power dissipation* ............................................................................. 2.0W Operating temperature range ........................................... –40°C to +85°C Storage temperature range ............................................. –65°C to +150°C For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. *Derate 20.0mW/°C above TA = 70 NOTE: (1) Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional operation under any of these conditions is not necessarily implied. TYPICAL PERFORMANCE CURVES TA = +25°C unless otherwise noted. SETTLING TIME vs SOURCE RESISTANCE FOR 20V STEP CHANGE CROSSTALK vs SIGNAL FREQUENCY 1 Crosstalk (% of Off Channel Signal) 1k Settling Time (µs) 100 To ±0.01% 10 To ±0.1% 1 0.1 0.01 0.1 Rs = 100kΩ Rs = 10kΩ 0.01 Rs = 1kΩ Rs = 100Ω 0.001 0.0001 0.1 10 1 1 100 10 1k 100 10k Signal Frequency (Hz) Source Resistance (kΩ) COMBINED CMR vs FREQUENCY MPC507A AND INA110 Common-Mode Rejection (dB) 120 G = 500 100 G = 100 80 G = 10 60 40 20 0 1 10 100 1k 10k Frequency (Hz) 4 MPC506A, MPC507A www.ti.com SBFS018A DISCUSSION OF SPECIFICATIONS DC CHARACTERISTICS Input Offset Voltage The static or dc transfer accuracy of transmitting the multiplexer input voltage to the output depends on the channel ON resistance (RON), the load impedance, the source impedance, the load bias current and the multiplexer leakage current. Bias current generates an input OFFSET voltage as a result of the IR drop across the multiplexer ON resistance and source resistance. A load bias current of 10nA will generate an offset voltage of 20µV if a 1kΩ source is used. In general, for the MPC506A, the OFFSET voltage at the output is determined by: Single-Ended Multiplexer Static Accuracy The major contributors to static transfer accuracy for singleended multiplexers are: Source resistance loading error Multiplexer ON resistance error dc offset error caused by both load bias current and multiplexer leakage current. Resistive Loading Errors The source and load impedances will determine the input resistive loading errors. To minimize these errors: • Keep loading impedance as high as possible. This minimizes the resistive loading effects of the source resistance and multiplexer ON resistance. As a guideline, load impedance of 108Ω or greater will keep resistive loading errors to 0.002% or less for 1000Ω source impedances. A 106Ω load impedance will increase source loading error to 0.2% or more. • Use sources with impedances as low as possible. A 1000Ω source resistance will present less than 0.001% loading error and 10kΩ source resistance will increase source loading error to 0.01% with a 108 load impedance. Input resistive loading errors are determined by the following relationship (see Figure 1). where IB = Bias current of device multiplexer is driving IL = Multiplexer leakage current RON = Multiplexer ON resistance RS = Source resistance Differential Multiplexer Static Accuracy Static accuracy errors in a differential multiplexer are difficult to control, especially when it is used for multiplexing low-level signals with full-scale ranges of 10mV to 100mV. The matching properties of the multiplexer, source and output load play a very important part in determining the transfer accuracy of the multiplexer. The source impedance unbalance, common-mode impedance, load bias current mismatch, load differential impedance mismatch, and common-mode impedance of the load all contribute errors to the multiplexer. The multiplexer ON resistance mismatch, leakage current mismatch and ON resistance also contribute to differential errors. Referring to Figure 2, the effects of these errors can be minimized by following the general guidelines described in this section, especially for low-level multiplexing applications. IBIAS RON RS1 VOFFSET = (IB + IL) (RON + RS) RS1A RON1A IBIAS A VM VS1 RS16 ROFF Cd/2 Measured Voltage IL RCM VS1 ZL RCM1 VS16 Rd/2 IL RCM RS1B RON1B IBIAS B ZL CCM Cd/2 Rd/2 RS8A ROFF8A RS8B ROFF8B FIGURE 1. MPC506A Static Accuracy Equivalent Circuit. VS8 Source and Multiplexer Resistive Loading Error ∈(RS + RON ) = RCM8 RS + RON × 100 RS + RON + RL where RS = source resistance RL = load resistance RON = multiplexer ON resistance FIGURE 2. MPC507A Static Accuracy Equivalent Circuit. MPC506A, MPC507A SBFS018A www.ti.com 5 Load (Output Device) Characteristics • Use devices with very low bias current. Generally, FET input amplifiers should be used for low-level signals less than 50mV FSR. Low bias current bipolar input amplifiers are acceptable for signal ranges higher than 50mV FSR. Bias current matching will determine the input offset. • The system dc common-mode rejection (CMR) can never be better than the combined CMR of the multiplexer and driven load. System CMR will be less than the device which has the lower CMR figure. • Load impedances, differential and common-mode, should be 1010Ω or higher. SOURCE CHARACTERISTICS see that the amplitude of the switching transients seen at the source and load decrease proportionally as the capacitance of the load and source increase. The trade-off for reduced switching transient amplitude is increased settling time. In effect, the amplitude of the transients seen at the source and load are: dVL = (i/C) dt where i = C (dV/dt) of the CMOS FET switches C = load or source capacitance The source must then redistribute this charge, and the effect of source resistance on settling time is shown in the Typical Performance Curves. This graph shows the settling time for a 20V step change on the input. The settling time for smaller step changes on the input will be less than that shown in the curve. • The source impedance unbalance will produce offset, common-mode and channel-to-channel gain-scatter errors. Use sources which do not have large impedance unbalances if at all possible. • Keep source impedances as low as possible to minimize resistive loading errors. • Minimize ground loops. If signal lines are shielded, ground all shields to a common point at the system analog common. RSA Node A CSA RCMS Source CSB CCMS RSB CdA RdA ZCM MPC507A Load Channel RdB Node B CdB If the MPC507A is used for multiplexing high-level signals of 1V to 10V full-scale ranges, the foregoing precautions should still be taken, but the parameters are not as critical as for low-level signal applications. DYNAMIC CHARACTERISTICS Settling Time The gate-to-source and gate-to-drain capacitance of the CMOS FET switches, the RC time constants of the source and the load determine the settling time of the multiplexer. Governed by the charge transfer relation i = C (dV/dt), the charge currents transferred to both load and source by the analog switches are determined by the amplitude and rise time of the signal driving the CMOS FET switches and the gate-to-drain and gate-to-source junction capacitances as shown in Figures 3 and 4. Using this relationship, one can MPC506A Channel Source RS CS CL Switching Time This is the time required for the CMOS FET to turn ON after a new digital code has been applied to the Channel Address inputs. It is measured from the 50 percent point of the address input signal to the 90 percent point of the analog signal seen at the output for a 10V signal change between channels. Crosstalk Load Node A FIGURE 4. Settling and Common-Mode Effects— MPC507A RL Crosstalk is the amount of signal feedthrough from the seven (MPC507A) or 15 (MPC506A) OFF channels appearing at the multiplexer output. Crosstalk is caused by the voltage divider effect of the OFF channel, OFF resistance and junction capacitances in series with the RON and RS impedances of the ON channel. Crosstalk is measured with a 20Vp-p 1000Hz sine wave applied to all off channels. The crosstalk for these multiplexers is shown in the Typical Performance Curves. FIGURE 3. Settling Time Effects—MPC506A. 6 MPC506A, MPC507A www.ti.com SBFS018A Factors which will degrade multiplexer and system DC CMR are: Common-Mode Rejection (MPC507A Only) The matching properties of the load, multiplexer and source affect the common-mode rejection (CMR) capability of a differentially multiplexed system. CMR is the ability of the multiplexer and input amplifier to reject signals that are common to both inputs, and to pass on only the signal difference to the output. For the MPC507A, protection is provided for common-mode signals of ±20V above the power supply voltages with no damage to the analog switches. • Amplifier bias current and differential impedance mismatch • Load impedance mismatch • Multiplexer impedance and leakage current mismatch • Load and source common-mode impedance AC CMR roll-off is determined by the amount of commonmode capacitances (absolute and mismatch) from each signal line to ground. Larger capacitances will limit CMR at higher frequencies; thus, if good CMR is desired at higher frequencies, the common-mode capacitances and unbalance of signal lines and multiplexer to amplifier wiring must be minimized. Use twisted-shielded pair signal lines wherever possible. The CMR of the MPC507A and Burr-Brown's INA110 instrumentation amplifier (G = 100) is 110dB at DC to 10Hz with a 6dB/octave roll-off to 70dB at 1000Hz. This measurement of CMR is shown in the Typical Performance Curves and is made with a Burr-Brown INA110 instrumentation amplifier connected for gains of 500, 100, and 10. SWITCHING WAVEFORMS Typical at +25°C, unless otherwise noted. BREAK-BEFORE-MAKE DELAY (tOPEN) MPC506A1 VAM 4.0V Address Drive VA (VA) 0V 50Ω Output 50% A3 A2 A1 A0 In 1 In 2 Thru In 15 1 On In 16 VOUT En 50% VA Input 2V/Div +5V GND +4.0V Out 16 On Output 0.5V/Div 12.5pF 1kΩ tOPEN 100ns/Div NOTE: (1) Similar connection for MPC507A. ENABLE DELAY (tON (EN), tOFF (EN)) Enable Drive MPC506A1 VAM = 4.0V A3 A2 A1 A0 50% 0V Output 90% 90% tON(EN) VA En In 1 +10V In 2 Thru In 16 GND Out 1 On 12.5pF 1kΩ 50Ω tOFF(EN) In 1 Thru In 16 Off Output 2V/Div NOTE: (1) Similar connection for MPC507A. 100ns/Div MPC506A, MPC507A SBFS018A www.ti.com 7 PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS TA = +25°C, VS = ±15V, VAM = +4V, VAL = 0.8V and VREF = Open, unless otherwise noted. ON RESISTANCE vs INPUT SIGNAL, SUPPLY VOLTAGE 100µA RON = V2/100µA V2 In Out VIN NORMALIZED ON RESISTANCE vs SUPPLY VOLTAGE ON RESISTANCE vs ANALOG INPUT VOLTAGE 1.6 1.4 Normalized On Resistance (Referred to Value at ±15V) On Resistance (kΩ) 1.2 TA = +25°C 1.1 1.0 TA = –55°C 0.9 ±125°C > T A > –55°C VIN = +5V 1.5 TA = +125°C 1.3 0.8 1.4 1.3 1.2 1.1 1.0 0.9 0.7 0.8 0.6 –10 –8 –6 –4 –2 0 2 4 6 8 ±5 10 ±6 ±7 ±8 ±9 ±10 ±11 ±12 ±13 ±14 ±15 Supply Voltage (V) Analog Input (V) ANALOG INPUT OVERVOLTAGE CHARACTERISTICS 7 21 A A +VIN 18 6 15 5 Analog Input Current (IIN) 12 4 3 9 6 2 Output Off Leakage Current IO (Off) 3 0 +12 +15 +18 +21 +24 +27 +30 +33 1 Output Off Leakage Current (nA) IO (Off) IIN Analog Input Current (mA) Positive Input Overvoltage 0 +36 Analog Input Overvoltage (V) 21 A −V IN A 4 15 Analog Input Current (IIN) 12 2 9 6 Output Off Leakage Current IO (Off) 3 Output Off Leakage Current (µA) IO (Off) IIN Analog Input Current (mA) Negative Input Overvoltage 18 0 0 −12 −15 −18 −21 −24 −27 −30 −33 −36 Analog Input Overvoltage (V) 8 MPC506A, MPC507A www.ti.com SBFS018A PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (CONT) TA = +25°C, VS = ±15V, VAM = +4V, VAL = 0.8V and VREF = Open, unless otherwise noted. LEAKAGE CURRENT vs TEMPERATURE En +0.8V Out Out A ±10V ID (Off) ± 10V A0 A En A1 ID (On) ±10V 10V ± +4.0V Leakage Current 100nA Out IS (Off) A ±10V En +0.8V 10V Off Output Current ID (Off) 10nA On Leakage Current ID (On) 1nA Off Input Leakage Current IS (Off) ± 100pA NOTE: (1) Two measurements per channel: +10V/–10V and –10V/+10V. (Two measurements per device for ID (Off): +10V/–10V and –10V/+10V). 10pA 25 50 75 100 125 Temperature (°C) ON-CHANNEL CURRENT vs VOLTAGE ±14 –55°C A ±V IN Switch Current (mA) ±12 +25°C +125°C ±10 ±8 ±6 ±4 ±2 0 0 ±2 ±4 ±6 ±8 ±10 ±12 ±14 ±16 VIN –Voltage Across Switch (V) MPC506A, MPC507A SBFS018A www.ti.com 9 PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (CONT) TA = +25°C, VS = ±15V, VAM = +4V, VAL = 0.8V and VREF = Open, unless otherwise noted. SUPPLY CURRENT vs TOGGLE FREQUENCY +15V/+10V 8 MPC506A(1) +V A3 In 1 A2 A In 2 Thru In 15 VA Supply Current (mA) A +ISUPPLY ±10V/±5V 1 50Ω A0 ±10V/±5V In 16 –V Out En GND +4V 10MΩ 6 4 VS = ±15V 2 VS = ±10V 14pF A –ISUPPLY 0 100 1k 10k 100k 1M 10M –15V/–10V Toggle Frequency (Hz) NOTE: (1) Similar connection for MPC507A. ACCESS TIME vs LOGIC LEVEL (High) 1000 +15V VA 50Ω +4V 900 +V In 1 In 2 Thru In 15 MPC 506A(1) In 16 En GND –10V +10V Access Time (ns) A3 A2 A1 A0 VREF Probe –V Out 10MΩ 14pF –15V 800 VREF = Open for logic high levels ≤ 6V VREF = Logic high for logic high levels > 6V 700 600 500 400 300 3 NOTE: (1) Similar connection for MPC507A. 4 5 6 7 8 9 10 11 12 13 14 15 Logic Level High (V) ACCESS TIME WAVEFORM VAH 4.0V Address Drive (VA) 1/2VAH VA Input 2V/Div 0V 10V 90% Output A 5V/Div 10V tA 200ns/Div 10 MPC506A, MPC507A www.ti.com SBFS018A INSTALLATION AND OPERATING INSTRUCTIONS 16 Analog Inputs 21 22 23 24 25 Multiplexer Output Direct 6-Bit To Binary Group Counter 2 A 3 A2 A1 A0 Buffered OPA602 1/4 OPA404 Single vs Multitiered Channel Expansion In addition to reducing programming complexity, two-tier configuration offers the added advantages over single-node expansion of reduced OFF channel current leakage (reduced OFFSET), better CMR, and a more reliable configuration if a channel should fail ON in the single-node configuration, data cannot be taken from any channel, whereas only one channel group is failed (8 or 16) in the multitiered configuration. In 1 In 2 In 3 28 MPC506A In 16 Out En 18 A 0 A1 A 2 A3 Multiplexer Output +V In 1 Out Direct 28 MPC506A To Group 3 Group 4 18 Enable MPC506A Group 4 Out 49-64 28 Two-Tier Expansion Using an 8 x 8 two-tier structure for expansion to 64 channels, the programming is simplified. The 6-bit counter output does not require a 1-of-8 decoder. The 3LSBs of the counter drive the A0, A1 and A2 inputs of the eight first-tier multiplexers and the 3MSBs of the counter are applied to the A0, A1, and A2 inputs of the second-tier multiplexer. 16 Analog Inputs (Ch1 to 16) 20 Single-Node Expansion The 64 x 1 configuration is simply eight (MPC507A) units tied to a single node. Programming is accomplished with a 6-bit counter, using the 3LSBs of the counter to control Channel Address inputs A0, A1, A2 and the 3MSBs of the counter to drive a 1-of-8 decoder. The 1-of-8 decoder then is used to drive the ENABLE inputs (pin 18) of the MPC507A multiplexers. Settling time to 0.01% for RS 100Ω —Two MPC506A units in parallel 10µs —Four MPC507A units in parallel 12µs 16 Analog Inputs (Ch241 to 256) In 1 In 2 MPC Out In 3 506A 28 Group 1 Ch1-16 Group 1 In 16 18 Enable A3 A 2 A 1 A 0 1 of 4 Decoder 16 Analog Inputs The ENABLE input, pin 18, is included for expansion of the number of channels on a single node as illustrated in Figure 5. With ENABLE line at a logic 1, the channel is selected by the 3-bit (MPC507A or 4-bit MPC506A) Channel Select Address (shown in the Truth Tables). If ENABLE is at logic 0, all channels are turned OFF, even if the Channel Address Lines are active. If the ENABLE line is not to be used, simply tie it to +V supply. If the +15V and/or –15V supply voltage is absent or shorted to ground, the MPC507A and MPC506A multiplexers will not be damaged; however, some signal feedthrough to the output will occur. Total package power dissipation must not be exceeded. For best settling speed, the input wiring and interconnections between multiplexer output and driven devices should be kept as short as possible. When driving the digital inputs from TTL, open collector output with pull up resistors are recommended (see Typical Performance Curves, Access Time). To preserve common-mode rejection of the MPC507A, use twisted-shielded pair wire for signal lines and inter-tier connections and/or multiplexer output lines. This will help common-mode capacitance balance and reduce stray signal pickup. If shields are used, all shields should be connected as close as possible to system analog common or to the common-mode guard driver. Differential Multiplexer (MPC507A) Single or multitiered configurations can be used to expand multiplexer channel capacity up to 64 channels using a 64 x 1 or an 8 x 8 configuration. En 18 In 1 In 2 In 3 In 16 A 0 A1 A2 A3 +V Buffered OPA602 1/4 OPA404 Out 18 MPC506A En 28 +V In 16 A 0 A1 A2 A3 FIGURE 5. 64-Channel, Single-Tier Expansion. CHANNEL EXPANSION Single-Ended Multiplexer (MPC506A) Up to 64 channels (four multiplexers) can be connected to a single node, or up to 256 channels using 17 MPC506A multiplexers on a two-tiered structure as shown in Figures 5 and 6. Settling Time to 0.01% is 20µs with RS = 100Ω FIGURE 6. Channel Expansion up to 256 Channels Using 16x16 Two-Tiered Expansion MPC506A, MPC507A SBFS018A 4LSBs 4MSBs 8-Bit Channel Address Generator www.ti.com 11 PACKAGE OPTION ADDENDUM www.ti.com 27-Aug-2004 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY MPC506AP ACTIVE PDIP NTD 28 13 MPC506AU ACTIVE SOIC DW 28 1 MPC506AU/1K ACTIVE SOIC DW 28 1000 MPC507AP ACTIVE PDIP NTD 28 13 MPC507AU ACTIVE SOIC DW 28 28 MPC507AU/1K ACTIVE SOIC DW 28 1000 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. MECHANICAL DATA MPDI056 – APRIL 2001 NTD (R-PDIP-T28) PLASTIC DUAL-IN-LINE D 1.565 (39,75) 1.380 (35,05) 28 15 0.580 (14,73) 0.485 (12,32) 1 D 14 Index Area H 0.015 (0,38) MIN C 0.070 (1,78) Base Plane 0.030 (0,76) 0.250 (6,35) MAX C E 0.195 (4,95) 0.125 (3,18) 0.625 (15,88) 0.600 (15,24) –C– E Seating Plane 0.005 (0,13) MIN 4 PL D Full Lead 0.100 (2,54) 0.200 (5,08) 0.115 (2,92) 0.022 (0,56) 0.014 (0,36) 0.010 (0,25) M C 0.600 (15,26) C 0.015 (0,38) 0.008 (0,20) 0.060 (1,52) F 0.000 (0,00) 0.700 (17,78) MAX F 4202496/A 03/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Dimensions are measured with the package seated in JEDEC seating plane gauge GS-3. D. Dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 (0,25). E. Dimensions measured with the leads constrained to be perpendicular to Datum C. F. Dimensions are measured at the lead tips with the leads unconstrained. G. Pointed or rounded lead tips are preferred to ease insertion. H. Maximum dimension does not include dambar protrusions. Dambar protrusions shall not exceed 0.010 (0,25). POST OFFICE BOX 655303 I. Distance between leads including dambar protrusions to be 0.005 (0,13) minumum. J. A visual index feature must be located within the cross-hatched area. K. For automatic insertion, any raised irregularity on the top surface (step, mesa, etc.) shall be symmetrical about the lateral and longitudinal package centerlines. L. Controlling dimension in inches. M. Falls within JEDEC MS-011-AB. • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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