® PW PWS740 S74 0 Distributed Multi-Channel Isolated DC-TO-DC CONVERTER FEATURES APPLICATIONS ISOLATED ±7 TO ±20VDC OUTPUTS BARRIER 100% TESTED AT 1500VAC, 60Hz LOWEST POSSIBLE COST PER CHANNEL MINIMUM PC BOARD SPACE 80% EFFICIENCY (8 CHANNELS, RATED LOADS) ● FLEXIBLE USE WITH PWS745 COMPONENTS ● INDUSTRIAL MEASUREMENT AND CONTROL ● DATA ACQUISITION SYSTEMS ● ● ● ● ● ● TEST EQUIPMENT The PWS740-1 is a high-frequency (400kHz nominal) oscillator/driver, handling up to eight channels. This part is a hybrid containing an oscillator and two power FETs. It is supplied in a TO-3 case to provide the power dissipation necessary at full load. Transformer impedance limits the maximum input current to about 700mA at 15V input, well within the unit’s thermal limits. A TTL-compatible ENABLE pin provides output shut-down if desired. A SYNC pin allows synchronization of several PWS740-1s. DESCRIPTION The PWS740 is a multichannel, isolated DC-to-DC converter with a 1500VAC continuous isolation rating. The outputs track the input voltage to the converter over the range of 7 to 20VDC. The converter’s modular design, comprising three components, minimizes the cost of isolated multichannel power for the user. The PWS740-2 is a trifilar-wound isolation transformer using a ferrite core and is encapsulated in a plastic package, allowing a higher isolation voltage rating. One PWS740-2 is used per isolated channel. –VO Gnd1 +VO 10µH Functional Diagram 10µH 10µH 0.3µF 0.3µF 2 1 10µH 0.3µF BAV99 BAV99 V+ –VO Gnd1 +VO 0.3µF BAV99 3 BAV99 1 2 3 6 5 4 PWS740-2 PWS740-1 8 6 4 5 4 TO *7 *2 Freq Adj *1 Oscillator/ Driver 10µF 5 VDRIVE 0.3µF 6 3 20µH 0.3µF Up to 6 More Channels TO * Optional features; if unused, leave open. ** User Option International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1987 Burr-Brown Corporation PDS-758H 1 Printed in U.S.A. January, 1998 PWS740 SPECIFICATIONS ELECTRICAL At VIN = 15V, output load on each of 8 channels = ±15mA, TA = +25°C, unless otherwise specified. PARAMETER CONDITION MIN TYP MAX UNITS 1500 2121 VACrms VDC VACrms Ω || pF µA PWS740 SYSTEM ISOLATION Rated Voltage Continuous, AC, 50/60Hz Continuous, DC 10s, minimum Measured from Pin 2 to Pin 5 of the PWS740-2 240VACrms, 60Hz Per Channel Test Voltage Impedance Leakage Current INPUT Rated Voltage Voltage Range Current 4000 1012 || 3 0.5 1.5 15 7 ±30mA Output Load on 8 Channels, VIN = 15V Rated Output Load on 8 Channels, VIN = 15V Full Output Load on 8 Channels, VIN = 15V with π Filter on Input Current Ripple OUTPUT Rated Voltage Voltage at Min Load Voltage Range VOUT vs Temp Load Regulation Tracking Regulation Ripple Voltage Noise Voltage Current | +IOUT | + | –IOUT | ±15mA Output Load on 8 Channels ±1mA/Channel ±15mA Output Load on Each Channel ±15mA Output Load on Each Channel ±3mA < Output Load < ±30mA VOUT/VIN See Typical Performance Curves See Theory of Operation Each Channel TEMPERATURE Specification Operation 20 520 300 1 14 ±7 15 30 ±0.05 0.25 1.2 –25 –25 16 ±20 VDC VDC mA mA mA VDC VDC VDC V/°C V/mA V/V 60 mA +85 +85 °C °C 470 20 VS 0.8 kHz V V V PWS740-1 OSCILLATOR/DRIVER VIN = 15V Frequency Supply Enable 350 7 2 0 Drivers On Drivers Off 400 15 PWS740-2 ISOLATION TRANSFORMER Isolation Test Voltage Rated Isolation Voltage Isolation Impedance Isolation Leakage Primary Inductance Winding Ratio 10s, minimum 60s, minimum Continuous 4000 1500 1500 1012 || 3 0.5 300 68/76 240VAC 400kHz, Pin 1 to Pin 5 Primary/Secondary 1.5 VACrms VACrms VACrms Ω || pF µA µH DIODE BRIDGE SPECIFICATIONS Reverse Recovery Reverse Breakdown Reverse Current Forward Voltage IF = IR = 50mA IR = 100µA VR = 40V IF = 100mA 40 55 1.5 1.8 ns V µA V The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® PWS740 2 ELECTROSTATIC DISCHARGE SENSITIVITY PIN CONFIGURATION Top Views This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. TO-3 Gnd TO Plastic DIP Sync 2 3 4 1 PWS740-1 Return 5 Freq Adj 8 +VIN 7 Enable AC 1 6 TO Gnd 2 5 VD AC 3 4 TO ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 6 PWS740-2 TO (Drawings Not to Scale) PACKAGE INFORMATION PRODUCT PWS740-1 Driver PWS740-2 Transformer PACKAGE PACKAGE DRAWING NUMBER(1) TO-3 6-Pin Plastic DIP 030 216 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ® 3 PWS740 TYPICAL PERFORMANCE CURVES LINE REGULATION 1 THROUGH 8 CHANNELS VRIPPLE vs C LOAD 25 25 ±IO = ±15mA/Channel VIN = 15V IO = ±15mA/Channel 20 15 ±VOUT (V) VRIPPLE (mVp-p) 20 10 15 1 channel 10 4 or 8 channels 5 5 0 0 0 0.2 0.4 0.6 0.8 1.0 0 5 10 CLOAD (µF) EFFICIENCY vs LOAD 1,4, AND 8 CHANNELS 20 25 OUTPUT VOLTAGE DRIFT 100 0 8 Channels 80 Rated V OUT (%) 4 Channels Efficiency (%) 15 VIN (V) 60 40 1 Channel –5 20 V IN = +15V 0 –10 5 0 10 15 20 25 30 LOAD REGULATION 1, 4 AND 8 CHANNELS PWS740-1 Operating Frequency (kHz) 15 ±VOUT 4 and 8 Channel 10 VIN = 15V 5 10 15 20 25 30 500 400 300 200 100 See Functional Diagram 0 1 10 100 1k 10k Frequency Adjustment Resistor (Ω ) ±I OUT (mA) ® PWS740 +85 FREQUENCY ADJUSTMENT RANGE 1 Channel 5 +50 Temperature (°C) 20 0 +25 0 –25 ±I OUT (mA) 4 100k PIN DESCRIPTIONS OF PWS740-1 DRIVER If this feature is not required, leave the SYNC pin open. The SYNC pin is sensitive to capacitance loading. 150pF or less is recommended. Also external parasitic capacitive feedback between either TO and the SYNC pin can cause unstable operation (commonly seen as jitter in the TO outputs). Keep SYNC connections and TO lines as physically isolated as possible. Avoid shorting the SYNC pin directly to ground or supply potentials; otherwise, damage may result. +VIN, RETURN, AND GND These are the power supply pins. The ground connection, RETURN, for the N-channel MOSFET sources is brought out separately from the ground connection for the oscillator/ driver chip. The waveform of the FETs’ ground return current (and also the current in the VDRIVE line) is an 800kHz sawtooth. A capacitor between +VIN and the FET ground provides a bypass for the AC portion of this current. Figure 1 shows a method for synchronizing a greater number of PWS740-1 drivers. One unit is chosen as the master. Its synchronization signal, buffered by a high-speed unity gain amplifier can synchronize up to 20 slave units. Pin 1 of each slave unit must be grounded to assure synchronization. Minimize capacitive coupling between the buffered sync line and the outputs of the drivers, especially at the end of long lines. Capacitance to ground is not critical, but total stray capacitance between the sync line and switching outputs should be kept below 50pF. Where extreme line lengths are needed, such as between printed circuit boards, additional OPA633 buffers may be added to keep drive impedance at an acceptably low value. Because of temperatureinfluenced shifts in the switching levels, best operation of this circuit will occur when differences in ambient temperatures between the PWS740-1 drivers are minimized, typically within a 35°C range. The power should never be instantaneously interrupted to the PWS740 system (i.e., a break in the line from V+, either accidental or by means of a series switch). Normal powerdown of the V+ supply is not considered instantaneous. Should a rapid break in input power occur, however, the transformers’ voltage will rapidly increase to maintain current flow. Such a voltage spike may damage the PWS740-1. The bypass capacitors at the +VIN pin of the PWS740-1 and the VDRIVE pins of the transformers provide a path for the primary current if power is interrupted; however, total protection requires some type of bidirectional 1A voltage clamping at the +VIN pin. A low cost SA20A TransZorb® from General Semiconductor(1) or equivalent, which will clamp the +VIN pin between –0.6V and +23V, is recommended. TO AND TO These pins are the drains of the N-channel MOSFET switches which drive all the transformer primaries in parallel. The signals on these pins are 400kHz complementary square waves with twice the amplitude of the voltage at +VIN. It is these lines that allow the power to be distributed to the individual high voltage isolation transformers. Without proper printed circuit board layout techniques, these lines could generate interference to analog circuits. See the next section on PCB layout. 8 Channels 4 1 6 Master +15V 2 OPA633 740-1 NC Typical at 25°C 3.0V –15V 2.5V 200ns 400kHz ENABLE A high TTL logic level on this pin activates the MOSFET driver circuitry. A low TTL level applied to the ENABLE pin shuts down all drive to the transformers and the output voltages go to zero (only the oscillator is unaffected). For continuous operation, the ENABLE pin can be left open or tied to a voltage between +2V and +V. 4 1 Slave 740-1 #1 2 8 Channels 6 4 SYNCHRONIZATION 1 The SYNC pin is used to synchronize up to eight PWS7401 oscillators. Synchronization is useful to prevent beat frequencies in the supply voltages. The SYNC pins of two or more PWS740-1s are tied together to force all units to the same frequency of oscillation. The resultant frequency is slightly higher than that of the highest unsynchronized unit. Slave 740-1 #20 2 8 Channels 6 FIGURE 1. Master/Slave Synchronization of Multiple PWS740 Drivers. (1) General Semiconductor Industries Inc., 2001 W. 10th Place, Tempe AZ 85281, 602-968-3101. TransZorb® General Semiconductor Industries Inc. ® 5 PWS740 +VIN (7-20V) 2N3904 330Ω 1W +5V 2 8 TTL Sync (1) 2.5V Peripheral Driver (MC1472 or Equivalent) 1 2 PWS740-1 4.0V(2) 620Ω 3 1/8W 1 200ns 2N3904 4 2 PWS740-1 100Ω NOTES: (1) See text for frequency range; duty cycle = 5-75%. (2) Typical waveform at 25°C. Active pull-up initiates synchronization; pulse width is set by PWS740 pull-down characteristics and is not affected by frequency of operation. Other PWS740s 1 Other PWS740s FIGURE 2. External Synchronization of Multiple PWS740 Drivers with TTL-Level Signals. If larger temperature gradients are likely to occur, the user may wish to consider the synchronization method shown in Figure 2. This circuit is driven from an external TTLcompatible source such as a system clock or a simple freerunning oscillator constructed of TTL gates. The output stage provides temperature compensation over the rated temperature range of the PWS740. The signal source frequency should be about 800kHz for rated performance, but may range from 500kHz to 2MHz with slightly reduced performance. Precautions with regard to circuit coupling and layout are the same as for the circuit of Figure 1. Repeaters using the OPA633 may be used for long line lengths. Symmetry and good high-frequency layout practice are important in successful application of both of these synchronization techniques. with the addition of two components—a bypass capacitor between the +VIN pin and ground, and a series inductor in the VDRIVE line. A 10µF tantalum capacitor is adequate for bypass. A parallel 0.33µF ceramic capacitor will extend the bandwidth of the tantalum. Additional bypass capacitors at each primary center-tap of the transformers are recommended. In general, the higher the capacitance, the lower the ripple, but the parasitic series inductance of the bypass capacitors will eventually be the limiting factor. The inductor value recommended is approximately 20µH. Greater reduction in ripple current is achieved with values up to 100µH; then physical size may become a concern. The inductor should be rated for at least 2A and its DC resistance should be less than 0.1Ω. An example of a low cost indicator is part number 51591 from Pulse Engineering(2). FREQUENCY ADJUSTMENT The FREQ ADJ pin may be connected to an external potentiometer to lower an unsynchronized PWS740-1 oscillator frequency. This may be useful if the frequency of the PWS740-1 is too close to some other signal’s frequency in the system and beat interference is possible. See Typical Performance Curves. Use of this pin is not usually required; if not used, leave open for rated performance. Output voltage filtering is achieved with a 0.33µF capacitor connecting each VOUT pin of the diode bridge to ground. Short leads and close placement of the capacitors to the unit provide optimum high frequency bypassing. The 800kHz output ripple should be below 5mVp-p. Higher frequency noise bursts are also present at the outputs. They coincide with the switch times and are approximately 20mV in amplitude. Inductance of 10µH or less in series with the output loads will significantly reduce the noise as seen by the loads. PC BOARD LAYOUT CONSIDERATIONS Multilayer printed circuit boards are recommended for PWS740 systems. Two-layer boards are certainly possible with satisfactory operation; however, three layers provide greater density and better control of interference from the FET switch signals. Should four-layer boards be required for other circuitry, the use of separate layers for power and ground planes, a layer for switching signals, and a layer for analog signals would allow the most straightforward layout for the PWS740 system. The following discussion pertains to a three- or four-layer board layout. THEORY OF OPERATION EXTERNAL FILTER COMPONENTS Filter components are necessary to reduce the input ripple current and the output voltage noise. Without any input filtering, the sawtooth currents in the FET switches would flow in the +V supply line. Since this AC current can be as great as 1A peak, voltage interference with other components using this supply line would likely occur. The input ripple current can be reduced to approximately 1mA peak (2) Pulse Engineering, PO Box 12235, San Diego CA 92112, 619-268-2400. ® PWS740 6 VDRIVE + +15V 20µH 10µF 0.3µF PWS740-2 1 BAV99 6 0.3µF 2 4 TO 5 +VIN 8 PWS740-1 0.3µF BAV99 3 6 T O 4 3 0.3µF 10µH(2) 10µH(2) +15V(1) –15V(1) Gnd1 5 Switch Power to Other 7 Channels 0.1µF 0.1µF 24 1 4 13 12 2 VIN1 Isolation Amplifier ISO102(3) 10 13 –15V 22 4 14 16 Input From Other 7 Channels 21 1 5 6 7 12 11 10 9 MPC8S Multiplexer 8 AO 16 AO VOUT System Uses: 1 Oscillator/Driver 8 Transformers 8 Bridges 8 ISO102s 1 Multiplexer Not all components are shown. GND 3 –15V Offset 14 NOTES: (1) Supplies ±15mA of isolated supply current per channel. (2) WestCap DKM-10 or equivalent. (3) Or ISO120 or ISO122. FIGURE 3. Low Cost Eight-Channel Isolation Amplifier Block with Channel-to-Channel Isolation. Critical consideration should go to minimizing electromagnetic radiation from the switching signal’s lines. TO and TO. You can identify the path of the switching current by starting at the +VIN pin. The dynamic component of the current is supplied primarily from the bypass capacitor. The high frequency current flows through the inductor and down the VDRIVE line, through one side of the transformer windings, returning in the TO with the “on” FET switch, and then back up through the bypass capacitor. This current path defines a loop antenna which transmits magnetic energy. The magnetic field lines reinforce at the center of the loop, while the field lines reinforce at the center of the loop, while the field lines from opposite points of the loop oppose each other outside the loop. Cancellation of magnetic radiation occurs when the loop is collapsed to two tightly spaced parallel line segments, each carrying the same current in opposite directions. For this reason, the printed circuit traces for both TO connections should lay directly over a power plane forming the VDRIVE connection. This plane need not extend much wider than TO and TO. All of the current in the plane will flow directly under the TO traces because this is the path of least inductance (and least radiation). these lines. Additional shielding can be obtained by running ground trace(s) along the TO lines, which also facilitate minimum loop area connections for the transformer’s center tap bypass capacitors. The connections between the secondary (output side) of the transformer and the diode bridges should be kept as short as possible. Unnecessary stray capacitance on these lines could cause tuned circuit peaking to occur, resulting in a slight increase of output voltage. The PWS740 is intended for use with the ISO102, ISO120 or ISO122 isolation amplifiers (see Figure 3). Place the PWS740-2 transformer on the VOUT side of the buffer rather than on the C1 (bandwidth control) side to prevent possible pickup of switch signal by the ISO102. The best ground connection ties the ISO102 output analog common pin to the PWS740-1 ground pin with a ground plane. This is where a four-layer board design becomes convenient. The digital ground of the ISO102 can be connected to the ground plane or closer to the +V supply. If possible, you should include the analog components that the ISO102 drives on the same board. For example, if several ISO102s are multiplexed to an analog/digital converter, then having all components sharing the same ground plane will significantly simplify ground errors. Avoid connecting Another potential problem with the TO lines is electric field radiation. Fortunately, the VDRIVE plane is effective at terminating most of the field lines because of its proximity to ® 7 PWS740 digital ground and the PWS740 ground together locally, leaving the ISO102 analog ground to be connected off of the board; the differential voltage between analog and digital ground may become too great. It should be noted that many analog circuit functions do not simultaneously draw full rated current from both the positive and negative supplies. Thus, the PWS740 can power more circuits per channel than is first apparent. For example, an operational amplifier does not draw maximum current from both supplies simultaneously. If a circuit draws 10mA from the positive supply and 3mA from the negative supply, the PWS740 could power (60 ÷ 13), about four devices per channel. OUTPUT CURRENT RATINGS The PWS740-1 driver contains “soft-start” driver circuitry to protect the driver FETs and eliminate high inrush currents during turn-on. Because the PWS740 can have between one and eight channels connected, it was not possible to provide a suitable internal current limit within the driver. Instead, impedance-limiting protects the driver and transformer from overload. This means that the internal impedance of each PWS740-2 transformer is high enough that, when shortcircuited at its output, it limits the current drawn from the driver to a safe value. In addition, the wire size and mass of the transformer are large enough that the transformer does not receive damage under continuous short-circuit conditions. ISOLATION VOLTAGE RATINGS Because a long-term test is impractical in a manufacturing situation, the generally accepted practice is to perform a production test at a higher voltage for some shorter period of time. The relationship between actual test conditions and the continuous derated maximum specification is an important one. Burr-Brown has chosen a deliberately conservative one: VTEST = (2 x VCONTINUOUS RATING) + 1000V. This choice is appropriate for conditions where system transient voltages are not well defined.(3) Where the real voltages are well-defined or where the isolation voltage is not continuous, the user may choose a less conservative derating to establish a specification from the test voltage. The PWS740-1 is capable of driving up to eight individual channels to their full current rating. The total current which can be drawn from each isolation channel is a function of total power being drawn from both DC V+ and V– outputs. For example, if one output is not used, then maximum current can be drawn from the other output. In all cases, the maximum total current that can be drawn from any individual channel is: | IL + | + | IL – | ≤ 60mA (3) Reference National Electrical Manufacturers Association (NEMA) Standards part ICS I-109 and ICS1-111. ® PWS740 8