BB ISO107

®
ISO107
High-Voltage, Internally Powered
ISOLATION AMPLIFIER
FEATURES
APPLICATIONS
● SIGNAL AND POWER IN ONE
TRIPLE-WIDE PACKAGE
● 8000Vpk TEST VOLTAGE
● 2500Vrms CONTINUOUS AC BARRIER
RATING
● WIDE INPUT SIGNAL RANGE:
–10V to +10V
● WIDE BANDWIDTH: 20kHz Small Signal,
20kHz Full Power
● BUILT-IN ISOLATED POWER:
±10V to ±18V Input, ±50mA Output
● MULTICHANNEL SYNCHRONIZATION
CAPABILITY (TTL)
● MULTICHANNEL ISOLATED DATA
ACQUISITION
● BIOMEDICAL INSTRUMENTATION
● POWER SUPPLY AND MOTOR CONTROL
● GROUND LOOP ELIMINATION
ISO107 BLOCK DIAGRAM
Sense
VIN
Duty Cycle
Modulator
Com 1
+VCC1
Sync
Gnd 1
Rectifiers
Filters
–VCC1
Duty Cycle
Demodulator
VOUT
Com 2
–VCC2
Sync
+VCC2
Oscillator
Driver
Enable
Gnd 2
DESCRIPTION
The ISO107 isolation amplifier provides both signal
and power across an isolation barrier. The ceramic
side-brazed hybrid package contains a transformercoupled DC/DC converter and a capacitor-coupled
signal channel.
Extra power is available on the isolated input side for
external input conditioning circuitry. The converter is
protected from shorts to ground with an internal current limit, and the soft-start feature limits the initial
currents from the power source. Multiple-channel synchronization can be accomplished by applying a TTL
clock signal to paralleled Sync pins. The Enable con-
trol is used to turn off transformer drive while keeping
the signal channel demodulator active. This feature
provides a convenient way to reduce quiescent current
for low power applications.
The wide barrier pin spacing and internal insulation
allow for the generous 2500Vrms continuous rating.
Reliability is assured by 100% barrier breakdown
testing that conforms to UL544 test methods. Low
barrier capacitance minimizes AC leakage currents.
These specifications and built-in features make the
ISO107 easy to use, as well as providing for compact
PC board layouts.
International Airport Industrial Park • Mailing Address: PO Box 11400
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP •
• Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1989 Burr-Brown Corporation
PDS-898C
Printed in U.S.A. October, 1993
SPECIFICATIONS
ELECTRICAL
TA = +25°C and VCC2 = ±15V, ±15mA output current unless otherwise noted.
PARAMETERS
MAX
UNITS
100
160
1012 || 13
1.2
2
Vrms
VDC
Vpk
dB
dB
Ω || pF
µA
GAIN
Nominal
Initial Error
Gain vs Temperature
Nonlinearity
1
±0.1
±50
±0.01
±0.25
±120
±0.025
V/V
% FSR
ppm/°C
% FSR
INPUT OFFSET VOLTAGE
Initial Offset
vs Temperature
vs Power Supplies
±20
±150
±2
ISOLATION
Rated Continuous Voltage (1)
AC, 60Hz
DC
Test Breakdown, AC, 60Hz
Isolation-Mode Rejection
Barrier Impedance
Leakage Current
CONDITIONS
MIN
TMIN to TMAX
TMIN to TMAX
10s
2500Vrms, 60Hz
2121VDC
2500
3500
8000
240Vrms, 60Hz
INPUT
Voltage Range
Resistance
VCC2 = ±10V to ±18V
Output Voltage in Range
SIGNAL OUTPUT
Voltage Range
Current Drive
Ripple Voltage, 800kHz Carrier (See Figure 4)
Capacitive Load Drive
Voltage Noise
FREQUENCY RESPONSE
Small Signal Bandwidth
Slew Rate
Settling Time
POWER SUPPLIES
Rated Voltage, VCC2
Voltage Range
Input Current
Ripple Current
Rated Output Voltage
Output Current
Load Regulation
Line Regulation
Output Voltage vs Temperature
Voltage Balance Error, ±VCC1
Voltage Ripple
Output Capacitive Load (See Figure 1)
Sync Frequency
±50
±400
±15
200
V
kΩ
±10
±5
±12.5
±15
20
1000
4
V
mA
mVp-p
pF
µV/√Hz
20
1.5
75
kHz
V/µs
µs
±10
±15
No External Capacitors
+75/–4.5
10
3
±15
±15
30
0.5
1.18
10
0.05
10
Sync-Pin Grounded(3)
1.6
±14.25
Balanced Load
Single
Balanced Load
±18
±15.75
±50
100
1
TEMPERATURE RANGE
Specification
Operating
Storage
mV
µV/°C
mV/V
±10
0.1%, –10/10V
IO = ±15mA(2)
No Filter
CIN = 1µF
TYP
–25
–25
–25
+85
+85
+125
V
V
mA
mAp-p
mAp-p
V
mA
mA
%/mA
V/V
mV/°C
%
mVp-p
µF
MHz
°C
°C
°C
NOTES: (1) Conforms to UL544 test methods. 100% tested at 2500Vrms for 1 minute. (2) For other conditions, see Performance Curve, Input Current (+VCC2) vs Output
Current. Input Current (–VCC2) is constant at –4.5mA (typ) for all output currents. (3) If using external synchronization with a TTL-level clock, frequency should be between
1.2MHz and 2MHz with a duty-cycle greater than 25%.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
ISO107
2
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
Supply Without Damage .................................................................... ±18V
VIN, Sense Voltage ............................................................................ ±50V
Com 1 to Gnd 1 or Com 2 to Gnd 2 ........................................... ±200mV
Enable, Sync ........................................................................... 0V to +VCC2
Continuous Isolation Voltage ..................................................... 2500Vrms
VISO, dv/dt ...................................................................................... 20kV/µs
Junction Temperature ...................................................................... 150°C
Storage Temperature ..................................................... –25°C to +125°C
Lead Temperature, (soldering, 10s) ................................................ 300°C
Output Short to Gnd 2 Duration .............................................. Continuous
±VCC1 to Gnd 1 Duration .......................................................... Continuous
Top View
DIP
NC
1
32
NC
+VCC1
2
31
Gnd 1
NC
3
30
VIN
–VCC1
4
29
Com 1
Com 2
13
20
–VCC2
VOUT 14
19
Sync*
PACKAGE INFORMATION(1)
MODEL
PACKAGE
PACKAGE DRAWING
NUMBER
ISO107
32-Pin Side-Braze Ceramic
210
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
ELECTROSTATIC
DISCHARGE SENSITIVITY
Sense
15
18
+VCC2
Gnd 2
16
17
Enable
*Operation requires that this pin be grounded or driven with TTL levels.
Any integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet published specifications.
®
3
ISO107
TYPICAL PERFORMANCE CURVES
TA = +25°C, VCC2 = ±15VDC, ±15mA output current unless otherwise noted.
RECOMMENDED RANGE OF ISOLATION VOLTAGE
IMR/LEAKAGE vs FREQUENCY
Barrier Voltage Rating
3.5k
Non-Specified
Signal Operation
Operational
Region
100
10
1
100
80
Leakage at
240 Vrms
100
1k
10k
100k
10µA
40
1µA
1M
10
100
Isolation Voltage Frequency (Hz)
1k
100nA
100k
10k
Isolation Voltage Frequency (Hz)
PSRR vs FREQUENCY
GAIN/PHASE vs FREQUENCY
60
3
–45
Gain
+VCC2
54
0
0
40
–3
–6
90
–9
135
–12
180
20
0
1k
10k
45
Phase
Gain (dB)
–VCC2
100
100µA
60
20
10
Power Supply Rejection Ratio (dB)
1mA
–15
100
100k
Supply Modulation Frequency (Hz)
300
1k
3k
10k
30k
Phase Shift (°)
1k
Leakage at
2500 Vrms
IMR
Barrier Leakage Current (rms)
10mA
120
Isolation-Mode Rejection (dB)
Maximum Isolation Voltage (Vpk)
10k
225
100k
Small Signal Frequency (Hz)
ISOLATED POWER SUPPLY
LOAD REGULATION AND EFFICIENCY
LARGE SIGNAL TRANSIENT RESPONSE
20
18
60
10
0
–10
–20
16
45
Output Voltage
Balanced Loads
14
Output Voltage
Single-Ended Loads
12
10
0
50
100
0
0
Time (µs)
®
ISO107
4
10
20
30
40
20
40
60
80
±VCC1 Supply Output Current (mA)
30
15
0
50
100
Efficiency (%)
±VCC1 Output Voltage (V)
Output Voltage (V)
Balanced Load Efficiency
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, VCC2 = ±15VDC, ±15mA output current unless otherwise noted.
ISOLATED POWER SUPPLY VOLTAGE
vs TEMPERATURE
ISOLATED POWER SUPPLY LINE REGULATION
19
2
18
17
∆VCC1 (%)
±VCC1 (V)
1
±15mA Load
16
15
14
1.18 V/V
13
12
0
–1
11
10
–2
9
9
10
11
12
13
14
15
16
17
18
19
–25
25
0
+VCC2 (V)
ISOLATED SUPPLY VOLTAGE AND VOS
vs SYNC FREQUENCY
VOS
0
0
–2.5
–25
–5
–50
2
∆VCC1 (mV)
25
2.5
±VCC2 Input Current (mA)
+VCC2 = 15V
VCC1
∆VOS (mV)
100
145
50
1.5
75
ISOLATED POWER SUPPLY
INPUT CURRENT vs OUTPUT CURRENT
5
1
50
Temperature (°C)
120
95
70
45
0
2.5
10
20
30
40
50
+VCC1 Supply Balanced Output Current (mA)
Sync Frequency (MHz)
®
5
ISO107
THEORY OF OPERATION
OPTIONAL GAIN AND OFFSET ADJUSTMENTS
Rated gain accuracy and offset performance can be achieved
with no external adjustments, but the circuit of Figure 2a
may be used to provide a gain trim of ±0.5% for the values
shown; greater range may be provided by increasing the size
of R1 and R1. Every 2kΩ increase in R1 will give an
additional 1% adjustment range, with R2 ≥ R1. If safety or
convenience dictates location of the adjustment potentiometer on the other side of the barrier from the position shown
in Figure 2a, the position of R1 and R2 may be reserved.
The block diagram on the front page shows the isolation
amplifier’s synchronized signal and power configuration,
which eliminates beat frequency interference. A proprietary
800kHz oscillator chip, power MOSFET transformer drivers, patented square core wirebonded transformer, and single
chip diode bridge provide power to the input side of the
isolation amplifier as well as external loads. The signal
channel capacitively couples a duty-cycle encoded signal
across the ceramic high-voltage barrier built into the package. A proprietary transmitter-receiver pair of integrated
circuits, laser trimmed at wafer level, and coupled through a
pair of matched “fringe” capacitors, result in a simple,
reliable design.
Gains greater than 1 may be obtained by using the circuit of
Figure 2b. Note that the effect of input offset errors will be
multiplied at the output in proportion to the increase in gain.
Also, the small-signal bandwidth will be decreased in in2kΩ
SIGNAL AND POWER CONNECTIONS
Figure 1 shows the proper power supply and signal connections. All power supply pins should be bypassed as shown
with the π filter for +VCC2 an option recommended if more
than ±15mA are drawn from the isolated supply. The separate input and output common pins and output sense are low
current inputs tied to the signal source ground, output
ground, and output load, respectively, to minimize errors
due to IR drop in long conductors. Otherwise, connect Com
1 to Gnd 1, Com 2 to Gnd 2, and Sense to VOUT at the ISO107
socket. The enable pin may be left open if the ISO107 is
continuously operated. If not, a TTL low level will disable
the internal DC/DC converter. The Sync input must be
grounded for unsynchronized operation while a 1.2MHz to
2MHz TTL clock signal provides synchronization of multiple units.
1kΩ
30
R2
15
R1
VIN
29
13
VOUT
14
FIGURE 2a. Gain Adjust.
30
Sense
15
VIN
29
13
Gain = 1 +
( RR
1
2
VOUT
14
+
R1
R1
)
200k
R2
FIGURE 2b. Gain Setting.
Isolation Barrier
–VCC2
C2
Com
1µF
LI
(3)
+
31
NC
30
29
20
Gnd 1 VIN Com 1
19
–VCC2
Sync
18
+VCC2
1µF
C1
VIN
17
10µF Tantalum
+VCC2 Enable
(2)
(1)
ISO107
NC +VCC1
LO*
+VCC1
CO*
NC
2
–VCC1
4
1µF
max*
Com 2
13
VOUT
14
1µF
max*
Sense Gnd 2
15
16
NOTES: (1) Enable = pin open
or TTL high. (2) Ground sync if
not used. (3) π filter reduces
ripple current: LI = 10µH, <10Ω.
Sense
VOUT
LO*
–VCC1
Com 2
CO*
Com Return
FIGURE 1. Signal and Power Connections.
®
ISO107
6
*Optional Filtering:
LO = 10µH, <10Ω
CO = 0.1 – 10pF
ISOLATION BARRIER VOLTAGE
The typical performance of the ISO107 under conditions of
barrier voltage stress is indicated in the first two performance curves—Recommended Range of Isolation Voltage
and IMR/Leakage vs Frequency. At low barrier modulation
levels, errors can be determined by the IMRR characteristic.
At higher barrier voltages, typical performance is obtained
as long as the dv/dt across the barrier is below the shaded
area in the first curve. Otherwise, the signal channel will be
interrupted, causing the output to distort, and/or shift DC
level. This condition is temporary, with normal operation
resuming as soon as the transient subsides. Permanent damage to the integrated circuits occurs only if transients exceed
20kV/µs. Even in this extreme case, the barrier integrity is
assured.
verse proportion to the increase in gain. In most instances, a
precision gain block at the input of the isolation amplifier
will provide better overall performance.
Figure 3 shows a method for trimming VOS of the ISO107.
This circuit may be applied to either Signal Com (input or
output) as desired for safety or convenience. With the values
shown, ±15V supplies and unity gain, the circuit will provide ±150mV adjustment range and 0.25mV resolution with
a typical trim potentiometer. The output will have some
sensitivity to power supply variations. For a ±100mV trim,
power supply sensitivity is 8mV/V at the output.
+VCC1 or +VCC2
1MΩ
Signal Com 1
or
Signal Com 2
100kΩ
HIGH VOLTAGE TESTING
The ISO107 was designed to reliably operate with 2500Vrms
continuous isolation barrier voltage. To confirm barrier
integrity, a two-step breakdown test is performed on 100%
of the units. First, an 8000V peak, 60Hz barrier potential is
applied for 10s to verify that the dielectric strength of the
insulation is above this level. Following this exposure, a
2500Vrms, 60Hz potential is applied for one minute to
conform to UL544. Life-test results show reliable operation
under continuous rated voltage and maximum operating
temperature conditions.
10kΩ
–VCC1 or –VCC2
FIGURE 3. VOS Adjust.
OPTIONAL OUTPUT FILTER
Figure 4 shows an optional output ripple filter that reduces
the 800kHz ripple voltage to <3mVp-p without compromising DC performance. The small signal bandwidth is extended above 30kHz as a result of this compensation.
Sense
30
400Ω
15
VIN
29
13
VOUT
14
4.7nF
FIGURE 4. Ripple Reduction.
MULTICHANNEL SYNCHRONIZATION
Synchronization of multiple ISO107s can be accomplished
by connecting pin 19 of each device to an external TTL level
oscillator, as shown in Figure 6. The PWS750-1 oscillator is
convenient because its nominal synchronizing output frequency is 1.6MHz, resulting in a 800kHz carrier in the
ISO107 (its nominal unsynchronized value). The open collector output typically switches 7.5mA to a 0.2V low level
so that the external pull-up resistor can be chosen for
different pull-up voltages as shown in Figure 6. The number
of channels synchronized by one PWS750-1 is determined
by the total capacitance of the sync voltage conductors. They
must be less than 1000pF to ensure TTL level switching at
800kHz. At higher frequencies the capacitance must be
proportionally lower.
Customers can supply their own TTL level synchronization
logic, provided the frequency is between 1.2MHz and 2MHz,
and the duty cycle is greater than 25%.
®
7
ISO107
APPLICATIONS
+
+
+15V
R8
R9
2kΩ 100kΩ
R1
330kΩ
1
–
11, 12
16
R4
RA
Q1
C1
2.2nF
R2
Q2
330kΩ
C2
10nF
R6
10kΩ
–
IC2A
RL
6
C3
0.33µF 5
–
+
4
–
7
IC2B
31
R7
29
19
10kΩ
Q4
20 13 16
4
Q3
R14
10kΩ
R11
10kΩ
C4
0.1µF
2
3
–
IC2
Q1, Q2, Q4
Q3
D1
R1, R2, R3
R4, R5
IC1, IC3 Bypass
IC2 Bypass
*Burr-Brown P/N
–15V
OPA2111*
2N3904
2N7000
IN4148
1%, 1/2W
1%, 2210Ω
1.0µF
0.1µF
FIGURE 5. ECG Amplifier with Right Leg Drive, Defibrillator Protection, and E.S.U. Blanking.
–VCC2
+VCC2
VIN1
31 30 29
20 19 18
Sync ≈ 1.6MHz
Channel 1
ISO
12
107
14 11
PWS750-1
3
2
4
13 14
15 16
+
–
7
R
VIN2
31 30 29
20 19 18
NOTES: (1) PWS750-1 can sync
>20 ISO107s. (2) Bypass supplies
as shown in Figure 1.
Channel 2
ISO
107
VOUT1
2
4
13 14
15 16
+
–
VOUT2
Additional Channels
FIGURE 6. Synchronized-Multichannel Isolation.
®
ISO107
VOUT
2kΩ
R13
IC3
ISO107*
D1
10MΩ
R12
+
–
8
R3
9
7
3
+
2
+
330kΩ
R10
100kΩ
6
LA
14
15
10
IC1
INA110*
R5
18
2
30
8
8