BSI Ultra Low Power/Voltage CMOS SRAM 32K X 8 bit BS62UV256 DESCRIPTION FEATURES • Ultra low operation voltage : 1.8V ~ 3.6V • Ultra low power consumption : Vcc = 2.0V C-grade : 10mA (Max.) operating current I- grade : 15mA (Max.) operating current 0.005uA (Typ.) CMOS standby current Vcc = 3.0V C-grade : 20mA (Max.) operating current I-grade : 25mA (Max.) operating current 0.01uA (Typ.) CMOS standby current • High speed access time : -15 150ns (Max.) at Vcc = 2.0V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE and OE options The BS62UV256 is a high performance, ultra low power CMOS Static Random Access Memory organized as 32,768 words by 8 bits and operates from a wide range of 1.8V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.005uA and maximum access time of 150ns in 2V operation. Easy memory expansion is provided by an active LOW chip enable (CE), and active LOW output enable (OE) and three-state output drivers. The BS62UV256 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62UV256 is available in the JEDEC standard 28 pin 330mil Plastic SOP, 8mmx13.4mm TSOP (normal type), 300mil Plastic SOJ and 600mil Plastic DIP. PRODUCT FAMILY PRODUCT FAMILY OPERATING TEMPERATURE BS62UV256SC BS62UV256TC BS62UV256PC BS62UV256JC BS62UV256DC BS62UV256SI BS62UV256TI BS62UV256PI BS62UV256JI BS62UV256DI Vcc RANGE (ICCSB1, Max) Vcc= Vcc= 3.0V 2.0V Vcc= 2.0V O 1.8V ~ 3.6V 150 0.2uA 0.1uA 20mA 10mA O O 1.8V ~ 3.6V 150 0.4uA 0.3uA 25mA 15mA -40 C to +85 C 1 • 28 VCC A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A6 A7 A12 A11 A3 OE A13 A1 7 BS62UV256SC 22 8 BS62UV256SI 21 BS62UV256PC 9 BS62UV256PI 20 A14 A8 CE A0 10 19 DQ7 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 GND 14 15 DQ3 • BS62UV256TC BS62UV256TI A5 A10 DQ0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SOP-28 TSOP-28 PDIP-28 SOJ-28 DICE SOP-28 TSOP-28 PDIP-28 SOJ-28 DICE BLOCK DIAGRAM A14 A2 PKG TYPE (ICC, Max) Vcc= Vcc= 3.0V 2.0V O +0 C to +70 C PIN CONFIGURATIONS OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 POWER DISSIPATION STANDBY Operating SPEED (ns) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Address Input Buffer 18 512 Row Memory Array 512 x 512 Decoder A9 A11 512 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 8 8 Data Input Buffer Data Output Buffer Column I/O 8 8 Write Driver Sense Amp 64 Column Decoder 12 CE WE Control Address Input Buffer OE Vdd Gnd A4 A3 A2 A1 A0 A10 Brilliance Semiconductor Inc. reserves the right to modify document contents without notice. R0201-BS62UV256 1 Revision 2.2 April 2001 BSI BS62UV256 PIN DESCRIPTIONS Name Function A0-A14 Address Input These 15 address inputs select one of the 32768 x 8-bit words in the RAM CE Chip Enable Input CE is active LOW. Chip enables must be active to read from or write to the device. If chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. DQ0-DQ7 Data Input/Output Ports These 8 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Supply Gnd Ground TRUTH TABLE MODE WE CE OE I/O OPERATION Vcc CURRENT Not selected X H X High Z ICCSB, ICCSB1 Output Disabled H L H High Z ICC Read H L L DOUT ICC Write L L X DIN ICC ABSOLUTE MAXIMUM RATINGS(1) SYMBOL PARAMETER OPERATING RANGE RATING UNITS -0.5 to Vcc+0.5 V V TERM Terminal Voltage with Respect to GND T BIAS Temperature Under Bias -40 to +125 O C T STG Storage Temperature -60 to +150 O C PT Power Dissipation 1.0 W I OUT DC Output Current 20 mA RANGE AMBIENT TEMPERATURE Vcc Commercial 0 O C to +70 O C 1.8V ~ 3.6V Industrial -40 O C to +85 O C 1.8V ~ 3.6V CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. R0201-BS62UV256 2 CIN CDQ PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT VIN=0V 6 pF VI/O=0V 8 pF 1. This parameter is guaranteed and not tested. Revision 2.2 April 2001 BSI BS62UV256 DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC ) PARAMETER NAME VIL VIH PARAMETER TEST CONDITIONS Guaranteed Input Low Voltage(2) Guaranteed Input High Voltage(2) Vcc=2.0V Vcc=3.0V Vcc = Max, VIN = 0V to Vcc IOL Output Leakage Current Vcc = Max, CE = VIH, or OE = VIH, VI/O = 0V to Vcc Output Low Voltage -- 0.6 0.8 V 1.4 2.0 -- Vcc+0.2 V -- -- 1 uA -- -- 1 uA -- -- 0.4 V -- -- V -- 10 Vcc=3.0V Input Leakage Current Vcc = Max, IOL = 1mA VOH Output High Voltage Vcc = Min, IOH = -0.5mA ICC Operating Power Supply Current CE = VIL, IDQ = 0mA, F = Fmax(3) ICCSB Standby Current-TTL CE = VIH, IDQ = 0mA ICCSB1 Standby Current-CMOS CE Њ Vcc-0.2V, VIN Њ Vcc - 0.2V or VIN Љ 0.2V UNITS -0.5 Vcc=2.0V IIL VOL MIN. TYP. (1) MAX. Vcc=2.0V Vcc=3.0V Vcc=2.0V 1.6 2.4 -- Vcc=3.0V -- -- 20 Vcc=2.0V -- -- 0.5 Vcc=3.0V -- -- 1.0 Vcc=2.0V -- 0.005 0.1 Vcc=3.0V -- 0.01 0.2 Vcc=2.0V Vcc=3.0V mA mA uA 1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC . DATA RETENTION CHARACTERISTICS ( TA = 0oC to + 70oC ) SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS VDR Vcc for Data Retention CE Њ Vcc - 0.2V VIN Њ Vcc - 0.2V or VIN Љ 0.2V 1.5 -- -- V ICCDR Data Retention Current CE Њ Vcc -0.2V VIN Њ Vcc - 0.2V or VIN Љ 0.2V -- 0.005 0.1 uA tCDR Chip Deselect to Data Retention Time 0 -- -- ns TRC (2) -- -- ns tR See Retention Waveform Operation Recovery Time 1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time LOW VCC DATA RETENTION WAVEFORM (1) ( CE Controlled ) Data Retention Mode Vcc VDR ≥ 1.5V Vcc CE R0201-BS62UV256 VIH Vcc tR t CDR CE ≥ Vcc - 0.2V 3 VIH Revision 2.2 April 2001 BSI BS62UV256 KEY TO SWITCHING WAVEFORMS AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Vcc/0V 5ns WAVEFORM 0.5Vcc AC TEST LOADS AND WAVEFORMS 1333 Ω 2V 1333 Ω 2V OUTPUT OUTPUT 5PF INCLUDING JIG AND SCOPE 2000 Ω 2000 Ω FIGURE 1A FIGURE 1B THEVENIN EQUIVALENT 800 Ω OUTPUT OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H , 100PF INCLUDING JIG AND SCOPE INPUTS DON T CARE: ANY CHANGE PERMITTED CHANGE : STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE 1.2V ALL INPUT PULSES Vcc GND 10% → 90% 90% → ← 10% ← 5ns FIGURE 2 AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 2.0V ) READ CYCLE JEDEC PARAMETER NAME t AVAX t AVQV t ELQV t GLQV t ELQX t GLQX t EHQZ t GHQZ t AXOX R0201-BS62UV256 PARAMETER NAME t RC t AA t ACS t OE t CLZ t OLZ t CHZ t OHZ t OH DESCRIPTION BS62UV256 -15 MIN. TYP. MAX. UNIT 150 -- -- ns Address Access Time -- -- 150 ns Chip Select Access Time -- -- 150 ns Read Cycle Time Output Enable to Output Valid -- -- 100 ns Chip Select to Output Low Z 10 -- -- ns Output Enable to Output in Low Z 10 -- -- ns Chip Deselect to Output in High Z 0 -- 35 ns Output Disable to Output in High Z 0 -- 30 ns Output Disable to Output Address Change 10 -- -- ns 4 Revision 2.2 April 2001 BSI BS62UV256 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) t RC ADDRESS t t t OH AA OH D OUT READ CYCLE2 (1,3,4) CE t t (5) ACS t CHZ (5) CLZ D OUT READ CYCLE3 (1,4) t RC ADDRESS t AA OE t OE t OH t OLZ CE t ACS (5) t CLZ t OHZ (5) (1,5) t CHZ D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL . 5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. R0201-BS62UV256 5 Revision 2.2 April 2001 BSI BS62UV256 AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 2.0V ) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME BS62UV256-15 MIN. TYP. MAX. DESCRIPTION UNIT t AVAX t WC Write Cycle Time 150 -- -- ns t E1LWH t CW Chip Select to End of Write 150 -- -- ns t AVWL t AS Address Set up Time 0 -- -- ns t AVWH t AW Address Valid to End of Write 150 -- -- ns t WLWH t WP Write Pulse Width 80 -- -- ns t WHAX t WR Write Recovery Time 0 -- -- ns t WLOZ t WHZ Write to Output in High Z -- -- 30 ns t DVWH t DW Data to Write Time Overlap 40 -- -- ns t WHDX t DH Data Hold from Write Time 0 -- -- ns t GHOZ t OHZ Output Disable to Output in High Z 0 -- 30 ns t WHQX t OW End ot Write to Output Active 5 -- -- ns (CE , WE) SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) t WC ADDRESS t (3) WR OE (11) t CW (5) CE t AW WE t WP t AS (2) (4,10) t OHZ D OUT t t DH DW D IN R0201-BS62UV256 6 Revision 2.2 April 2001 BSI BS62UV256 WRITE CYCLE2 (1,6) t WC ADDRESS (11) t CW (5) CE t AW t WP (2) WE t t AS DH (4,10) t WHZ (7) D OUT (8) t DW t DH (8) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE going low to the end of write. R0201-BS62UV256 7 Revision 2.2 April 2001 BSI BS62UV256 ORDERING INFORMATION BS62UV256 X X ˀˀ Y Y SPEED 15: 150ns GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE S: SOP P: PDIP J : SOJ T: TSOP (8mm x 13.4mm) D : DICE PACKAGE DIMENSIONS 0.020 ̈́ 0.005X45̓ θ WITH PLATING b c c1 BASE METAL b1 SOP - 28 R0201-BS62UV256 8 Revision 2.2 April 2001 BSI BS62UV256 PACKAGE DIMENSIONS (continued) UNIT SYMBOL 12̓(2x) e 12̓(2x) HD 1 E cL b 28 y Seating Plane 14 15 12̓ (2X) "A" D A A2 GAUGE PLANE A1 0 14 15 MM 0.0433̈́0.004 1.10̈́0.10 A1 A2 b b1 c 0.0045̈́0.0026 0.039̈́0.002 0.009̈́0.002 0.008̈́0.001 0.004 ~ 0.008 0.115̈́0.065 1.00̈́0.05 0.22̈́0.05 0.20̈́0.03 0.10 ~ 0.21 c1 D E e HD 0.004 ~ 0.006 0.465̈́0.004 0.315̈́0.004 0.022̈́0.004 0.528̈́0.008 0.10 ~ 0.16 11.80̈́0.10 8.00̈́0.10 0.55̈́0.10 13.40̈́0.20 L L1 y 0 0.0197 +0.008 - 0.004 0.0315̈́0.004 0.004 Max. 0̓~ 8̓ 0.50 +0.20 - 0.10 0.80̈́0.10 0.1 Max. 0̓~ 8̓ 0.254 A INCH A A SEATING PLANE 12 (2X) L "A" DATAIL VIEW b WITH PLATING 1 28 L1 c c1 BASE METAL b1 SECTION A-A TSOP - 28 PDIP - 28 R0201-BS62UV256 9 Revision 2.2 April 2001 BSI BS62UV256 SOJ - 28 R0201-BS62UV256 10 Revision 2.2 April 2001 BSI BS62UV256 REVISION HISTORY Revision Description Date 2.2 2001 Data Sheet release Apr. 15, 2001 R0201-BS62UV256 11 Note Revision 2.2 April 2001