BSI BS616LV2010EC

BSI
Very Low Power/Voltage CMOS SRAM
128K X 16 bit
BS616LV2010
„ DESCRIPTION
„ FEATURES
• Very low operation voltage : 2.7 ~ 3.6V
• Very low power consumption :
Vcc = 3.0V
C-grade: 25mA (Max.) operating current
I-grade: 30mA (Max.) operating current
0.15uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max.) at Vcc = 3.0V
-10
100ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
The BS616LV2010 is a high performance, very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a wide range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.15uA and maximum access time of 70/100ns in 3V operation.
Easy memory expansion is provided by active LOW chip
enable(CE), active LOW output enable(OE) and three-state output
drivers.
The BS616LV2010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2010 is available in DICE form , JEDEC standard
44-pin TSOP Type II package. 48-pin TSOP Type I package and 48-ball
BGA package.
„ PRODUCT FAMILY
PRODUCT
FAMILY
BS616LV2010EC
BS616LV201 0EI
OPERATING
TEMPERATURE
Vcc
RANGE
POWER DISSIPATION
STANDBY
Operating
SPEED
(ns)
( ICCSB1, Max )
( ICC, Max )
Vcc=3.0V
Vcc=3.0V
Vcc=3.0V
PKG TYPE
O
O
2.7V ~ 3.6V
70 / 100
8uA
25mA
TSOP2-44
O
O
2.7V ~ 3.6V
70 / 100
12uA
30mA
TSOP2-44
+0 C to +70 C
-40 C to +85 C
„ PIN CONFIGURATIONS
„ BLOCK DIAGRAM
A8
A13
A15
Address
A16
A14
Input
A12
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
BS616LV2010EC
BS616LV2010EI
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Buffer
A7
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
20
1024
Row
Memory Array
Decoder
1024 x 2048
A6
A5
A4
2048
16
DQ0
.
.
.
.
.
.
.
.
Data
Input
Buffer
16
Column I/O
Write Driver
Sense Amp
16
Data
Output
Buffer
DQ15
16
128
Column Decoder
14
CE
WE
OE
UB
LB
Control
Address Input Buffer
A11 A9 A3 A2 A1 A0 A10
Vcc
Gnd
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616LV2010
1
Revision 2.2
April. 2001
BSI
BS616LV2010
„ PIN DESCRIPTIONS
Name
Function
A0-A16 Address Input
These 17 address inputs select one of the 131,072 x 16-bit words in the RAM.
CE Chip Enable Input
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
Lower byte and upper byte data input/output control pins.
DQ0 - DQ15 Data Input/Output
Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Gnd
Ground
„ TRUTH TABLE
MODE
CE
WE
OE
LB
UB
DQ0~DQ7
DQ8~DQ15
Vcc CURRENT
Not selected
(Power Down)
H
X
X
X
X
High Z
High Z
ICCSB, ICCSB1
Output Disabled
L
H
H
X
X
High Z
High Z
ICC
L
L
Dout
Dout
ICC
H
L
High Z
Dout
ICC
L
H
Dout
High Z
ICC
L
L
Din
Din
ICC
H
L
X
Din
ICC
L
H
Din
X
ICC
Read
Write
R0201-BS616LV2010
L
L
H
L
L
X
2
Revision 2.2
April. 2001
BSI
BS616LV2010
„ ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
PARAMETER
with
„ OPERATING RANGE
RATING
UNITS
-0.5 to
Vcc+0.5
V
VTERM
Terminal Voltage
Respect to GND
TBIAS
Temperature Under Bias
-40 to +125
O
C
TSTG
Storage Temperature
-60 to +150
O
C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
20
mA
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial
0 O C to +70 O C
2.7V ~ 3.6V
O
Industrial
O
-40 C to +85 C
2.7V ~ 3.6V
„ CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
CIN
CDQ
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
VIN=0V
6
pF
VI/O=0V
8
pF
1. This parameter is guaranteed and not tested.
„ DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
MIN. TYP. (1) MAX.
UNITS
IIL
Guaranteed Input Low
Voltage(2)
Guaranteed Input High
Voltage(2)
Input Leakage Current
IOL
Output Leakage Current
Vcc = Max, CE = VIH, or OE = VIH,
VI/O = 0V to Vcc
VOL
Output Low Voltage
Vcc = Max, IOL = 2mA
Vcc=3.0V
--
--
0.4
V
VOH
Output High Voltage
Vcc = Min, IOH = -1mA
Vcc=3.0V
2.4
--
--
V
ICC
Operating Power Supply
Current
CE = VIL, IDQ = 0mA, F = Fmax(3)
Vcc=3.0V
--
--
25
mA
ICCSB
Standby Current-TTL
CE = VIH, IDQ = 0mA
Vcc=3.0V
--
--
1
mA
ICCSB1
Standby Current-CMOS
CE Њ Vcc-0.2V,
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
Vcc=3.0V
--
0.15
8
uA
VIL
VIH
Vcc=3.0V
-0.5
--
0.8
V
Vcc=3.0V
2.0
--
Vcc+0.2
V
Vcc = Max, VIN = 0V to Vcc
--
--
1
uA
--
--
1
uA
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC .
„ DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP. (1)
MAX.
UNITS
V DR
Vcc for Data Retention
CE Њ Vcc - 0.2V
V IN Њ Vcc - 0.2V or V IN Љ 0.2V
1.5
--
--
V
ICCDR
Data Retention Current
CE Њ Vcc - 0.2V
V IN Њ Vcc - 0.2V or V IN Љ 0.2V
--
0.1
5
uA
tCDR
Chip Deselect to Data
Retention Time
0
--
--
ns
T RC (2)
--
--
ns
tR
See Retention Waveform
Operation Recovery Time
1. Vcc = 1.5V, TA = + 25OC
2. tRC = Read Cycle Time
R0201-BS616LV2010
3
Revision 2.2
April. 2001
BSI
BS616LV2010
„ LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
Vcc
VDR ≥ 1.5V
Vcc
Vcc
tR
t CDR
CE ≥ Vcc - 0.2V
VIH
CE
„ KEY TO SWITCHING WAVEFORMS
„ AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
VIH
Vcc/0V
5ns
WAVEFORM
0.5Vcc
„ AC TEST LOADS AND WAVEFORMS
1269 Ω
3.3V
1269 Ω
3.3V
OUTPUT
OUTPUT
100PF
INCLUDING
JIG AND
SCOPE
1404 Ω
1404 Ω
FIGURE 1A
FIGURE 1B
THEVENIN EQUIVALENT
667 Ω
OUTPUT
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
5PF
INCLUDING
JIG AND
SCOPE
INPUTS
DON T CARE:
ANY CHANGE
PERMITTED
CHANGE :
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
1.73V
ALL INPUT PULSES
Vcc
GND
→
10%
90% 90%
10%
←
→
← 5ns
FIGURE 2
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
t AVAX
tRC
Read Cycle Time
70
--
--
100
--
--
t AVQV
tAA
Address Access Time
--
--
70
--
--
100
ns
tELQV
tACS
Chip Select Access Time
(CE)
--
--
70
--
--
100
ns
tBA
tBA
Data Byte Control Access Time
(LB,UB)
--
--
40
--
--
50
ns
tGLQV
tOE
Output Enable to Output Valid
--
--
50
--
--
60
ns
t E1LQX
tCLZ
Chip Select to Output Low Z
(CE)
10
--
--
15
--
--
ns
tBE
tBE
Data Byte Control to Output Low Z
(LB,UB)
10
--
--
15
--
--
ns
tGLQX
tOLZ
Output Enable to Output in Low Z
tEHQZ
tCHZ
Chip Deselect to Output in High Z
tBDO
tBDO
Data Byte Control to Output High Z
tGHQZ
tOHZ
Output Disable to Output in High Z
t AXOX
tOH
Output Disable to Address Change
R0201-BS616LV2010
BS616LV2010-70
MIN. TYP. MAX.
DESCRIPTION
4
BS616LV2010-10
MIN. TYP. MAX.
UNIT
ns
10
--
--
15
--
--
ns
(CE)
0
--
35
0
--
40
ns
(LB,UB)
0
--
30
0
--
35
ns
0
--
30
0
--
35
ns
10
--
--
15
--
--
ns
Revision 2.2
April. 2001
BSI
BS616LV2010
„ SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t RC
ADDRESS
t
t
t OH
AA
OH
D OUT
READ CYCLE2 (1,3,4)
CE
t ACS
t BA
LB,UB
t BE
D OUT
t
t BDO
(5)
t
(5)
CHZ
CLZ
READ CYCLE3 (1,4)
t RC
ADDRESS
t
AA
OE
t OH
t OE
t OLZ
CE
(5)
t CLZ
t
t OHZ (5)
t CHZ(1,5)
ACS
t BA
LB,UB
t BE
t BDO
D OUT
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL .
5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
R0201-BS616LV2010
5
Revision 2.2
April. 2001
BSI
BS616LV2010
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.0V )
WRITE CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
t AVAX
t E1LWH
t AVWL
t AVWH
t WLWH
t WHAX
t BW
t WLQZ
t DVWH
t WHDX
t GHQZ
t WC
t CW
t AS
t AW
t WP
t WR
t BW
t WHZ
t DW
t DH
t OHZ
t WHOX
t OW
BS616LV2010-70
MIN. TYP. MAX.
DESCRIPTION
Write Cycle Time
70
--
Chip Select to End of Write
70
0
Address Valid to End of Write
Write Pulse Width
--
100
--
--
100
--
--
0
70
--
--
100
50
--
--
70
(CE,WE)
0
--
--
(LB,UB)
60
--
--
Address Setup Time
Write recovery Time
Date Byte Control to End of Write
BS616LV2010-10
MIN. TYP. MAX.
--
UNIT
--
ns
--
--
ns
--
--
ns
--
--
ns
--
--
ns
0
--
--
ns
80
--
--
ns
0
--
30
0
--
40
ns
Data to Write Time Overlap
30
--
--
40
--
--
ns
Data Hold from Write Time
0
--
--
0
--
--
ns
Output Disable to Output in High Z
0
--
30
0
--
40
ns
End of Write to Output Active
5
--
--
10
--
--
ns
Write to Output in High Z
„ SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t WC
ADDRESS
(3)
t WR
OE
(11)
t CW
(5)
CE
t BW
LB,UB
t AW
WE
(3)
t WP
t AS
(2)
(4,10)
t OHZ
D OUT
t
DH
t DW
D IN
R0201-BS616LV2010
6
Revision 2.2
April. 2001
BSI
BS616LV2010
WRITE CYCLE2 (1,6)
t WC
ADDRESS
(11)
t CW
(5)
CE
t BW
LB,UB
t AW
WE
t WR
t WP
(3)
(2)
t
t AS
DH
(4,10)
t WHZ
D OUT
(7)
(8)
t DW
t
DH
(8,9)
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
R0201-BS616LV2010
7
Revision 2.2
April. 2001
BSI
BS616LV2010
„ ORDERING INFORMATION
BS616LV2010
X X
-- Y Y
SPEED
70: 70ns
10: 100ns
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
E: TSOP 2 - 44 PIN
„ PACKAGE DIMENSIONS
TSOP2-44
R0201-BS616LV2010
8
Revision 2.2
April. 2001
BSI
BS616LV2010
REVISION HISTORY
Revision
Description
Date
2.2
2001 Data Sheet release
Apr. 15, 2001
R0201-BS616LV2010
9
Note
Revision 2.2
April. 2001