CM3102 Micropower 1.2V/150mA CMOS LDO Regulator with Power Good Features Product Description • • • • • • • • • • • The CM3102 is a low quiescent current (90uA) regulator that delivers up to 150mA of load current at a fixed 1.2V output. In addition, the CM3102 features a Power Good output signal (PG) that goes open drain 1 to 5 ms after the output voltage has exceeded typically 93% of its nominal level. 1-5ms Power Good (PG) control signal Regulated 1.2V output 150mA output current Low quiescent operating current (90µA typical) "Zero" disable mode current Foldback current limiting protection Thermal shutdown protection Stable with low-ESR capacitors SOT23-5 package "MIC5258" pinout Lead-free version available Applications • • • • • Pentium 4 Motherboards Processor Power-up Sequencing Desktop, Notebook and Palmtop Computers PC Cards Peripheral Adapter Cards A dedicated control input (EN, Active High) has been included for power-up sequencing flexibility. When this input is taken low, the regulator is disabled. In this state, the supply current will drop to near zero. An internal discharge MOSFET resistance (500Ω) will force the output to ground whenever the device has been shutdown. The CM3102 is fully protected, offering both overload current limiting and high temperature thermal shutdown. Available in a tiny SOT23 package, the device is ideal for space critical applications. The CM3102 is available with optional lead-free finishing. Pentium 4 Motherboard Application Circuit Simplified Electrical Schematic CM3102-12Sx 10Ω IN VCC3 OUT EN 1.2V PG VCCVID PG GND .1µF* 1.2V/150mA IN OUT EN .1µF + VREF 1.2V * Input capacitor optional. - Typical Application Circuit 47kΩ + 2.5ms CM3102-12Sx PG VREF X 0.93 VIN IN OUT VOUT EN EN PG PG 1X GND 1µF* 1µF GND GND * Input capacitor optional. © 2004 California Micro Devices Corp. All rights reserved. 01/20/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 1 CM3102 PACKAGE / PINOUT DIAGRAM Top View 1 GND 2 EN 3 BA12/BB12 IN 5 OUT 4 PG 5-pin SOT23 Note: This drawing is not to scale. PIN DESCRIPTIONS PIN NAME 1 IN 2 GND 3 EN DESCRIPTION Positive input voltage for the regulator. The internal loading on this input is typically 300µA whenever the regulator is enabled, and less than 1µA when the regulator is disabled. Although an input filter capacitor is not required, it is recommended that a 1µF ceramic capacitor be used for additional filtering and stability if this pin is greater than 2 inches from the main input filter. The negative reference for all voltages. Enable/shutdown input. When EN is asserted high (VEN ≥ 1.6V), the regulator is enabled. When EN is asserted low (VEN ≤0.4V), the regulator’s series pass transistor is forced into a high impedance mode and an internal discharge resistance (500Ω) is applied to the output to quickly reduce the output voltage to 0 volts. 4 PG 5 OUT Power Good output. This is an open drain output and functions as a supply voltage supervisor for the output voltage. It is asserted low when the output falls below 89% of its nominal value. This output becomes inactive when VOUT remains above 97% of its nominal value for 1 to 5ms. The regulated voltage output. An output capacitor of 1µF is recommended to minimize any transient load disturbances under normal operating conditions. Additional output capacitance can be used to further improve transient load response. Ordering Information PART NUMBERING INFORMATION Standard Finish Ordering Part Lead-free Finish Ordering Part Regulator Pins Package Number1 Part Marking Number1 Part Marking CM3102-12 5 SOT23-5 CM3102-12ST BA12 CM3102-12SO BB12 Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. © 2004 California Micro Devices Corp. All rights reserved. 2 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 01/20/04 CM3102 Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS +2000 V [GND - 0.6] to +6.0 [GND - 0.6] to [VIN+0.6] [GND - 0.6] to [VIN+0.6] V V V -40 to +150 °C Operating Temperature Range Ambient Junction 0 to +70 0 to +150 °C °C Power Dissipation (See note 1) Internally Limited W ESD Protection (HBM) Pin Voltages VIN VOUT VEN Storage Temperature Range Note 1: The power rating is based on a printed circuit board heat spreading capability equivalent to 2 square inches of copper connected to the GND pins. Typical multi-layer boards using power plane construction will provide this heat spreading ability without the need for additional dedicated copper area. Please consult with factory for thermal evaluation assistance. STANDARD OPERATING CONDITIONS PARAMETER VALUE UNITS VIN 2.7 to 5.5 V Ambient Operating Temperature Range 0 to +70 °C Load Current 0 to 150 mA COUT 1 +20% µF © 2004 California Micro Devices Corp. All rights reserved. 01/20/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 3 CM3102 ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOUT Regulator Output Voltage 0.1mA < ILOAD < 150mA 1.1 1.2 1.3 V VR LOAD Load Regulation 10mA < ILOAD < 150mA 30 mV VR LINE Line Regulation xx ILOAD = 5mA; 2.7V < V IN < to 3.6V 20 mV 350 mA ILIM Overload Current Limit ISC Short Circuit Current Limit VOUT < 0.5V 140 mA Discharge Resistance EN tied to GND 500 Ω IGND Ground Current Regulator Enabled (EN=VIN); ILOAD= 0mA Regulator Enabled (EN=VIN); ILOAD= 150mA Regulator Disabled (EN=GND); (Disable Mode) 90 100 0.01 VEN EN Input Logic High Threshold Regulator Enabled VDIS EN Input Logic Low Threshold IEN Enable Input Current RDISCH 160 200 250 10 1.6 V Regulator Disabled 0.4 VPGL Power Good Low Threshold % of VOUT (PG ON) VPGH Power Good High Threshold % of VOUT (PG OFF) VOL Power Good Logic "0" Voltage IL=100µA; Fault Condition 0.02 IPG Power Good Leakage Current Power Good Off; V PG=5.5V 0.01 V µA 0.01 89 PG DELAY Delay Time to Power Good µA µA µA % 1 97 % 0.1 V µA 5 mS Note 1: Operating Characteristics are over Standard Operating Conditions unless otherwise specified. Timing Diagram © 2004 California Micro Devices Corp. All rights reserved. 4 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 01/20/04 CM3102 Performance Information CM3102 Typical DC Characteristics (nominal conditions unless specified otherwise) Load Regulation Line Regulation (1% and 100% rated load) 1.30 1.23 OUTPUT VOLTAGE [V] OUTPUT VOLTAGE [V] 1.25 1.21 1.19 1.17 1.15 50 100 150 200 LOAD CURRENT [mA] 150mA 1.15 250 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 INPUT VOLTAGE [V] Power Good Pull-up Resistor vs. VPG Foldback Current Protection 1.4 3.5 POWER GOOD VOLTAGE [V] OUTPUT VOLTAGE [V] 1mA 1.20 1.10 0 1.2 1.0 0.8 0.6 0.4 0.2 3.0 Power Good 2.5 2.0 1.5 1.0 0.5 Power Fail 0.0 10000 GROUND CURRENT [uA] 125 25 1000 125 50 100 150 75 PULL-UP RESISTOR [kΩ ] Ground Current vs. Input Voltage (1mA Load) 150 100 10 Ground Current vs. Load Current (VIN=3.3V) 1 400 0.1 100 200 300 LOAD CURRENT [mA] 0.01 0 0.001 0.0 GROUND CURRENT [uA] 1.25 100 75 50 25 0 0 0 50 100 150 200 LOAD CURRENT [mA] 250 0 2 4 6 INPUT VOLTAGE [V] © 2004 California Micro Devices Corp. All rights reserved. 01/20/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 5 CM3102 Performance Information (cont’d) CM3102 Typical DC Characteristics (cont’d, nominal conditions unless specified otherwise) Current Limit vs. Input Voltage (VOUT=1.15V) 600 160 CURRENT LIMIT [mA] SHORT CIRCUIT CURRENT [mA] Short Circuit Current vs. Input Voltage 180 140 120 100 80 60 40 500 400 300 200 100 20 0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.5 3.0 INPUT VOLTAGE [V] 5.0 PGDELAY vs. Input Voltage 1.10 2.0 1.08 1.5 PGDELAY [ms] ENABLE THRESHOLD VOLTAGE [V] Enable Voltage vs. Input Voltage 3.5 4.0 4.5 INPUT VOLTAGE [V] 1.06 1.04 1.0 0.5 1.02 1.00 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 INPUT VOLTAGE [V] 2.5 3.0 3.5 4.0 4.5 INPUT VOLTAGE [V] 5.0 © 2004 California Micro Devices Corp. All rights reserved. 6 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 01/20/04 CM3102 Performance Information (cont’d) CM3102 Transient Characteristics (nominal conditions unless specified otherwise) (PG connected to VIN with a 47kΩ resistor) Line Transient (0.6Vpp) Step Response (1mA Load, COUT = 1uF Ceramic, no CIN) Load transient (10% to 90%) Step Response (VIN = 3.3V, CIN = COUT = 1uF Ceramic) Enable Response (150mA Load, CIN = COUT = 1uF Ceramic) Cold Start & Power Down (150mA Load, CIN = COUT = 1uF Ceramic) © 2004 California Micro Devices Corp. All rights reserved. 01/20/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 7 CM3102 Performance Information (cont’d) CM3102-12ST/SO Typical Thermal Characteristics The overall junction to ambient thermal resistance (θJA) for device power dissipation (PD) consists primarily of two paths in series. The first path is the junction to the case (θ JC) which is defined by the package style, TJUNC = TAMB + PD (θ JC) + PD (θCA) OUTPUT VOLTAGE [V] and the second path is case to ambient (θ CA) thermal resistance which is dependent on board layout. The final operating junction temperature for any set of conditions can be estimated by the following thermal equation: VOUT 1.230 = 70°C + 55°C = 125°C Thermal characteristics were measured using a double sided board with two square inches of copper area connected to the GND pin for "heat spreading". Measurements showing performance up to junction temperature of 125°C were performed under light load conditions (1mA). This allows the ambient temperature to be representative of the internal junction temperature. Note: The use of multi-layer board construction with separate ground and power planes will further enhance the overall thermal performance. In the event of no copper area being dedicated for heat spreading, a multi-layer board construction, using only the minimum size pad layout, will provide the CM3102-12ST/SO with an overall θJA of 175°C/W which allows up to 450mW to be safely dissipated for the maximum junction temperature. 1.190 0 25 50 AMBIENT TEMPERATURE [oC] 75 VOUT Variation with TJUNCT (1mA Load) 1.230 OUTPUT VOLTAGE [V] = 70°C + 315mW X (175°C/W) 1.200 -25 1.220 1.210 1.200 1.190 1.180 1.170 -25 0 25 50 75 100 JUNCTION TEMPERATURE [oC] 125 Short Circuit Current vs. TJUNCT 200 SHORT CIRCUIT CURRENT [mA] = TAMB + PD (θ JA) 1.210 1.170 The CM3102-12ST/SO uses a SOT23-5 package. When this package is mounted on a double sided printed circuit board with two square inches of copper allocated for "heat spreading", the resulting θJA is 175°C/W. TJUNC 1.220 1.180 = TAMB + PD (θJA) Based on a maximum power dissipation of 315mW (2.1Vx150mA), with an ambient of 70°C the resulting junction temperature will be: Variation with TAMB (150mA Load) 150 100 50 0 -50 -25 0 25 50 75 100 125 JUNCTION TEMPERATURE [oC] © 2004 California Micro Devices Corp. All rights reserved. 8 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 01/20/04 CM3102 Mechanical Details SOT23-5 Mechanical Specifications Mechanical Package Diagrams Dimensions for CM3102-12ST/SO device packaged in 5-pin SOT23 package are presented below. TOP VIEW For complete information on the SOT23-5 package, see the California Micro Devices SOT23 Package Information document. e1 e 5 4 E1 E 1 2 3 PACKAGE DIMENSIONS Package SOT23-5 (JEDEC name is MO-178) Pins 5 Dimensions Millimeters Min Max Min Max -- 1.45 -- 0.0571 A1 0.00 0.15 0.0000 0.0059 b 0.30 0.50 0.0118 0.0197 c 0.08 0.22 0.0031 0.0087 D 2.75 3.05 0.1083 0.1201 E 2.60 3.00 0.1024 0.1181 E1 1.45 1.75 0.0571 0.0689 e 0.95 BSC 0.0374 BSC e1 1.90 BSC 0.0748 BSC L1 # per tape and reel 0.30 0.60 0.60 REF SIDE VIEW Inches A L b 0.0118 D A A1 END VIEW c 0.0236 L1 L 0.0236 REF 3000 pieces Package Dimensions for SOT23-5. © 2004 California Micro Devices Corp. All rights reserved. 01/20/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 9