TI SN74ALVCH16646

SN74ALVCH16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES032E– JULY 1995 – REVISED FEBRUARY 1999
D
D
D
D
D
D
Member of the Texas Instruments
Widebus  Family
EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
description
This 16-bit bus transceiver and register is
designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH16646 can be used as two 8-bit
transceivers or one 16-bit transceiver. Data on the
A or B bus is clocked into the registers on the
low-to-high transition of the appropriate clock
(CLKAB or CLKBA) input. Figure 1 illustrates the
four fundamental bus-management functions that
can be performed with the SN74ALVCH16646.
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1DIR
1CLKAB
1SAB
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2SAB
2CLKAB
2DIR
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
1OE
1CLKBA
1SBA
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2SBA
2CLKBA
2OE
Output-enable (OE) and direction-control (DIR)
28
29
inputs are provided to control the transceiver
functions. In the transceiver mode, data present at
the high-impedance port may be stored in either
register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent
mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer
during the transition between stored and real-time data. DIR determines which bus receives data when OE is
low. In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the
other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16646 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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1
SN74ALVCH16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES032E– JULY 1995 – REVISED FEBRUARY 1999
FUNCTION TABLE
INPUTS
DATA I/Os
OE
DIR
CLKAB
CLKBA
SAB
SBA
A1–A8
B1–B8
X
X
↑
X
X
X
Input
Unspecified†
OPERATION OR FUNCTION
X
X
X
↑
X
X
Unspecified†
Input
Store A, B unspecified†
Store B, A unspecified†
H
X
↑
↑
X
X
Input
Input
Store A and B data
H
X
H or L
H or L
X
X
Input disabled
Input disabled
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B bus
L
H
H or L
X
H
X
Input
Output
Stored A data to B bus
† The data-output functions may be enabled or disabled by various signals at OE and DIR. Data-input functions always are
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
2
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SN74ALVCH16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
OE
L
DIR
L
CLKAB CLKBA
X
X
SAB
X
BUS B
BUS A
BUS A
BUS B
SCES032E– JULY 1995 – REVISED FEBRUARY 1999
SBA
L
OE
L
DIR
H
DIR
X
X
X
CLKAB CLKBA
X
↑
X
↑
↑
↑
SAB
L
SAB
X
X
X
SBA
X
BUS B
BUS A
BUS A
OE
X
X
H
CLKBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
CLKAB
X
SBA
X
X
X
OE
L
L
DIR
L
H
CLKAB
X
H or L
CLKBA
H or L
X
SAB
X
H
SBA
H
X
TRANSFER STORED DATA
TO A AND/OR B
STORAGE FROM
A, B, OR A AND B
Figure 1. Bus-Management Functions
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3
SN74ALVCH16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES032E– JULY 1995 – REVISED FEBRUARY 1999
logic symbol†
1OE
1DIR
1CLKBA
1SBA
1CLKAB
1SAB
2OE
2DIR
2CLKBA
2SBA
2CLKAB
2SAB
1A1
56
1
55
54
2
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
C6
3
G7
29
28
30
31
27
26
G10
10 EN8 [BA]
10 EN9 [AB]
C11
G12
C13
G14
≥1
5
1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
7
1
2A3
2A4
2A5
2A6
2A7
2A8
≥1
7
51
49
9
48
10
47
12
45
13
44
14
43
15
16
≥1
8
1 14
12 11D
42
≥1
1B3
1B4
1B5
1B6
1B7
1B8
2B1
9
41
17
40
19
38
20
37
21
36
23
34
24
33
POST OFFICE BOX 655303
1B2
12 1
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
4
1B1
2
8
13D 14
2A2
52
5 1
6D
6
4D
5
• DALLAS, TEXAS 75265
2B2
2B3
2B4
2B5
2B6
2B7
2B8
SN74ALVCH16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES032E– JULY 1995 – REVISED FEBRUARY 1999
logic diagram (positive logic)
56
1OE
1DIR
1CLKBA
1SBA
1CLKAB
1SAB
1
55
54
2
3
One of Eight Channels
1D
C1
1A1
5
52
1B1
1D
C1
2OE
To Seven Other Channels
29
28
2DIR
2CLKBA
2SBA
2CLKAB
2SAB
30
31
27
26
One of Eight Channels
1D
C1
2A1
15
42
2B1
1D
C1
To Seven Other Channels
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5
SN74ALVCH16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES032E– JULY 1995 – REVISED FEBRUARY 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
High-level input voltage
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VIL
VI
VO
IOH
Low-level input voltage
MIN
MAX
1.65
3.6
2
0.35 × VCC
0.7
0
0
IOL
Low level output current
Low-level
∆t/∆v
Input transition rise or fall rate
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
V
0.8
Output voltage
VCC = 2.7 V
VCC = 3 V
V
1.7
Input voltage
High level output current
High-level
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V
VCC = 2.3 V
UNIT
VCC
VCC
V
V
–4
–12
–12
mA
–24
4
12
12
mA
24
10
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ALVCH16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES032E– JULY 1995 – REVISED FEBRUARY 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
IOH = –100 µA
IOH = –4 mA
1.65 V
IOH = –6 mA
VOH
IOH = –12 mA
IOH = –24 mA
IOL = 100 µA
IOZ§
ICC
∆ICC
Ci
2
2.3 V
1.7
UNIT
2.7 V
2.2
3V
2.4
3V
2
V
0.2
2.3 V
0.4
2.3 V
0.7
2.7 V
0.4
3V
0.55
±5
3.6 V
VI = 0.58 V
VI = 1.07 V
1.65 V
25
1.65 V
–25
VI = 0.7 V
VI = 1.7 V
2.3 V
45
2.3 V
–45
VI = 0.8 V
VI = 2 V
3V
75
3V
–75
V
µA
µA
VI = 0 to 3.6 V‡
3.6 V
±500
VO = VCC or GND
VI = VCC or GND,
3.6 V
±10
µA
3.6 V
40
µA
750
µA
One input at VCC – 0.6 V,
Control inputs
2.3 V
0.45
IOL = 24 mA
VI = VCC or GND
II(hold)
(
)
MAX
VCC–0.2
1.2
1.65 V
IOL = 12 mA
II
TYP†
1.65 V to 3.6 V
IOL = 4 mA
IOL = 6 mA
VOL
MIN
IO = 0
Other inputs at VCC or GND
3 V to 3.6 V
VI = VCC or GND
VO = VCC or GND
3.3 V
3.5
pF
Cio
A or B ports
3.3 V
8.5
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§ For I/O ports, the parameter IOZ includes the input leakage current.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 4)
VCC = 1.8 V
MIN
fclock
tw
Clock frequency
MAX
¶
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 2.7 V
MIN
150
MAX
VCC = 3.3 V
± 0.3 V
MIN
150
UNIT
MAX
150
MHz
Pulse duration
CLKAB or CLKBA high or low
¶
tsu
Setup time
A before CLKAB↑ or
B before CLKBA↑
¶
1.6
1.7
1.4
ns
th
Hold time
A after CLKAB↑ or
B after CLKBA↑
¶
0.6
0.4
0.7
ns
3.3
3.3
3.3
ns
¶ This information was not available at the time of publication.
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SN74ALVCH16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES032E– JULY 1995 – REVISED FEBRUARY 1999
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 4)
PARAMETER
FROM
(INPUT)
VCC = 1.8 V
TO
(OUTPUT)
MIN
†
fmax
A or B
tpd
B or A
CLKAB or CLKBA
SAB or SBA
A or B
TYP
VCC = 2.5 V
± 0.2 V
MIN
MAX
150
VCC = 2.7 V
MIN
MAX
150
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
150
MHz
†
1
4.8
4.5
1
3.9
†
1
5.6
5.2
1
4.5
†
1
6.8
6.4
1
5.3
ns
OE
A or B
†
1
6.5
6.2
1
5.1
ns
tdis
OE
A or B
†
1.6
5.7
5
1.4
4.7
ns
ten
DIR
A or B
†
1
7.8
6.2
1
5.1
ns
†
1.5
6.5
6
1.1
5.3
ns
ten
tdis
A or B
DIR
† This information was not available at the time of publication.
operating characteristics, TA = 25°C
PARAMETER
Cpd
d
Power dissipation
capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 50 pF,
pF
VCC = 1.8 V
TYP
†
f = 10 MHz
† This information was not available at the time of publication.
8
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†
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
39
43
10
12
UNIT
pF
SN74ALVCH16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES032E– JULY 1995 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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SN74ALVCH16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES032E– JULY 1995 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ALVCH16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES032E– JULY 1995 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
1.5 V
1.5 V
Input
0V
1.5 V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
2.7 V
1.5 V
0V
tPZL
2.7 V
Input
1.5 V
1.5 V
0V
tPLH
VOH
Output
1.5 V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLZ
3V
1.5 V
tPZH
tPHL
1.5 V
VOL
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
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