TI SN74LVCH16952ADL

SN74LVCH16952A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS320F – NOVEMBER 1993 – REVISED JUNE 1998
D
D
D
D
D
D
D
D
D
D
Member of the Texas Instruments
Widebus  Family
EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V VCC)
Power Off Disables Outputs, Permitting
Live Insertion
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 16-bit registered transceiver is designed for
1.65-V to 3.6-V VCC operation.
DGG OR DL PACKAGE
(TOP VIEW)
1OEAB
1CLKAB
1CEAB
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2CEAB
2CLKAB
2OEAB
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEBA
1CLKBA
1CEBA
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2CEBA
2CLKBA
2OEBA
The SN74LVCH16952A contains two sets of
D-type flip-flops for temporary storage of data
flowing in either direction. It can be used as two
8-bit transceivers or one 16-bit transceiver. Data
on the A or B bus is stored in the registers on the
low-to-high transition of the clock (CLKAB or
CLKBA) input, provided that the clock-enable
(CEAB or CEBA) input is low. Taking the
output-enable (OEAB or OEBA) input low
accesses the data on either port.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVCH16952A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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1
SN74LVCH16952A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS320F – NOVEMBER 1993 – REVISED JUNE 1998
FUNCTION TABLE†
INPUTS
OUTPUT
B
CEAB
CLKAB
OEAB
A
H
X
L
X
X
L
L
X
L
↑
L
L
L
L
↑
L
H
H
B0‡
B0‡
X
X
H
X
Z
† A-to-B data flow is shown; B-to-A data flow is
similar, but uses CEBA, CLKBA, and OEBA.
‡ Level of B before the indicated steady-state input
conditions were established
2
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SN74LVCH16952A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS320F – NOVEMBER 1993 – REVISED JUNE 1998
logic symbol†
1OEBA
56
54
1CEBA
1CLKBA
55
1
1OEAB
3
1CEAB
1CLKAB
2
29
2OEBA
31
2CEBA
2CLKBA
2OEAB
30
28
26
2CEAB
2CLKAB
1A1
27
5
EN3
G1
1C5
EN4
G2
2C6
EN9
G7
7C11
EN10
G8
8C12
3
6D
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A3
2A4
2A5
2A6
2A7
2A8
52
51
8
49
9
48
10
47
12
45
13
44
14
43
15
42
9
1B1
4
6
12D
2A2
5D
11D
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
10
16
41
17
40
19
38
20
37
21
36
23
34
24
33
2B2
2B3
2B4
2B5
2B6
2B7
2B8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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3
SN74LVCH16952A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS320F – NOVEMBER 1993 – REVISED JUNE 1998
logic diagram (positive logic)
1CLKENAB
1CLKAB
1OEBA
1A1
3
54
2
55
56
1
5
One of Eight
Channels
C1
CE
1D
52
1CLKENBA
1CLKBA
1OEAB
1B1
C1
CE
1D
To Seven Other Channels
2CLKENAB
2CLKAB
2OEBA
26
31
27
30
29
28
One of Eight
Channels
2A1
C1
CE
1D
15
C1
CE
1D
To Seven Other Channels
4
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42
2CLKENBA
2CLKBA
2OEAB
2B1
SN74LVCH16952A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS320F – NOVEMBER 1993 – REVISED JUNE 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Input voltage range, VI: (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
VCC
Supply voltage
VIH
High-level input voltage
Operating
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VIL
VI
VO
IOH
Low-level input voltage
Output voltage
High level output current
High-level
Low level output current
Low-level
∆t/∆v
Input transition rise or fall rate
MAX
1.65
3.6
1.5
UNIT
V
0.65 × VCC
V
1.7
2
0.35 × VCC
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
Input voltage
IOL
MIN
0.7
V
0.8
0
5.5
V
High or low state
0
3 state
0
VCC
5.5
V
VCC = 1.65 V
VCC = 2.3 V
–4
VCC = 2.7 V
VCC = 3 V
–12
–8
mA
–24
VCC = 1.65 V
VCC = 2.3 V
4
VCC = 2.7 V
VCC = 3 V
12
8
mA
24
0
10
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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5
SN74LVCH16952A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS320F – NOVEMBER 1993 – REVISED JUNE 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
IOH = –4 mA
VCC
1.65 V to 3.6 V
IOH = –8 mA
VOH
12 mA
IOH = –12
IOH = –24 mA
IOL = 100 µA
VOL
II
Control inputs
A or B ports
2.4
3V
2.2
2.3 V
0.7
IOL = 12 mA
IOL = 24 mA
2.7 V
0.4
3V
0.55
VI = 0 to 5.5 V
VI = 0.58 V
3.6 V
±5
1 65 V
1.65
23V
2.3
VI = 1.7 V
VI = 0.8 V
VO = 0 to 5.5 V
ICC
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V#
A or B ports
3V
3V
IO = 0
One input at VCC – 0.6 V,
Other inputs at
VCC or GND
VI = VCC or GND
POST OFFICE BOX 655303
µA
‡
‡
45
µA
–45
75
–75
±500
0
±10
µA
3.6 V
±10
µA
20
36V
3.6
20
2.7 V to 3.6 V
3.3 V
• DALLAS, TEXAS 75265
V
3..6 V
VO = VCC or GND
3.3 V
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This information was not available at the time of publication.
§ This is the bus-hold maximum dynamic current required to switch the input from one state to another.
¶ For I/O ports, the parameter IOZ includes the input leakage current, but not II(hold).
# This applies in the disabled state only.
6
UNIT
V
0.2
IOZ¶
Control inputs
2.2
0.45
Ioff
Cio
1.7
2.7 V
1.65 V
VI or VO = 5.5 V
Ci
2.3 V
MAX
1.65 V to 3.6 V
VI = 2 V
VI = 0 to 3.6 V§
∆ICC
1.65 V
VCC–0.2
1.2
TYP†
IOL = 4 mA
IOL = 8 mA
VI = 1.07 V
VI = 0.7 V
II(hold)
(
)
MIN
500
µA
µA
5
pF
8.5
pF
SN74LVCH16952A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS320F – NOVEMBER 1993 – REVISED JUNE 1998
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
VCC = 1.8 V
± 0.15 V
MIN
fclock
tw
MAX
Clock frequency
Setup time
th
Hold time
MIN
MAX
†
Pulse duration, CLK high or low
tsu
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
MIN
MAX
†
VCC = 3.3 V
± 0.3 V
MIN
150
150
†
†
3.3
3.3
Data before CLK↑
†
†
3.4
2.8
CE before CLK↑
†
†
1.8
1.4
Data after CLK↑
†
†
0.5
0.5
CE after CLK↑
†
†
1.1
1.9
UNIT
MAX
MHz
ns
ns
ns
† This information was not available at the time of publication.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
fmax
tpd
ten
tdis
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
CLKAB or CLKBA
B or A
†
†
†
†
OE
A or B
†
†
†
OE
A or B
†
†
†
MIN
MAX
MIN
†
MAX
†
VCC = 2.7 V
MIN
MAX
150
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
150
MHz
7.6
1.6
6.6
ns
†
8
1.1
6.6
ns
†
7.1
1.9
6.7
ns
1
ns
tsk(o)‡
† This information was not available at the time of publication.
‡ Skew between any two outputs of the same package switching in the same direction
operating characteristics, TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
Power dissipation capacitance
per transceiver
Outputs enabled
Outputs disabled
f = 10 MHz
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
TYP
TYP
TYP
†
†
87
†
†
43
UNIT
pF
† This information was not available at the time of publication.
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SN74LVCH16952A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS320F – NOVEMBER 1993 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1k Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1k Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
Open
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
8
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SN74LVCH16952A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS320F – NOVEMBER 1993 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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SN74LVCH16952A
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS320F – NOVEMBER 1993 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
1.5 V
0V
tPLH
tPHL
VOH
1.5 V
2.7 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
VOL
tPLZ
3V
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
0V
tPZL
2.7 V
Output
Input
1.5 V
1.5 V
tsu
Input
1.5 V
1.5 V
tPZH
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
10
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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