Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. 18-Bit Registered Transceivers SCCS056A - August 1994 - Revised October 2001 Features • • • • • • • • CY74FCT16500T CY74FCT162500T Functional Description FCT-C speed at 4.6 ns Ioff supports partial-power- mode operation Edge-rate control circuitry for significantly improved noise characteristics Typical output skew < 250 ps ESD > 2000V TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages Industrial temperature range of −40˚C to +85˚C VCC = 5V ± 10% These 18-bit universal bus transceivers can be operated in transparent, latched, or clock modes by combining D-type latches and D-type flip-flops. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock inputs (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B-to-A is similar to that of A-to-B and is controlled by OEBA, LEBA, and CLKBA. CY74FCT16500T Features: • 64 mA sink current, 32 mA source current • Typical VOLP (ground bounce) <1.0V at VCC = 5V, TA = 25˚C This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. CY74FCT162500T Features: • Balanced 24 mA output drivers • Reduced system switching noise • Typical VOLP (ground bounce) <0.6V at VCC = 5V, TA= 25˚C The CY74FCT16500T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162500T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162500T is ideal for driving transmission lines. SSOP/TSSOP Top View Logic Block Diagram OEAB LEAB 1 56 2 55 GND CLKAB A1 3 54 B1 GND 4 53 GND A2 5 52 B2 A3 6 51 B3 VCC 7 50 VCC A4 49 B4 OEBA 8 A5 9 48 B5 CLKAB A6 10 47 B6 GND 11 46 GND A7 12 13 45 B7 44 B8 A9 A 10 14 43 B9 15 42 B10 A 11 16 41 B11 A 12 17 40 B12 GND 18 39 38 GND B13 OEAB CLKBA LEBA LEAB C A8 C B1 A1 D D C C A 13 19 D D A 14 20 37 B14 A 15 21 36 B15 VCC 22 35 VCC A 16 A 17 23 34 B16 24 25 33 B17 32 GND 26 31 B18 27 30 CLKBA 28 29 GND TO 17 OTHER CHANNELS FCT16500-1 GND A 18 OEBA LEBA FCT16500-2 Copyright © 2001, Texas Instruments Incorporated CY74FCT16500T CY74FCT162500T Maximum Ratings[5, 6] Pin Summary Name (Above which the useful life may be impaired. For user guidelines, not tested.) Description OEAB A-to-B Output Enable Input OEBA B-to-A Output Enable Input (Active LOW) LEAB A-to-B Latch Enable Input Ambient Temperature with Power Applied................................... Com’l −55°C to +125°C LEBA B-to-A Latch Enable Input DC Input Voltage .................................................−0.5V to +7.0V CLKAB A-to-B Clock Input (Active LOW) DC Output Voltage ..............................................−0.5V to +7.0V CLKBA B-to-A Clock Input (Active LOW) A A-to-B Data Inputs or B-to-A Three-State Outputs DC Output Current (Maximum Sink Current/Pin) ...........................−60 to +120 mA B B-to-A Data Inputs or A-to-B Three-State Outputs Storage Temperature ....................... Com’l −55°C to +125°C Power Dissipation .......................................................... 1.0W Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015) [1, 2] Function Table Inputs Operating Range Outputs OEAB LEAB CLKAB A B L X X X Z H H X L L H H X H H H L L L H L H H H L H X B[3] H L L X B[4] Range Industrial Ambient Temperature VCC −40°C to +85°C 5V ± 10% Electrical Characteristics Over the Operating Range Parameter Description VIH Input HIGH Voltage VIL Input LOW Voltage Test Conditions Min. Typ.[7] Max. 2.0 V 0.8 Hysteresis[8] VH Input VIK Input Clamp Diode Voltage VCC=Min., IIN=−18 mA IIH Input HIGH Current IIL Input LOW Current IOZH Unit 100 mV −1.2 V VCC=Max., VI=VCC ±1 µA VCC=Max., VI=GND. ±1 µA High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=2.7V ±1 µA IOZL High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=0.5V ±1 µA IOS Short Circuit Current[9] VCC=Max., VOUT=GND −80 −200 mA IO Output Drive Current[9] VCC=Max., VOUT=2.5V −50 −180 mA Power-Off Disable VCC=0V, VOUT≤4.5V[10] ±1 µA IOFF −0.7 V −140 Notes: 1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = HIGH Impedance. = HIGH-to-LOW Transition. 2. A-to-B data flow is shown, B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA. 3. Output level before the indicated steady-state input conditions were established. 4. Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW. 5. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range. 6. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground. 7. Typical values are at VCC= 5.0V, TA= +25˚C ambient. 8. This parameter is specified but not tested. 9. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. 10. Tested at +25˚C. 2 CY74FCT16500T CY74FCT162500T Output Drive Characteristics for CY74FCT16500T Parameter VOH VOL Min. Typ.[7] VCC=Min., IOH=−3 mA 2.5 3.5 VCC=Min., IOH=−15 mA 2.4 3.5 VCC=Min., IOH=−32 mA 2.0 3.0 Description Output HIGH Voltage Output LOW Voltage Test Conditions VCC=Min., IOL=64 mA Max. Unit V 0.2 0.55 V Typ.[7] Max. Unit Output Drive Characteristics for CY74FCT162500T Parameter Description [9] Test Conditions Min. IODL Output LOW Current VCC=5V, VIN=VIH or VIL, VOUT=1.5V 60 115 150 mA IODH Output HIGH Current[9] VCC=5V, VIN=VIH or VIL, VOUT=1.5V −60 −115 −150 mA VOH Output HIGH Voltage VCC=Min., IOH=−24 mA 2.4 3.3 VOL Output LOW Voltage VCC=Min., IOL=24 mA V 0.3 0.55 V Typ.[7] Capacitance[8] (TA = +25˚C, f = 1.0 MHz) Parameter Description Test Conditions Max. Unit CIN Input Capacitance VIN = 0V 4.5 6.0 pF COUT Output Capacitance VOUT = 0V 5.5 8.0 pF Power Supply Characteristics Parameter Description Test Conditions Typ.[7] Max. Unit 5 500 µA 0.5 1.5 mA ICC Quiescent Power Supply Current VCC=Max. VIN≤0.2V, VIN≥VCC−0.2V ∆ICC Quiescent Power Supply Current (TTL inputs HIGH) VCC=Max. VIN=3.4V[11] ICCD Dynamic Power Supply Current[12] VCC=Max., One Input Toggling, VIN=VCC or 50%DutyCycle,OutputsOpen, VIN=GND OEAB=OEBA=VCC or GND 75 120 µA/MHz IC Total Power Supply Current[13] VCC=Max., f0=10 MHz (CLKAB), f1=5 MHz, 50% Duty Cycle, Outputs Open, One Bit Toggling, OEAB=OEBA=VCC LEAB=GND VIN=VCC or VIN=GND 0.8 1.7 mA VIN=3.4V or VIN=GND 1.3 3.2 mA VIN=VCC or VIN=GND 3.8 6.5[14] mA VIN=3.4V or VIN=GND 8.5 20.8[14] mA VCC=Max., f0=10 MHz, f1=2.5 MHz, 50% Duty Cycle, Outputs Open, Eighteen Bits Toggling, OEAB=OEBA=VCC LEAB=GND Notes: 11. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND. 12. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 13. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC+∆ICCDHNT+ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) = Duty Cycle for TTL inputs HIGH DH = Number of TTL inputs at DH NT ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 = Input signal frequency f1 = Number of inputs changing at f1 N1 All currents are in milliamps and all frequencies are in megahertz. 14. Values for these conditions are examples of the ICC formula. These limits are specified but not tested. 3 CY74FCT16500T CY74FCT162500T Switching Characteristics Over the Operating Range[15] CY74FCT16500CT/ CY74FCT162500AT CY74FCT162500CT Parameter Description Min. Max. Min. Max. Unit 150 Fig. No.[16] fMAX CLKAB or CLKBA frequency 150 MHz tPLH tPHL Propagation Delay A to B or B to A 1.5 5.1 1.5 4.6 ns 1, 3 tPLH tPHL Propagation Delay LEBA to A, LEAB to B 1.5 5.6 1.5 5.3 ns 1, 5 tPLH tPHL Propagation Delay CLKBA to A, CLKAB to B 1.5 5.6 1.5 5.3 ns 1, 5 tPZH tPZL Output Enable Time OEBA to A, OEAB to B 1.5 6.0 1.5 5.4 ns 1, 7, 8 tPHZ tPLZ Output Disable Time OEBA to A, OEAB to B 1.5 5.6 1.5 5.2 ns 1, 7, 8 tSU Set-Up Time, HIGH or LOW A to CLKAB, B to CLKBA 3.0 3.0 ns 9 tH Hold Time, HIGH or LOW A to CLKAB, B to CLKBA 0 0 ns 9 tSU Set-Up Time, HIGH or LOW A to LEAB, B to LEBA Clock HIGH 3.0 3.0 ns 4 Clock LOW 1.5 1.5 ns 4 tH Hold Time, HIGH or LOW A to LEAB, B to LEBA 1.5 1.5 ns 4 tW LEAB or LEBA Pulse Width HIGH 3.0 2.5 ns 5 tW CLKAB or CLKBA Pulse Width HIGH or LOW 3.0 ns 5 tSK(O) Output Skew[17] 3.0 0.5 0.5 ns Ordering Information CY74FCT16500T Speed (ns) 4.6 Ordering Code Package Name Package Type CY74FCT16500CTPACT Z56 56-Lead (240-Mil) TSSOP CY74FCT16500CTPVC/PVCT O56 56-Lead (300-Mil) SSOP Operating Range Industrial Ordering Information CY74FCT162500T Speed (ns) 4.6 5.1 Ordering Code Package Name Package Type CY74FCT162500CTPVC O56 56-Lead (300-Mil) SSOP 74FCT162500CTPVCT O56 56-Lead (300-Mil) SSOP CT74FCT162500ATPVC O56 56-Lead (300-Mil) SSOP 74FCT162500ATPVCT O56 56-Lead (300-Mil) SSOP Notes: 15. Minimum limits are specified but not tested on Propagation Delays. 16. See “Parameter Measurement Information” in the General Information section. 17. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design. 4 Operating Range Industrial Industrial CY74FCT16500T CY74FCT162500T Package Diagrams 56-Lead Shrunk Small Outline Package O56 56-Lead Thin Shrunk Small Outline Package Z56 5 PACKAGE OPTION ADDENDUM www.ti.com 27-Sep-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74FCT162500ATPVCG4 ACTIVE SSOP DL 56 74FCT162500ATPVCT ACTIVE SSOP DL 56 74FCT162500CTPVCG4 ACTIVE SSOP DL 56 74FCT162500CTPVCT ACTIVE SSOP DL 74FCT16500CTPACTE4 ACTIVE TSSOP 74FCT16500CTPACTG4 ACTIVE 74FCT16500CTPVCG4 20 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ACTIVE SSOP DL 56 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74FCT16500CTPVCTG4 ACTIVE SSOP DL 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY74FCT162500ATPVC ACTIVE SSOP DL 56 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY74FCT162500CTPVC ACTIVE SSOP DL 56 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY74FCT16500CTPACT ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY74FCT16500CTPVC ACTIVE SSOP DL 56 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY74FCT16500CTPVCT ACTIVE SSOP DL 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM FCT162500ATPVCTG4 ACTIVE SSOP DL 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM FCT162500CTPVCTG4 ACTIVE SSOP DL 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 20 20 20 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 27-Sep-2007 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device 74FCT162500ATPVCT Package Package Pins Type Drawing SSOP SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 74FCT162500CTPVCT SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 CY74FCT16500CTPACT TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1 CY74FCT16500CTPVCT SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74FCT162500ATPVCT SSOP DL 56 1000 346.0 346.0 49.0 74FCT162500CTPVCT SSOP DL 56 1000 346.0 346.0 49.0 CY74FCT16500CTPACT TSSOP DGG 56 2000 346.0 346.0 41.0 CY74FCT16500CTPVCT SSOP DL 56 1000 346.0 346.0 49.0 Pack Materials-Page 2 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). 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