FX805 Sub-Audio Signalling Processor Rx SUB-AUDIO OUT COMPARATOR IN OUT Rx LOWPASS Rx SUB-AUDIO IN + DIGITAL – FILTER NOISE FREQUENCY NOTONE ASSESMENT TIMER COMPARATOR AMP 180Hz/260Hz OUT COMMAND DATA Raw NRZ “Data” REPLY DATA NRZ Rx + DATA and IN – Rx AMP BAUD RATE FREQUENCY EXTRACTOR MEASUREMENT NRZ Rx Data (COUNTER) NRZ Rx Baud Rate V BIAS WAKE V SS NRZ Tx Data Variable Bandwidth NRZ Tx BAUD RATE CTCSS Tx TONE INTERRUPT SERIAL CLOCK ADDRESS SELECT and XTAL CHIP SELECT Tx SHIFT REGISTER CLOCK AND Rx DATA BUFFER XTAL/CLOCK C-BUS INTERFACE CONTROL LOGIC VDD GENERATOR NOTONE Tx LEVEL CTCSS “Sub-Audio” Frequency Tx SUB-AUDIO OUT ADJUST SUB-AUDIO BANDSTOP NRZ Rx CLOCK RATE Tx SUB-AUDIO LOWPASS Audio Signal Path AUDIO IN AUDIO OUT Audio By-Pass Fig.1 FX805 Sub-Audio Signalling Processor FX805 Sub-Audio Signalling Processor A µProcessor controlled, sub-audio frequency signalling processor to provide an outband audio and digital signalling facility for PMR radio systems. This device caters for the transmission and non-predictive reception of: ● Continuous Tone Controlled Squelch (CTCSS) tones and other non-standard sub-audio frequencies. ● Non-Return-to-Zero (NRZ) data to facilitate Continuous Digitally Coded Squelch (CDCS/DPL ) system operations. To achieve these functions, the FX805 has on-chip: ● A non-predictive CTCSS Tone Decoder and CDCS subaudio signal demodulator. ● A CTCSS/NRZ Encoder with Tx level adjustment and lowpass filter output stage with optional NRZ pre-emphasis. ● A selectable sub-audio bandstop filter. ● A Notone (CTCSS Rx) period timer. Setting of the FX805 functions and modes is by data loaded from the µController to the controlling registers within the device. Reply Data and Interrupt protocol keep the µController up to date on the operational status of the circuitry –– all via the “C-BUS” interface. CTCSS tone data for transmission is generated within the µController, loaded to CTCSS Tx Frequency Register, encoded and output as a tone via the Tx Sub-Audio Lowpass Filter. Received non-predicted CTCSS tone frequencies are measured and the resulting data, in the form of a 2-byte data-word, is presented via the CTCSS Rx Frequency Register to the µController for matching against a ‘look-up’ table. Noise filtering is provided to improve the signal quality prior to measurement. NRZ coded data streams for transmission, when generated within a µController, are loaded to the NRZ Tx Data Buffer and output, in 8-bit bytes, through the Lowpass Filter circuitry as sub-audio signals. CDCS turn-off tones can be added to the data signals by switching the FX805 to the CTCSS transmit mode at the appropriate time. NRZ coding is produced by the µController and translated into sub-audio signals by the FX805. Received NRZ data is filtered, detected and placed into the NRZ Rx Data Register which is then available for transfer one byte at a time, to the µController, for decoding by software. Clock extraction circuitry is provided on chip and Rx and Tx baud rates are selectable. Provision is made in both hardware and system software allocations to address two FX805 Sub-Audio Signalling Processors consecutively to achieve multi-mode, duplex operation. The FX805 has a powersaving function which may be controlled by software or a dedicated (Wake) input. The FX805 is a low-power, 5-volt CMOS integrated circuit and is available in 24-pin DIL cerdip and 24-pin/lead plastic SMD packages. DPL is a registered trademark of Motorola Inc. Publication D/805/3 July 1994 Pin Number Function FX805 J/LG/LS 1 Xtal: The output of the on-chip clock oscillator. External components are required at this input when a Xtal (fXTAL) input is used. See Figure 2. 2 Xtal/Clock: The input to the on-chip clock oscillator inverter. A Xtal or externally derived clock (fXTAL) should be connected here. See Figure 2. 3 Address Select: This pin enables two FX805 devices to be used on the same “C-BUS,” providing fullduplex operation. See Tables 1 and 2. 4 Interrupt Request (IRQ): The output of this pin indicates an interrupt condition to the µController, by going to a logic “0.” This is a “wire-or able” output, allowing the connection of up to 8 peripherals to 1 interrupt port on the µController. This pin has a low impedance pulldown to logic “0” when active and a high impedance when inactive. The System IRQ line requires 1 pullup resistor to VDD. The conditions that cause interrupts are indicated in the Status Register (Table 4) and are shown below: Rx CTCSS Tone Measurement Complete 1 NRZ Rx Data Byte Received NRZ Tx Buffer Ready CTCSS NOTONE Timer Expired New NRZ Rx Data Received Before Last Byte Read NRZ Data Transmission Complete 5 Serial Clock: The “C-BUS” serial clock input. This clock, produced by the µController, is used for transfer timing of commands and data to and from the Sub-Audio Signalling Processor. See Timing Diagrams. 6 Command Data: The “C-BUS” serial data input from the µController. Data is loaded to this device in 8-bit bytes, MSB (B7) first, and LSB (B0) last, synchronized to the Serial Clock. See Timing Diagrams. 7 Chip Select (CS): The “C-BUS” data loading control function. This input is provided by the µController. Data transfer sequences are initiated, completed or aborted by the CS signal. See Timing Diagrams. 8 Reply Data: The “C-BUS” serial data output to the µController. The transmission of Reply Data bytes is synchronized to the Serial Clock under the control of the Chip Select input. This 3-state output is held at high impedance when not sending data to the µController. See Timing Diagrams. 9 Tx Sub-Audio Out: The sub-audio output (pure or NRZ derived). Signals are band-limited, the Tx Output Filter has a variable bandwidth, see Table 6. This output is at VBIAS (a) when the NRZ Encoder is enabled but no data is being transmitted, (b) when the FX805 is placed in the Powersave All condition. 10 Audio In: The input to the switched sub-audio bandstop (highpass) filter. This input is internally biased and requires to be a.c. coupled by capacitor C7. 11 Audio Out: The output of the ‘audio signal path’ (filter or by-pass). This output is controlled by the Control Register and when disabled is held at VDD/2. 12 VSS: Negative Supply (Signal Ground). 2 Pin Number Function FX805 J/LG/LS 13 Rx Amp (-) In: The inverting input to the on-chip Rx Input Amp. See Figures 2, 3 and 4. 14 Rx Amp (+) In: The non-inverting input to the on-chip Rx Input Amp. 15 Rx Amp Out: The output of the on-chip Rx Input Op-Amp. This circuit may be used, with external components, as a signal amplifier and an anti-aliasing filter prior to the Rx Lowpass Filter, or for other purposes. See Figure 2 for component details. 16 Rx Sub-Audio In: The received sub-audio (CTCSS/NRZ) input. This input is internally biased to VDD/2 and requires to be a.c. coupled or biased. See Figure 2 for component details. 17 Rx Sub-Audio Out: The output of the Rx Lowpass Filter. This output may be coupled into the on-chip amplifier or comparator as required. 18 VBIAS: The internal circuitry bias line, held at VDD/2 this pin must be decoupled to VSS by capacitor C8 (see Figure 2). 19 Comparator In (-): The inverting input to the on-chip “comparator” amplifier. See Figures 2, 3 and 4. 20 Comparator (+): The non-inverting input to the on-chip “comparator” amplifier. See Figures 2, 3 and 4. 21 Comparator Out: The output of the “comparator” amplifier. This node is also internally connected to the input of the Digital Noise Filter (see Figure 1). When both decoders are Powersaved, this output is at a logic “0.” 22 NOTONE Timing: External RC components connected to this pin form the timing mechanism of a NOTONE period timer. The external network determines the ‘charge-rate’ of the timer to VDD/2. Expiry of the timer will cause an interrupt. This facility is only used in the CTCSS Rx mode. 23 Wake: This ‘real-time ’ input can be used to reactivate the FX805 from the ‘Powersave All’ condition using an externally derived signal. The FX805 will be in a ‘Powersave All’ condition when both this pin and Bit 0 of the Control Register are set to a logic “1.” Recovery from “Powersave All” is achieved by putting either the Wake pin or the ‘Powersave All’ bit to logic “0,” thus allowing FX805 activation by the µController or an external signal, such as R.S.S.I. or Carrier Detect. 24 VDD: Positive supply rail. A single +5-volt power supply is required. Levels and voltages within the SubAudio Signalling Processor are dependant upon this supply. NOTE: (i) Further information on external components and DBS 800 system integration of this microcircuit are contained in the System Support Document. (ii) A glossary of abbreviations used in this document is supplied. (iii) Guidance upon the generation and manipulation of NRZ Rx and Tx data is given in DBS 800 Application Support Document. “C-BUS” is CML’s proprietry standard for the transmission of commands and data between a µController and DBS 800 microcircuits. It may be used with any µController, and can, if desired, take advantage of the hardware serial I/O functions embodied into many types of µController. The “C-BUS” data rate is determined soley by the µController. 3 Application Information External Components VDD SEE INSET XTAL 1 XTAL/CLOCK ADDRESS SELECT IRQ 24 2 23 3 22 4 21 SERIAL CLOCK 20 5 COMMAND DATA 6 CS 8 FX805J 19 7 REPLY DATA R C5 R6 R7 18 C7 VSS WAKE C6 NOTONE COMPARATOR OUT 8 R4 C8 COMPARATOR IN (+) COMPARATOR IN (-) VBIAS Rx SUB-AUDIO OUT 17 Tx SUB-AUDIO OUT * VDD C3 Rx SUB-AUDIO IN 9 AUDIO IN AUDIO OUT VSS 16 10 15 11 14 12 13 R3 D1 D2 Rx AMP OUT Rx AMP IN (+) Rx AMP IN (-) R R5 2 C4 VSS INSET XTAL X C2 R 1 1 Value R1 R2 R3 R4 R5 R6 R7 R8 1.0MΩ 360kΩ 10.0kΩ 150kΩ 100kΩ 150kΩ 22.0kΩ 360kΩ FX805J XTAL/CLOCK V C1 Component 1 2 SS = R9 R10 R11 C1 C2 C3 C4 C5 = Fig.4 Fig.4 Fig.4 33.0pF 33.0pF 1.5µF 15.0µF 1.0µF C6 C7 C8 C9 D1 D2 X1 = 1.0µF 0.1µF 1.0µF Fig.4 silicon small sig silicon small sig fXTAL 4.00MHz Fig.2 Recommended External Components Notes on external components and connections 1. Xtal/clock circuitry components shown INSET are recommended in accordance with CML Application Note D/XT/2 December 1991. The DBS 800 System Information Document contains additional notes on Xtal/ clock distribution and frequencies. 2. R8 is a System Component. Its value is chosen, for example, with the FX806 Modulation Summing Amplifier, to provide a sub-audio signal level of -11.0dB to the system modulator. 3. Components R6 and C6 are NOTONE timing components. FX805 Rx LPF 4. R2 and R5 are dependant upon the input signal level. Values given are for the specified composite signal. 5. R7 is used as the DBS 800 system common-pullup for the “C-BUS” Interrupt Request (IRQ) line, the optimum value of this component will depend upon the circuitry connected to the IRQ line. FX805 Rx AMP 17 14 D.C. RESTORATION + Rx AMP IN 13 16 FX805 COMPARATOR HYSTERESIS 15 – R4 R3 R2 D2 D1 C3 20 19 Rx Sub-Audio Input + COMPARATOR IN R5 C4 21 – COMPARATOR OUT VSS Fig.3 Employment of FX805 Input Components With reference to Figure 2, Figures 3 and 4 show in detail recommended alternative component configurations for the FX805. 4 Application Information ...... External Components ...... The output resistance (open loop) of the on-chip Rx Amp is ≈ 6kΩ. In the configuration shown in Figure 3, the (Rx Amp) RC time-constant is therefore 90ms. If this period is too long for some systems, ie. those employing half-duplex, short data bursts, an external amplifier should be considered in place of the FX805 on-chip Rx Amp. Figure 3 shows an input component configuration for use generally for CTCSS signal and NRZ data reception. Input coupling capacitor C3 is required because the Rx Sub-Audio Input is held at VBIAS during all powered conditions of the FX805. Diodes D1 and D2 can be any silicon smallsignal diode. FX805 Rx LPF From Rx Discriminator FX805 Rx AMP 16 EXTERNAL OP-AMP 17 FX805 COMPARATOR + 14 Rx AMP IN 15 – 13 + R3 – C9 D2 R2 R9 D1 R4 + 20 21 COMPARATOR IN – 19 D.C. RESTORATION R 10 R5 C4 COMPARATOR OUT HYSTERESIS R 11 VDD VSS Fig.4 FX805 Input Components Using an External Op-Amp Using an External Op-Amp For d.c. coupling the FX805 to the receiver’s discriminator output when using NRZ communication, it is recommended that an additional, external Op-Amp is employed as configured in Figure 4. This configuration will allow long sequences of logic “1s” or “0s” to be successfully decoded (eg. LTR trunking systems). Components R9, R10 and R11 should be calculated to provide an accurate potential of 2.5V d.c. (equal to VBIAS) at pin-junction 15/16 when using a discriminator input. C9 is an optional component which, if additional filtering is required, should be calculated, with R9 to provide a lowpass cut-off frequency (fCO) of 500Hz. LTR is a registered trademark of E.F. Johnson Company FX805 Operational Modes NRZ Tx (Encoding) NRZ Rx (Decoding) The NRZ Encoder is formed by a shift register and the Tx Sub-Audio Lowpass Filter. Data loaded from the Command Data line is output one 8-bit byte at a time from the NRZ Tx Data Register. The output data-signal level may be adjusted and filtered. Data may be pre-emphasized via a “C-BUS” command. The Tx baud rate is programmed as the NRZ Tx Baud Rate (RNRZ Tx) (Table 5). Input (NRZ type) sub-audio signals are filtered and the data clock extracted. Decoded data is serially loaded into a shift register buffer. This data is output one 8-bit byte at a time as Reply Data from the NRZ Rx Data Register (Page 14) to the µController. The expected Rx baud rate is programmed as the NRZ Rx Baud Rate (RNRZ Rx) (Table 5). Any codeword recognition can be carried out by software. CTCSS Tx (Encoding) CTCSS Rx ( Decoding) The CTCSS Tone Encoder comprises a clock-divider programmed by an 11-bit binary number (Q) loaded to the CTCSS Tx Frequency Register (Table 5) via the “C-BUS” Command Data line. The square-wave output of the encoder is fed through the Tx Level Adjust variable gain block to the Tx Sub-Audio Lowpass Filter, a variable bandwidth circuit controlled by 4-bits (P) of the CTCSS Tx Frequency Register. The Tx SubAudio output is a sine-wave. Standard and non-standard sub-audio tones are available, a ‘CDCS’ turn-off tone may be generated. Received CTCSS signals are filtered, coherence is increased by the digital noise filter. The quality of the signal is assessed by measurement of the cycle-to-cycle period variance and, provided it is sufficiently good, the frequency is measured over a period of 122.64 milliseconds. If the average signal quality is consistently too low, N OTONE is indicated, if not, the input frequency is precisely indicated in the CTCSS Rx Frequency Register in a binary form as shown in Figure 6. As any single sub-audio tone within the specified range may be selected, this would enable a ‘CDCS’ turn-off tone (of 134Hz) to be decoded whilst operating in the NRZ Rx mode. 5 Controlling Protocol Control of the FX805 Sub-Audio Signalling Processor's operation is by communication between the µController and the FX805 internal registers on the “C-BUS,” using Address/Commands (A/Cs) and appended instructions or data (see Figure 9). The use and content of these instructions is detailed in the following paragraphs and tables. The Address Select input enables the addressing of 2 separate FX805s on the “C-BUS” to provide full-duplex multi-mode signalling. FX805 Internal Registers FX805 internal registers are detailed below: Control Register (70H/78H) – Write only, control and configuration of the FX805. NRZ Rx Data Register (74H/7CH) – Read Only, a single-byte of received NRZ data. Status Register (71H/79H) – Read Only, reporting of device functions. NRZ Tx Data Register (75H/7DH) – Write Only, to load a single-byte of NRZ data for transmission one byte at a time. CTCSS Rx Frequency Register (72H/7AH) – Read Only, a 2-byte binary word indicating the frequency of the received sub-audio input. Gain-Set Register (76H/7EH) – Write Only, a single byte to set the gain of the Tx Lowpass Filter. CTCSS Tx Frequency / NRZ Tx or Rx Baud Rate Register (73H/7BH) – Write Only, a 2-byte command to set the relevant parameters. Address/Commands Instructions and data are loaded and transferred, via “C-BUS,” in accordance with the timing information given in Figures 9 and 10. Placing the Address Select input at a logic “0” will address FX805 No.1, a logic “1” will address FX805 No.2. Tables 1 and 2 show the list of A/C bytes relevant to the FX805. A complete list of DBS 800 “C-BUS” Address allocations is published in the System Support Document. The first byte of a loaded data sequence is always recognized by the “C-BUS” as an Address/Command (A/C) byte. Instruction and data transactions to and from this device consist of an Address/Command byte followed by either: (i) (ii) further instructions or data or, a Status or data Reply. Command Assignment Address/Command (A/C) Byte Hex. Binary MSB General Reset Write to Control Reg. Read Status Reg. Read CTCSS Rx Freq. Reg. Write to CTCSS Tx Frequency/ NRZ Baud Rate Reg. Read NRZ Rx Data Reg. Write to NRZ Tx Data Reg. Write to Gain-Set Reg. + Data Byte/s 1 byte Instruction to Control Reg. 1 byte Reply from Status Reg. 2 byte Reply of CTCSS Rx data 2 byte Instruction for Tx Frequency and NRZ Tx/Rx baud rates 1 byte binary data Reply 1 byte binary data Command 1 byte Instruction for Tx Output LSB 01 70 71 72 73 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 + + + + 74 75 76 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 0 0 1 0 1 0 + + + Table 1 – FX805 No.1 “C-BUS” Address/Commands Command Assignment Address Select input at a logic “0” Address/Command (A/C) Byte Hex. Binary MSB General Reset Write to Control Reg. Read Status Reg. Read CTCSS Rx Frequency Reg. Write to CTCSS Tx Frequency/ NRZ Baud Rate Reg. Read NRZ Rx Data Reg. Write to NRZ Tx Data Reg. Write to Gain-Set Reg. + Data Byte/s 1 byte Instruction to Control Reg. 1 byte Reply from Status Reg. 2 byte Reply of CTCSS Rx data 2 byte Instruction for Tx Frequency and NRZ Tx/Rx baud rates 1 byte binary data Reply 1 byte binary data Command 1 byte Instruction for Tx Output LSB 01 78 79 7A 7B 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 + + + + 7C 7D 7E 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 + + + Table 2 – FX805 No.2 “C-BUS” Address/Commands Address Select input at a logic “1” 6 Controlling Protocol ...... “Write to Control Register” – A/C 70H (78H), followed by 1 byte of Command Data. Table 3 (below) shows the configurations available to the FX805. Bits 5, 6 and 7 are used together to Enable and Powersave circuit sections as required. Control Bits Setting Transmitted First MSB 7 6 5 Functions Enabled Functions Powersaved 0 0 0 CTCSS Decoder NRZ Decoder and Both Encoders CTCSS Decoder and Both Encoders 0 0 1 NRZ Decoder 0 1 0 CTCSS Encoder All Decoders All Decoders 0 1 1 NRZ Encoder 1 0 0 CTCSS Encoder and Decoder NRZ Encoder and Decoder 1 0 1 NRZ Encoder and CTCSS Decoder None 1 1 1 1 0 1 NRZ Decoder and CTCSS Decoder All Encoders NRZ Decoder All Encoders (except Tx Sub-Audio LPF) and CTCSS Decoder 4 1 0 3 1 0 2 1 0 1 1 0 0 1 0 Enable Audio Output – Used with Bit 3 Disable Audio Output – Output to VBIAS Enable Sub-Audio Bandstop Filter (Audio Signal Path) By-pass Sub-Audio Bandstop Filter Enable All FX805 Interrupts Disable All FX805 Interrupts Set Rx Lowpass Filter bandwidth to 180Hz – For low CTCSS Tones or NRZ Data Set Rx Lowpass Filter bandwidth to 260Hz All Encoders and Decoders Powersaved (Powersave All) All Encoders and Decoders Enabled unless individually Powersaved Table 3 Control Register General Reset Glossary of Abbreviations Upon Power-Up the “bits” in the FX805 registers will be random (either “0” or “1”). A General Reset Command (01H) will be required to “reset” all microcircuits on the “C-BUS,” and has the following effect upon the FX805. Control Register Status Register NOTONE Timer Below is a list of abbreviations used within this Data Sheet. Set as 00H Set as 00H Discharged Warning – The following FX805 register configurations are not affected by a General Reset command: CTCSS Rx Frequency CTCSS Tx Frequency/NRZ Baud Rate Register NRZ Rx Data Register NRZ Tx Data Register Gain-Set Register Note that setting the Control Register in this way (General Reset) will set the FX805 to the CTCSS Decode mode and overwrite a “Powersave All” instruction. It should also be considered that a General Reset command will reset ALL DBS 800 microcircuits operating on the “C-BUS.” 7 CDCS Continuous Digitally Coded Squelch CTCSS Continuous Tone Controlled Squelch DPL LTR Digital Private Line Logic Trunked Radio NRZ Non-Return-to-Zero data levels fCO Filter cut-off frequency fCTCSS IN Sub-Audio Rx frequency fCTCSS OUT Sub-Audio Tx frequency fTONE Tone frequency fXTAL Xtal/clock frequency RNRZ Rx NRZ Rx baud rate RNRZ Tx NRZ Tx baud rate SINPUT Audio input signal Controlling Protocol ...... “Read Status Register” – A/C 71H (79H), followed by 1 byte of Reply Data. The Status Register indicates the operational condition of the FX805. Bits 0 to 5 are set individually to indicate specific actions within the device. When a Status Bit is set to a logic “1,” an Interrupt Request (IRQ) output is generated. A read of the Status Register will reset the interrupt condition and ascertain the state of this register. Table 4 (below) shows the conditions indicated by the Status Bits. Set By Logic Cleared By Logic Received First Not used “0” Not used “0” Status Bit MSB 7,6 5 NRZ data transmission complete. No new data loaded. “1” 1. 2. 3. Write to NRZ Tx Data Reg. or, General Reset or, NRZ Encoder Powersave. “0” 4 NRZ Tx Data Buffer ready for next data byte. “1” 1. 2. 3. Write to NRZ Tx Data Reg. or, General Reset or, NRZ Tx Powersave. “0” 3 New NRZ Rx data received before last byte was read. “1” 1. 2. 3. Read NRZ Rx Data Reg. or, General Reset or, NRZ Decoder Powersave. “0” 2 1 byte of NRZ Rx data received. “1” 1. 2. 3. Read NRZ Rx Data Reg. or, General Reset or, NRZ Decoder Powersave. “0” 1 NOTONE Timer period expired. “1” 1. 2. 3. Read Status Register or, General Reset or, CTCSS Decoder Powersave. “0” 0 Rx Tone Measurement complete. “1” 1. 2. 3. Read Status Register or, General Reset or, CTCSS Decoder Powersave. “0” Table 4 Status Register “Read CTCSS Rx Frequency Register” – A/C 72H(7AH), followed by 2 bytes of Reply Data. Measurement of CTCSS Rx Frequency (fCTCSS IN) The input sub-audio signal (fCTCSS IN), is filtered and measured in the Frequency Counter over the “measurement period” (122.64ms). When the measurement period of a successful decode is complete, the Rx Tone Measurement bit in the Status Register, and the Interrupt bit are set. The measuring function counts the number of complete input cycles occurring within the measurement period and then the number of measuring-clock cycles necessary to make up the period. The CTCSS Rx Frequency Register will now indicate the sub-audio signal frequency (fCTCSS IN) in the form of 2 data bytes (1 and 0) as illustrated in Figure 6. Measurement Period Complete Input Cycle Complete Input Cycle Complete Input Cycle Complete Input Cycle FILTERED and DOUBLED SUB-AUDIO INPUT SIGNAL N Complete Measuring Clock Input Cycles Cycle 2 x f CTCSS IN R Fig.5 Measurement of a CTCSS Rx Frequency 8 Controlling Protocol ...... “Read CTCSS Rx Frequency Register” ...... The Integer (N) – Byte 1 The Remainder (R) – Byte 0 A binary number representing ‘twice the number of complete input sub-audio cycle periods’ counted during the measurement period of 122.64ms A binary number representing the remainder part, R, of 2 x Sub-Audio Input Frequency. ‘R = number of specified measuring-clock cycles’ required to complete the specified measurement period (See N). The clock-cycle frequency is 4166.6Hz (REPLY DATA) (MSB) – TRANSMITTED FIRST 15 14 “0” “0” 13 Byte 1 12 11 Byte 0 10 9 8 7 6 5 “0” “0” Integer (N) 4 3 (REPLY DATA) (LSB) – TRANSMITTED LAST 2 1 0 Remainder (R) Fig. 6 Format of the CTCSS Rx Frequency Register CTCSS Rx Frequency Register Figure 6 (above) shows the format of the CTCSS Rx Frequency Register. Bits 0 (LSB) to 5 (MSB) (Byte 0) are used to represent the Remainder (R). From Byte 0, valid values of R = ≤ 31. Bits 8 (LSB) to 13 (MSB) are used to represent the Integer (N). From Byte 1, valid values of N = 16 ≤ N ≤ 61. This register is not affected by the General Reset command (01H) and may adopt any random configuration at Power-Up. ie. values of N less than 16 and greater than 61 are not within the specified frequency band. CTCSS Rx Frequency Measurement Formulæ To assist in the production of ‘look-up’ tables and limit-values in the µController and provide guidance upon the determination of N and R from a measured CTCSS frequency, the following formulæ show the derivation of the CTCSS Rx Frequency (fCTCSS IN) from the measured data bytes (N and R). fCTCSS IN In the measurement period of 122.64ms there are N cycles at 2 x fCTCSS IN and R clock-cycles at 4166.6Hz, for any input frequency. So fCTCSS IN = N x fXTAL Hz [1] R 1920 x (511 -R) N = INT (1920 x 511 x fCTCSS IN ) = INT 511 – N x fXTAL + 0.5 [3] 1920 x fCT CSS IN [2] fXTAL Calculate N first Examples (fXTAL = 4.00MHz): fCTCSS IN = 100Hz N = 24 R = 11; fCTCSS IN = 250Hz N = 61 R = 3 NOTONE Timing If there is no signal or the signal is of a consistently poor quality, the NOTONE Timer will start to charge via the timing components. When the timing period has expired (at VDD/2), an Interrupt and a Status bit (NOTONE Timer Expired) are generated. This is a one-shot function and is reset by a “Tone Measurement Complete” interrupt. The input sub-audio signal is monitored by the Frequency Assessment circuitry. Before any NOTONE action is enabled, the FX805 must have achieved at least one successful “Tone Measurement Complete” action. 9 Controlling Protocol ...... “Write to CTCSS Tx Frequency/NRZ Baud Rate Register” Command Data. The information loaded to this register will set either the: (a) CTCSS Tx Tone Frequency – A/C 73H (7BH), followed by 2 bytes of fCTCSS OUT (b) NRZ Tx Baud Rate RNRZ Tx (c) NRZ Rx Baud Rate RNRZ Rx The chosen mode for this register (a, b or c) is determined by the FX805 operational mode enabled by the Control Register (Table 3), as shown in the table below. Control Register Bits 7 6 5 FX805 Mode Enabled CTCSS Tx/NRZ Baud Rate Register Function 0 0 0 CTCSS Decode 0 0 0 1 1 0 NRZ Decode CTCSS Encode 0 1 1 NRZ Encode NRZ Tx Baud Rate 1 0 0 CTCSS Encode and Decode CTCSS Tx Frequency 1 0 1 NRZ Encode and CTCSS Decode NRZ Tx Baud Rate 1 1 0 NRZ and CTCSS Decode NRZ Rx Baud Rate 1 1 1 NRZ Decode NRZ Rx Baud Rate NRZ Rx Baud Rate CTCSS Tx Frequency Table 5 CTCSS Frequency/NRZ Baud Rate Register Configurations Data Format Data is transmitted, via “C-BUS,” to this register as 2 bytes of Command Data (1 and 2) distributed as command words P and Q, in the form illustrated in Figure 7. This register is not affected by the General Reset command (01H) and may adopt any random configuration at Power-Up. Byte 1 (COMMAND DATA) (MSB) – LOADED FIRST 15 14 13 12 Byte 0 11 10 9 8 7 6 “0” P 5 4 3 (COMMAND DATA) (LSB) – LOADED LAST 2 1 0 Q Fig.7 Format of the CTCSS Tx Frequency/NRZ Baud Rate Register Command Words P and Q With reference to Figure 7, the two data words, P and Q, loaded to this register are interpreted as: P = a binary number to set the Tx Sub-Audio Lowpass Filter bandwidth (applicable to NRZ Encode and CTCSS Encode modes). Q = a binary number to set the frequency or baud rate of the selected function (see Table 5). Command Word ‘P’ Bits 15 14 LSB 13 12 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 1 1 0 ‘P’ LPF Bandwidth 2 3 4 5 6 7 8 300Hz 200Hz 150Hz 120Hz 100Hz 85.7Hz 75Hz 0 1 0 1 0 1 0 Bits 12 to 15 are used to produce the data word ‘P’ as shown in Table 6 (left). The cut-off frequency fCO (0.5dB point) of the Tx Sub-Audio Lowpass Filter is calculated as: fCO = fXTAL 32 x 208.33 x ‘P’ so ‘P’ = fXTAL 32 x 208.33 x fCO Table 6 Valid Values of ‘P’ Table 6 is given as an example and calculated using a Xtal/ clock (fXTAL) frequency of 4.00MHz. As illustrated, only values of ‘P’ of 2 to 8 are usable. 10 Controlling Protocol ...... “Write to CTCSS Tx Frequency/NRZ Baud Rate Register” ...... Command Word ‘Q’ With reference to Figure 7, Bits 0 to 10 are used to produce the data word ‘Q’ which sets one of the parameters described below. As can be seen, command word ‘Q’ could be used to produce a word whose value would produce a parameter outside that specified, care should be taken not to do this. Examples for limits of ‘Q’ in each operational configuration are included. ‘Q’ = 0 is not valid in the following calculations. Bit 11 is not used and must be set to logic “0”. (a) CTCSS Tx Tone Frequency (fCTCSS OUT) fCTCSS OUT = fXTAL Example Limits Hz fCTCSS OUT = 67Hz so ‘Q’ = 1866 fCTCSS OUT = 250Hz so ‘Q’ = 500 RNRZ Tx = 67 bits/sec so ‘Q’ = 1866 RNRZ Tx = 300 bits/sec so ‘Q’ = 417 RNRZ Rx = 100 bits/sec so ‘Q’ = 114 RNRZ Rx = 300 bits/sec so ‘Q’ = 38 32 x ‘Q’ so ‘Q’ = fXTAL Hz “11101001010” 32 x fCTCSS OUT “00111110100” (b) NRZ Tx Baud Rate (R NRZ Tx) RNRZ Tx = fXTAL bits/sec 32 x ‘Q’ so ‘Q’ = “11101001010” fXTAL 32 x RNRZ Tx “00110100001” (c) NRZ Rx Baud Rate (R NRZ Rx) RNRZ Rx = fXTAL bits/sec 32 x 11 x ‘Q’ so ‘Q’ = “00001110010” fXTAL 352 x RNRZ Rx 11 “00000100110” Controlling Protocol ...... “Read NRZ Rx Data Register” – A/C 74H (7CH), followed by 1 byte of Reply Data. Word synchronization is not provided. Byte synchronization and any codeword recognition will be performed by the host µController. The Rx baud rate is set by writing to the CTCSS Tx Frequency/NRZ Baud Rate Register (73H/7BH). The first bit received is the first bit sent to the µController. Received NRZ data bits are organized into bytes and made available to the µController via the Reply Data line. As 8 bits are received into this register an interrupt is generated to indicate that a complete byte has been received, this byte must be read before the arrival of the last (8th) bit of the next incoming byte, if this is not done, an interrupt to indicate this condition will be generated and the previous Rx data is discarded (See Table 4, Status Register, Bits 2 and 3). “Write to NRZ Tx Data Register” This register is not affected by the General Reset command (01H) and may adopt any random configuration at Power-Up. – A/C 75H (7DH), followed by 1 byte of Command Data. A byte for transmission is loaded from the “C-BUS” Command Data line with this A/C. The first data-bit received via the “C-BUS” is transmitted first. This transmitter operation is non-inverting. Transmission is terminated, the Tx Sub-Audio Output placed at VBIAS, and an interrupt generated if the next byte is not loaded within 7 bit periods. (See Table 4, Status Register, Bits 4 and 5). The first data-byte loaded after the NRZ Encoder is enabled (Control Register) initiates the transmission sequence and an interrupt will be generated when the NRZ Tx Data Buffer is ready for the next data-byte. Subsequently, interrupts occur for every 8 bits transmitted. This register is not affected by the General Reset command (01H) and may adopt any random configuration at Power-Up. “Write to Gain-Set Register” Setting – A/C 76H (7EH), followed by 1 byte of Command Data. Gain Setting The Gain-Set Register Settings MSB 7 6 0 0 5 0 4 0 3 1 0 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 The settings of this register control the CTCSS and NRZ signal level that is presented at the Tx Sub-Audio Output. Bit 3, when enabled, is used to produce a pre-emphasis effect on the NRZ Tx Data by increasing the gain of the data bit before a level change (Figure 8 below), by 1.72dB to make that data pulse level slightly more positive (or negative). The signal level will be 1.72dB greater than that set by Bits 0 to 2. If the Tx Sub-Audio Output level is set to +2.58dB, the pre-emphasized level will be +4.3dB. Transmitted Bit 7 First These 4 Bits Must be “0” Pre-Emphasis Setting 1.72dB Gain Enabled 1.72dB Gain Disabled 0 0 1 0 1 0 1 0 1 Tx Level Adjust Gain Setting -2.58 dB -1.72 dB -0.86 dB 0 dB +0.86 dB +1.72 dB +2.58 dB Not Used The pre-emphasis function, will remain enabled until disabled by setting Bit 3 to a logic “0.” If this function remains enabled when using the CTCSS Encoder the output signal level may be adversely affected, therefore this function should only be enabled when in the NRZ Encode mode. This register is not affected by the General Reset command (01H) and may adopt any random configuration at Power-Up. Table 7 Gain-Set Register Settings NRZ Tx DATA BIT PERIODS GAIN-SET NRZ Tx DATA with PRE-EMPHASIS ENABLED Gain-Set +1.72dB Gain-Set +1.72dB Gain-Set +1.72dB Fig.8 Gain-Set with Pre-Emphasis 12 Gain-Set +1.72dB Timing Information Timing Diagrams Figure 9 shows the timing parameters for two-way communication between the µController and the FX805 on the “C-BUS.” Figure 10 shows, in detail, the timing relationships for “C-BUS” information transfer. t CSOFF CHIP SELECT t CSE t NXT t NXT SERIAL CLOCK t CSH t CK COMMAND DATA 7 6 5 4 3 2 1 MSB REPLY DATA 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 LSB ADDRESS/COMMAND BYTE FIRST DATA BYTE LAST DATA BYTE t HIZ 7 6 5 4 3 2 1 0 MSB 7 5 4 3 2 LSB FIRST REPLY DATA BYTE Logic level is not important 6 LAST REPLY DATA BYTE Fig.9 “C-BUS” Timing Information NOT TO SCALE Parameter tCSE tCSH tCSOFF tNXT tCK tCH tCL tCDS tCDH tRDS tRDH tHIZ Min. Typ. Max. Unit 2.0 4.0 2.0 4.0 2.0 500 500 250 0 250 50.0 – – – – – – – – – – – – – – – – – – – – – – – – 2.0 µs µs µs µs µs ns ns ns ns ns ns µs Notes (1) Command Data is transmitted to the peripheral MSB (bit 7) first, LSB (bit 0) last. Reply Data is read from the FX805 MSB (bit 7) first, LSB (bit 0) last. (2) Data is clocked into the FX805 and into the µController on the rising Serial Clock edge. (3) Loaded data instructions are acted upon at the end of each individual, loaded byte. (4) To allow for differing µController serial interface formats, the FX805 will work with either polarity Serial Clock pulses. t CK t CL 70% VDD t CH t CDH 30% VDD SERIAL CLOCK (from µC) tCDS COMMAND DATA (from µC) tRDH tRDS REPLY DATA (to µC) Fig.10 “C-BUS” Timing Relationships NOT TO SCALE 13 Specification Absolute Maximum Ratings Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied. Supply voltage Input voltage at any pin (ref VSS = 0V) Sink/source current (supply pins) (other pins) Total device dissipation @ TAMB 25°C Derating Operating temperature range: FX805J FX805LG/LS Storage temperature range: FX805J FX805LG/LS -0.3 to 7.0V -0.3 to (VDD + 0.3V) +/- 30mA +/- 20mA 800mW Max. 10mW/°C -40°C to +85°C (cerdip) -40°C to +85°C (plastic) -55°C to +125°C (cerdip) -40°C to +85°C (plastic) Operating Limits All device characteristics are measured under the following conditions unless otherwise specified: VDD = 5.0V. TAMB = 25°C. Xtal/Clock fXTAL = 4.0MHz. Audio Level 0dB ref: = 308mVrms @ 1kHz. Composite Signal = 308mVrms @ 1kHz + 75mVrms Noise + 31mVrms Sub-Audio Signal. Noise Bandwidth = 5kHz Band Limited Gaussian. Characteristics Static Values Supply Voltage Supply Current See Note Min. Typ. Max. Unit 4.5 – – – 5.0 5.0 1.9 0.9 5.5 – – – V mA mA mA 350 350 – 1.0 1.0 1. 0 – – – – – – – 2.0 10.0 10.0 10.0 2.0 2.0 500 2.0 500 – – – – – – – – – – – kΩ kΩ kΩ MΩ MΩ MΩ kΩ kΩ kΩ kΩ kΩ – – 6.0 600 – – kΩ Ω 1 1 2 3 3 1 1 4 3.5 – 4.6 – – – – – – – – – – – – – – 1.5 – 0.4 4.0 7.5 1.0 4.0 V V V V µA pF µA µA 6 – -26.0 – dB – – – – – – – – 0.2 0.5 – 20.0 250 375 – – 250 – ms ms % % ms /Hr (All Functions Enabled) (Decoders Only Enabled) (Powersave All) Analogue Impedances Rx Sub-Audio Input Audio Input Audio By-Pass Switch ‘On’ Audio By-Pass Switch ‘Off’ Rx Amp Input (+ and -) Comparator Input (+ and -) Rx Sub-Audio Output Tx Sub-Audio Output (Encoder Enabled) (Encoder Disabled) Audio Output (Enabled) (Disabled) Rx Amp and Comparator Outputs Large Signal Small Signal Dynamic Values Digital Interface Input Logic “1” Input Logic “0” Output Logic “1” (IOH = -120µA) Output Logic “0” (IOL = 360µA) IOUT Tristate (Logic “1” or “0”) Input Capacitance Logic Input Current (VIN = 0 to 5.0V) IOX (VOUT = 5.0V) Overall Performance CTCSS – Decode Sensitivity (Pure CTCSS Tone) Response Time (Composite Signal) 100Hz to 257Hz Tone 65Hz Tone Tone Measurement Resolution Tone Measurement Accuracy NOTONE Response Time (Composite Signal) False Tone Interrupts (Noise input only) 5 5 5 5 5 5 9 7 10 14 Specification ...... Characteristics See Note CTCSS – Encode Frequency Range Tone Frequency Resolution Tone Amplitude Tolerance Rise Time (to 90%) Fall Time (to 10%) Total Harmonic Distortion NRZ – Decode Rx Bit-Rate Sync Time Rx Bit Error Rate NRZ – Tx Tx Bit Rate Tx LPF (3dB) Bandwidth Sub-Audio Tx Output Level CTCSS NRZ Amplitude Adjustment Range Adjustment Step Size (7 steps) 11 8 Sub-Audio Bandstop Filter Passband Passband Gain Passband Gain (w.r.t. gain at 1.0kHz) Stopband Attenuation at 250 Hz at 150 Hz at 100 Hz Residual Hum and Noise Alias Frequency Xtal/Clock Frequency (f XTAL) Min. Typ. Max. Unit 65.0 – -1.0 – – – – – – – – 257 0.2 +1.0 30.0 50.0 5.0 Hz % dB ms ms % – – 2 1 x 10-3 – – edges P(error) 67.0 75 – – 300 300 bits/s Hz – – -2.58 – 0 0.871 0.86 – – 2.58 – dB V p-p dB dB 297 – -1.5 0 – 3000 – +0.5 Hz dB dB – – – – – 36.0 24.0 18.0 -50.0 – – – – -46.0 62.5 dB dB dB dBp kHz 3.9 – 4.1 MHz Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Device control pins; Serial Clock, Command Data, Wake and CS. Reply Data output. Reply Data and IRQ outputs. Leakage current into the “Off” IRQ output. See Control Register. With Input gain components set as recommended in Figure 2. Probability 0.97 See Gain-Set Register, Table 7 - Bits 0, 1, 2 and 3. For fCTCSS IN of 65Hz to 100Hz, Response Time tR = (100/fTONE) x 250 ms. Distributed across the Rx frequency band. With 10dB signal-to-noise ratio in a bit-rate bandwidth. 15 Package Outlines Handling Precautions The FX805 is available in the package styles outlined below. Mechanical package diagrams and specifications are detailed in Section 10 of this document. Pin 1 identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top. The FX805 is a CMOS LSI circuit which includes input protection. However precautions should be taken to prevent static discharges which may cause damage. FX805J FX805LG 24-pin quad plastic encapsulated bent and cropped (L1) 24-pin cerdip DIL (J4) NOT TO SCALE NOT TO SCALE Max. Body Length Max. Body Width 32.03mm 14.81mm Max. Body Length Max. Body Width FX805LS 10.25mm 10.25mm 24-lead plastic leaded chip carrier (L2) NOT TO SCALE Ordering Information FX805J 24-pin cerdip DIL (J4) FX805LG 24-pin encapsulated bent and cropped (L1) FX805LS 24-lead plastic leaded chip carrier (L2) Max. Body Length Max. Body Width CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied and CML reserves the right at any time without notice to change the said circuitry. 10.40mm 10.40mm CML Microcircuits COMMUNICATION SEMICONDUCTORS CML Product Data In the process of creating a more global image, the three standard product semiconductor companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc (USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA) Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits. These companies are all 100% owned operating companies of the CML Microsystems Plc Group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. CML Microcircuits Product Prefix Codes Until the latter part of 1996, the differentiator between products manufactured and sold from MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX respectively. These products use the same silicon etc. and today still carry the same prefixes. In the latter part of 1996, both companies adopted the common prefix: CMX. This notification is relevant product information to which it is attached. Company contact information is as below: CML Microcircuits (UK)Ltd CML Microcircuits (USA) Inc. CML Microcircuits (Singapore)PteLtd COMMUNICATION SEMICONDUCTORS COMMUNICATION SEMICONDUCTORS COMMUNICATION SEMICONDUCTORS Oval Park, Langford, Maldon, Essex, CM9 6WG, England Tel: +44 (0)1621 875500 Fax: +44 (0)1621 875600 [email protected] www.cmlmicro.com 4800 Bethania Station Road, Winston-Salem, NC 27105, USA Tel: +1 336 744 5050, 0800 638 5577 Fax: +1 336 744 5054 [email protected] www.cmlmicro.com No 2 Kallang Pudding Road, 09-05/ 06 Mactech Industrial Building, Singapore 349307 Tel: +65 7450426 Fax: +65 7452917 [email protected] www.cmlmicro.com D/CML (D)/1 February 2002