CML Semiconductor Products
Wireless Modem Data Pump
FX909A
D/909A/4 March 1996
1.0
Features
Provisional Issue
• GMSK Modulation
• Flexible Operating Modes
• Rx or Tx up to 19.2k bits/sec
• Host Processor Interface
• Full Data Packet Framing
• Low Power 3.3V/5V Operation
• Mobitex Compatible
• 24-Pin Small Form Package Option
1.1
Brief Description
The FX909A is a CMOS integrated circuit that contains all of the baseband signal processing and
Medium Access Control (MAC) protocol functions required for a high performance GMSK Wireless
Packet Data Modem. It interfaces with the modem host processor and the radio
modulation/demodulation circuits to deliver reliable two-way transfer of the application data over the
wireless link.
The FX909A assembles application data received from the processor, adds error correction code
(FEC), adds error detection code (CRC), time-spreads this data by interleaving (burst-error
protection) and scrambles (randomises) the bit pattern. After adding bit and frame sync codewords,
it converts the packet into analogue GMSK signals for modulating the radio transmitter.
In receive mode, the FX909A performs the reverse function using the analogue signals from the
receiver discriminator. After error correction and removal of the packet overhead, the recovered
application data is supplied to the processor. Any residual uncorrected errors in the data will be
flagged. A readout of the SNR value during receipt of a packet is also provided.
The FX909A uses data block sizes and FEC/CRC algorithms compatible with the Mobitex Wide Area
Network over-air standard. The format used is suitable for other private applications which require
the high-speed transfer of data over narrow-band wireless links. The FX909A is programmable to
operate at most standard bit-rates from a wide choice of Xtal/clock frequencies.
1996 Consumer Microcircuits Limited
Wireless Modem Data Pump
FX909A
CONTENTS
Section
Page
1.0 Features.......................................................................................................... 1
1.1 Brief Description............................................................................................ 1
1.2 Block Diagram................................................................................................ 3
1.3 Signal List....................................................................................................... 4
1.4 External Components.................................................................................... 6
1.5 General Description....................................................................................... 7
1.5.1 Description of Blocks.................................................................... 7
1.5.2 Modem - µC Interaction.............................................................. 10
1.5.3 Data Formats ............................................................................. 11
1.5.4 The Programmer's View............................................................. 13
1.5.5 CRC, FEC, Interleaving and Scrambling Details........................ 29
1.6 Application Notes ........................................................................................ 32
1.6.1 Transmit Frame Example........................................................... 32
1.6.2 Receive Frame Example............................................................ 34
1.6.3 Clock Extraction & Level Measurement Systems ...................... 36
1.6.4 AC Coupling ............................................................................... 37
1.6.5 Radio Performance .................................................................... 39
1.7 Performance Specification ......................................................................... 40
1.7.1 Electrical Performance ............................................................... 40
1.7.2 Packaging .................................................................................. 45
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1.2
FX909A
Block Diagram
Figure 1 Block Diagram
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1.3
FX909A
Signal List
Package
D2/D5/P4
Signal
Description
Pin No.
Name
Type
1
IRQN
O/P
2
3
4
5
6
7
8
9
D7
D6
D5
D4
D3
D2
D1
D0
BI
BI
BI
BI
BI
BI
BI
BI
)
)
)
)
)
)
)
)
10
RDN
I/P
Read. An active low logic level input used to
control the reading of data from the modem into
the host µC.
11
WRN
I/P
Write. An active low logic level input used to
control the writing of data into the modem from
the host µC.
12
Vss
Power
13
CSN
I/P
Chip Select. An active low logic level input to the
modem, used to enable a data read or write
operation.
14
15
A0
A1
I/P
I/P
)
)
16
XTALN
O/P
The output of the on-chip oscillator.
17
XTAL/CLOCK
I/P
The input to the on-chip oscillator, for external
Xtal circuit or clock.
18
19
DOC 2
DOC 1
O/P
O/P
)
)
)
1996 Consumer Microcircuits Limited
A 'wire-ORable' output for connection to the host
µC's Interrupt Request input. This output has a
low impedance pull down to VSS when active
and is high impedance when inactive.
8-bit bidirectional 3-state µC interface data
lines.
The negative supply rail (ground).
4
Two logic level modem register select
inputs.
Connections to the Rx level measurement
circuitry. A capacitor should be connected
from each pin to VSS.
D/909A/4
Wireless Modem Data Pump
FX909A
Package
D2/D5/P4
Signal
Description
Pin No.
Name
Type
20
TXOP
O/P
The Tx signal output from the modem.
21
VBIAS
O/P
A bias line for the internal circuitry, held at
½ VDD. This pin must be decoupled to VSS by a
capacitor mounted close to the device pins.
22
RXIN
I/P
The input to the Rx input amplifier.
23
RXFB
O/P
The output of the Rx input amplifier and the input
to the Rx filter.
24
VDD
Power
The positive supply rail. Levels and voltages are
dependent upon this supply. This pin should be
decoupled to VSS by a capacitor.
Notes: I/P =
O/P =
BI
=
Input
Output
Bidirectional
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1.4
FX909A
External Components
Figure 2 Recommended External Components
R1
R2
R3
R4
See section 1.5.1.10
100k ohm
1M ohm *
See section 1.5.1.12
C1
C2
C3
C4
0.1 µF
0.1 µF
See section 1.5.4.3 *
See section 1.5.4.3 *
C5
C6
C7
X1
See section 1.5.1.12
See note below
See note below
See section 1.5.4.3 *
* Refer also to 1.5.1.14
Tolerances:
R4 ±5%
R2, C5 ±10%
all other components ±20%
C6 and C7 values should satisfy the following: C (in Farads) x data rate (bits/second) = 120 x 10-6
e.g.
Data Rate (kbits/sec)
4.0
4.8
8.0
9.6
16.0
19.2
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C6/C7 (nF)
30
22
15
12
6.8
6.8
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Wireless Modem Data Pump
1.5
FX909A
General Description
This product has been designed to be compliant with the appropriate sections of the "Mobitex
Interface Specification".
1.5.1
Description of Blocks
1.5.1.1
Data Bus Buffers
8 bidirectional 3-state logic level buffers between the modem's internal registers and the host µC's
data bus lines.
1.5.1.2
Address and R/W Decode
This block controls the transfer of data bytes between the µC and the modem's internal registers,
according to the state of the Write and Read Enable inputs (WRN and RDN), the Chip Select input
(CSN) and the Register Address inputs A0 and A1.
The Data Bus Buffers, Address and R/W Decode blocks provide a byte-wide parallel µC interface,
which can be memory-mapped, as shown in Figure 3.
Figure 3 Typical Modem µC Connections
1.5.1.3
Status and Data Quality Registers
8-bit registers which the µC can read to determine the status of the modem and the received data
quality.
1.5.1.4
Command, Mode and Control Registers
The values written by the µC to these 8-bit registers control the operation of the modem.
1.5.1.5
Data Buffer
An 18-byte buffer used to hold receive or transmit data to or from the µC.
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1.5.1.6
CRC Generator/Checker
A circuit which generates (in transmit mode) or checks (in receive mode) the Cyclic Redundancy
Checksum bits, which are included in transmitted Mobitex data blocks so that the receive modem can
detect transmission errors.
1.5.1.7
FEC Generator/Checker
In transmit mode this circuit calculates and adds the Forward Error Correction (4 bits) to each byte
presented to it. In receive mode the FEC information is used to correct most transmission errors that
have occurred in a Mobitex Data Block or in the Frame Head control bytes.
1.5.1.8
Interleave/De-interleave Buffer
This circuit interleaves data bits within a data block before transmission and de-interleaves the
received data block so that the FEC system is best able to handle short noise bursts or signal fades.
1.5.1.9
Frame Sync Detect
This circuit, which is only active in receive mode, is used to look for the user specified 16-bit Frame
Synchronisation pattern which is transmitted to mark the start of every frame.
1.5.1.10 Rx I/P Amp
This amplifier allows the received signal input to the modem to be set to the optimum level by
suitable selection of the external components R1 and R2. The value of R1 should be calculated to
give 0.2 x VDD pk-pk at the RXFB pin for a received '...11110000...' sequence.
A capacitor may be fitted if ac coupling of the received signal is desired (see section 1.6.4), otherwise
the dc level of the received signal should be adjusted so that the signal at the modem's RXFB pin is
centred around VBIAS (½ VDD).
1.5.1.11 Tx/Rx Low Pass Filter
This filter, which is used in both transmit and receive modes, is a low pass transitional Gaussian filter
having a loss of 3dB at 0.3 times the selected bit rate (BT = 0.3). See Figure 4.
In transmit mode, the bits are passed through this filter to eliminate the high frequency components
which would otherwise cause interference into adjacent radio channels.
In receive mode this filter is used with an increased BT factor (0.56) to reject HF noise, so that the
signal is suitable for extraction of the received data.
1.5.1.12 Tx Output Buffer
This is a unity gain amplifier used in transmit mode to buffer the output of the Tx low pass filter. In
receive mode, the input of this buffer is connected to VBIAS. When changing from Rx to Tx mode the
input to this buffer will be connected to VBIAS for 2 bit periods to prevent unwanted signals, from the
low pass filter, at the output. When the modem is set to power save mode, the buffer is turned off
and the TXOP pin connected to VBIAS via a high value resistance. When exiting from power save
mode the Tx output is only reconnected to the buffer after 2 bit periods, to prevent unwanted signals,
from the low pass filter, at the output.
Note: The RC low pass filter formed by the external components R4 and C5 between the Tx Output
Buffer and the input to the radio's frequency modulator forms an important part of the transmit signal
filtering. These components may form part of any dc level-shifting and gain adjustment circuitry. The
ground connection to the capacitor C5 should be positioned to give maximum attenuation of high
frequency noise into the modulator. R4 and C5 should be chosen so that the product of the
resistance of R4 (in Ohms) and capacitance of C5 (in Farads) is 0.34/bit rate (bit rate in bits per
second). R4 should be not less than 47k and the value used for the external capacitor should take
into account parasitic capacitance.
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FX909A
Suitable values being:
8000 bits/sec
4800 bits/sec
R4
100k
100k
C5
430pF
710pF
The signal at the TXOP pin is centred around VBIAS and is approx 0.2 x VDD pk-pk, going positive for
a logic '1' and negative for a logic '0', if the modem is not inverting the Tx data.
A capacitor may be fitted if ac coupling of the input to the frequency modulator is desired, see section
1.6.4.
The 'eye' diagram of the transmitted signal (after the external R4/C5 network) is shown in Figure 5.
Figure 4 Typical Tx Filter Frequency Response (after the external RC filter)
Figure 5 Transmitted Signal Eye Diagram (after the external RC filter)
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FX909A
1.5.1.13 Rx Level/Clock Extraction
These circuits, which operate only in receive mode, extract a bit rate clock from the received signal
and measure the received signal amplitude and dc offset. This information is then used to extract the
received bits and also to provide an input to the received Data Quality measuring circuit. The external
capacitors C6 and C7 form part of the received signal level measuring circuit.
1.5.1.14 Clock Oscillator and Dividers
This circuit derives the transmit bit rate (and the nominal receive bit rate) by frequency division of a
reference frequency which may be generated by the on-chip Xtal oscillator or applied from an
external source.
Note: If the on-chip xtal oscillator is to be used, then the external components X1, C3, C4 and R3
are required. If an external clock source is to be used, then it should be connected to the
XTAL/CLOCK input pin, the XTALN pin should be left unconnected, and X1, C3, C4 and R3 not
fitted.
1.5.1.15 Scramble/De-scramble
This block may be used to scramble/de-scramble the transmitted/received data blocks. It does this
by modulating the data with a 511-bit pseudorandom sequence, as described in section 1.5.5.4.
Scrambling smooths the transmitted spectrum, especially when repetitive sequences are to be
transmitted.
1.5.2
Modem - µC Interaction
In general, data is transmitted over air in the form of messages, or 'Frames', consisting of a 'Frame
Head' optionally followed by one or more formatted data blocks. The Frame Head includes a Frame
Synchronisation pattern designed to allow the receiving modem to identify the start of a frame. The
following data blocks are constructed from the 'raw' data using a combination of CRC (Cyclic
Redundancy Checksum) generation, Forward Error Correction coding, Interleaving and Scrambling.
Details of the message formats handled by this modem are given in section 1.5.3.
To reduce the processing load on the host µC, this modem has been designed to perform as much
as possible of the computationally intensive work involved in Frame formatting and de-formatting and
(when in receive mode) in searching for and synchronising onto the Frame Head. In normal operation
the modem will only require servicing by the µC once per received or transmitted data block.
Thus, to transmit a block, the host µC has only to load the unformatted (raw) binary data into the
modem's data buffer then instruct the modem to format and transmit that data. The modem will then
calculate and add the CRC bits as required, encode the result with Forward Error Correction coding,
interleave then scramble the bits before transmission.
In receive mode, the modem can be instructed to assemble a block's worth of received bits, descramble and de-interleave the bits, check and correct them (using the FEC coding) and check the
resulting CRC before placing the received binary data into the Data Buffer for the µC to read.
The modem can also handle the transmission and reception of unformatted data, to allow the
transmission of special Bit and Frame Synchronisation sequences or test patterns.
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1.5.3
FX909A
Data Formats
General Purpose Formats
In a proprietary system the user may employ the data elements provided by this device to construct a
custom, over-air data structure.
For example, 16 bits of bit sync + 2 bytes of frame sync + 4 bytes of receiver and sender address + n
data blocks would be sent as:
TQB (bit and frame sync) + TQB (addresses) + (n x TDB) + TSB
And received as:
SFS + RSB + RSB + RSB + RSB + (n x RDB)
Note that it is important to have established frame synchronisation before receiving data to enable
the receiving device to decode synchronously. Also the user may add, by way of algorithms
performed on the controlling device, additional data correction with the bytes in the data block task.
Mobitex Frame Structure
The Mobitex format for transmitted data is in the form of a Frame Head immediately followed by a
number of Data Blocks (0 to 32).
The Frame Head consists of 7 bytes:
2 bytes of bit sync:
1100110011001100 from base,
0011001100110011 from mobile
bits are transmitted from left to right
2 bytes of frame sync:
System specific.
2 bytes of control data.
1 byte of FEC code, 4 bits for each of the control bytes:
bits 7-4 (leftmost) operate on the first control byte.
bits 3-0 (rightmost) operate on the second control byte.
Each byte in the Frame Head is transmitted bit 7 (MSB) first to bit 0 (LSB) last.
The Data Block consists of:
18 bytes of data.
2 bytes of CRC calculated from the 18 data bytes.
4 bits of FEC code for each of the data and CRC bytes
The resulting 240 bits are interleaved and scrambled before transmission.
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Figure 6 shows how the over air signal is built up from Frame Sync and Bit Sync patterns, Control
bytes and Data Blocks.
The binary data transferred between the modem and the host µC is that shown enclosed by the thick
dashed rectangles near the top of the diagram.
Figure 6 Mobitex Over Air Signal Format
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1.5.4
FX909A
The Programmer's View
The modem appears to the programmer as 4 write only 8-bit registers shadowed by 3 read only
registers, individual registers being selected by the A0 and A1 chip inputs:
A1
0
0
1
1
1.5.4.1
A0
0
1
0
1
Write to Modem
Data Buffer
Command Register
Control Register
Mode Register
Read from Modem
Data Buffer
Status Register
Data Quality Register
not used
Data Buffer
This is an 18-byte read/write buffer which is used to transfer data (as opposed to command, status,
mode, data quality and control information) between the modem and the host µC.
It appears to the µC as a single 8-bit register; the modem ensuring that sequential µC reads or writes
to the buffer are routed to the correct locations within the buffer.
The µC should only access this buffer when the Status Register BFREE (Buffer Free) bit is '1'.
The buffer should only be written to while in Tx mode and read from while in Rx mode (except when
loading Frame Sync detection bytes while in Rx mode).
1.5.4.2
Command Register
Writing to this register tells the modem to perform a specific action or actions, depending on the
setting of the TASK, AQLEV and AQBC bits.
When it has no action to perform (but is not 'powersaved'), the modem will be in an 'idle' state. If the
modem is in transmit mode the input to the Tx filter will be connected to VBIAS. In receive mode the
modem will continue to measure the received data quality and extract bits from the received signal,
supplying them to the de-interleave buffer, but will otherwise ignore the received data.
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FX909A
Command Register B7: AQBC - Acquire Bit Clock
This bit has no effect in transmit mode.
In receive mode, whenever a byte with the AQBC bit set to '1' is written to the Command Register,
and TASK is not set to RESET, it initiates an automatic sequence designed to achieve bit timing
synchronisation with the received signal as quickly as possible. This involves setting the Phase
Locked Loop of the received bit timing extraction circuits to its widest bandwidth, then gradually
reducing the bandwidth as timing synchronisation is achieved, until it reaches the 'normal' value set
by the PLLBW bits of the Control Register.
Setting this bit to '0' (or changing it from '1' to '0') has no effect, however note that the acquisition
sequence will be re-started every time that a byte written to the Command Register has the AQBC bit
set to '1'.
The AQBC bit will normally be set up to 12 bits before an SFS (Search for Frame Sync) or SFH
(Search for Frame Head) task, however it may also be used independently to re-establish clock
synchronisation quickly after a long fade. Alternatively, a SFS or SFH task may be written to the
Command Register with the AQBC bit '0' if it is known that clock synchronisation does not need to be
re-established. More details of the bit clock acquisition sequence are given in section 1.6.3.
Command Register B6: AQLEV - Acquire Receive Signal Levels
This bit has no effect in transmit mode.
In receive mode, whenever a byte with the AQLEV bit set to '1' is written to the Command Register
and TASK is not set to RESET, it initiates an automatic sequence designed to measure the amplitude
and dc offset of the received signal as rapidly as possible. This sequence involves setting the
measurement circuits to respond quickly at first, then gradually increasing their response time, hence
improving the measurement accuracy, until the 'normal' value set by the LEVRES bits of the Control
Register is reached.
Setting this bit to '0' (or changing it from '1' to '0') has no effect, however note that the acquisition
sequence will be re-started every time that a byte written to the Command Register has the AQLEV
bit set to '1'.
The AQLEV bit will normally be set up to 12 bits before an SFS (Search for Frame Sync) or SFH
(Search for Frame Head) task is initiated, however it may also be used independently to re-establish
signal levels quickly after a long fade. Alternatively, a SFS or SFH task may be written to the
Command Register with the AQLEV bit at '0' if it is known that there is no need to re-establish the
received signal levels. More details of the level measurement acquisition sequence are given in
section 1.6.3.
The error rate is highest immediately after a AQBC and AQLEV sequence is triggered and rapidly
reduces to its static value soon after. These erroneous bits could incorrectly trigger the frame sync
detection circuits and so it is suggested that a SFH or SFS task is set 12 bits after setting either of
the AQLEV or AQBC sequences.
Command Register B5, B4, B3
These bits should be set to '0'.
Command Register B2, B1, B0: TASK - Task
Operations such as transmitting a data block are treated by the modem as 'tasks' and are initiated
when the µC writes a byte to the Command Register with the TASK bits set to anything other than
the 'NULL' code.
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FX909A
The µC should not write a task (other than NULL or RESET) to the Command Register or write to or
read from the Data Buffer when the BFREE (Buffer Free) bit of the Status Register is '0'.
Different tasks apply in receive and transmit modes.
When the modem is in transmit mode, all tasks other than NULL, RESET and TSO instruct the
modem to transmit data from the Data Buffer, formatting it as required. For these tasks the µC should
wait until the BFREE (Buffer Free) bit of the Status Register is '1', before writing the data to the Data
Buffer, then it should write the desired task to the Command Register. If more than 1 byte needs to
be written to the Data Buffer, byte number 0 of the block should be written first.
Once the byte containing the desired task has been written to the Command Register, the modem
will:
Set the BFREE (Buffer Free) bit of the Status Register to '0'.
Take the data from the Data Buffer as quickly as it can - transferring it to the Interleave Buffer
for eventual transmission. This operation will start immediately if the modem is 'idle' (i.e. not
transmitting data from a previous task), otherwise it will be delayed until there is sufficient room
in the Interleave Buffer.
Once all of the data has been transferred from the Data Buffer the modem will set the BFREE
and IRQ bits of the Status Register to '1', (causing the chip IRQN output to go low if the
IRQNEN bit of the Mode Register has been set to '1') to tell the µC that it may write new data
and the next task to the modem.
In this way the µC can write a task and the associated data to the modem while the modem is still
transmitting the data from the previous task. See Figure 7.
When the modem is in receive mode, the µC should wait until the BFREE bit of the Status Register is
'1', then write the desired task to the Command Register.
Once the byte containing the desired task has been written to the Command Register, the modem
will:
Set the BFREE bit of the Status Register to '0'.
Wait until enough received bits are in the De-interleave Buffer.
Decode them as needed, and transfer any resulting data to the Data Buffer
Then the modem will set the BFREE and IRQ bits of the Status Register to '1', (causing the
IRQN output to go low if the IRQNEN bit of the Mode Register has been set to '1') to tell the µC
that it may read from the Data Buffer and write the next task to the modem. If more than 1 byte
is contained in the Data Buffer, byte number '0' of the data will be read first.
In this way the µC can read data and write a new task to the modem while the received bits needed
for this new task are being stored in the De-interleave Buffer. See Figure 8.
The above is not true for loading the Frame Sync detection bytes (LFSB): the bytes to be compared
with the incoming data must be loaded prior to the task bits being written.
Detailed timings for the various tasks are given in Figures 9 and 10.
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FX909A
Figure 7 The Transmit Process
Figure 8 The Receive Process
Mobitex modem tasks:
B2
B1
B0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Receive Mode
NULL
SFH
R3H
RDB
SFS
RSB
LFSB
RESET
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Transmit Mode
Search for Frame Head
Read 3 byte Frame Head
Read Data Block
Search for Frame Sync
Read Single Byte
Load Frame Sync Bytes
Cancel any current action
16
NULL
T7H
TDB
TQB
TSB
TSO
RESET
Transmit 7 byte Frame Head
Reserved
Transmit Data Block
Transmit 4 Bytes
Transmit Single Byte
Transmit Scrambler Output
Cancel any current action
D/909A/4
Wireless Modem Data Pump
FX909A
NULL - No effect
This task is provided so that a AQBC or AQLEV command can be initiated without loading a new
task.
SFH - Search for Frame Head
Causes the modem to search the received signal for a Frame Head. The Frame Head will consist of
a 16-bit Frame Sync followed by control data (see Figure 6 - Mobitex Over Air Signal). The search
will continue until a Frame Head has been found, or until the RESET task is loaded.
The search is carried out by first attempting to match the incoming bits against the previously
programmed (task LFSB) 16-bit Frame Sync pattern (allowing up to any one bit (of 16) in error).
When a match has been found, the modem will read the next 3 received bytes as Frame Head bytes,
these bytes will be checked, and corrected if necessary, using the FEC bits. The two Frame Head
Data bytes are then placed into the Data Buffer.
The BFREE and IRQ bits of the Status Register will then be set to a logic '1' to indicate that the µC
may read the 2 Frame Head Data bytes from the Data Buffer and write the next task to the
Command Register. If the FEC indicates uncorrectable errors the modem will set the CRCFEC bit in
the Status Register to a logic '1'. The MOBAN bit (Mobile or Base) in the Status Register will be set
according to the polarity of the 3 bits preceding the Frame Sync pattern.
R3H - Read 3-byte Frame Head
This task, which would normally follow an SFS task, will place the next 3 bytes directly into the Data
Buffer. It also causes the modem to check the 3 bytes as Frame Head control data bytes and will set
the CRCFEC bit to a logic '1' (high) only if the FEC bits indicate uncorrectable errors. Note: This task
will not correct any errors and, due to the Mobitex FEC specification, will not detect all possible
uncorrectable error patterns The BFREE and IRQ bits of the Status Register will be set to '1' when
the task is complete to indicate that the µC may read the data from the Data Buffer and write the next
task to the modem's Command Register.
The CRCFEC bit in the Status Register will be set according to the validity of the received FEC bits.
RDB - Read Data Block
This task causes the modem to read the next 240 bits as a Mobitex Data Block.
It will de-scramble and de-interleave the bits, FEC correct and CRC check the resulting 18 data bytes
and place them into the Data Buffer, setting the BFREE and IRQ bits of the Status Register to '1'
when the task is complete to indicate that the µC may read the data from the Data Buffer and write
the next task to the modem's Command Register. The CRCFEC bit will be set according to the
outcome of the CRC check.
Note: in receive mode the CRC checksum circuits are initialised on completion of any task other than
NULL.
SFS - Search for Frame Sync
This task, which is intended for special test and channel monitoring purposes, performs the first part
only of a SFH task. It causes the modem to search the received signal for a 16-bit sequence which
matches the Frame Synchronisation pattern with up to any 1 bit in error.
When a match is found the modem will set the BFREE and IRQ bits of the Status Register to '1' and
update the MOBAN bit. The µC may then write the next task to the Command Register.
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RSB - Read Single Byte
This task causes the modem to read the next 8 bits and translate them directly (without deinterleaving or FEC) to an 8-bit byte which is placed into the Data Buffer (B7 will represent the
earliest bit received). The BFREE and IRQ bits of the Status Register will then be set to '1' to indicate
that the µC may read the data byte from the Data Buffer and write the next task to the Command
Register.
This task is intended for special tests and channel monitoring - perhaps preceded by an SFS task.
LFSB - Load Frame Sync Bytes
This task takes 2 bytes from the Data Buffer and updates the Frame Sync detect bytes. The MSB of
byte '0' is compared to the first bit of a received Frame Sync pattern and the LSB of byte '1' is
compared to the last bit of a received Frame Sync pattern. This task does not enable Frame Sync
detection.
Unlike other Rx tasks, the data buffer must be loaded before the task is issued and the task must
only be issued 'between' received messages, i.e. before the first task for receiving a message and
after the last data is read out of the data buffer.
Once the modem has read the Frame Sync bytes from the Data Buffer, the BFREE and IRQ bits of
the Status Register will be set to '1', indicating to the µC that it may write the next task to the modem.
T7H - Transmit 7-byte Frame Head
This task takes 6 bytes of data from the Data Buffer, calculates and appends 8 bits of FEC from
bytes '4' and '5' then transmits the result as a complete Mobitex Frame Head.
Bytes '0' and '1' form the bit sync pattern, bytes '2' and '3' form the frame sync pattern and bytes '4'
and '5' are the frame head control bytes. Bit 7 of byte '0' of the Data Buffer is sent first, bit 0 of the
FEC byte last.
Once the modem has read the data bytes from the Data Buffer, the BFREE and IRQ bits of the
Status Register will be set to '1', indicating to the µC that it may write the next task and its data to the
modem.
TQB - Transmit 4 Bytes
This task takes 4 bytes of data from the Data Buffer and transmits them, bit 7 first.
Once the modem has read the data bytes from the Data Buffer, the BFREE and IRQ bits of the
Status Register will be set to '1', indicating to the µC that it may write the next task and its data to the
modem.
TDB - Transmit Data Block
This task takes 18 bytes of data from the Data Buffer, calculates and applies a 16-bit CRC and forms
the FEC for the 18 data bytes and the CRC. This data is then interleaved and passed through the
scrambler, if enabled, before being transmitted as a Mobitex Data Block.
Once the modem has read the data bytes from the Data Buffer, the BFREE and IRQ bits of the
Status Register will be set to '1', indicating to the µC that it may write the next task and its data to the
modem.
Note: In transmit mode the CRC checksum circuit is initialised on completion of any task other than
NULL.
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TSB - Transmit Single Byte
This task takes a byte from the Data Buffer and transmits the 8 bits, bit 7 first.
Once the modem has read the data byte from the Data Buffer, the BFREE and IRQ bits of the Status
Register will be set to '1', indicating to the µC that it may write the next task and its data to the
modem.
TSO - Transmit Scrambler Output
This task, intended for channel set-up, enables the scrambler and transmits its output.
When the modem has started the task the Status Register bits will not be changed and hence an IRQ
will not be raised. The µC may write the next task and its data to the modem at any time and the
scrambler output will stop when the new task has produced its first data.
RESET - Stop any current action
This task takes effect immediately, and terminates any current action (task, AQBC or AQLEV) the
modem may be performing and sets the BFREE bit of the Status Register to '1', without setting the
IRQ bit. It should be used when VDD is applied to set the modem into a known state.
Note that due to delays in the internal switched capacitor filter, it will take approximately 3 bit times
for any change to become apparent at the TXOP pin.
Task Timings
The device should not be given a new task for at least 2 bit times after the following:
Changing from powersave state to normal operation.
Changing the Tx/Rx bit.
Resetting or after power is applied to the device.
This is to ensure that the internal operation of the device is initialised correctly for the new task. Note
that this only applies to the Command Register, the other registers may be accessed as normal.
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Figure 9 Transmit Mode Timing Diagram
t1
t2
Time from writing first task (modem in 'idle'
state) to application of first transmit bit to Tx
Low Pass filter
Time from application of first bit of
task to Tx Low Pass filter until BFREE
goes to a logic '1' (high).
t3
Time to transmit all bits of task
t4
Max time allowed from BFREE going to a
logic '1' (high) for next task (and data) to
be written to modem
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Task
Typical time
(bit-times)
Any
1
T7H
TQB
TDB
TSB
T7H
TQB
TDB
TSB
T7H
TQB
TDB
TSB
36
24
20
1
56
32
240
8
18
6
218
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FX909A
Figure 10 Receive Mode Timing Diagram
Task
t3
Time to receive all bits of task
t6
Maximum time between first bit of task
entering de-interleave circuit and task
being written to modem.
t7
Time from last bit of task entering de-interleave
circuit to BFREE going to a logic '1' (high)
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SFH
R3H
RDB
RSB
SFH
R3H
RDB
RSB
Any
Typical time
(bit-times)
56
24
240
8
14
18
218
6
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Tx/Rx Low Pass Filter Delay
The previous task timing figures are based on the signal at the input to the Tx Low Pass filter (in
transmit mode) or the input to the de-interleave buffer (in receive mode). There is an additional delay
of about 2 bit times in both transmit and receive modes due to the Tx/Rx Low Pass filter, as
illustrated in Figure 11.
Figure 11 Low Pass Filter Delay
1.5.4.3
Control Register
This 8-bit write only register controls the modem's bit rate, the response times of the receive clock
extraction and signal level measurement circuits and the internal analogue filters.
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Control Register B7, B6: CKDIV - Clock Division Ratio and
B5: HILON - Xtal Range Selection
These bits control a frequency divider driven from the clock signal present at the XTALN pin, and
hence determine the nominal bit rate. The table below shows how bit rates of 4000/8000/16000 or
4800/9600/19200 bits/sec may be obtained from common Xtal frequencies:
B5
Xtal/Clock Frequency (MHz)
8.192
9.8304
4.096
(12.288/3)
4.9152
1
0
4.096
(12.288/3)
2.048
(6.144/3)
4.9152
2.4576
(12.288/5)
2.048
(6.144/3)
1.024
2.4576
(12.288/5)
1.2288
8000
4000
9600
4800
Division Ratio:
B7
B6
0
0
1
1
0
1
0
1
Xtal Frequency
Data Rate
256
512
1024
2048
128
256
512
1024
Data Rate (bits per second)
16000
8000
4000
19200
9600
4800
16000
8000
4000
19200
9600
4800
Note: Device operation is not guaranteed below 4000 or above 19200 bits/sec.
The values used for C3 and C4 should be suitable for the frequency of the crystal X1. As a guide;
C3 = C4 = 33pF for X1 < 5MHz, and C3 = C4 = 18pF for X1 > 5MHz.
Control Register B4: DARA - Data Rate
This bit operates in both transmit and receive modes, optimising the modem's internal signal filtering
according to the relevent bit rate.
If the bit rate used is above 10k bits/sec this bit should be set to '1' else it should be set to '0'.
Control Register B3, B2: LEVRES - Level Measurement Response Time
These two bits have no effect in transmit mode.
In receive mode, they set the 'normal' response time of the Rx signal amplitude and dc offset
measuring circuits. This setting will be temporarily overridden by the automatic sequencing of an
AQLEV command.
B3
0
0
1
1
B2
0
1
0
1
Hold
Peak Averaging
Peak Detect
Lossy Peak Detect
Keep current values of amplitude and offset
Track input signal using bit peak averaging
Track input signal using peak detect
Track input signal using lossy peak detection
For Mobitex systems, and most general purpose applications using the modem, these bits should
normally be set to 'Peak Averaging', except when the µC detects a receive signal fade, when 'Hold'
should be selected.
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The 'Lossy Peak Detect' setting is intended for systems where the µC cannot detect signal fades or
the start of a received message, as it allows the modem to respond quickly to fresh messages and
recover rapidly after a fade without µC intervention - although at the cost of reduced Bit Error Rate
versus Signal to Noise performance.
Note that, since the measured levels are stored on the external capacitors C6 and C7, they will
decay gradually towards VBIAS when the 'Hold' setting is chosen, the discharge time-constant being
approximately 2000 bit times. More details of the level measurement system are given in section
1.6.3.
Control Register B1, B0: PLLBW
These two bits have no effect in transmit mode.
In receive mode, they set the 'normal' bandwidth of the Rx clock extraction Phase Locked Loop
circuit. This setting will be temporarily overridden by the automatic sequencing of an AQBC
command.
B1
0
0
1
1
B0
0
1
0
1
PLL Bandwidth
Hold
Narrow
Medium
Wide
Suggested use
Signal fades
± 20ppm or better Xtals
Wide tolerance Xtals or long preamble acquisition
Quick acquisition
The 'hold' setting is intended for use during signal fades, otherwise the minimum bandwidth
consistent with the transmit and receive modem bit rate tolerances should be chosen.
The wide and medium bandwidth settings are intended for systems where the µC cannot detect
signal fades or the start of a received message, as they allow the modem to respond rapidly to fresh
messages and recover rapidly after a fade without µC intervention - although at the cost of reduced
Bit Error Rate versus Signal to Noise performance.
Note: More details of the clock extraction system are given in section 1.6.3.
1.5.4.4
Mode Register
The contents of this 8-bit write only register control the basic operating modes of the modem:
Mode Register B7: IRQNEN - IRQN Output Enable
When this bit is set to '1', the IRQN chip output pin is pulled low (to Vss) whenever the IRQ bit of the
Status Register is a '1'.
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Mode Register B6: INVBIT - Invert Bits
This bit controls inversion of transmitted and received bit voltages. When set to '1' all data is inverted
in the Tx and Rx data paths so a transmitted '1' is a voltage below VBIAS at the TXOP pin and a
received '0' is a voltage above VBIAS at the RXIN pin. Data will be inverted immediately after this bit
is set to '1'.
Mode Register B5: TXRXN - Tx/Rx Mode
Setting this bit to '1' puts the modem into Transmit mode, clearing it to '0' puts the modem into
Receive mode. When changing from Rx to Tx there must be a 2-bit pause before setting a new task
to allow the filter to stabilise. (See also PSAVE bit).
Note that changing between receive and transmit modes will cancel any current task
Mode Register B4: SCREN - Scramble Enable
The scrambler only takes effect during the transmission or reception of a Mobitex Data Block and
during a TSO task. Setting this bit to '1' enables scrambling, clearing it to '0' disables scrambling.
The scrambler is only operative, if enabled by this control bit, during TSO, RDB or TDB, it is held in a
reset state at all other times.
This bit should not be changed while the modem is decoding or transmitting a Mobitex Data Block.
Mode Register B3: PSAVE - Powersave
When this bit is a '1', the modem will be in a 'powersave' mode in which the internal filters, the Rx bit
and Clock extraction circuits and the Tx o/p buffer will be disabled, and the TXOP pin will be
connected to VBIAS through a high value resistance. The Xtal Clock oscillator and the µC interface
logic will continue to operate.
Setting the PSAVE bit to '0' restores power to all of the chip circuitry. Note that the internal filters will
take about 2 bit times to settle after the PSAVE bit is taken from '1' to '0'.
Mode Register B2: DQEN - Data Quality IRQ Enable
In receive mode, setting this bit to '1' causes the IRQ bit of the Status Register to be set to '1'
whenever a new Data Quality reading is ready. (The DQRDY bit of the Status Register will also be
set to '1' at the same time.)
In transmit mode this bit has no effect.
Mode Register B1, B0
These bits should be set to '0'.
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1.5.4.5
FX909A
Status Register
This register may be read by the µC to determine the current state of the modem.
Status Register B7: IRQ - Interrupt Request
This bit is set to '1' by:
The Status Register BFREE bit going from '0' to '1', unless this is caused by a RESET
task or by a change to the Mode Register PSAVE or TXRXN bits.
or
The Status Register IBEMPTY bit going from '0' to '1', unless this is caused by a
RESET task or by changing the Mode Register PSAVE or TXRXN bits.
or
The Status Register DQRDY bit going from '0' to '1' (If DQEN = '1' ).
or
The Status Register DIBOVF bit going from '0' to '1'.
The IRQ bit is cleared to '0' immediately after a read of the Status Register.
If the IRQEN bit of the Mode Register is '1', then the chip IRQN output will be pulled low (to Vss)
whenever the IRQ bit is '1'.
Status Register B6: BFREE - Data Buffer Free
This bit reflects the availability of the Data Buffer and is cleared to '0' whenever a task other than
NULL, RESET or TSO is written to the Command Register.
In transmit mode, the BFREE bit will be set to '1' (also setting the Status Register IRQ bit to '1') by
the modem when the modem is ready for the µC to write new data to the Data Buffer and the next
task to the Command Register.
In receive mode, the BFREE bit is set to '1' (also setting the Status Register IRQ bit to '1') by the
modem when it has completed a task and any data associated with that task has been placed into
the Data Buffer. The µC may then read that data and write the next task to the Command Register.
The BFREE bit is also set to '1', but without setting the IRQ bit, by a RESET task or when the Mode
Register PSAVE or TXRXN bits are changed.
Status Register B5: IBEMPTY - Interleave Buffer Empty
In transmit mode, this bit will be set to '1', also setting the IRQ bit, when less than two bits remain in
the Interleave Buffer. Any transmit task written to the modem after this bit goes to '1' will be too late to
avoid a gap in the transmit output signal.
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The bit is also set to '1' by a RESET task or by a change of the Mode Register TXRXN or PSAVE
bits, but in these cases the IRQ bit will not be set.
The bit is cleared to '0' by writing a task other than NULL, RESET or TSO to the Command Register.
Note: When the modem is in transmit mode and the Interleave Buffer is empty, a mid-level voltage
(VBIAS) will be applied to the Tx low pass filter.
In receive mode this bit will be '0'.
Status Register B4: DIBOVF - De-Interleave Buffer Overflow
In receive mode this bit will be set to '1' (also setting the IRQ bit) when a task is written to the
Command Register too late to allow continuous reception.
The bit is cleared to '0' by reading the Status Register or by writing a RESET task to the Command
Register or by changing the PSAVE or TXRXN bits of the Mode Register.
In transmit mode this bit will be '0'.
Status Register B3: CRCFEC - CRC or FEC Error
In receive mode this bit will be updated at the end of a Mobitex Data Block task, after checking the
CRC, and at the end of receiving Frame Head control bytes, after checking the FEC. A '0' indicates
that the CRC was received correctly or the FEC did not find uncorrectable errors, a '1' indicates that
errors are present.
The bit is cleared to '0' by a RESET task or by changing the PSAVE or TXRXN bits of the Mode
Register.
In transmit mode this bit will be '0'.
Status Register B2: DQRDY - Data Quality Reading Ready
In receive mode, this bit is set to '1' whenever a Data Quality reading has been completed. See
section 1.5.4.6.
The bit is cleared to '0' by a read of the Data Quality Register.
Immediately after a RESET task, or a change in the PSAVE or TXRXN bits to '0', the DQRDY bit may
be set and generate an interrupt. The value in the Data Quality Register will not be valid in this case.
Status Register B1: MOBAN - Mobile or Base Bit Sync Received
In receive mode this bit is updated at the end of the SFS and SFH tasks. This bit is set to '1'
whenever the 3 bits immediately preceding a detected Frame sync are '011' (received left to right),
with up to any one bit in error. The bit is set to '0' if the bit pattern is '100', again with up to any one
bit in error. Thus, if this bit is set to '1' then the received message is likely to have originated from a
Mobile and if it is set to '0' from a Base Station. See section 1.5.3.
In transmit mode this bit is a logic '0'.
Status Register B0
This bit will always be set to '0'.
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1.5.4.6
FX909A
Data Quality Register
This is intended to indicate the quality of the receive signal during a Mobitex Data Block or 30 single
bytes. In receive mode, the modem measures the 'quality' of the received signal by comparing the
actual received zero crossing time against an internally generated time. This value is averaged over
240 bits and at the end of the measurement the Data Quality Register and the DQRDY bit in the
Status Register is updated. Note: An interrupt will only occur at this time if the DQEN bit = '1'.
To provide synchronisation with Data Blocks, and hence ensure the Data Quality Register is updated
in preparation to be read when the RDB task finishes, the measurement process is reset at the end
of tasks SFH, SFS, RDB and R3H.
In transmit mode all bits of the Data Quality Register will be '0'.
Figure 12 shows how the value (0-240) read from the Data Quality Register varies with received
signal to noise ratio.
Figure 12 Typical Data Quality Reading (after 240 bits) vs S/N, (noise in bit rate bandwidth)
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1.5.5
CRC, FEC, Interleaving and Scrambling Information
1.5.5.1
CRC
This is a 16-bit CRC code used in the Mobitex Data Block. In transmit it is calculated by the modem
from the 18 data bytes using the following generator polynomial:
g(x) = x16 + x12 + x5 + 1
i.e.
CRC - CCITT X.25.
This code detects all (single) error bursts of up to 16 bits in length and about 99.998% of all other
error patterns.
The CRC register is initialised to all '1s' and the CRC is calculated octet by octet starting with the
least significant bit of 'byte 0'. The CRC calculated is bit-wise inverted and appended to the data
bytes with the most significant bit transmitted earliest.
In receive mode, a 16-bit CRC code is generated from the 18 data bytes of each Mobitex Data Block
as above and the bit-wise inverted value is compared with the received CRC bytes. If a mis-match is
present, then an error has been detected.
1.5.5.2
FEC
In transmit mode, during T7H and TDB, the modem generates a 4-bit Forward Error Correction code
for each coded byte. The FEC is defined by the following H matrix:
7_______0
11101100
H = 11010011
10111010
01110101
3___0
1000
0100
0010
0001
Generation of the FEC consists of logically ANDing the byte to be transmitted with bits 7 to 0 of each
row of the H matrix. Even parity is generated for each of the 4 results and these 4 parity bits, in the
positions indicated by the last 4 columns of the H matrix, form the FEC code.
In checking the FEC, the received 12-bit word is logically ANDed with each row of the H matrix
(earliest bit received compared with the first column). Again even parity is generated for the 4
resulting words and these parity bits form a 4-bit nibble. If this nibble is all zero then no errors have
been detected. Other results 'point' to the bit in error or indicate that uncorrectable errors have
occurred.
This code can correct any single error that has occurred in each 12-bit (8 data + 4 FEC) section of
the message.
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Example:
If the byte to be coded is '00101100' then the FEC is derived as follows:
H matrix row:
A
B
A AND B
Even Parity:
1
11101100
00101100
00101100
1
2
11010011
00101100
00000000
0
3
10111010
00101100
00101000
0
4
01110101
00101100
00100100
0
where A is bits 7 - 0 of one row of the H matrix and B is the byte to be coded. The even parity bits
apply to the result of 'A AND B'.
So the word formed will be: '00101100 1000' sent left to right
When the same process is carried out on these 12 bits as above, using all 12 bits of each H matrix
row, the resulting 4 parity bits will be '0000'.
1.5.5.3
Interleaving
The 240 bits of a Mobitex Data Block are interleaved by the modem before transmission to give
protection against noise bursts and short fades. Interleaving is not performed on any bits in the
Mobitex Frame Head.
Considering the 240 bits to be numbered sequentially before interleaving as 0 to 239 ('0' = bit 7 of
byte 0, '11' = bit 0 of FEC for byte 0, ... ,'239' = bit 0 of FEC for byte 19 - see Figure 6), then they will
be transmitted as shown in Figure 13.
The modem performs the inverse operation (de-interleaving) in receive mode on Mobitex Data
Blocks.
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FX909A
Figure 13 Interleaving - Input/Output
1.5.5.4
Scrambling
All formatted bits of a Mobitex Data Block are passed through a 9-bit scrambler. This scrambler is
initialised at the beginning of the first Data Block in every Frame. The 511-bit sequence is generated
with a 9-bit shift register with the output of the 5th and 9th stages XOR'ed and fed back to the input of
the first stage. The scrambler is disabled during all other tasks, apart for TSO.
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1.6
Application Notes
1.6.1
Transmit Frame Example
If the device is required to send a Mobitex Frame the following control signals and data should be
issued to the modem, assuming the device is not starting from a powersave state, TXRXN is set to '1'
and that SCREN, DARA, CKDIV, and DQEN have been set as required after power was applied to
the device:
1. 6 bytes forming the Frame Head are loaded into the Data Buffer, followed by a 2-bit pause to let
the filter stabilise, followed by setting T7H task.
2. Device interrupts host µC with IRQN when the 6th byte is read from the Data Buffer.
3. Status Register is read and 18 bytes are loaded, followed by setting TDB task.
4. Device interrupts host µC with IRQN when 18th byte is read from the Data Buffer.
5. Status Register is read, host may load data and set next task as required:
GOTO '1'
GOTO '3'
GOTO '6'
if the last Data Block for this Frame has been transmitted
and another Frame is to be immediately transmitted
if another Data Block in this Frame is to be transmitted
if no more data is to be immediately sent
6. 1 byte representing the 'hang byte' is loaded into the Data Buffer, followed by setting the TSB
task.
If the 'hang byte' has been transmitted and no more data is to be sent then a new task need not be
written and the µC can wait for the IBEMPTY interrupt when, after a few bits to allow for the Tx filter
delay, it can shut down the Tx RF circuits.
A top level flowchart of the transmit process is shown in Figure 14.
Hang Byte
The filtering required to reduce the transmitted bandwidth causes energy from each bit of information
to be smeared across 3 bit times. To ensure that the last bit transmitted is received correctly it is
necessary to add an 8-bit 'hang byte' to the end of each message. Thus the tasks required to
transmit an isolated Mobitex frame are:
T7H + (n x TDB) + TSB
When receiving this data, the extra byte can be ignored as its only function is to ensure integrity of
the last bit and not to carry any information itself.
It is suggested that a '00110011' or '11001100' pattern is used for this 'hang byte'.
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Figure 14 Transmit Process
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1.6.2
FX909A
Receive Frame Example
If the device is required to decode a Mobitex Frame the following control signals should be issued to
the modem, assuming the device is initially not in powersave, PLLBW, LEVRES, SCREN are set as
required, TXRXN bit is set to '0', the Frame Sync bytes have not been set and the carrier has been
detected, or a Frame Head is imminently expected:
1. 2 Frame Sync bytes are loaded.
2. 2 bits after the carrier has been detected, a LFSB task is loaded, along with setting the AQLEV
and AQBC bits, to initiate the level acquisition and bit clock extraction sequences.
3. Device interrupts host µC with IRQN when 2nd byte is read from Data Buffer.
4. Status Register is read, 12 bits later task is set to SFH to search for a Mobitex Frame Head.
5. Device will interrupt host µC with IRQN when valid Frame Sync is detected and header bytes
decoded.
6. Host µC reads Status Register, checks MOBAN and CRCFEC bit and reads out 2 Frame Head
control bytes.
7. Host µC sets the task to RDB to receive a Mobitex Data Block.
8. Device will interrupt host µC with IRQN when the Data Block has been received and the CRC
has been calculated.
9. Host µC reads Status Register, checks CRC validity and reads 18 Data Block bytes. The Data
Quality Register can also be read to obtain the received S/N level.
10. Host µC sets task if more information is expected:
GOTO '4'
GOTO '7'
if last Data Block and another Frame Head imminently expected.
if another Mobitex Data Block expected.
If the last Data Block has been decoded and no more information is expected then the task bits need
not be set as the device will automatically select the idle state.
A top level flowchart of the receive process is shown in Figure 15.
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Figure 15 Receive Process
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1.6.3
FX909A
Clock Extraction and Level Measurement Systems
The modem needs to make accurate measurements of the received signal amplitude, dc offset and
bit timing to achieve reasonable error rates. Accurate measurements, especially in the presence of
noise, are best made by averaging over a relatively long time.
However, in most cases the modem will be used to receive isolated messages from a distant
transmitter that is only turned on for a very short time before the message starts. Also, the received
baseband signal out of the radio's frequency discriminator will have a dc offset due to small
differences between the receiver and transmitter reference oscillators and hence their 'carrier'
frequencies.
To cater for this situation, AQBC and AQLEV (Acquire Bit Clock and Level) commands are provided
which, when triggered, causes the modem to follow an automatic sequence designed to perform
these measurements as quickly as possible.
The AQLEV sequence always starts with a measurement of the average signal voltage over a period
of 1 bit time. The sequence continues by measuring the positive going and negative going peaks of
the signal. The attack and decay times used in this 'Lossy Peak Detect' mode are such that a
sufficiently accurate measurement can be made within 16 bits of a ' 1100 ...' pattern (i.e. the bit sync
sequence) to allow the bit clock extraction circuits to operate.
If SFH or SFS is set within 28 bit times of AQLEV the device will switch to the Residual setting when
Frame Sync is found. If a SFH or SFS task is not set then the Residual setting will be active 30 bits
after AQLEV was set. The Residual setting is that programmed in the LEVRES bits and is either
'Lossy Peak Detect', 'Peak Detect', 'Peak Averaging' or 'Hold'. Note: For normal operation the
LEVRES bits would only be set to 'hold' for the duration of a fade.
If SFH or SFS is set within 14 bit times of AQBC the device will switch to the Medium setting when
Frame Sync is found. If a SFH or SFS task is not set then the Medium setting will be active 16 bits
after AQBC was set. The PLLBW will change to the Residual setting 30 bits later.
The complete AQBC and AQLEV sequence is illustrated below, for the situation where the µC can
detect the received carrier so that it knows when to issue the AQBC and AQLEV commands. Note
that due to the delay through the Rx low pass filter, the AQBC and AQLEV sequences should not be
started until about 2 bit times after the received carrier has been detected at the discriminator output.
See Figure 16.
In a system where the host µC is not able to detect the received carrier, the AQBC and AQLEV
sequences may be started at any time - possibly when no carrier is being received. However, in this
case the clock and level acquisition will take longer since the circuits will have to recover from the
change from a large amplitude noise signal at the output of the frequency discriminator to the wanted
signal, probably with a dc offset. In this type of system, the time between the turn-on of the
transmitter and the start of the Frame Sync pattern should be extended - preferably by extending the
Bit Sync sequence to 32 or even 48 bits.
Note that the clock extraction circuits work by detecting the timing of edges, i.e. a change from '0' to
'1' or '1' to '0'. They will eventually fail if '1' or '0' is transmitted continuously. Similarly, the level
measuring circuits require '00' and '11' bit pairs to be received at reasonably frequent intervals.
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D/909A/4
Wireless Modem Data Pump
FX909A
AQLEV Sequence
AQBC Sequence
SFH or SFS is set up to 28 bits after AQLEV;
Frame Sync is being searched for:
1 bit of clamp.
Lossy Peak detect until Frame Sync is detected.
Residual setting.
SFH or SFS is set up to 14 bits after AQBC;
Frame Sync is being searched for:
'Wide' setting until Frame Sync detected.
30 bits of 'Medium' setting.
Residual setting.
SFH or SFS is not set; Frame Sync is not being
searched for:
1 bit of clamp.
30 bits of Lossy Peak Detect.
Residual setting.
SFH or SFS is not set; Frame Sync is not being
searched for:
16 bits of 'Wide' setting.
30 bits of 'Medium' setting.
Residual setting.
Figure 16 Bit Clock and Level Acquisition Example
1.6.4
AC Coupling
For a practical circuit, ac coupling from the modem's transmit output to the Frequency Modulator and
between the receiver's Frequency Discriminator and the receive input of the modem may be desired.
There are, however, two problems.
Firstly, ac coupling of the signal degrades the Bit Error Rate performance of the modem. See Figure
17.
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D/909A/4
Wireless Modem Data Pump
FX909A
Figure 17 Typical Bit Error Rates (at 8kbits/sec, without FEC, for different degrees of ac coupling)
Secondly, any ac coupling at the receive input will transform any step in the voltage at the
discriminator output to a slowly decaying pulse which can confuse the modem's level measuring
circuits. As illustrated below, the time for this step to decay to 37% of its original value is 'RC' where
RC = 1/( 2 x π x the 3dB cut-off frequency of the RC network )
and is 8 msec - or 64 bit times at 8kbits/sec for a 20Hz network. See Figure 18.
Figure 18 Decay Time - AC Coupling
For these reasons the maximum 3dB cut-off frequencies would seem to be around 5Hz in the Tx
path and 20Hz in the Rx path at 8kbits/sec.
1996 Consumer Microcircuits Limited
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D/909A/4
Wireless Modem Data Pump
1.6.5
FX909A
Radio Performance
The maximum data rate that can be transmitted over a radio channel using this modem depends on:
-
RF channel spacing.
Allowable adjacent channel interference.
Bit rate.
Peak carrier deviation (modulation index).
Tx and Rx reference oscillator accuracies.
Modulator and demodulator linearity.
Receiver IF filter frequency and phase characteristics.
Use of error correction techniques.
Acceptable error rate.
As a guide, 8000 bits/sec can be achieved (subject to local regulatory requirements) over a system
with 12.5kHz channel spacing if the transmitter frequency deviation is set to ± 2kHz peak for a
repetitive ' 1100... ' pattern and the maximum difference between transmitter and receiver 'carrier'
frequencies is less than 1500Hz.
The modulation scheme employed by this modem is designed to achieve high data throughput by
exploiting as much as possible of the RF channel bandwidth. This does, however, place constraints
on the performance of the radio. In particular, attention must be paid to:
-
Linearity, frequency and phase response of the Tx Frequency Modulator.
The bandwidth and phase response of the receiver's IF filters.
Accuracy of the Tx and Rx reference oscillators, as any difference will shift the received signal
towards the skirts of the IF filter response and cause a dc offset at the discriminator output.
Viewing the received signal eye pattern, using the output of the frequency discriminator, gives a good
indication of the overall transmitter/receiver performance.
Figure 19 Typical System Installation
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D/909A/4
Wireless Modem Data Pump
1.7
Performance Specification
1.7.1
Electrical Performance
FX909A
Absolute Maximum Ratings
Exceeding these maximum ratings can result in damage to the device.
Min.
-0.3
-0.3
-30
-20
Max.
7.0
VDD + 0.3
+30
+20
Units
V
V
mA
mA
D2 Package
Total Allowable Power Dissipation at Tamb = 25°C
... Derating
Storage Temperature
Operating Temperature
Min.
Max.
800
13
+125
+85
Units
mW
mW/°C
°C
°C
D5 Package
Total Allowable Power Dissipation at Tamb = 25°C
... Derating
Storage Temperature
Operating Temperature
Min.
Max.
550
9
+125
+85
Units
mW
mW/°C
°C
°C
P4 Package
Total Allowable Power Dissipation at Tamb = 25°C
... Derating
Storage Temperature
Operating Temperature
Min.
Max.
800
13
+125
+85
Units
mW
mW/°C
°C
°C
Max.
5.5
+85
10.0
Units
V
°C
MHz
Supply (VDD - VSS)
Voltage on any pin to VSS
Current into or out of VDD and VSS pins
Current into or out of any other pin
-55
-40
-55
-40
-55
-40
Operating Limits
Correct operation of the device outside these limits is not implied.
Notes
Supply (VDD - VSS)
Operating Temperature
Xtal Frequency
1996 Consumer Microcircuits Limited
40
Min.
3.0
-40
1.0
D/909A/4
Wireless Modem Data Pump
FX909A
Operating Characteristics
For the following conditions unless otherwise specified:
Xtal Frequency = 4.096MHz, Bit Rate = 8k bits/sec, Noise Bandwidth = Bit Rate,
VDD = 3.3V to 5.0V, Tamb = - 40°C to +85°C.
Notes
DC Parameters
IDD (not powersaved)
IDD (powersaved)
IDD (not powersaved)
IDD (powersaved)
(VDD = 3.3V)
(VDD = 3.3V)
(VDD = 5.0V)
(VDD = 5.0V)
AC Parameters
Tx Output
TXOP Impedance (not powersaved)
TXOP Impedance (powersaved)
Signal Level
Tx Data Delay
Rx Input
RXIN Impedance (at 100Hz)
RXIN Amp Voltage Gain (I/P = 1mVrms at 100Hz)
Input Signal Level
Rx Data Delay
Xtal/Clock Input
'High' Pulse Width
'Low' Pulse Width
Input Impedance (at 100Hz)
Gain (I/P = 1mVrms at 100Hz)
µC Interface
Input Logic "1" Level
Input Logic "0" Level
Input Leakage Current (Vin = 0 to VDD)
Input Capacitance
Output Logic "1" Level (lOH = 120µA)
Output Logic "0" Level (lOL = 360µA)
'Off' State Leakage Current (Vout = VDD)
Notes:
Min.
Typ.
Max.
Units
1
1
1
1
2.2
0.4
3
0.9
3.3
0.6
4.5
1.4
mA
mA
mA
mA
2
2
3
4
1.0
300
1.0
4
2.5
0.9
1.1
6
10.0
5
6
0.7
7
7
40
40
10.0
20
8, 9
8, 9
8, 9
8, 9
9
9,10
10
500
1.0
3.5
1.3
kΩ
kΩ
V pk-pk
bits
MΩ
V/V
V pk-pk
bits
ns
ns
MΩ
dB
70%
30%
+5.0
5.0
10.0
90%
10%
10
VDD
VDD
µA
pF
VDD
VDD
µA
1. Not including any current drawn from the modem pins by external circuitry.
2. Small signal impedance, at VDD = 5.0V and Tamb = 25°C.
3. For "1111000011110000.." bit sequence, at VDD = 5.0V and Tamb = 25°C
(output level is proportional to VDD).
4. Measured between issuing first task after idle and the centre of the first bit at TXOP
(See Figure 7, 'The Transmit Process').
5. For optimum performance, measured at RXFB pin,
for a "...11110000..." bit sequence, at VDD = 5.0V and Tamb = 25°C.
6. Measured between centre of last bit of an Rx single byte or Frame Sync at RXIN and an IRQ
interrupt to the host µC.
7. Timing for an external input to the CLOCK/XTAL pin.
8. WRN, RDN, CSN, A0 and A1 pins.
9. D0 - D7 pins.
10. IRQN pin.
1996 Consumer Microcircuits Limited
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D/909A/4
Wireless Modem Data Pump
1.7.1
FX909A
Electrical Performance (continued)
Timing Diagrams
Figure 20 µC Parallel Interface Timings
1996 Consumer Microcircuits Limited
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D/909A/4
Wireless Modem Data Pump
FX909A
For the following conditions unless otherwise specified:
Xtal Frequency = 4.096MHz, VDD = 3.3V to 5.0V, Tamb = - 40°C to +85°C.
Notes
Min.
Typ.
Max.
Units
µC Parallel Interface Timings (ref. Figure 20)
tACSL
Address valid to CSN low time
0
ns
tAH
Address hold time
0
ns
tCSH
CSN hold time
0
ns
tCSHI
CSN high time
6
clock cycles
tCSRWL
CSN to WRN or RDN low time
0
ns
tDHR
Read data hold time
0
ns
tDHW
Write data hold time
0
ns
tDSW
Write data setup time
90
ns
tRHCSL
RDN high to CSN low time (write)
0
ns
tRACL
Read access time from CSN low
11
175
ns
tRARL
Read access time from RDN low
11
145
ns
tRL
RDN low time
tRX
RDN high to D0-D7 3-state time
tWHCSL
WRN high to CSN low time (read)
tWL
WRN low time
Notes:
11. With 30pF max to VSS on D0 - D7 pins.
12. Xtal/Clock cycles at the XTAL/CLOCK pin.
1996 Consumer Microcircuits Limited
12
200
ns
50
43
ns
0
ns
200
ns
D/909A/4
Wireless Modem Data Pump
FX909A
N.B. A block is deemed to be in error if the CRC fails.
Figure 21 Typical Bit Error Rate (noise in bit rate bandwidth)
1996 Consumer Microcircuits Limited
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D/909A/4
Wireless Modem Data Pump
1.7.2
FX909A
Packaging
Figure 22 D2 Mechanical Outline: Order as part no. FX909AD2
Figure 23 D5 Mechanical Outline: Order as part no. FX909AD5
1996 Consumer Microcircuits Limited
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D/909A/4
Wireless Modem Data Pump
FX909A
Figure 24 P4 Mechanical Outline: Order as part no. FX909AP4
Handling precautions: This product includes input protection, however, precautions should be taken to prevent
device damage from electro-static discharge. CML does not assume any responsibility for the use of any
circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without
notice to change the said circuitry and this product specification. CML has a policy of testing every product
shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing
of all circuit parameters is not necessarily performed.
CONSUMER MICROCIRCUITS LIMITED
1 WHEATON ROAD
WITHAM - ESSEX CM8 3TD - ENGLAND
Telephone:
Telefax:
+44 1376 513833
+44 1376 518247
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
In the process of creating a more global image, the three standard product semiconductor
companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc
(USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst
maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA)
Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits.
These companies are all 100% owned operating companies of the CML Microsystems Plc
Group and these changes are purely changes of name and do not change any underlying legal
entities and hence will have no effect on any agreements or contacts currently in force.
CML Microcircuits Product Prefix Codes
Until the latter part of 1996, the differentiator between products manufactured and sold from
MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX
respectively. These products use the same silicon etc. and today still carry the same prefixes.
In the latter part of 1996, both companies adopted the common prefix: CMX.
This notification is relevant product information to which it is attached.
Company contact information is as below:
CML Microcircuits
(UK)Ltd
CML Microcircuits
(USA) Inc.
CML Microcircuits
(Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
COMMUNICATION SEMICONDUCTORS
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon,
Essex, CM9 6WG, England
Tel: +44 (0)1621 875500
Fax: +44 (0)1621 875600
[email protected]
www.cmlmicro.com
4800 Bethania Station Road,
Winston-Salem, NC 27105, USA
Tel: +1 336 744 5050,
0800 638 5577
Fax: +1 336 744 5054
[email protected]
www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/
06 Mactech Industrial Building,
Singapore 349307
Tel: +65 7450426
Fax: +65 7452917
[email protected]
www.cmlmicro.com
D/CML (D)/1 February 2002