PRELIMINARY DS1135 3-in-1 High-Speed Silicon Delay Line www.dalsemi.com FEATURES PIN ASSIGNMENT All-silicon timing circuit Three independent buffered delays Stable and precise over temperature and voltage Leading and trailing edge precision preserves the input symmetry Standard 8-pin DIP and 8-pin SOIC (150 mil) Vapor phasing, IR and wave solderable Available in Tape and Reel Commercial and industrial temperature ranges available; see order info table 5V operation (for 3V operation, see part number DS1135L) Recommended replacement for DS1013 and DS1035 IN1 1 8 VCC IN2 2 7 OUT1 IN3 3 6 OUT2 GND 4 5 OUT3 DS1135M 8-Pin DIP IN1 1 8 VCC IN2 2 7 OUT1 IN3 3 6 OUT2 GND 4 5 OUT3 DS1135Z 8-Pin SOIC (150 mil) IN1 1 8 VCC IN2 2 7 OUT1 IN3 3 6 OUT2 GND 4 5 OUT3 DS1135U 8-Pin 118-mil uSOP PIN DESCRIPTION IN1-IN3 OUT1-OUT3 VCC GND - Input Signals - Output Signals - +5V Supply - Ground DESCRIPTION The DS1135 series is a low-power, +5-volt high-speed version of the popular DS1013 and DS1035. The DS1135 series of delay lines have three independent logic buffered delays in a single package. The device is Dallas Semiconductor’s fastest 3-in-1 delay line. It is available in a standard 8-pin DIP and 150 mil 8-pin Mini-SOIC, as well as an 8-pin, 118 mil uSOP. The device features precise leading and trailing edge accuracy. It has the inherent reliability of an allsilicon delay line solution. Each output is capable of driving up to 10 LS loads. Standard delay values are indicated in Table 1. Customers may contact Dallas Semiconductor at (972) 371-4348 for further information on custom delay values. 1 of 6 061500 DS1135 LOGIC DIAGRAM Figure 1 IN TIME DELAY OUT ONE OF THREE PART NUMBER DELAY TABLE (tPLH , tPHL ) Table 1 PART NUMBER DS1135-5 DS1135-6 DS1135-8 DS1135-10 DS1135-12 DS1135-15 DS1135-20 DS1135-25 DS1135-30 DELAY PER OUTPUT (ns) 5/5/5 6/6/6 8/8/8 10/10/10 12/12/12 15/15/15 20/20/20 25/25/25 30/30/30 INITIAL TOLERANCE (Note 1) ±1.0 ns ±1.0 ns ±1.0 ns ±1.0 ns ±1.0 ns ±1.0 ns ±1.0 ns ±1.5 ns ±1.5 ns TOLERANCE OVER TEMP AND VOLTAGE (Note 2) 0°C to +70°C -40°C to +85°C ±1.0 ns ±1.5 ns ±1.0 ns ±1.5 ns ±1.0 ns ±1.5 ns ±1.0 ns ±1.5 ns ±1.0 ns ±1.5 ns ±1.5 ns ±2 ns ±1.5 ns ±2 ns ±1.5 ns ±2 ns ±1.5 ns ±2 ns NOTES: 1. Nominal conditions are +25°C and VCC =+5.0 volts. 2. Voltage range of 4.75 volts to 5.25 volts. 3. Delay accuracies are for both leading and trailing edges. TEST SETUP DESCRIPTION Figure 2 illustrates the hardware configuration used for measuring the timing parameters of the DS1135. The input waveform is produced by a precision pulse generator under software control. Time delays are measured by a time interval counter (20 ps resolution ) connected to the output. The DS1135 output taps are selected and connected to the interval counter by a VHF switch control unit. All measurements are fully automated with each instrument controlled by the computer over an IEEE 488 bus. 2 of 6 DS1135 DS1135 TEST CIRCUIT Figure 2 PULSE GENERATOR START TIME INTERVAL COUNTER 3 IN 50Ω STOP VHF SWITCH CONTROL UNIT UNIT UNDER TEST OUT 50Ω TAPS 1-3 3 of 6 DS1135 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature Short Circuit Output Current -1.0V to +7.0V -40°C to +85°C -55°C to +125°C See J-STD-020A specification 50 mA for 1 second * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Supply Voltage Active Current VCC High Level Input Voltage VIH Low Level Input Voltage Input Leakage High Level Output Current VIL IL Low Level Output Current ICC TEST CONDITION (-40°C to +85°C;VCC=+5V±5%) MIN TYP 4.75 0V≤VI ≤VCC VCC =4.75V VOH =4V ICC VCC =4.75V VOL=0.5V Input-to-Output Delay Output Rise or Fall Time Power-up Time tWI tPLH, tPHL tOF, tOR tPU NOTES 5.25 V mA 1 35 VCC +0.5 0.8 +1.0 2.2 ICC SYMBOL tPERIOD UNITS VCC =5.25V Period=1µs -0.5 -1.0 V V µA mA -1.0 1 1 (-40°C to +85°C;VCC=+5V±5%) MIN TYP 2 (tWI ) 100% of Tap Delay See Table 1 2.0 MAX ns 2.5 100 UNITS ns NOTES 2 ns 2 ns ms 3 CAPACITANCE PARAMETER Input Capacitance 1 1 mA 12 AC ELECTRICAL CHARACTERISTICS PARAMETER Period Input Pulse Width 5.00 MAX (TA=25°C) SYMBOL CIN MIN 4 of 6 TYP MAX 10 UNITS pF NOTES DS1135 TEST CONDITIONS Ambient Temperature: 25°C ±=3°C Supply Voltage (VCC ): 5.0V ±=0.1V Input Pulse: High: 3.0V ±=0.1V Low: 0.0V ±=0.1V Source Impedance: 50Ω=Max. Rise and Fall Time: 3.0 ns Max. - Measured between 0.6V and 2.4V. Pulse Width: 500 ns Pulse Period: 1 µs Output Load Capacitance: 15 pF Output: Each output is loaded with the equivalent of one 74F04 input gate. Data is measured at the 1.5V level on the rising and falling edges. NOTE: The above conditions are for test only and do not restrict the devices under other data sheet conditions. TIMING DIAGRAM PERIOD tRISE tFALL 80% 1.5V 1.5V 1.5V 20% IN tWI tWI tPLH tPHL tOR 1.5V tOF 1.5V OUT NOTES: 1. All voltages are referenced to ground. 2. Pulse width and duty cycle specifications may be exceeded, however, accuracy will be application sensitive with respect to decoupling, layout, etc. 3. Power-up time is the time from the application of power to the time stable delays are being produced at the output. 5 of 6 DS1135 TERMINOLOGY Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. tWI (Pulse Width): The elapsed time on the pulse between the 1.5-volt point on the leading edge and the 1.5-volt point on the trailing edge or the 1.5-volt point on the trailing edge and the 1.5-volt point on the leading edge. tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the input pulse. tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge on the input pulse. tPLH (Time Delay, Rising): The elapsed time between the 1.5-volt point on the leading edge of the input pulse and the 1.5-volt point on the leading edge of the output pulse. tPHL (Time Delay, Falling): The elapsed time between the 1.5-volt point on the falling edge of the input pulse and the 1.5-volt point on the falling edge of the output pulse. ORDERING INFORMATION DS1135 TIME DELAY (ns): 5, 6, 8, 10, 12, 15, 20, 25, 30 PACKAGE TYPE: M = DIP Z = SOIC (150 Mil) U = uSOP (118 Mil) 6 of 6