DS2064 DS2064 8K x 8 Static RAM FEATURES PIN ASSIGNMENT • Low power CMOS design • Standby current NC 1 28 VCC A12 2 27 WE A7 3 26 CE2 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 • Data Retention Voltage = 5.5V to 2.0V A3 7 22 OE A2 8 21 A10 • Access time equals 200 ns at 5.0V A1 9 20 CE1 A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 GND 14 15 DQ3 50 nA max at 100 nA max at 1 µA max at tA = 25°C VCC = 3.0V tA = 25°C VCC = 5.5V tA = 60°C VCC = 5.5V • Full operation for VCC = 4.5V to 5.5V • Operating temperature range of –40°C to +85°C • Full static operation • TTL compatible inputs and outputs DS2064–200 28–PIN DIP (600 MIL) DS2064S–200 28–PIN SOIC (330 MIL) • Available in 28–pin DIP and 28–pin SOIC packages • Suitable for both battery operated and battery backup applications PIN DESCRIPTION A0–A12 DQ0–DQ7 CE1, CE2 WE OE VCC GND NC – – – – – – – – Address Inputs Data Input/Output Chip Enable Inputs Write Enable Input Output Enable Input 5V Power Supply Input Ground No Connection DESCRIPTION The DS2064 is a 65536–bit low power, fully static random access memory organized as 8192 words by eight bits using CMOS technology. The device operates from a single power supply with a voltage input between 4.5V and 5.5V. The chip enable inputs (CE1 and CE2) are used for device selection and can be used in order to achieve the minimum standby current mode, which fa- cilitates both battery operate and battery backup applications. The device provides fast access time of 200 ns and is most suitable for low power applications where battery operation or battery backup for nonvolatility are required. The DS2064 is a JEDEC–standard 8K x 8 SRAM and is pin–compatible with ROM and EPROM of similar density. 022598 1/9 DS2064 ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RATING VCC Power Supply Voltage –0.3V to +7.0V VIN, VI/O Input, Input/Output Voltage –0.3 to VCC + 0.3V TSTG Storage Temperature –55°C to +125°C TOPR Operating Temperature –40°C to +85°C TSOLDER Soldering Temperature/Time 260°C for 10 seconds (tA = –40°C to +85°C) RECOMMENDED DC OPERATING CONDITIONS PARAMETER SYMBOL MIN TYP MAX UNITS Power Supply Voltage VCC 4.5 5.0 5.5 V Input High Voltage VIH 2.0 VCC + 0.3 V Input Low Voltage VIL –0.3 0.8 V Data Retention Voltage VDR 2.0 5.5 V (tA = –40°C to +85°C; VCC=5V ± 10%) DC CHARACTERISTICS PARAMETER NOTES SYMBOL CONDITIONS Input Leakage Current IIL I/O Leakage Current MIN TYP MAX UNITS 0V < VIN < VCC +0.1 µA ILO CE1=VIH, 0V<VIO<VCC +0.5 µA Output High Current IOH VOH = 2.4V –1.0 mA Output Low Current IOL VOL = 0.4V 4.0 mA Standby Current ICCS1 CE1 = 2.0V Standby Current ICCS2 Standby Current ICCS2 Operating Current ICCO 0.5 mA CE1>VCC–0.5V tA=60°C 1 µA CE1>VCC–0.5V tA=25°C 100 nA CE1=0.8V, 200 ns cycle 70 mA CAPACITANCE PARAMETER (tA = 25°C) SYMBOL MIN TYP MAX UNITS Input Capacitance CIN 5 10 pF Input/Output Capacitance CI/O 5 12 pF 022598 2/9 NOTES DS2064 (tA = –40°C to +85°C; VCC=5V ± 10%) AC CHARACTERISTICS, READ CYCLE PARAMETER SYMBOL MIN TYP Read Cycle Time tRC 200 Access Time tACC 200 ns OE to Output Valid tOE 100 ns CE to Output Valid tCO 200 ns CE or OE to Output Active tCOE 5 Output to High–Z from Deselection tOD 10 Output Hold from Address Change tOH 5 UNITS ns 60 ns ns (tA = –40°C to +85°C; VCC=5V ± 10%) SYMBOL MIN Write Cycle Time tWC 200 ns Write Pulse Width tWP 150 ns Address Setup Time tAW 0 ns Write Recovery Time tWR 10 ns Output High–Z from WE tODW Output Active from WE tOEW Data Setup Time Data Hold Time NOTES ns AC CHARACTERISTICS, WRITE CYCLE PARAMETER MAX TYP MAX UNITS 70 NOTES ns 7 5 ns 7 tDS 80 ns tDH 0 ns TIMING DIAGRAM: READ CYCLE tRC ADDRESSES VIH VIL VIH VIL VIH VIL tOH tACC VIH VIH CE tCO VIL tOD VIH OE tOE VIL tCOE tCOE DOUT VIH tOD VOH OUTPUT VOH VOL DATA VALID VOL SEE NOTE 1 022598 3/9 DS2064 TIMING DIAGRAM: WRITE CYCLE 1 tWC ADDRESSES VIH VIL VIH VIL VIH VIL tAW CE VIL VIL tWP tWR WE VIH VIH VIL VIL tOEW tODW DOUT tDS tDH VIH DIN VIL SEE NOTES 2, 3, 4, 5, 6 AND 7 022598 4/9 VIH DATA IN STABLE VIL DS2064 TIMING DIAGRAM: WRITE CYCLE 2 tWC ADDRESSES VIH VIH VIH VIL VIL VIL tWP tAW tWR CE VIH VIH VIL VIL VIH WE VIL tCOE VIL tODW DOUT tDS tDH VIH VIH DATA IN STABLE DIN VIL VIL SEE NOTES 2, 3, 4, 5, 6 AND 7 TIMING DIAGRAM: DATA RETENTION – POWER UP, POWER DOWN DATA RETENTION MODE VCC 2.7V VIH tCDR CE VCC - 0.2V tR VIL GND SEE NOTE 8 022598 5/9 DS2064 DATA RETENTION CHARACTERISTICS PARAMETER (tA=–40°C to +85°C) SYMBOL CONDITIONS MIN Data Retention Supply Voltage VDR CE1 > VCC – 0.5V 2.0 Data Retention Current at 5.5V ICCR1 CE1 > VCC – 5.0V Data Retention Current at 2.0V ICCR2 CE1 > VCC – 5.0V Chip Deselect to Data Retention tCDR 0 µs tR 2 ms Recovery Time TYP MAX UNITS 5.5 V 0.1* 1 µA 50* 750 nA * Typical values are at 25°C FUNCTION TABLE MODE CE1 READ L WRITE OE WE A0 – A12 DQ – DQ7 POWER H L H STABLE DATA OUT ICCO L H X L STABLE DATA IN ICCO DESELECT L H H H X HIGH–Z ICCO STANDBY H X X X X HIGH–Z ICCS STANDBY X L X X X HIGH–Z ICCS 022598 6/9 CE2 DS2064 NOTES: 1. WE is high for read cycles. 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state. 3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDH and tDS are measured from the earlier of CE or WE going high. 5. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain in a high impedance state. 6. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high impedance state. 7. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state. 8. If the VIH level of CE is 2.0V during the period that VCC voltage is going down from 4.5V to 2.7V, ICCS1 current flows. DC TEST CONDITIONS AC TEST CONDITIONS Outputs Open All voltages are referenced to ground Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0V – 3.0V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5 ns 022598 7/9 DS2064 DS2064 28–PIN DIP PKG DIM MAX A IN. MM 1.440 30.99 1.460 32.00 B IN. MM 0.540 13.72 0.560 14.22 C IN. MM 0.140 3.56 0.160 4.06 D IN. MM 0.590 14.99 0.625 15.88 E IN. MM 0.015 0.380 0.040 1.02 C F IN. MM 0.110 2.79 0.135 3.43 F G IN. MM 0.090 2.29 0.110 2.79 H IN. MM 0.625 15.88 0.675 17.15 J IN. MM 0.008 0.20 0.012 0.30 K IN. MM 0.015 0.38 0.021 0.53 B D 1 A K G J H 022598 8/9 E 28–PIN MIN DS2064 DS2064S 28–PIN SOIC PKG 28–PIN DIM MIN MAX A IN. MM 0.080 2.04 0.120 3.05 A1 IN. MM 0.002 0.05 0.014 0.35 b IN. MM 0.012 0.30 0.020 0.50 C IN MM 0.004 0.10 0.0125 0.32 D IN. MM 0.697 17.70 0.728 18.50 e IN. MM 0.050 BSC 1.27 BSC E1 IN. MM 0.324 8.23 0.350 8.90 H IN MM 0.453 11.5 0.500 12.7 L IN MM 0.016 0.40 0.051 1.30 0° 10° The chamfer on the body is optional. If it is not present, a terminal 1 identifier must be positioned so that 1/2 or more of its area is contained in the hatched zone. 022598 9/9