DALLAS DS2016

DS2016
2k x 8 3V/5V Operation Static RAM
www.dalsemi.com
FEATURES
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Low-power CMOS design
Standby current
− 50 nA max at tA = 25°C VCC = 3.0V
− 100 nA max at tA = 25°C VCC = 5.5V
− 1 µA max at tA = 60°C VCC = 5.5V
Full operation for VCC = 5.5V to 2.7V
Data retention voltage = 5.5V to 2.0V
Fast 5V access time
− DS2016 - 100
100 ns
− DS2016 - 150
150 ns
Reduced-speed 3V access time
− DS2016 - 100
250 ns
− DS2016 - 150
250 ns
Operating temperature range of -40°C to
+85°C
Full static operation
TTL compatible inputs and outputs over
voltage range of 5.5V to 2.7 volts.
Available in 24-pin DIP and 24-pin SOIC
packages
Suitable for both battery operated and battery
backup applications
PIN ASSIGNMENT
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
A8
A9
WE
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DS2016 24-Pin DIP (600-mil)
DS2016R 24-Pin SOIC (300-mil)
PIN DESCRIPTION
A0 - A10
DQ0 - DQ7
CE
WE
OE
VCC
GND
- Address Inputs
- Data Input/Output
- Chip Enable Input
- Write Enable Input
- Output Enable Input
- Power Supply Input 2.7V - 5.5V
- Ground
DESCRIPTION
The DS2016 2k x 8 3V/5V Operation Static RAM is a 16,384-bit, low-power, fully static random access
memory organized as 2048 words by 8 bits using CMOS technology. The device operates from a single
power supply with a voltage input between 2.7 and 5.5 volts. The chip enable input ( CE ) is used for
device selection and can be used in order to achieve the minimum standby current mode, which facilitates
both battery operated and battery backup applications. The device provides access times as fast as 100 ns
when operated from a 5-volt power supply input and also provides relatively good performance of 250 ns
access while operating from a 3-volt input. The device maintains TTL-level inputs and outputs over the
input voltage range of 2.7 to 5.5 volts. The DS2016 is most suitable for low-power applications where
battery operation or battery backup for nonvolatility is required. The DS2016 is a JEDEC-standard 2k x 8
SRAM and is pin-compatible with ROM and EPROM of similar density.
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092399
DS2016
OPERATION MODE
MODE
READ
WRITE
DESELECT
STANDBY
CE
OE
WE
L
L
L
H
L
X
H
X
H
L
H
X
A0-A10
STABLE
STABLE
X
X
DQ-DQ7
DATA OUT
DATA IN
HIGH-Z
HIGH-Z
POWER
ICCO
ICCO
ICCO
ICCS
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
Power Supply Voltage
Input, Input/Output Voltage
Storage Temperature
Operating Temperature
Soldering Temperature/Time
VCC
VIN , VI/O
TSTG
TOPR
TSOLDER
RATING
-0.3V to +7.0V
-0.3 to VCC +0.3V
-55°C to +125°C
-40°C to +85°C
260 °C for 10 seconds
CAPACITANCE
(TA= 25°C)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
CIN
CI/O
MIN
TYP
5
5
MAX
10
12
UNITS
pF
pF
NOTES
+5-VOLT OPERATION
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Power Supply Voltage
Input High Voltage
Input Low Voltage
Data Retention Voltage
SYMBOL
VCC
VIH
VIL
VDR
MIN
4.5
2.0
-0.3
2.0
SYMBOL
IIL
ILO
IOH
IOL
ICCS1
ICCS2
ICCS2
ICCO
(TA= -40°C to +85°C)
MAX
5.5
VCC+0.3
0.8
5.5
UNITS
V
V
V
V
NOTES
(TA= -40°C to +85°C; VCC = 5V ± 10%)
DC CHARACTERISTICS
PARAMETER
Input Leakage Current
I/O Leakage Current
Output High Current
Output Low Current
Standby Current
Standby Current
Standby Current
Operating Current
TYP
5.0
CONDITIONS
0V ≤ VIN ≤ VCC
CE = VIH, 0V ≤ VIO ≤ VCC
VOH = 2.4V
VOL = 0.4V
CE = 2.0V
CE ≥ VCC -0.5V tA =60°C
CE ≥ VCC -0.5V tA =25°C
CE = 0.8V, 200 ns cycle
2 of 9
MIN TYP
MAX
± 0.1
± 0.5
-1.0
4.0
0.3
1
100
55
UNITS
µA
µA
mA
mA
mA
µA
nA
mA
DS2016
(TA= -40°C to +85°C; VCC = 5V ± 10%)
AC CHARACTERISTICS READ CYCLE
PARAMETER
Read Cycle Time
Access Time
OE to Output Valid
CE to Output Valid
CE or OE to Output
Active
Output High-Z from
Deselection
Output Hold from
Address Change
SYMBOL
tRC
tACC
tOE
tCO
tCOE
DS2016-100
DS2016-150
MIN TYP MAX MIN TYP MAX
100
150
100
150
50
70
100
150
5
5
tOD
5
tOH
5
35
Write Cycle Time
Write Pulse Width
Address Setup Time
Write Recovery
Time
Output High-Z from
WE
Output Active from
WE
Data Setup Time
Data Hold Time
60
10
10
10
tODW
ns
ns
ns
ns
ns
ns
ns
DS2016-100
DS2016-150
SYMBOL
MIN TYP MAX MIN TYP MAX
tWC
100
150
tWP
75
120
tAW
0
0
tWR
UNITS
ns
35
70
ns
5
5
ns
tDS
tDH
40
0
60
0
ns
ns
DATA RETENTION CHARACTERISTICS
CONDITIONS
NOTES
ns
ns
ns
tOEW
PARAMETER
SYMBOL
Data Retention Supply
VDR
Voltage
Data Retention
ICCR1
Current at 5.5V
Data Retention
ICCR2
Current at 2.0V
Chip Deselect to Data
tCDR
Retention
Recovery Time
tR
* Typical values are at 25°C
NOTES
(TA= -40°C to +85°C; VCC = 5V ± 10%)
AC CHARACTERISTICS WRITE CYCLE
PARAMETER
10
UNITS
(TA = -40°C to +85°C)
MIN TYP
MAX
UNITS
5.5
V
CE
≥ VCC - 0.5V
CE
≥ VCC - 0.5V
0.1*
1
µA
CE
≥ VCC - 0.5V
50*
750
nA
3 of 9
2.0
0
µs
2
ms
DS2016
+3-VOLT OPERATION
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Power Supply Voltage
Input High Voltage
Input Low Voltage
Data Retention Voltage
SYMBOL
VCC
VIH
VIL
VDR
DC CHARACTERISTICS
PARAMETER
Input Leakage Current
I/O Leakage Current
Output High Current
Output Low Current
Standby Current
Standby Current
Standby Current
Operating Current
MIN
2.7
2.0
-0.3
2.0
TYP
3.0
(TA = -40°C to +85°C)
MAX
3.5
VCC + 0.3
0.6
3.5
UNITS
V
V
V
V
NOTES
(TA = -40°C to +85°C; VCC = 2.7V to 3.5V)
SYMBOL
IIL
ILO
IOH
IOL
ICCS1
ICCS2
ICCS2
ICCO
CONDITIONS
0V ≤ VIN ≤ VCC
CE =VIH, 0V≤VIO≤VCC
VOH = 2.2V
VOL = 0.4V
CE = 2.0V
CE ≥VCC-0.3V TA=60°C
CE ≥VCC-0.3V TA=25°C
CE =0.6V min cycle
MIN TYP
MAX
±0.1
±0.5
-0.5
4.0
0.1
500
50
25
UNITS
µA
µA
mA
mA
mA
nA
nA
mA
AC CHARACTERISTICS READ CYCLE
(TA = -40°C to +85°C; VCC = 2.7V to 3.5V)
PARAMETER
Read Cycle Time
Access Time
OE to Output Valid
CE to Output Valid
CE or OE to Output Active
Output High-Z
from Deselection
Output Hold from
Address Change
SYMBOL
tRC
tACC
tOE
tCO
tCOE
MIN
250
tOD
5
tOH
15
TYP
MAX
250
120
250
15
4 of 9
100
UNITS
ns
ns
ns
ns
ns
ns
ns
NOTES
DS2016
AC CHARACTERISTICS WRITE CYCLE
(TA = -40°C to +85°C; VCC = 2.7V to 3.5V)
PARAMETER
Write Cycle Time
Write Pulse Width
Address Setup Time
Write Recovery Time
Output High-Z from WE
Output Active from WE
Data Setup Time
Data Hold Time
SYMBOL
tWC
tWP
tAW
tWR
tODW
tOEW
tDS
tDH
MIN
250
190
0
25
TYP
MAX
90
5
100
0
DATA RETENTION CHARACTERISTICS
PARAMETER
SYMBOL
Data Retention
VDR
Supply Voltage
Data Retention
ICCR1
Current at 3.5V
Data Retention
ICCR2
Current at 2.0V
Chip Deselect to
tCDR
Data Retention
Recovery Time
tR
* Typical values are at 25°C
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
CONDITIONS
NOTES
(TA = -40°C to +85°C)
MIN TYP
MAX
UNITS
3.5
V
CE
≥ VCC - 0.3V
CE
≥ VCC - 0.3V
50*
1000
nA
CE
≥ VCC - 0.3V
50*
750
nA
TIMING DIAGRAM: READ CYCLE
SEE NOTE 1
5 of 9
2.0
0
µs
2
ms
DS2016
TIMING DIAGRAM: WRITE CYCLE 1
SEE NOTES 2, 3, 4, 5, 6 AND 7
TIMING DIAGRAM: WRITE CYCLE 2
SEE NOTES 2, 3, 4, 5, 6 AND 7
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DS2016
TIMING DIAGRAM: DATA RETENTION - POWER-UP, POWER-DOWN Figure 1
SEE NOTE 8
NOTES:
1.
WE is
high for read cycles.
2.
OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance
state.
3.
tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4.
tDH and tDS are measured from the earlier of CE or WE going high.
5.
If the CE low transition occurs simultaneously with or later than the WE low transition, the
output buffers remain in a high impedance state.
6.
If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high impedance state.
7.
If WE is low or the WE low transition occurs prior to or simultaneously with the CE low
transition, the output buffers remain in a high impedance state.
8.
If the VIH level of CE is 2.0V during the period that VCC voltage is going down from 4.5V to
2.7V, ICCS1 current flows.
9.
The DS2016 maintains full operation from 5.5V to 2.7V. The electrical characteristics tables show
two tested and guaranteed points of operation. For operation between 4.5V and 3.5 volts, use the
composite worst case characteristics from both 5V and 3V operation for design purposes.
DC TEST CONDITIONS
Outputs Open
All voltages are referenced to ground.
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0V - 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5 ns
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DS2016
DS2016 24-PIN DIP
PKG
DIM
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
8 of 9
24-PIN
MIN
MAX
1.245
1.270
31.62
32.25
0.530
0.550
13.46
13.97
0.140
0.160
3.56
4.06
0.600
0.625
15.24
15.88
0.015
0.050
0.380
1.27
0.120
0.145
3.05
3.68
0.090
0.110
2.29
2.79
0.625
0.675
15.88
17.15
0.008
0.012
0.20
0.30
0.015
0.022
0.38
0.56
DS2016
DS2016S 24-PIN SOIC
PKG
DIM
A IN.
MM
A1 IN.
MM
b IN.
MM
C IN.
MM
D IN.
MM
e IN.
MM
E1 IN.
MM
H IN.
MM
L IN.
MM
α
The chamfer on the body is optional. If it is not present, a
terminal 1 identifier must be positioned so that ½ or more of its
area is contained in the hatched zone.
9 of 9
24-PIN
MIN
MAX
0.094
0.105
2.38
2.68
0.004
0.012
0.102
0.30
0.013
0.020
0.33
0.51
0.009
0.013
0.229
0.33
0.598
0.612
15.19
15.54
0.050 BSC
1.27 BSC
0.290
0.300
7.37
7.62
0.398
0.416
10.11
10.57
0.016
0.040
0.40
1.02
0°
8°