DS2175 T1/CEPT Elastic Store www.dalsemi.com FEATURES • • • • • • • • PIN ASSIGNMENT Rate buffer for T1 and CEPT transmission systems Synchronizes loop–timed and system timed data streams on frame boundaries Ideal for T1 (1.544 MHz) to CEPT (2.048 MHz), CEPT to T1 interfaces Supports parallel and serial backplanes Buffer depth is 2 frames Comprehensive on–chip “slip” control logic – Slips occur only on frame boundaries – Outputs report slip occurrences and direction – Align feature allows buffer to be recentered at any time – Buffer depth easily monitored Compatible with DS2180A T1 and DS2181A CEPT Transceivers Industrial temperature range of –40°C to +85°C available, designated DS2175N RCLKSEL 1 16 VDD RCLK 2 15 SYSCLK RSER 3 14 SSER RMSYNC 4 13 SMSYNC FSD 5 12 SFSYNC SLIP 6 11 SCHCLK ALN VSS 7 10 8 9 S/P SCLKSEL 16-PIN DIP (300 MIL) 16-PIN SOIC (300 MIL) DESCRIPTION The DS2175 is a low–power CMOS elastic–store memory optimized for use in primary rate telecommunications transmission equipment. The device serves as a synchronizing element between async data streams and is compatible with North American (T1–1.544 MHz) and European (CEPT–2.048 MHz) rate networks. The chip has several flexible operating modes which eliminate support logic and hardware currently required to interconnect parallel or serial TDM backplanes. Application areas include digital trunks, drop and insert equipment, digital cross–connects (DACS), private network equipment and PABX–to–computer interfaces such as DMI and CPI. 1 of 12 092099 DS2175 DS2175 BLOCK DIAGRAM Figure 1 2 of 12 DS2175 PIN Description Table 1 PIN 1 SYMBOL RCLKSEL TYPE I 2 3 4 RCLK RSER RMSYNC I I I 5 FSD O 6 SLIP O 7 ALN I 8 9 VSS SCLKSEL – I 10 S/ P I 11 SCHCLK O 12 SFSYNC I 13 SMSYNC O 14 15 16 SSER SYSCLK VDD O I – DESCRIPTION Receive Clock Select. Tie to VSS for 1.544 MHz applications, to VDD for 2.048 MHz. Receive Clock. 1.544 or 2.048 MHz data clock. Receive Serial Data. Sampled on falling edge of RCLK. Receive Multifram Sync. Rising edge establishes receive side frame and multiframe boundaries. Frame Slip Directions. State indicates direction of last slip; latched on slip occurrence. Frame Slip. Active low, open collector output. Held low for 65 SYSCLK cycles when a slip occurs. Align. Recenters buffer on next system side frame boundary when forced low; negative edge-triggered. Signal Ground. 0.0 volts. System Clock Select. Tie to VSS for 1.544 MHz applications, to VDD for 2.048 MHz. Serial/Parallel Select. Tie to VSS for parallel backplane applications, to VDD for serial. System Channel Clock. Transitions high on channel boundaries; useful for serial to parallel conversion of channel data. System Frame Sync. Rising edge establishes system side frame boundaries. System Multiframe Sync. Slip-compensated multiframe output; used with RMSYNC to monitor depth of store real time. System Serial Data. Updated on rising edge of SYSCLK. System Clock. 1.544 or 2.048 MHz data clock. Positive Supply. 5.0 volts. PCM BUFFER The DS2175 utilizes a 2–frame buffer to synchronize in-coming PCM data to the system backplane clock. Buffer depth is mode–dependent; 2.048 MHz to 2.048 MHz applications utilize 64 bytes of buffer memory, while all other modes are supported by 48 bytes. The buffer samples data at RSER on the falling edge of RCLK. Output data appears at SSER and is updated on the rising edge of SYSCLK. The buffer depth is constantly monitored by onboard contention logic; a “slip” occurs when the buffer is completely emptied or filled. Slips automatically recenter the buffer to a one–frame depth and always occur on frame boundaries. DATA FORMAT Data is presented to, and output from, the elastic store in a “framed” format. A rising edge at RMSYNC and SFSYNC establishes frame boundaries for the receive and system sides. North American (T1) frames contain 24 data channels of 8 bits each and an F–bit (193 bits total). European (CEPT) frames contain 32 data channels (256 bits). The frame rate of both systems is 8 KHz. RMSYNC and SFSYNC do not require a pulse at every frame boundary; if desired, they may be pulsed once to establish frame alignment. Internal counters will then maintain the frame alignment and may be reinforced by the next rising edge at RMSYNC and/or SFSYNC. 3 of 12 DS2175 SLIP CORRECTION CAPABILITY The 2–frame buffer depth is adequate for T–carrier and CEPT applications where short term jitter synchronization, rather than correction of significant frequency differences, is required. The DS2175 provides an ideal balance between total delay (less than 250 microse-conds at its full depth) and slip correction capability. BUFFER RECENTERING Many applications require that the buffer be recentered during system power–up and/or initialization. Forcing ALN low recenters the buffer on the occurrence of the next frame sync boundary. A slip will occur during this recentering if the buffer depth is adjusted. If the depth is presently optimum, no adjustment (slip) occurs. SLIP REPORTING SLIP is held low for 65 SYSCLK cycles when a slip occurs. SLIP is an active–low, open collector output. FSD indicates slip direction. When low (buffer empty) a frame of data was “repeated” at SSER during the previous slip. When high (buffer full), a frame of data was “deleted”. FSD is updated at every slip occurrence. BUFFER DEPTH MONITORING SMSYNC is a system side output pulse which indicates system side multiframe boundaries. The distance between rising edges of RMSYNC and SMSYNC indicates the current buffer depth. Impending slip conditions may be determined by monitoring RMSYNC and SMSYNC real time. SMSYNC is held high for 65 SYSCLK periods. CLOCK SELECT Receive and system side clock frequencies are independently selectable by inputs RCLKSEL and SCLKSEL. 1.544 MHz is selected when RCLKSEL (SCLKSEL) = 0; 2.048 MHz is selected when RCLKSEL (SCLKSEL) = 1. In 1.544 MHz (receive) to 1.544 MHz (system) applications, the F-bit position is passed through the receive buffer and presented at SSER immediately after the rising edge of the system side frame sync. The F–bit position is forced to 1 in 2.048 MHz to 1.544 MHz applications. No F–bit position exists in 2.048 MHz system side applications. PARALLEL COMPATIBILITY The DS2175 is compatible with parallel and serial backplanes. Channel 1 data appears at SSER after a rising edge at SFSYNC (serial applications, S/ P = 1). The device utilizes a look–ahead circuit in parallel applications (S/ P = 0), and presents data 8 clocks early as shown in Figures 4 and 5. Converting SSER to a parallel format requires an HC595 shift register. 4 of 12 DS2175 RECEIVE SIDE TIMING (RCLK = 1.544 MHz) Figure 2 RECEIVE SIDE TIMING (RCLK = 2.048 MHz) Figure 3 NOTES: 1. All channel data is passed through the elastic store in 2.048 MHz system side applications (SCLKSEL = 1); 2. Data in channels >24 is ignored in 1.544 MHz system side applications (SCLKSEL = 0). SYSTEM MULTIFRAME BOUNDARY TIMING (SYSCLK = 1.544 MHz) Figure 4 NOTES: 1. In 1.544 MHz receive side applications (RCLKSEL=0), the F–bit position contains F–bit data extracted from the data stream at RSER. The F–bit position is forced to “1” in 2.048 MHz receive side applications (RCLKSEL=1). 2. In 2.048 MHz receive side applications (RCLKSEL=1), the E–bit position is forced to “1” and data in channels >24 is ignored. 5 of 12 DS2175 SYSTEM MULTIFRAME BOUNDARY TIMING (SYSCLK = 2.048 MHz) Figure 5 NOTES: 1. In 2.048 MHz receive side applications (RCLKSEL=1), all channel data is passed through the elastic store. 2. In 1.544 MHz receive side applications (RCLKSEL=0), all channel data is passed through the elastic store, except the F–bit position which is ignored. Data in channels >24 on the system side is forced to all ones. ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature –1.0V to +7.0V 0°C to 70°C –55°C to +125°C 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. 6 of 12 DS2175 RECOMMENDED DC OPERATING CONDITIONS PARAMETER Logic 1 Logic 0 Supply SYMBOL VIH VIL VDD MIN 2.0 -0.3 4.5 TYP (0°C TO 70°C) MAX VDD+0.3 +0.8 5.5 UNITS V V V CAPACITANCE PARAMETER Input Capacitance Output Capacitance (tA=25°C) SYMBOL CIN COUT MIN TYP DC ELECTRICAL CHARACTERISTICS PARAMETER Supply Current Input Leakage Output Current @ 2.4V Output Current @ 0.4V SYMBOL IDD IIL IOH IOL MIN -1.0 -1.0 +4.0 NOTES: 1. 2. 3. 4. NOTES SYSCLK = RCLK = 2.048 MHz Outputs open All outputs except SLIP , which is open collector All outputs 7 of 12 MAX 5 7 UNITS PF PF NOTES (0°C TO 70°C; VDD=5V±10%) TYP 9 MAX 16 +1.0 UNITS mA µA mA mA NOTES 1,2 3 4 DS2175 AC ELECTRICAL CHARACTERISTICS PARAMETER RCLK Period RCLK, SYSCLK Rise and Fall Times RCLK Pulse Width SYSCLK Pulse Width SYSCLK Period RMSYNC Setup to RCLK Falling SFSYNC Setup to SYSCLK Falling RMSYNC, SFSYNC, ALN Pulse Width RSER Setup from RCLK Falling RSER Hold from RCLK Falling Propagation Delay SYSCLK to SSER Propagation Delay SYSCLK to SMSYNC High Propagation Delay SYSCLK or RCLK to SLIP Low, FSD Low/High ALN Setup to SFSYNC Rising (0°C TO 70°C; VDD=5V±10%) SYMBOL tRCLK tR, tF MIN 200 TYP MAX tRWH, tRWL tSWH, tSWL 100 ns 100 ns tSYSCLK tSC 200 20 tRWH-5 ns ns tSC 20 tSWH-5 ns tPW 50 ns tSD 50 ns tHD 50 ns 20 UNITS ns ns tPVD 75 ns tPSS 75 ns tPS 100 ns tSR 500 NOTES: 1. Measured at VIH =2.0V, VIL –0.8V, and 10 ns maximum rise and fall times. 2. Output load capacitance = 100 pF. 8 of 12 ns NOTES DS2175 RECEIVE AC TIMING DIAGRAM Figure 6 SYSTEM AC TIMING DIAGRAM Figure 7 9 of 12 DS2175 DS2175 T1/CEPT ELASTIC STORE PKG 10 of 12 16-PIN DIM MIN MAX A IN. 0.740 0.780 B IN. 0.240 0.260 C IN. 0.120 0.140 D IN. 0.300 0.325 E IN. 0.015 0.040 F IN. 0.120 0.140 G IN. 0.090 0.110 H IN. 0.290 0.420 J IN. 0.008 0.012 K IN. 0.015 0.021 DS2175 DS2175S T1/CEPT ELASTIC STORE PKG DIM MIN MAX A IN. 0.402 0.412 B IN. 0.290 0.300 C IN. 0.089 0.095 E IN. 0.004 0.012 F IN. 0.094 0.105 G IN. 11 of 12 16-PIN 0.050 BSC H IN. 0.398 0.416 J IN. 0.009 0.013 K IN. 0.013 0.019 L IN. 0.016 0.040 DS2175 DATA SHEET REVISION SUMMARY The following represent the key differences between 04/19/95 and 06/13/97 version of the DS2175 data sheet. Please review this summary carefully. 1. SYNC/CLOCK Relationship in timing diagram 12 of 12