DALLAS DS2180A

DS2180A
T1 Transceiver
www.dalsemi.com
FEATURES
1
40
VDD
TFSYNC
2
39
RLOS
TCLK
3
38
RFER
TCHCLK
4
37
RBV
TSER
5
36
RCL
TMO
6
35
RNEG
TSIGSEL
7
34
RPOS
TSIGFR
8
33
RST
TABCD
9
32
TEST
TLINK
10
31
RSIGSEL
TLCLK
11
30
RSIGFR
TPOS
12
29
RABCD
TNEG
13
28
RMSYNC
INT
14
27
RFSYNC
SDI
15
26
RSER
SDO
16
25
RCHCLK
CS
17
24
RCLK
SCLK
18
23
RLCLK
SPS
19
22
RLINK
VSS
20
21
RYEL
40-Pin DIP (600-mil)
TSER
TMO
TSIGSEL
TSIGFR
TABCD
TLINK
TLCLK
TPOS
TNEG
INT
SDI
5
4
3
2
1
44
43
42
41
TMSYNC
NC
TCHCLK
TCLK
NC
TFSYNC
TMSYNC
VDD
RLOS
RFER
RBV
RCL
PIN ASSIGNMENT
7
8
9
10
11
12
13
14
15
16
17
19
20
21
22
23
24
25
26
27
Single chip DS1 rate transceiver
Supports common framing standards
– 12 frames/superframe “193S”
– 24 frames/superframe “193E”
Three zero suppression modes
– B7 stuffing
– B8ZS
– Transparent
Simple serial interface used for configuration, control and status monitoring in
“processor” mode
=“Hardware” mode requires no host
processor; intended for stand-alone applications
Selectable 0, 2, 4, 16 state robbed bit
signaling modes
Allows mix of “clear” and “non-clear” DS0
channels on same DS1 link
Alarm generation and detection
Receive error detection and counting for
transmission performance monitoring
5V supply, low-power CMOS technology
Surface-mount package available, designated
DS2180AQ
Industrial temperature range of -40°C to
+85°C available, designated DS2180AN or
DS2180AQN
Compatible to DS2186 Transmit Line
Interface, DS2187 Receive Line Interface,
DS2188 Jitter Attenuator, DS2175 T1/CEPT
Elastic Store, DS2290 T1 Isolation Stik, and
DS2291 T1 Long Loop Stik
39
38
37
36
35
34
33
32
31
30
29
RNEG
RPOS
RST
TEST
RSIGSEL
RSIGFR
RABCD
RMSYNC
RFSYNC
RSER
RCHCLK
SDO
CS
SCLK
SPS
VSS
RYEL
RLINK
NC
RLCLK
RCLK
NC
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112099
DS1386/DS1386P
DESCRIPTION
The DS2180A is a monolithic CMOS device designed to implement primary rate (1.544 MHz) T-carrier
transmission systems. The 193S framing mode is intended to support existing Ft/Fs applications (12
frames/superframe).
The 193E framing mode supports the extended superframe format (24
frames/superframe). Clear channel capability is provided by selection of appropriate zero suppression
and signaling modes.
Several functional blocks exist in the transceiver. The transmit framer/formatter generates appropriate
framing bits, inserts robbed bit signaling, supervises zero suppression, generates alarms, and provides
output clocks useful for data conditioning and decoding. The receive synchronizer establishes frame and
multi-frame boundaries by identifying frame signaling bits, extracts signaling data, reports alarms and
transmission errors, and provides output clocks useful for data conditioning and decoding.
The control block is shared between transmit and receive sides. This block determines the frame, zero
suppression, alarm and signaling formats. User access to the control block is by one of two modes.
In the processor mode, pins 14 through 18 are a micro-processor/ microcontroller-compatible serial port
which can be used for device configuration, control and status monitoring.
In the hardware mode, no offboard processor is required. Pins 14 through 18 are reconfigured into “hardwired” select pins. Features such as selection “clear” DS0 channels, insertion of idle code and alteration
of sync algorithm are unavailable in the hardware mode.
DS2180A BLOCK DIAGRAM Figure 1
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DS2180A
TRANSMIT PIN DESCRIPTION (40-PIN DIP ONLY) Table 1
PIN
1
SYMBOL
TMSYNC
TYPE
I
2
TFSYNC
I
3
4
TCLK
TCHCLK
I
O
5
6
TSER
TMO
I
O
7
TSIGSEL
O
8
9
TSIGFR
TABCD
O
I
10
TLINK
I
11
12
13
TLCLK
TPOS
TNEG
O
O
DESCRIPTION
Transmit Multiframe Sync. May be pulsed high at multiframe boundaries to
reinforce multiframe alignment or tied low, which allows internal multiframe
counter to free run.
Transmit Frame Sync. Rising edge identifies frame boundary; may be pulsed
every frame to reinforce internal frame counter or tied low (allowing TMSYNC to
establish frame and multiframe alignment).
Transmit Clock. 1.544 MHz primary clock.
Transmit Channel Clock. 192 kHz clock which identifies time slot (channel)
boundaries. Useful for parallel-to-serial conversion of channel data.
Transmit Serial Data. NRZ data input, sample on falling edge of TCLK.
Transmit Multiframe Out. Output of internal multiframe counter indicates
multiframe boundaries. 50% duty cycle.
Transmit Signaling Select. .667 kHz clock which identifies signaling frame A and
C in 193E framing. 1.33 kHz clock in 193S.
Transmit Signaling Frame. High during signaling frames, low otherwise.
Transmit ABCD Signaling. When enabled via TCR.4, sampled during channel
LSB time in signaling frames on falling edge of TCLK.
Transmit Link Data. Sampled during the F-bit time (falling edge of TCLK) of odd
frames for insertion into the outgoing data stream (193E-FDL insertion). Sampled
during the F-bit time of even frames for insertion into the outgoing data (193SExternal S-Bit insertion).
Transmit Link Clock. 4 kHz demand clock for TLINK input.
Transmit Bipolar Data Outputs. Updated on rising edge of TCLK.
PORT PIN DESCRIPTION (40-PIN DIP ONLY) Table 2
PIN
14
SYMBOL
15
16
SDI1
SDO1
17
18
19
INT
1
CS 1
SCLK1
SPS
TYPE
O
I
O
DESCRIPTION
Receive Alarm Interrupt. Flags host controller during alarm conditions. Active
low, open drain output.
Serial Data In. Data for onboard registers. Sampled on rising edge of SCLK.
Serial Data Out. Control and status information from onboard registers. Updated
I
on falling edge of SCLK, tri-stated during serial port write or when CS is high.
Chip Select. Must be low to write or read the serial port registers.
I
I
Serial Data Clock. Used to write or read the serial port registers.
Serial Port Select. Tie to VDD to select serial port. Tie to VSS to select hardware
mode.
NOTE:
1. Multifunction pins. See “Hardware Mode Description."
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DS2180A
POWER AND TEST PIN DESCRIPTION (40-PIN DIP ONLY) Table 3
PIN
20
32
40
SYMBOL
VSS
TEST
VDD
TYPE
I
-
DESCRIPTION
Signal Ground. 0.0 volts.
Test Mode. Tie to VSS for normal operation.
Positive Supply. 5.0 volts.
RECEIVE PIN DESCRIPTION (40-PIN DIP ONLY) Table 4
PIN
21
SYMBOL
RYEL
TYPE
0
22
RLINK
0
23
24
25
26
27
RLCLK
RCLK
RCHCLK
RSER
RFSYNC
0
I
O
O
O
28
RMSYNC
O
29
RABCD
O
30
RSIGFR
O
31
RSIGSEL
O
33
RST
I
34
35
36
RPOS
RNEG
RCL
I
O
37
RBV
O
38
RFER
O
39
RLOS
O
DESCRIPTION
Receive Yellow Alarm. Transitions high when yellow alarm detected, goes low
when alarm clears.
Receive Link Data. Updated with extracted FDL data one RCLK before start of
odd frames (193E) and held until next update. Updated with extracted S-bit data one
RCLK before start of even frames (193S) and held until next update.
Receive Link Clock. 4 kHz demand clock for RLINK.
Receive Clock. 1.544 MHz primary clock.
Receive Channel Clock. 192 kHz clock identifies time slot (channel) boundaries.
Receive Serial Data. Received NRZ serial data, updated on rising edges of RCLK.
Receive Frame Sync. Extracted 8 kHz clock, one RCLK wide, indicates F-Bit
position in each frame.
Receive Multiframe Sync. Extracted multiframe sync; edge indicates start of
multiframe, 50% duty cycle.
Receive ABCD Signaling. Extracted signaling data output, valid for each channel
time in signaling frames. In non-signaling frames, RABCD outputs the LSB of each
channel word.
Receive Signaling Frame. High during signaling frames, low during resync and
non-signaling frames.
Receive Signaling Select. In 193E framing a .667 kHz clock which identifies
signaling frames A and C. A 1.33 kHz clock in 193S.
Reset. A high-low transition clears all internal registers and resets receive side
counters. A high-low-high transition will initiate a receive resync.
Receive Bipolar Data Inputs. Samples on falling edge of RCLK. Tie together to
receive NRZ data and disable bipolar violation monitoring circuitry.
Receive Carrier Loss. High if 32 consecutive 0's appear at RPOS and RNEG; goes
low after next 1.
Receive Bipolar Violation. High during accused bit time at RSER if bipolar
violation detected, low otherwise.
Receive Frame Error. High during F-Bit time when FT or FS errors occur (193S)
or when FPS or CRC errors occur (193E). Low during resync.
Receive Loss of Sync. Indicates sync status; high when internal resync is in
progress, low otherwise.
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DS2180A
REGISTER SUMMARY Table 5
REGISTER
RSR
RIMR
ADDRESS
0000
0001
T/R1
R2
R
BVCR
0010
R
ECR
0011
R
CCR3
0100
T/R
RCR3
0101
R
TCR3
TIR1
TIR2
TIR3
TTR1
TTR2
TTR3
RMR1
RMR2
RMR3
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
T
T
T
T
T
T
T
R
R
R
DESCRIPTION/FUNCTION
Receive Status Register. Reports all receive alarm conditions.
Receive Interrupt Mask Register. Allows masking of individual alarmgenerated interrupts.
Bipolar Violation Count Register. 8-bit presettable counter which records
individual bipolar violations.
Error Count Register. Two independent 4-bit counters which record OOF
occurrences and individual frame bit or CRC errors.
Common Control Register. Selects device operating characteristics common
to receive and transmit sides.
Receive Control Register. Programs device operating characteristics
unique to the receive side.
Transmit Control Register. Selects additional transmit side modes.
Transmit Idle Registers. Designate which outgoing channels are to be
substituted with idle code.
Transmit Transparent Registers. Designate which outgoing channels are to be
treated transparently. (No robbed bit signaling or bit 7 zero insertion.)
Receive Mark Registers. Designate which incoming channels are to be replaced
with idle or digital milliwatt codes (under control of RCR).
NOTES:
1. Transmit or receive side register.
2. RSR is a read only register; all other registers are read/write.
3. Reserved bit locations in the control registers should be programmed to 0 to maintain compatibility
with future transceiver products.
SERIAL PORT INTERFACE
Pins 14 through 18 of the DS2180A serve as a microprocessor/microcontroller-compatible serial port.
Sixteen onboard registers allow the user to update operational characteristics and monitor device status
via host controller, minimizing hardware interfaces. Port read/write timing is unrelated to the system
transmit and receive timing, allowing asynchronous reads and/or writes by the host.
ADDRESS/COMMAND
Reading or writing the control, configuration or status registers requires writing one address command
byte prior to transferring register data. The first bit written (LSB) of the address/command word specifies
register read or write. The following 4-bit nibble identifies register address. The next two bits are
reserved and must be set to 0 for proper operation. The last bit of the address/ command word enables
burst mode when set; the burst mode causes all registers to be consecutively written or read. Data is
written to and read from the transceiver LSB first.
CHIP SELECT AND CLOCK CONTROL
All data transfers are initiated by driving the CS input low. Input data is latched on the rising edge of
SCLK and must be valid during the previous low period of SCLK to prevent momentary corruption of
register data during writes. Data is output on the falling edge of SCLK and held on the next falling edge.
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DS2180A
All data transfers are terminated if the CS input transitions high. Port control logic is disabled and SDO is
tri-stated when CS is high.
DATA I/O
Following the eight SCLK cycles that input an address/ command byte to write, a data byte is strobed into
the addressed register on the rising edges of the next eight SCLK cycles. Following an address/command
word to read, contents of the selected register are output on the falling edges of the next eight SCLK
cycles. The SDO pin is tri-stated during device write and may be tied to SDI in applications where the
host processor has a bi-directional I/O pin.
BURST MODE
The burst mode allows all onboard registers to be consecutively read and written by the host processor. A
burst read is used to poll all registers; RSR contents will be unaffected. This feature minimizes device
initialization time on power-up or system reset. Burst mode is initiated when ACB.7 is set and the address
nibble is 0000. Burst is terminated by a low-high transition on CS .
ACB: ADDRESS COMMAND BYTE Figure 2
(MSB)
BM
(LSB)
-
-
SYMBOL
POSITION
BM
ACB.7
ADD3
ADD0
R/ W
ACB.6
ACB.5
ACB.4
ACB.1
ACB.0
ADD3
ADD2
ADD1
AD0
R/ W
NAME AND DESCRIPTION
Burst Mode. If set (and ACB.1 through ACB.4=0) burst read or
write is enabled.
Reserved, must be 0 for proper operation.
Reserved, must be 0 for proper operation.
MSB of register address.
LSB of register address.
Read/Write Select.
0 = write addressed register.
1 = read addressed register.
SERIAL PORT READ/WRITE Figure 3
NOTES:
1. SDI sampled on rising edge of SCLK.
2. SDO updated on falling edge of SCLK.
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DS2180A
ACB: ADDRESS COMMAND BYTE Figure 4
(MSB)
-
(LSB)
FRSR2
EYELMD
SYMBOL
POSITION
FRSR2
CCR.7
CCR.6
EYELMD
CCR.5
FM
CCR.4
SYELMD
CCR.3
B8ZS
CCR.2
B7
CCR.1
LPBK
CCR.0
FM
SYELMD
B8ZS
B7
LPBK
NAME AND DESCRIPTION
Reserved, must be 0 for proper operation.
Function of REC Status Register 2.
0 = Detected B8ZS code words reported at RSR.2.
1 = COFA (Change-of-Frame Alignment) reported at RSR.2 when
last resync resulted in change of frame or multiframe alignment.
193E Yellow Mode Select.
0 = Yellow alarm is a repeating pattern set of 00 hex and FF hex.
1 = Yellow alarm is a 0 in the bit 2 position of all channels.
Frame Mode Select.
0 = D4 (193S, 12 frames/superframe).
1 = Extended (193E, 24 frames/superframe).
193S Yellow Mode Select. Determines yellow alarm type to be
transmitted and detected while in 193S framing. If set, yellow
alarms are a 1 in the S-bit position of frame 12; if cleared, yellow
alarm is a 0 in bit 2 of all channels. Does not affect 193E yellow
alarm operation.
Bipolar eight zero substitution.
0 = No B8ZS.
1 = B8ZS enabled.
(Note: This bit must be set to 0 when CCR.1=1)
Bit seven zero suppression. If CCR.1=1, channels with an all zero
content will be transmitted with bit 7 forced to 1. If CCR.1=0, no
bit 7 stuffing occurs.
(Note: This bit must be set to 0 when CCR.2=1)
Loopback. When set, the device internally loops output transmit
data into the incoming receive data buffers and TCLK is internally
substituted for RCLK.
LOOPBACK (Refer to Figure 4)
Enabling loopback will typically induce an out-of-frame (OOF) condition. If appropriate bits are set in
the receive control register, the receiver will resync to the looped transmit frame alignment. During the
looped condition, the transmit outputs (TPOS, TNEG) will transmit unframed all 1's. All operating modes
(B8ZS, alarm, signaling, etc.) except for blue alarm transmission are available in loopback.
BIT SEVEN STUFFING
Existing systems meet 1's density requirements by forcing bit 7 of all zero channels to 1. Bit 7 stuffing is
globally enabled by asserting bit CCR.1 and may be disabled on an individual channel basis by setting
appropriate bits in TTR1–TTR3. Bit 7 stuffing and B8ZS modes should not be enabled simultaneously.
Enabling both results in LOS.
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DS2180A
B8ZS
The DS2180A supports existing and emerging zero suppression formats. Selection of B8ZS coding
maintains system 1’s density requirements without disturbing data integrity as required in emerging clear
channel applications. B8ZS coding replaces eight consecutive outgoing 0's with a B8ZS code word. Any
received B8ZS code word is replaced with all 0’s. B8ZS and bit 7 stuffing modes should not be enabled
simultaneously. Enabling both results in LOS.
TCR: TRANSMIT CONTROL REGISTER Figure 5
(MSB)
ODF
TFPT
TCP
SYMBOL
POSITION
ODF
TCR.7
TFPT
TCR.6
TCP
TCR.5
RBSE
TCR.4
TIS
TCR.3
193SI
TCR.2
TBL
TCR.1
TYEL
TCR.0
RBSE
TIS
(LSB)
193SI
TBL
TYEL
NAME AND DESCRIPTION
Output Data Format.
0 = Bipolar data at TPOS and TNEG.
1 = NRZ data at TPOS; TNEG=0.
Transmit Framing Pass-through.
0 = FT/FPS sourced internally.
1 = FT/FPS sampled at TSER during F-bit time.
Transmit CRC Pass-through.
0 = Transmit CRC code internally generated.
1 = TSER sampled at CRC F-bit time for external CRC insertion.
Robbed Bit Signaling Enable.
1 = Signaling inserted in all channels during signaling frames.
0 = No signaling inserted. (The TTR registers allow the user to
disable signaling insertion on selected DS0 channels.)
Transmit Idle Code Select. Determines idle code format to be
inserted into channels marked by the TIR registers.
0 = Insert 7F (Hex) into marked channels.
1 = Insert FF (Hex) into marked channels.
193S S-bit Insertion. Determines source of transmitted S-bit.
0 = Internal S-bit generator.
1 = External (sampled at TLINK input).
Transmit Blue Alarm.
0 = Disabled.
1 = Enabled.
TYEL TCR.0 Transmit Yellow Alarm.
0 = Disabled.
1 = Enabled.
TRANSMIT BLUE ALARM
The blue alarm (also known as the AIS, Alarm Indication Signal) is an unframed, all 1’s sequence
enabled by asserting TCR.1. Blue alarm overrides all other transmit data patterns and is disabled by
clearing TCR.1. Use of the TIR registers allows a framed, all 1’s alarm transmission if required by the
network.
TRANSMIT YELLOW ALARM
In 193E framing, a yellow alarm is a repeating pattern set of FF(Hex) and 00 (Hex) on the 4 kHz facility
data link (FDL). In 193S framing the yellow alarm format is dependent on the state of bit CCR.3. In all
modes, yellow alarm is enabled by asserting TCR.0 and disabled by clearing TCR.0.
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DS2180A
TRANSMIT SIGNALING
When enabled (via TCR.4) channel signaling is inserted in frames 6 and 12 (193S) or in frames 6, 12, 18
and 24 (193E) in the 8th bit position of every channel word. Signaling data is sampled at TABCD on the
falling edge of TCLK during bit 8 of each input word during signaling frames. Logical combination of
clocks TMO, TSIGFR and TSIGSEL allows external multiplexing of separate serial links for A, B or A,
B, C, D signaling sources.
TTR1–TTR3: TRANSMIT TRANSPARENCY REGISTERS Figure 6
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TIR1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TIR2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TIR3
SYMBOL
POSITION
CH24
CH1
TTR3.7
TTR1.0
NAME AND DESCRIPTION
Transmit Transparent Registers. Each of these bit positions
represents a DS0 channel in the outgoing frame. When set, the
corresponding channel is transparent.
TIR1–TIR3: TRANSMIT IDLE REGISTERS Figure 7
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TIR1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TIR2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TIR3
SYMBOL
POSITION
CH24
CH1
TIR3.7
TIR1.0
NAME AND DESCRIPTION
Transmit Idle Registers. Each of these bit positions represents a
DS0 channel in the outgoing frame. When set, the corresponding
channel will output an idle code format determined by TCR.2.
TRANSMIT CHANNEL TRANSPARENCY
Individual DS0 channels in the T1 frame may be programmed clear (no inserted robbed bit signaling and
no bit 7 zero suppression) by setting the appropriate bits in the transmit transparency registers. Channel
transparency is required in mixed voice/data or data-only environments such as ISDN, where data
integrity must be maintained.
TRANSMIT IDLE CODE INSERTION
Individual outgoing channels in the frame can be programmed with idle code by asserting the appropriate
bits in the transmit idle registers. One of two idle code formats, 7F (Hex) and FF (Hex) may be selected
by the user via TCR.3. If enabled, robbed bit signaling data is inserted into the idle channel, unless the
appropriate TTR bit is set for that channel. This feature eliminates external hardware currently required to
intercept and stuff unoccupied channels in the DS1 bit stream.
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DS2180A
TRANSMIT INSERTION HIERARCHY Figure 8
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DS2180A
193S TRANSMIT MULTIFRAME TIMING Figure 9
NOTES:
1. Transmit frame and multiframe timing may be established in one of four ways:
a. With TFSYNC tied low, TMSYNC may be pulsed high once every multiframe period to establish
multiframe boundaries, allowing internal counters to determine frame timing.
b. TFSYNC may be pulsed every 125 microseconds; pulsing TMSYNC once establishes multiframe
boundaries.
c. TMSYNC and TFSYNC may be continuously pulsed to establish and reinforce frame and
superframe timing.
d. If TMSYNC is tied low and TFSYNC is pulsed at frame boundaries, the transmitter will establish
an arbitrary multiframe boundary as indicated by TMO.
2. Channels in which robbed bit signaling is enabled will sample TABCD during the LSB bit time in
frames indicated.
3. When external S-bit insertion is enabled, TLINK will be sampled during the F-bit time of even frames
and inserted into the outgoing data stream.
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DS2180A
193E TRANSMIT MULTIFRAME TIMING Figure 10
NOTES:
1. Transmit frame and multiframe timing may be established in one of four ways:
a. With TFSYNC tied low, TMSYNC may be pulsed high once every multiframe period to establish
multiframe boundaries, allowing internal counters to determine frame timing.
b. TFSYNC may be pulsed every 125 microseconds; pulsing TMSYNC once establishes multiframe
boundaries.
c. TMSYNC and TFSYNC may be continuously pulsed to establish and reinforce frame and
superframe timing.
d. If TMSYNC is tied low and TFSYNC is pulsed at frame boundaries, the transmitter will establish
an arbitrary multiframe boundary as indicated by TMO.
2. Channels in which robbed bit signaling is enabled will sample TABCD during the LSB bit time in
frames indicated.
3. TLINK is sampled during the F-bit time of odd frames and inserted into the outgoing data stream
(FDL data).
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DS2180A
TRANSMIT MULTIFRAME BOUNDARY TIMING Figure 11
NOTES:
1. TLINK timing shown is for 193E framing; in 193E framing, TLINK is sampled as indicated for
insertion into F-bit position of odd frames. When S-bit insertion is enabled in 193S, TLINK is
sampled during even frames.
2. If TCR.5=1, TSER is sampled during the F-bit time of CRC frames for insertion into the outgoing
data stream (193E framing only).
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DS2180A
RECEIVE CONTROL REGISTER Figure 12
(MSB)
ARC
OOF
RCI
SYMBOL
POSITION
ARC
RCR.7
OOF
RCR.6
RCI
RCR.5
RCS
RCR.4
SYNCC
RCR.3
SYNCT
RCR.2
SYNCE
RCR.1
RESYNC
RCR.0
RCS
SYNCC
(LSB)
SYNCT
SYNCE
RESYNC
NAME AND DESCRIPTION
Auto Resync Criteria.
0 = Resync on OOF or RCL event.
1 = Resync on OOF only.
Out-of-frame (OOF) Condition Detection.
0 = 2 of 4 framing bits in error.
1 = 2 of 5 framing bits in error.
Receive Code Insert. When set, the receive code selected by
RCR.4 is inserted into channels marked by RMR registers. If clear,
no code is inserted.
Receive Code Select.
0 = Idle code (7F Hex).
1 = Digital milliwatt.
Sync Criteria. Determines the type of algorithm utilized by the
receive synchronizer and differs for each frame mode.
193S Framing (CCR.4=0).
0 = Synchronize to frame boundaries using FT pattern, then search
for multiframe by using FS.
1 = Cross couple FT and FS patterns in sync algorithm.
193E Framing (CCR.4=1).
0 = Normal sync (utilizes FPS only).
1 = Validate new alignment with CRC before declaring sync.
Sync Time. If set, 24 consecutive F-bits of the framing pattern
must be qualified before sync is declared. If clear, 10 bits are
qualified.
Sync Enable. If clear, the transceiver will automatically begin a
resync if two of the previous four or five framing bits were in error
or if carrier loss is detected. If set, no auto resync occurs.
Resync. When toggled low to high, the transceiver will initiate
resync immediately. The bit must be cleared, then set again for
subsequent resyncs.
RECEIVE CODE INSERTION
Incoming receive channels can be replaced with idle (7F Hex) or digital milliwatt (µ-LAW format) codes.
The receive mark registers indicate which channels are inserted. When set, bit RCR.5 serves as a
“global” enable for marked channels and bit RCR.4 selects inserted code format: 0 = idle code, 1 = digital
milliwatt.
RECEIVE SYNCHRONIZER
Bits RCR.0 through RCR.3 allow the user to control operational characteristics of the synchronizer. Sync
algorithm, candidate qualify testing, auto resync, and command resync modes may be altered at any time
in response to changing span conditions.
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DS2180A
RECEIVE SIGNALING
Robbed bit signaling data is presented at RABCD during each channel time in signaling frames for all 24
incoming channels. Logical combination of clocks RMSYNC, RSIGFR and RSIGSEL allow the user to
identify and extract AB or ABCD signaling data.
RMR1–RMR3: RECEIVE MARK REGISTERS Figure 13
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
RMR1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
RMR2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
RMR3
SYMBOL
POSITION
CH24
CH1
RMR3.7
RMR1.0
NAME AND DESCRIPTION
Receive Mark Registers. Each of these bit positions represents a
DS0 channel in the incoming T1 frame. When set, the
corresponding channel will output codes determined by RCR.4 and
RCR.5.
193S RECEIVE MULTIFRAME TIMING Figure 14
NOTES:
1. Signaling data is updated during signaling frames on channel boundaries. RABCD is the LSB of each
channel word in non-signaling frames
2. RLINK data (S-bit) is updated one bit time prior to S-bit frames and held for two frames.
15 of 35
DS2180A
193E RECEIVE MULTIFRAME TIMING Figure 15
NOTES:
1. Signaling data is updated during signaling frames on channel boundaries. RABCD outputs the LSB of
each channel word in non-signaling frames.
2. RLINK data (FDL-bit) is updated one bit time prior to odd frames and held for two frames.
16 of 35
DS2180A
RECEIVE MULTIFRAME BOUNDARY TIMING Figure 16
NOTES:
1. RLINK timing is shown for 193E; in 193S, RLINK is updated on even frame boundaries and is held
across multiframe edges.
2. Total delay from RPOS and RNEG to RSER output is 13 RCLK periods.
17 of 35
DS2180A
RSR: RECEIVE STATUS REGISTER Figure 17
(MSB)
BVCS
ECS
RYEL
SYMBOL
POSITION
BVCS
RSR.7
ECS
RSR.6
RYEL
RSR.5
RCL
RSR.4
FERR
RSR.3
B8ZSD
RSR.2
RBL
RSR.1
RLOS
RSR.0
RCL
FERR
(LSB)
B8ZSD
RBL
RLOS
NAME AND DESCRIPTION
Bipolar Violation Count Saturation. Set when the 8-bit counter
at BVCR saturates.
Error Count Saturation. Set when either of the 4-bit counters at
ECR saturates.
Receive Yellow Alarm. Set when yellow alarm detected.
(Detected yellow alarm format determined by CCR.4 and CCR.3.)
Receive Carrier Loss. Set when 32 consecutive 0’s appear at
RPOS and RNEG.
Frame Bit Error. Set when FT (193S) or FPS (193E) bit error
occurs.
Bipolar Eight Zero Substitution Detect. Set when B8ZS code
word detected.
Receive Blue Alarm. Set when two consecutive frames have less
than three 0’s (total) in the data stream (F-bit positions not tested).
Receive Loss of Sync. Set when resync is in process; if RCR.1=0,
RLOS transitions high on an OOF event or carrier loss indicating
auto resync.
RECEIVE ALARM REPORTING
Incoming serial data is monitored by the transceiver for alarm occurrences. Alarm conditions are reported
in two ways: via transitions on the alarm output pins and registered interrupt, in which the host controller
reads the RSR in response to an alarm-driven interrupt. Interrupts may be direct, in which the transceiver
demands service for a real-time alarm, or count-overflow triggered, in which an onboard alarm event
counter exceeds a user-programmed threshold. The user may mask individual alarm conditions by
clearing the appropriate bits in the receive interrupt mask register (RIMR).
ALARM SERVICING
The host controller must service the transceiver in order to clear an interrupt condition. Clearing
appropriate bits in the RIMR will unconditionally clear an interrupt. Direct interrupt (those driven from
real-time alarms) will be cleared when the RSR is directly read unless the alarm condition still exists.
Count-overflow interrupts (BVCS, ECS) are not cleared by a direct read of the RSR. They will be cleared
only when the user presets the appropriate count register to a value other than all 1’s. A burst read of the
RSR will not clear an interrupt condition.
18 of 35
DS2180A
RIMR: RECEIVE INTERRUPT MASK REGISTER Figure 18
(MSB)
BVCS
ECS
RYEL
SYMBOL
POSITION
BVCS
RIMR.7
ECS
RIMR.6
RYEL
RIMR.5
RCL
RIMR.4
FERR
RIMR.3
B8ZSD
RIMR.2
RBL
RIMR.1
RLOS
RIMR.0
RCL
FERR
B8ZSD
(LSB)
RBL
RLOS
NAME AND DESCRIPTION
Bipolar Violation Count Saturation Mask.
1 = Interrupt masked.
0 = Interrupt masked.
Error Count Saturation Mask.
1 = Interrupt enabled.
0 = Interrupt masked.
Receive Yellow Alarm Mask.
1 = Interrupt enabled.
0 = Interrupt masked.
Receive Carrier Loss Mask.
1 = Interrupt enabled.
0 = Interrupt masked.
Frame Bit Error Mask.
1 = Interrupt enabled.
0 = Interrupt masked.
B8ZS Detect Mask.
1 = Interrupt enabled.
0 = Interrupt masked.
Receive Blue Alarm Mask.
1 = Interrupt enabled.
0 = Interrupt masked.
Receive Loss of Sync Mask.
1 = Interrupt enabled.
0 = Interrupt masked.
ALARM COUNTERS
The three onboard alarm event counters allow the transceiver to monitor and record error events without
processor intervention on each event occurrence. All of these counters are presettable by the user
establishing an event count interrupt threshold. As each counter saturates, the next error event occurrence
will set a bit in the RSR and generate an interrupt unless masked. The user may read these registers at any
time; in many systems, the host will periodically poll these registers to establish link error rate
performance.
OOF EVENTS AND ERRORED
SUPERFRAMES
Out of frame is declared when at least two of four (or five) consecutive framing bits are in error. FT bits
are tested for OOF occurrence in 193S; the FPS bits are tested in 193E. OOF events are recorded by the
4-bit OOF counter in the error counter register. In the 193E framing mode, the OOF event is logically
OR’ed with an on-chip generated CRC checksum. This event, known as errored superframe, is recorded
by the 4-bit ESF error counter in the error count register. In the 193S framing mode, the 4-bit ESF error
counter records individual FT and FS errors when RCR.3=1 or FT errors only when RCR.3=0.
19 of 35
DS2180A
BVCR: BIPOLAR VIOLATION COUNT REGISTER Figure 19
(MSB)
BVD7
BVD6
BVD5
SYMBOL
POSITION
BVD7
BDV0
BVCR.7
BVCR.0
BVD4
BVD3
BVD2
(LSB)
BVD1
BVD0
NAME AND DESCRIPTION
MSB of bipolar count.
LSB of bipolar count.
This 8-bit binary up counter saturates at 255 and will generate an interrupt for each occurrence of a
bipolar violation once saturated (RIMR.7=1). Presetting this register allows the user to establish specific
count interrupt thresholds. The counter will count “up” to saturation from the preset valued and may be
read at any time. Counter increments occur at all times and are not disabled by resync. If B8ZS is enabled
(CCR.2=1) bipolar violations are not counted for B8ZS code words.
ECR: ERROR COUNT REGISTER Figure 20
(MSB)
OOFD3
OOFD2
OOFD1
ERROR COUNT
SYMBOL
POSITION
OOFD3
OOFD0
ESDF3
ESFD0
ECR.7
ECR.4
ECR.3
ECR.0
OOFD0
ESFD3
(LSB)
ESFD2
ESFD1
ESF ERROR COUNT
ESFD0
NAME AND DESCRIPTION
MSB of OOF event count.
LSB of OOF event count.
MSB of extended superframe error count.
LSB of extended superframe error count.
These separate 4-bit binary up counters saturate at a count of 15 and will generate an interrupt for each
occurrence of an OOF event or an ESF error event after saturation (RIMR.6=1). Presetting these counters
allows the user to establish specific count interrupt thresholds. The counters will count “up” to saturation
from the preset value and may be read at any time. These counters share the same register address and
must be written to or read from simultaneously.
The OOF counter records out-of-frame events in both 193S and 193E. The ESF error counter records
errored superframes in 193E. In 193S, the ESF counter records individual FT and FS errors when
RCR.3=1; FT errors only when RCR.3=0. ECR counter increments are disabled when resync is in
progress (RLOS high).
ALARM OUTPUTS
The transceiver also provides direct alarm outputs for applications when additional decoding and
demuxing are required to supplement the onboard alarm logic.
RLOS OUTPUT
The receive loss of sync output indicates the status of the receiver synchronizer circuitry; when high, an
off-line resynchronization is in progress and a high-low transition indicates resync is complete. The
RLOS bit (RSR.0) is a “latched” version of the RLOS output. If the auto-resync mode is selected
(RCR.1=0), RLOS is a real time indication of a carrier loss or OOF event occurrence.
20 of 35
DS2180A
RYEL OUTPUT
The yellow alarm output transitions high when a yellow alarm is detected. A high-low transition indicates
the alarm condition has been cleared. The RYEL bit (RSR.5) is a “latched” version of the RYEL output.
In 193E framing, the yellow alarm pattern detected is 16 pattern sets of 00 (Hex) and FF (Hex) received
at RLINK. In 193S, framing the yellow alarm format is de-pendent on CCR.3; if CCR.3=0, the RYEL
output transitions high if bit 2 of 256 or more consecutive channels is 0; if CCR.3=1, yellow alarm is
declared when the S-bit received in frame 12 is 1.
RBV OUTPUT
The bipolar violation output transitions high when an accused bit emerges at RSER. RBV will go low at
the next bit time if no additional violations are detected.
RFER OUTPUT
The receive frame error output transitions high at the F-bit time and is held high for two bit periods when
a frame bit error occurs. In 193S framing, FT and FS patterns are tested. The FPS pattern is tested in 193E
framing. Additionally, in 193E framing, RFER reports a CRC error by a low-high-low transition (one bit
period wide) one half RCLK period before a low-high transition on RMSYNC.
RESET
A high-low transition on RST clears all registers and forces immediate receive resync when RST returns
high. This reset has no effect on transmit frame multiframe or channel counters. RST must be held low on
system power-up to insure proper initialization of transceiver counters and registers. Following reset, the
host processor should restore all control modes by writing appropriate registers with control data.
ALARM OUTPUT TIMING Figure 21
NOTES:
1. RFER transitions high during F-bit time if received framing pattern bit is in error. (Frame 12 F-bits in
193S are ignored if CCR.3=1). Also, in 193E, RFER transitions 1/2 bit time before the rising edge of
RMSYNC to indicate a CRC error for the previous multiframe.
2. RBV indicates received bipolar violation and transitions high when an accused bit emerges from
RSER. If B8ZS is enabled, RBV will not report the zero replacement code.
3. RCL transitions high (during 32nd bit time) when 32 consecutive bits received are 0; RCL transitions
low when the next 1 is received.
21 of 35
DS2180A
4. RLOS transitions high during the F-bit time that caused an OOF event (any two of four consecutive
FT or FPS bits are in error) if auto-resync mode is selected (RCR.1=0). Resync will also occur when
loss of carrier is detected (RCL=1). When RCR.1=1, RLOS remains low until resync occurs,
regardless of OOF or carrier loss flags. In this situation, resync is initiated only when RCR.0
transitions low-to-high or the RST pin transitions high-low-high.
HARDWARE MODE
For preliminary system prototyping or applications which do not require the features offered by the serial
port, the transceiver can be reconfigured by the SPS pin. Tying SPS to VSS disables the serial port, clears
all internal registers except CCR and TCR and redefines pins 14 through 18 as mode control inputs. The
hardware mode allows device retrofit into existing applications where mode control and alarm
conditioning hardware is often designed with discrete logic.
HARDWARE COMMON CONTROL
In the hardware mode bits TCR.2, CCR.4, TCR.0, CCR.1 and CCR.2 map to pins 14 through 18. The
loop-back feature (bit CCR.0) is enabled by tying pins 17 (zero suppression) and 18 (B8ZS) to 1. (The
last states of pins 17 and 18 are latched as when both pins are taken high, preserving the current zero
suppression mode). Robbed bit signaling (bit TCR.4) is enabled for all channels. The user may tie TSER
to TABCD externally to disable signaling if so desired. Bit CCR.3 is forced to 0 which selects bit 2
yellow alarm in 193S framing. Contents of the RCR, as well as the remaining bit locations in the CCR
and TCR are cleared in the hardware mode. The RST input may be used to force immediate receiver
resync and has no effect on transmit.
HARDWARE MODE Table 6
PIN
NUMBER
14 (16)
REGISTER BIT
LOCATION
TCR-D2
15 (17)
CCR-D4
16 (18)
TCR-D0
17 (19)
CCR-D1
18 (20)
CCR-D2
NAME AND DESCRIPTION
193S – S-bit insertion 3
1 = external; 0 = internal
Framing Mode Select.
1 = 193E; 0 = 193S
Transmit Yellow Alarm 2 ,3
1 = enabled; 0 = disabled
Zero Suppression 1
1 = bit 7 stuffing
0 = transparent
B8ZS1
1 = enabled; 0 = disabled
NOTES
1. Tying pins 17 and 18 high enables loopback in the hardware mode.
2. Bit 2 (193S) and data link (193E) yellow alarms are supported.
3. S-bit yellow alarm (193S) is not internally supported; however, the user may elect to insert external S
bits for alarm purposes.
4. Pin numbers for PLCC package are listed in parenthesis.
22 of 35
DS2180A
T1 OVERVIEW
Framing Standards
The DS2180A is compatible with the existing Bell System D4 framing standard described in ATT PUB
43801 and the new extended superframe format (ESF) as described in ATT C.B. #142. In this document,
D4 framing is referred to as 193S and ESF (also known as Fe) is referred to as 193E. Programmable
features of the DS2180A allow support of other framing standards which are derivatives of 193E and
193S. The salient differences between the 193S and 193E formats are the number of frames per
superframe and use of the F-bit position. In 193S, 12 frames make up a superframe, in 193E, 24. A frame
consists of 24 channels (timeslots) of 8-bit data preceded by an F-bit. Channel data is transmitted and
received MSB first.
F-Bits
The use of the F-bit position in 193S is split between the terminal framing pattern (know as FT-bits)
which pro-vides frame alignment information and the signaling framing pattern (known as FS-bits) which
provides multiframe alignment information. In 193E framing, the F-bit position is shared by the framing
pattern sequence (FPS) which provides frame and multiframe alignment information, a 4 kHz data link
known as FDL (Facility Data Link), and CRC (Cyclic Redundancy Check) bits. The FDL bits are used
for control and maintenance (inserted by the user at TLINK) and the CRC bits are an indicator of link
quality and may be monitored by the user to establish error performance.
Signaling
During frames 6 and 12 in 193S, A and B signaling information is inserted into the LSB of all channels
transmitted. In 193E, A and B data is inserted into frames 6 and 12 and C and D data is inserted into
frames 18 and 24. This allows a maximum of four signaling states to be transmitted per superframe in
193S and 16 states in 193E.
Alarms
The DS2180A supports all alarm pattern generation and detection required in typical Bell System
applications. These alarm modes are explained in ATT PUB 43801, ATT C.B. #142 and elsewhere in
this document.
23 of 35
DS2180A
193E FRAMING FORMAT Table 7
FRAME
NUMBER
FPS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
0
0
1
0
1
1
F-BIT USE
FPL2 CRC3
M
M
M
M
M
M
M
M
M
M
M
M
-
C1
C2
C3
C4
C5
C6
-
BIT USE IN EACH CHANNEL
DATA
SIGNALING
BITS 1-8
BITS 1-8
BITS 1-8
BITS 1-8
BITS 1-8
BITS 1-7
BITS 1-8
BITS 1-8
BITS 1-8
BITS 1-8
BITS 1-8
BITS 1-7
BITS 1-8
BITS 1-8
BITS 1-8
BITS 1-8
BITS 1-8
BITS 1-7
BITS 1-8
BITS 1-8
BITS 1-8
BITS 1-8
BITS 1-8
BITS 1-7
SIGNALING-BIT USE
2
4
16
STATE
STATE
STATE
BIT 8
A
A
A
BIT 8
A
B
B
BIT 8
A
C
C
BIT 8
A
B
D
NOTES:
1. FPS – Framing Pattern Sequence.
2. FDL – 4 kHz Facility Data Link; M = message bits.
3. CRC – Cyclic Redundancy Check bits. The CRC code will be internally generated by the device
when TCR.5=0. When TCR.5=1, externally supplied CRC data will be sampled at TSER during the
F-bit time of frames 2, 6, 10, 14, 18, 22.
4. The user may program any individual channels clear, in which case bit 8 will be used for data, not
signaling.
5. Depending on application, the user can support 2-state, 4-state or 16-state signaling by the appropriate
decodes of TMO, TSIGFR, TSIGSEL (Transmit Side) and RMSYNC, RSIGFR and RSIGSEL
(Receive Side).
24 of 35
DS2180A
193S FRAMING FORMAT Table 8
FRAME
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
F-BIT USE
FT1
FS2
1
0
0
0
1
1
0
1
1
1
0
03
BIT USE IN EACH CHANNEL
DATA
SIGNALING4
BITS 1-8
BITS 1-8
BITS 1-8
BITS 1-8
BITS 1-8
BITS 1-7
BIT 8
BITS 1-8
BITS 1-8
BITS 1-8
BITS 1-8
BITS 1-8
BITS 1-7
BIT 8
SIGNALING-BIT USE
A
B
NOTES:
1. FT (terminal framing) bits provide frame alignment information.
2. FS (signaling frame) bits provide multiframe alignment information.
3. The S-bit in frame 12 may be used for yellow alarm transmission and detection in some applications.
4. The user may program any individual channels clear, in which case bit 8 will be used for data, not
signaling.
Line Coding
T1 line data is transmitted in a bipolar alternative mark inversion line format; 1’s are transmitted as
alternating negative and positive pulses and 0’s are simply the absence of pulses. This technique
minimizes DC voltage on the T1 span and allows clock to be extracted from data. The network currently
has a 1’s density constraint to keep clock extraction circuitry functioning which is usually met by forcing
bit 7 of any channel consisting of all 0’s to 1. The use of Bipolar Eight Zero Substitution (B8ZS) satisfies
all the 1’s density requirement while allowing data traffic to be transmitted without corruption. This
feature is known as clear channel and is explained more completely in ATT C.B. #144. When the B8ZS
feature is enabled, any outgoing stream of eight consecutive 0’s is replaced with a B8ZS code word. If the
last 1 transmitted was positive, the inserted code is 000+-0-+; if negative, the code word inserted is 000+0+-. Bipolar violations occur in the fourth and seventh bit positions which are ignored by the DS2180A
error monitoring logic when B8ZS is enabled. Any received B8ZS code word is replaced with all 0’s if
B8ZS is enabled. Also, the receive status register will report any occurrence of B8ZS code words to the
host controller. This allows the user to monitor the link for upgrade to clear channel capability and
respond to it. The B8ZS monitoring feature works at all times and is independent of the state of CCR.2.
TRANSMIT SIDE OVERVIEW
The transmit side of the DS2180A is made up of six major functional blocks: timing and clock
generation, data selector, bipolar coder, yellow alarm, F-bit data and CRC. The timing and clock
generation circuit develops all onboard and output clocks to the system from inputs TCLK, TFSYNC, and
TMSYNC. The yellow alarm circuitry generates mode–dependent yellow alarms. The CRC block
generates checksum results utilized in 193E framing. F-bit data provides mode–dependent framing
patterns and allows insertion of link or S-bit data externally. All of these blocks feed into the data
selector where, under control of the CCR, TCR, TIRs and TTRs, the contents of the outgoing data stream
are established by bit selection and insertion. The bipolar coder formats the output of the data selector to
25 of 35
DS2180A
make it compatible with bipolar transmission techniques and inserts zero suppression codes. The bipolar
coder also supports the onboard loopback feature. Input-to-output delay of the transmitter is 10 TCLK
cycles.
RECEIVE SIDE OVERVIEW
Synchronizer
The heart of the receiver is the synchronizer monitor. This circuit serves two purposes: 1) monitoring the
incoming data stream for loss of frame or multiframe alignment, and 2) searching for new frame
alignment pattern when sync loss is detected. When sync loss is detected, the synchronizer begins an offline search for the new alignment; all output timing signals remain at the old alignment with the exception
of RSIGFR, which is forced low during resync. When one and only one candidate is qualified, the output
timing will move to the new alignment at the beginning of the next multiframe. One frame later, RLOS
will transition low, indicating valid sync and the resumption of the normal sync monitoring mode. Several
bits in the RCR allow tailoring of the resync algorithm by the user. These bits are described below.
Sync Time (RCR.2)
Bit RCR.2 determines the number of consecutive framing pattern bits to be qualified before SYNC is
declared. If RCR.2=1, the algorithm will validate 24 bits; if RCR.2=0, 10 bits are validated. 24-bit
testing results in superior false framing protection, while 10-bit testing minimizes reframe time (although
in either case, the synchronizer will only establish resync when one and only one candidate is found).
Resync (RCR.0)
A 0-to-1 transition of RCR.0 causes the synchronizer to search for the framing pattern sequence
immediately, regardless of the internal sync status. In order to initiate another resync command, this bit
must be cleared and then set again.
Sync Enable (RCR.1)
When RCR.1 is cleared, the receiver will initiate automatic resync if any of the following events occur: 1)
an OOF event (“out-of-frame”), or 2) carrier loss (32 consecutive 0’s appear at RPOS and RNEG). An
OOF event occurs any time that 2 of 4 F T or FPS bits are in error. When RCR.1 is set, the automatic
resync circuitry is disabled; in this case, resync can only be initiated by setting RCR.0 to 1 or externally
via a low-high transition on RST . Note that using RST to initiate resync resets the receive output timing
while RST is low; use of RCR.1 does not affect output timing until the new alignment is located.
Sync Criteria (RCR.3)
193E
Bit RCR.3 determines which sync algorithm is utilized when resync is in progress (RLOS=1). In 193E
framing, when RCR.3=0, the synchronizer will lock only to the FPS pattern and will move to the new
frame and multiframe alignment after the move to the new alignment. When RCR.3=1, the new
alignment is further tested by a CRC code match. RLOS will transition low after a CRC match occurs. If
no CRC match occurs in three attempts (three multiframes), the algorithm will reset and a new search for
the framing pattern begins. It takes 9 ms for the synchronizer to check the first CRC code after the new
alignment has been loaded. Each additional CRC test takes 3 ms. Regardless of the state of RCR.3, if
more than one candidate exists after about 24 ms, the synchronizer will begin eliminating emulators by
testing their CRC codes online in order to find the true framing candidate.
193S
In 193S framing, when RCR.3=1, the synchronizer will cross check the FT pattern with the FS pattern to
help eliminate false framing candidates such as digital milliwatts. The FS patterns are compared to the
26 of 35
DS2180A
repeating pattern ...00111000111000...(00111X0 if CCR.3–YELMD–is equal to a 1). In this mode, FT
and FS patterns must be correctly identified by the synchronizer before sync is declared. Clearing RCR.3
causes the synchronizer to search for FT patterns (101010...) without cross-coupling the FS pattern. Frame
sync will be established using the FT information, while multiframe sync will be established only if valid
FS information is present. If no valid FS pattern is identified, the synchronizer will move to the FT
alignment, RLOS will go low, and a false multiframe position may be indicated by RMSYNC. RFER will
indicate when the received S-bit pattern does not match the assumed internal multiframe alignment. This
mode will be used in applications where non-standard S-bit patterns exist. In such applications,
multiframe alignment information can be decoded externally by using the S-bits present at RLINK.
AVERAGE REFRAME TIME1 Table 9
FRAME
MODE
193S
193E
MIN
3.0
6.0
RCR.2=0
AVG
3.75
7.5
MAX
4.5
9.0
MIN
6.5
13.0
RCR.2=1
AVG
7.25
14.5
UNITS
MAX
8.0
16.0
ms
NOTE:
1. Average Reframe Time is defined here as the average time it takes from the start of sync (rising edge
of RLOS) to the actual loading of the new alignment (on a multiframe edge) into the output receive
timing.
BACKPLANE INTERFACE USING DS2180A AND DS2176 Figure 22
27 of 35
DS2180A
PROCESSOR-BASED TRANSMIT SIGNALING INSERTION Figure 23
PROCESSOR-BASED SIGNALING
Many robbed-bit signaling applications utilize a microprocessor to insert transmit signaling data into the
out-going data stream. The circuit shown in Figure 23 “decouples” the processor timing from that of the
DS2180A by use of a small FIFO memory. The processor writes to the FIFO (6 bytes are written: 3 for A
data, 3 for B data) only when signaling updates are required. The system is interrupt-driven from the
transmit multiframe sync input; the processor must update the FIFO prior to Frame 6 (625 µs after
interrupt) to prevent data corruption. The application circuit shown supports 193S framing. Additional
hardware is required for 193E applications.
28 of 35
DS2180A
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
-1.0V to +7.0V
0° to 70°C
-55°C to +125°C
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN
Input Logic 1
VIH
Input Logic 0
Supply
TYP
(0°C to 70°C)
MAX
UNITS
2.0
VDD+.3
V
VIL
-0.3
+0.8
V
VDD
4.5
5.5
V
5.0
CAPACITANCE
PARAMETER
(tA =25°C)
SYMBOL
Input Capacitance
Output Capacitance
MIN
MAX
UNITS
CIN
5
pF
COUT
7
pF
DC ELECTRICAL CHARACTERISTICS
PARAMETER
NOTES
SYMBOL
MIN
TYP
NOTES
(0°C to 70°C; VDD = 5.0V ± 10%)
TYP
MAX
UNITS
NOTES
3
10
mA
1,2
Supply Current
IDD
Input Leakage
IIL
1
µA
Output Leakage
ILO
1
µA
3
Output Current @ 2.4V
IOH
-1
mA
4
Output Current @ .4V
IOL
+4
mA
5
NOTES:
1. TCLK = RCLK = 1.544 MHz.
2. Outputs open.
3. Applies to SDO when tri-stated.
4. All outputs except INT , which is open collector.
5. All outputs.
29 of 35
DS2180A
AC ELECTRICAL CHARACTERISTICS
PARAMETER
(0°C to 70°C; VDD = 5.0V ± 10%)
SYMBOL
MIN
TYP
MAX
SDI to SCLK Setup
tCC
50
ns
SCLK to SDI Hold
tCDH
50
ns
SDI to SCLK Falling Edge
tCD
50
ns
SCLK Low Time
tCL
250
ns
SCLK High Time
tCH
250
ns
SCLK Rise and Fall Time
tR, tF
500
UNITS
ns
to SCLK Setup
tCC
50
ns
SCLK to CS Hold
tCCH
50
ns
CS Inactive Time
tCWH
250
ns
ACLK to SDO Valid2
tCDV
200
ns
CS to
tCDZ
75
ns
CS
SDO High Z
SCLK Setup to CS Falling
TSCC
50
NOTES
ns
NOTES:
1. Measured at VIH =2.0 V; VIL =.8 V and 10 ns maximum rise and fall time.
2. Output load capacitance = 100 pF.
SERIAL PORT WRITE AC TIMING DIAGRAM
NOTES:
1. Data byte bits must be valid across low clock periods to prevent transients in operating modes.
2. Shaded regions indicate “don’t care” states of input data.
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DS2180A
SERIAL PORT READ AC TIMING
NOTE:
1. Serial port write must precede a port read to provide address information.
AC ELECTRICAL CHARACTERISTICS1 – TRANSMIT
(0°C to 70°C; VDD = 5.0V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
tP
250
648
ns
tWL, tWH
125
324
ns
20
ns
TCLK Period
TCLK Pulse Width
MAX
UNITS
TCLK, RCLK Raise & Fall
Times
tW, tR
TSER, TABCD, TLINK
Setup to TCLK Falling
tSTD
50
ns
TSER, TABCD, TLINK Hold
from TCLK Falling
tHTD
50
ns
TFSYNC, TMSYNC Setup to
TCLK Rising
tSTS
-125
Propagation Delay TFSYNC
to TMO, TSIGSEL, TSIGFR,
TLCLK
125
ns
tPTS
75
ns
Propagation Delay TCLK to
TCHCLK
tPTCH
75
ns
TFSYNC, TMSYNC Pulse
Width
tTSP
100
NOTES:
1. Measured at VIH = 2.0V; VIL = .8V and 10 ns maximum rise and fall time.
2. Output load capacitance = 100 pF.
31 of 35
ns
NOTES
DS2180A
1
AC ELECTRICAL CHARACTERISTICS – RECEIVE
(0°C to 70°C; VDD = 5.0V ± 10%)
PARAMETER
SYMBOL
Propagation Delay RCLK to
RMSYNC, RFSYNC,
RSIGSEL, RSIGFR, RLCLK,
RCHCLK
MAX
UNITS
tPRS
75
ns
Propagation Delay RCLK to
RSER, RABCD, RLINK
tPRD
75
ns
Transition Time All Outputs
tTTR
20
ns
RCLK Period
RCLK Pulse Width
MIN
TYP
tP
250
648
ns
tWL, tWH
125
324
ns
20
ns
RCLK Rise and Fall Times
tR, tF
RPOS, RNEG Setup to RCLK
Falling
tSRD
50
ns
RPOS, RNEG Hold to RCLK
Falling
tHRD
50
ns
Propagation Delay RCLK to
RYEL, RCL, RFER, RLOS,
RBV
tPRA
Minimum RST Pulse Width
on System Power Up or
Restart
tRST
75
1
NOTES:
1. Measured at VIH = 2.0V; VIL = .8V and 10 ns maximum rise and fall times.
2. Output load capacitance = 100 pF.
32 of 35
ns
µs
NOTES
DS2180A
TRANSMIT AC TIMING DIAGRAM
RECEIVE AC TIMING DIAGRAM
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DS2180A
DS2180A SERIAL T1 TRANSCEIVER (600 MIL DIP)
DIM
A
B
C
D
E
F
G
H
J
K
MIN
2.050
0.530
0.140
0.600
0.015
0.120
0.090
0.625
0.008
0.015
INCHES
MAX
2.075
0.550
0.160
0.625
0.040
0.145
0.110
0.675
0.012
0.022
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DS2180A
DS2180AQ SERIAL T1 TRANSCEIVER (PLCC)
DIM
A
A1
A2
B
B1
C
CH1
D
D1
D2
E
E1
E2
e1
N
INCHES
MIN
MAX
0.165
0.180
0.090
0.120
0.020
0.026
0.033
0.013
0.021
0.009
0.012
0.042
0.048
0.685
0.695
0.650
0.656
0.590
0.630
0.685
0.695
0.650
0.656
0.590
0.630
0.050 BSC
44
-
35 of 35