Dual and Window 4ns High-Speed Comparators Features General Description • • • • • • The EL5287C comparator is designed for operation in single supply and dual supply applications with 5V to 12V between VS+ and VS-. For single supplies, the inputs can operate from 0.1V below ground for use in ground sensing applications. • • • • 4ns typ. propagation delay 5V to 12V input supply +2.7V to +5V output supply True-to-ground input Rail-to-rail outputs Separate analog and digital supplies Active low latch Single available (EL5185C) Quad available (EL5485C & EL5486C) Pin-compatible 6ns family available (EL5x81C, EL5283C & EL5482C) The output side of the comparators can be supplied from a single supply of 2.7V to 5V. The rail-to-rail output swing enables direct connection of the comparator to both CMOS and TTL logic circuits. The latch input of the EL5287C can be used to hold the comparator output value by applying a low logic level to the pin. The EL5287C contains two comparators set up as a window comparator. A single input is compared with a high and low reference. When the output goes beyond one of these reference signals, the relevant output goes high. The EL5287C is available in the 10-pin MSOP package and is specified for operation over the full -40°C to +85°C temperature range. Also available are a single (EL5185C) and quad versions (EL5485C and EL5486C.) Applications • • • • • • EL5287C - Preliminary EL5287C - Preliminary Threshold detection High speed sampling circuits High speed triggers Line receivers PWM circuits High speed V/F converters Pin Configurations Ordering Information Package Tape & Reel Outline # EL5287CY Part No. 10-Pin MSOP - MDP0043 EL5287CY-T13 10-Pin MSOP 13” MDP0043 VS+ 1 VREFH 2 10 VSD + - IN 3 VREFL 4 9 OUTH 8 LATCH + - 6 GND EL5287C (10-Pin MSOP) Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a “controlled document”. Current revisions, if any, to these specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation. © 2001 Elantec Semiconductor, Inc. September 7, 2001 VS- 5 7 OUTL EL5287C - Preliminary EL5287C - Preliminary Dual and Window 4ns High-Speed Comparators Absolute Maximum Ratings (T A = 25°C) Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Analog Supply Voltage (VS+ to VS-) +12V Digital Supply Voltage (VSD to GND) +7V Differential Input Voltage [(VS-) -0.2V] to [(VS+) +0.2V] Common-mode Input Voltage [(VS-) -0.2V] to [(VS+) +0.2V] Latch Input Voltage Storage Temperature Range Ambient operating Temperature Operating Junction Temperature Power Dissipation ESD Voltage -0.2V to [VSD+0.2V] -65°C to +150°C -40°C to +85°C 125°C TBDmW 2kV Important Note: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA. Electrical Characteristics VS = ±5V, VSD = 5V, RL = 2.3kΩ, CL = 15pF, TA = 25°C, unless otherwise specified. Parameter Description Typ Max Unit 2 4 mV Input Bias Current 8 15 µA CIN Input Capacitance 5 IOS Input Offset Current 500 nA VOS Input Offset Voltage IB Condition Min VCM = 0V, VO = 2.5V VCM = 0V, VO = 2.5V VCM Input Voltage Range AVO Large Signal Voltage Gain CMRR Common-mode Rejection Ratio PSRR Power Supply Rejection Ratio VOH Output High Voltage VIN > 250mV VOL Output Low Voltage VIN > 250mV VLH Latch Input Voltage High 100 (VS-) - 0.1 -5V < VCM < +2.75V, VO = 2.5V VSD - 0.5V pF (VS+) - 2V V 5000 V/V 80 dB 60 dB VSD - 0.4V GND + 0.4V V GND + 0.5V V 2.0 V 1 20 µA 40 80 VLL Latch Input Voltage Low ILH Latch Input Current High VLH = 3V 0.8 ILL Latch Input Current Low VLL = 0.3V IS + Positive Analog Supply Current (per comparator) 10.5 mA IS - Negative Analog Supply Current (per comparator) 7.5 mA IDD Digital Supply Current (per comparator) 6 td+ Positive Going Delay Time VOD = 5mV, CL = 15pF, I O= 2mA 4 6 ns td- Negative Going Delay Time VOD = 5mV, CL = 15pF, IO = 2mA 4 6 ns tpd+ Latch Disable to High Delay 6 ns tpd- Latch Disable to Low Delay 8 ns ts Minimum Setup Time 2 ns th Minimum Hold Time 1 ns tpw(D) Minimum Latch Disable Pulse Width 5 ns 2 V µA mA Typical Performance Curves 10 Supply Current vs Supply Voltage (per comparator) VIN=50mV RL=2.2k Output High Voltage vs Temperature 4.832 4.83 IS+ 8 VOH (V) IS (mA) 4.828 6 I S- 4 4.826 4.824 4.822 2 4.82 4.818 -50 0 0 1 2 3 4 5 6 -30 -10 10 30 50 70 90 50 70 90 50 70 90 Temperature (°C) ±VS (V) Input Bias Current vs Temperature Offset Voltage vs Temperature 3 8 7 2.5 6 5 IB (µA) VOS (mV) 2 1.5 4 3 1 2 0.5 1 0 -50 -30 -10 10 30 50 70 0 -50 90 -30 -10 Temperature (°C) Output Low Voltage vs Temperature 0.285 12 Supply Current (mA) VOL (V) 30 Supply Current vs Temperature (per comparator) 11 0.275 0.265 0.255 0.245 0.235 -50 10 Temperature (°C) I S+ 10 9 8 IS- 7 -30 -10 10 30 50 70 6 -50 90 Temperature (°C) -30 -10 10 30 Temperature (°C) 3 EL5287C - Preliminary EL5287C - Preliminary Dual and Window 4ns High-Speed Comparators Dual and Window 4ns High-Speed Comparators Typical Performance Curves 7.8 Propagation Delay vs Overdrive VIN=5VSTEP 15 VS=±5V VSD=5V RL=2.2k 7.6 TPD- Propagation Delay vs Source Resistance VIN=1VSTEP VS=±5V VSD=5V VOD=50mV RL=2.2k 13 Delay Time (ns) Delay Time (ns) 7.4 7.2 TPD+ 7 11 TPD9 TPD+ 6.8 7 6.6 5 6.4 0.2 0.6 1 1.4 1.8 2.2 2.6 0.4 0 Propagation Delay vs Supply Voltage 6.8 25 VSD=VS+ VOD=50mV RL=2.2k 6.6 1.2 1.6 2 Digital Supply Current vs Switching Frequency (per comparator) VS=±5V TA=25°C 20 6.4 6.2 ISD (mA) Delay Time (ns) 0.8 Source Resistance (kΩ) VOD (V) TPD- 15 VSD=5V 10 VSD=3V 6 5.8 5.6 5 TPD+ 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 0 6 10 0 Propagation Delay vs Overdrive VIN=1VSTEP 8 VS=±5V VSD=5V RL=2.2k 6 5.9 5.8 50 Propagation Delay vs Overdrive VIN=3VSTEP VS=±5V VSD=5V RL=2.2k 7.5 TPD- 5.7 5.6 5.5 TPD- 7 6.5 TPD+ 6 TPD+ 5.4 5.5 5.3 5.2 50 40 Frequency (MHz) Delay Time (ns) 6.1 30 20 ±VS (V) Delay Time (ns) EL5287C - Preliminary EL5287C - Preliminary 5 0.2 100 150 200 250 300 350 400 450 500 550 600 VOD (mV) 0.4 0.6 0.8 1 1.2 VOD (mV) 4 1.4 1.6 1.8 2 Typical Performance Curves Propagation Delay vs Load Capacitance VIN=1VSTEP VS=±5V VSD=5V VOD=50mV RL=2.2k 8.5 8 Delay Time (ns) 0.6 Package Power Dissipation vs Ambient Temp. JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board 486mW 0.5 7.5 Power Dissipation (W) 9 TPD- 7 6.5 TPD+ 6 0.4 MS OP 10 20 6° C/W 0.3 0.2 0.1 5.5 5 0 0 10 20 30 40 50 60 70 80 90 100 CLOAD (pF) 0 25 50 75 85 Ambient Temperature (°C) Output with 50MHz Input VIN=3VP-P Output with 50MHz Input VIN=1VP-P Output (5ns/div, 2V/div) Output (5ns/div, 2V/div) Input (5ns/div, 0.5V/div) Input (5ns/div, 2V/div) 5 100 125 EL5287C - Preliminary EL5287C - Preliminary Dual and Window 4ns High-Speed Comparators EL5287C - Preliminary EL5287C - Preliminary Dual and Window 4ns High-Speed Comparators Timing Diagram Compare Compare Latch Enable Input 1.4V Latch Latch Differential Input Voltage ts Latch th tpw(D) VIN VOS VOD tpd- td+ Comparator Output 2.4V Definition of Terms Term Definition VOS Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output VIN Input Voltage Pulse Amplitude - Usually set to 1V for comparator specifications VOD Input Voltage Overdrive - Usually set to 50mV and in opposite polarity to VIN for comparator specifications tpd+ Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS logic threshold of an output low to high transition tpd- Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS logic threshold of an output high to low transition td+ Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high transition to the point of the output crossing CMOS threshold in a low to high transition td- Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high transition to the point of the output crossing CMOS threshold in a high to low transition ts Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be present in order to be acquired and held at the outputs th Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain unchanged in order to be acquired and held at the output tpw (D) Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an input signal change 6 Pin Descriptions Pin Number Pin Name 1 VS+ Positive supply voltage Function 2 VREFH Upper voltage reference Equivalent Circuit VS+ VREF IN VSCircuit 4 3 IN Input (Reference Circuit 4) 4 VREFL Lower voltage reference (Reference Circuit 4) 5 VS- Negative supply voltage 6 GDN Digital ground 7 OUTL Low output (Reference Circuit 2) 8 LATCH Latch (Reference Circuit 3) 9 OUTH High output (Reference Circuit 2) 10 VSD Digital supply voltage 7 EL5287C - Preliminary EL5287C - Preliminary Dual and Window 4ns High-Speed Comparators EL5287C - Preliminary EL5287C - Preliminary Dual and Window 4ns High-Speed Comparators Applications Information Power Supplies and Circuit Layout imum slew rate requirements. In some applications, it may be helpful to apply some positive feedback (hysteresis) between the output and the positive input. The hysteresis effectively causes one comparator's input voltage to move quickly past the other, thus taking the input out of the region where oscillation occurs. For the EL5287C, the propagation delay increases when the input slew rate increases for low overdrive voltages. With high overdrive voltages, the propagation delay does not change much with the input slew rate. The EL5287C comparator operates with single and dual supply with 5V to 12V between VS+ and VS-. The output side of the comparator is supplied by a single supply from 2.7V to 5V. The rail to rail output swing enables direct connection of the comparator to both CMOS and TTL logic circuits. As with many high speed devices, the supplies must be well bypassed. Elantec recommends a 4.7µF tantalum in parallel with a 0.1µF ceramic. These should be placed as close as possible to the supply pins. Keep all leads short to reduce stray capacitance and lead inductance. This will also minimize unwanted parasitic feedback around the comparator. The device should be soldered directly to the PC board instead of using a socket. Use a PC board with a good, unbroken low inductance ground plane. Good ground plane construction techniques enhance stability of the comparators. Latch Pin Dynamics The EL5287C contains a “transparent” latch for each channel. The latch pin is designed to be driven with either a TTL or CMOS output. When the latch is connected to a logic high level or left floating, the comparator is transparent and immediately responds to the changes at the input terminals. When the latch is switched to a logic low level, the comparator output remains latched to its value just before the latch’s highto-low transition. To guarantee data retention, the input signal must remain the same state at least 1ns (hold time) after the latch goes low and at least 2ns (setup time) before the latch goes low. When the latch goes high, the new data will appear at the output in approximately 6ns (latch propagation delay). Input Voltage Considerations The EL5287C’s input range is specified from 0.1V below VS- to 2.25V below VS+. The criterion for the input limit is that the output still responds correctly to a small differential input signal. The differential input stage is a pair of PNP transistors, therefore, the input bias current flows out of the device. When either input signal falls below the negative input voltage limit, the parasitic PN junction formed by the substrate and the base of the PNP will turn on, resulting in a significant increase of input bias current. If one of the inputs goes above the positive input voltage limit, the output will still maintain the correct logic level as long as the other input stays within the input range. However, the propagation delay will increase. When both inputs are outside the input voltage range, the output becomes unpredictable. Large differential voltages greater than the supply voltage should be avoided to prevent damages to the input stage. Power Dissipation When switching at high speeds, the comparator's drive capability is limited by the rise in junction temperature caused by the internal power dissipation. For reliable operation, the junction temperature must be kept below TJMAX (125°C). An approximate equation for the device power dissipation is as follows. Assume the power dissipation in the load is very small: P DISS = ( V S × I S + V SD × I SD ) Input Slew Rate where: Most high speed comparators oscillate when the voltage of one of the inputs is close to or equal to the voltage on the other input due to noise or undesirable feedback. For clean output waveform, the input must meet certain min- VS is the analog supply voltage from VS+ to VSIS is the analog quiescent supply current per comparator 8 VSD is the digital supply voltage from VSD to ground of the range set by VREFH and VREFL, the input in range is low. ISD is the digital supply current per comparator ISD strongly depends on the input switching frequency. Please refer to the performance curve to choose the input driving frequency. Having obtained the power dissipation, the maximum junction temperature can be determined as follows: VREFH + - Input In Range VIN VREFL T JMAX = T MAX + Θ JA × P DISS where: TMAX is the maximum ambient temperature θJA is the thermal resistance of the package Window Detector If V IN is in the range of V REFL < VIN < VREFH, both outputs go high and the input in range is high. If VIN is out 9 OUTH + - OUTL EL5287C - Preliminary EL5287C - Preliminary Dual and Window 4ns High-Speed Comparators EL5287C - Preliminary EL5287C - Preliminary Dual and Window 4ns High-Speed Comparators General Disclaimer Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the circuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. September 7, 2001 WARNING - Life Support Policy Elantec, Inc. products are not authorized for and should not be used within Life Support Systems without the specific written consent of Elantec, Inc. Life Support systems are equipment intended to support or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death. Users contemplating application of Elantec, Inc. Products in Life Support Systems are requested to contact Elantec, Inc. factory headquarters to establish suitable terms & conditions for these applications. Elantec, Inc.’s warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages. 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