EXAR XR16L788

áç
XR16L788
HIGH PERFORMANCE OCTAL UART
SEPTEMBER 2001
REV. 1.1.4
GENERAL DESCRIPTION
The XR16L7881 (788), formerly XR16L758, is a 5V
and 3.3V with 5V tolerant inputs octal Universal Asynchronous Receiver and Transmitter (UART). The
highly integrated device is designed for high bandwidth requirement in communication systems. A new
feature increases device driver efficiency includes a
global interrupt pin with global interrupt source registers that provide complete and detailed interrupt status information for all 8 channels that will speed up interrupt parsing. Other new facilities include simultaneous UART registers initialization, individual UART
channel soft-reset, DTR/DSR hardware flow control,
software flow control (Xoff/Xon) detection indicators,
RS-485 half-duplex direction control with programmable turn-around delay, Intel or Motorola bus interface
and sleep mode now has a wake-up indicator.
NOTE:
Covered by US patents #5,649,122 and #5,949,787
APPLICATIONS
• Remote Access Servers
• Ethernet Network to Serial Ports
• Network Management
• Factory Automation and Process Control
• Point-of-Sale Systems
• Multi-port RS-232/RS-422/RS-485 Cards
NEW FEATURES:
• 5V and 3.3V with 5V Tolerant Inputs Operation
• Single Interrupt Output for all 8 UARTs
• Global Interrupt Source for all 8 UARTs
• 5G “Flat” UART Registers for Configurations
• Simultaneous UART Channels Initialization
• Auto RS485 Half-duplex Control with Programmable Turn-around Delay
• A General Purpose 16-bit Timer/Counter
• Sleep Mode with Wake-up Indication
• Highly Integrated Device for Space Saving
• First eight registers are 16C550 compatible
• 64-byte Transmit and Receive FIFOs
• Transmit and Receive FIFO Level Counters
• Programmable TX and RX FIFO Trigger Levels
• Automatic RTS/CTS or DTR/DSR Flow Control
• Selectable Hardware Flow Control Hysteresis
• Automatic Xon/Xoff Software Flow Control with Status Indicator
• Infrared (IrDA 1.0) Data Encoder/Decoder
• Programmable Data Rate with Prescaler
• Up to 6.25 Mbps Serial Data Rate at 5V
• 100-pin QFP Package (14x20x3 mm)
FIGURE 1. BLOCK DIAGRAM
U A R T C ha n ne l 0
UART
R eg s
BRG
RST#
IO R #
IO W #
IR
ENDEC
T X 0 , R X 0 , D T R 0# ,
D S R 0# , R T S 0# ,
C T S 0 # , C D 0 #, R I0 #
64 B yte R X F IF O
U A R T C ha n ne l 1
A 7:A 0
D 7 :D 0
64 B yte T X FIF O
TX & RX
D a ta B u s
Inte rfa ce
D e vice
C o n figu ra tio n
R e g isters
U A R T C ha n ne l 2
U A R T C ha n ne l 3
CS#
U A R T C ha n ne l 4
IN T #
U A R T C ha n ne l 5
1 6/6 8#
U A R T C ha n ne l 6
1 6-bit
T im e r/C o un ter
U A R T C ha n ne l 7
C rystal O sc/B u ffer
T X 7 , R X 7 , D T R 7# ,
D S R 7# , R T S 7# ,
C T S 7 # , C D 7 #, R I7 #
X T A L1
X T A L2
TM RCK
EXAR Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com • [email protected]
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XR16L788 OCTAL UART
REV. 1.1.4
TX2
DTR2#
RTS2#
RI2#
CD2#
DSR2#
CTS2#
RX2
TX3
DTR3#
RTS3#
RI3#
CD3#
DSR3#
CTS3#
RX3
TX4
DTR4#
RTS4#
RI4#
CD4#
DSR4#
CTS4#
RX4
TX5
DTR5#
RTS5#
RI5#
CD5#
DSR5#
FIGURE 2. PIN OUT OF THE DEVICE
X R 16 L788
10 0-Q F P
C T S 5#
RX5
VCC
GND
TX6
D T R 6#
R T S 6#
R I6#
C D 6#
D S R 6#
C T S 6#
RX6
TX7
D T R 7#
R T S 7#
R I7#
C D 7#
D S R 7#
C T S 7#
RX7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
RST#
16/68#
VCC
GND
D7
D6
D5
D4
D3
D2
D1
D0
IOW#
TMRCK
ENIR
INT#
VCC
GND
IOR#
A7
A6
A5
A4
A3
A2
A1
A0
VCC
GND
CS#
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
X T A L2
X T A L1
GND
VCC
TX1
D T R 1#
R T S 1#
R I1#
C D 1#
D S R 1#
C T S 1#
RX1
TX0
D T R 0#
R T S 0#
R I0#
C D 0#
D S R 0#
C T S 0#
RX0
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
XR16L788CQ
14x20x3mm 100-QFP
0°C to +70°C
XR16L788IQ
14x20x3mm 100-QFP
-40°C to +85°C
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XR16L788 OCTAL UART
REV. 1.1.4
PIN DESCRIPTIONS
NAME
PIN #
TYPE
DESCRIPTION
Address data lines [7:0]. A0:A3 selects individual UART’s 16 configuration registers, A4:A6 selects UART channel 0 to7, and A7 selects the global device
configuration registers.
DATA BUS INTERFACE
A7-A0
20-27
I
D7:D0
5-12
IO
IOR#
19
I
When 16/68# pin is at logic 1, it selects Intel bus interface and this input is
read strobe (active low). The falling edge instigates an internal read cycle and
retrieves the data byte from an internal register pointed by the address lines
[A7:A0], places it on the data bus to allow the host processor to read it on the
leading edge.
When 16/68# pin is at logic 0, it selects Motorola bus interface and this input
should be connected to VCC.
IOW#
13
I
When 16/68# pin is at logic 1, it selects Intel bus interface and this input
becomes write strobe (active low). The falling edge instigates the internal
write cycle and the leading edge transfers the data byte on the data bus to an
internal register pointed by the address lines.
When 16/68# pin is at logic 0, it selects Motorola bus interface and this input
becomes read (logic 1) and write (logic 0) signal (R/W#).
CS#
30
I
When 16/68# pin is at logic 1, this input is chip select (active low) to enable
the XR16L788 device.
When 16/68# pin is at logic 0, this input becomes the read and write strobe
(active low) for the Motorola bus interface.
INT#
16
OD
Data bus lines (7:0] (bidirectional).
Global interrupt output from XR16L788 (open drain, active low). This output
requires an external pull-up resistor (47K-100K ohms) to operate properly. It
may be shared with other devices in the system to form a single interrupt line
to the host processor and have the software driver polls each device for the
interrupt status.
MODEM OR SERIAL I/O INTERFACE
TX0
93
O
UART channel 0 Transmit Data or infrared transmit data.
RX0
100
I
UART channel 0 Receive Data or infrared receive data. Normal RXD input
idles at logic 1 condition. The infrared pulses can be inverted internally prior
the decoder by FCTR[4].
RTS0#
95
O
UART channel 0 Request to Send or general purpose output (active low).
This port may be used for one of two functions:
1) auto hardware flow control, see EFR bit-6, MCR bits-1 & 2, FCTR bits 0-3
and IER bit-6
2) RS485 half-duplex direction control, see FCTR bit-5, MCR bit-2 and MSR
bits 4-7.
CTS0#
99
I
UART channel 0 Clear to Send or general purpose input (active low). It can be
used for auto hardware flow control, see EFR bit-7, MCR bit-2 and IER bit-7.
DTR0#
94
O
UART channel 0 Data Terminal Ready or general purpose output (active low).
This port may be used one of two functions.
1) auto hardware flow control, see EFR bit-6, FCTR bits-0 to 3, MCR bits-0 &
2, and IER bit-6
2) RS485 half-duplex direction control, see FCTR bit-5, MCR bit-2 and MSR
bit 4-7.
DSR0#
98
I
UART channel 0 Data Set Ready or general purpose input (active low). It can
be used for auto hardware flow control, see EFR bit-7, MCR bit-2 and IER bit7.
CD0#
97
I
UART channel 0 Carrier Detect or general purpose input (active low).
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XR16L788 OCTAL UART
REV. 1.1.4
NAME
PIN #
TYPE
RI0#
96
I
DESCRIPTION
UART channel 0 Ring Indicator or general purpose input (active low).
TX1
85
O
UART channel 1 Transmit Data or infrared transmit data.
RX1
92
I
UART channel 1 Receive Data or infrared receive data. Normal RXD input
idles at logic 1 condition. The infrared pulses can be inverted internally prior
the decoder by FCTR[4].
RTS1#
87
O
UART channel 1 Request to Send or general purpose output (active low). See
description of RTS0# pin.
CTS1#
91
I
UART channel 1 Clear to Send or general purpose input (active low). See
description of CTS0# pin.
DTR1#
86
O
UART channel 1 Data Terminal Ready or general purpose output (active low).
See description of DTR0# pin.
DSR1#
90
I
UART channel 1 Data Set Ready or general purpose input (active low). See
description of DSR0# pin.
CD1#
89
I
UART channel 1 Carrier Detect or general purpose input (active low).
RI1#
88
I
UART channel 1 Ring Indicator or general purpose input (active low).
TX2
80
O
UART channel 2 Transmit Data or infrared transmit data.
RX2
73
I
UART channel 2 Receive Data or infrared receive data. Normal RXD input
idles at logic 1 condition. The infrared pulses can be inverted internally prior
the decoder by FCTR[4].
RTS2#
78
O
UART channel 2 Request to Send or general purpose output (active low). See
description of RTS0# pin.
CTS2#
74
I
UART channel 2 Clear to Send or general purpose input (active low). See
description of CTS0# pin.
DTR2#
79
O
UART channel 2 Data Terminal Ready or general purpose output (active low).
See description of DTR0# pin.
DSR2#
75
I
UART channel 2 Data Set Ready or general purpose input (active low). See
description of DSR0# pin.
CD2#
76
I
UART channel 2 Carrier Detect or general purpose input (active low).
RI2#
77
I
UART channel 2 Ring Indicator or general purpose input (active low).
TX3
72
O
UART channel 3 Transmit Data or infrared transmit data.
RX3
65
I
UART channel 3 Receive Data or infrared receive data. Normal RXD input
idles at logic 1 condition. The infrared pulses can be inverted internally prior
the decoder by FCTR[4].
RTS3#
70
O
UART channel 3 Request to Send or general purpose output (active low). See
description of RTS0# pin.
CTS3#
66
I
UART channel 3 Clear to Send or general purpose input (active low). See
description of CTS0# pin.
DTR3#
71
O
UART channel 3 Data Terminal Ready or general purpose output (active low).
See description of DTR0# pin.
DSR3#
67
I
UART channel 3 Data Set Ready or general purpose input (active low). See
description of DSR0# pin.
CD3#
68
I
UART channel 3 Carrier Detect or general purpose input (active low).
RI3#
69
I
UART channel 3 Ring Indicator or general purpose input (active low).
TX4
64
O
UART channel 4 Transmit Data or infrared transmit data.
RX4
57
I
UART channel 4 Receive Data or infrared receive data. Normal RXD input
idles at logic 1 condition. The infrared pulses can be inverted internally prior
the decoder by FCTR[4].
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XR16L788 OCTAL UART
REV. 1.1.4
NAME
PIN #
TYPE
DESCRIPTION
RTS4#
62
O
UART channel 4 Request to Send or general purpose output (active low). See
description of RTS0# pin.
CTS4#
58
I
UART channel 4 Clear to Send or general purpose input (active low). See
description of CTS0# pin.
DTR4#
63
O
UART channel 4 Data Terminal Ready or general purpose output (active low).
See description of DTR0# pin.
DSR4#
59
I
UART channel 4 Data Set Ready or general purpose input (active low). See
description of DSR0# pin.
CD4#
60
I
UART channel 4 Carrier Detect or general purpose input (active low).
RI4#
61
I
UART channel 4 Ring Indicator or general purpose input (active low).
TX5
56
O
UART channel 5 Transmit Data or infrared transmit data.
RX5
49
I
UART channel 5 Receive Data or infrared receive data. Normal RXD input
idles at logic 1 condition. The infrared pulses can be inverted internally prior
the decoder by FCTR[4].
RTS5#
54
O
UART channel 5 Request to Send or general purpose output (active low). See
description of RTS0# pin.
CTS5#
50
I
UART channel 5 Clear to Send or general purpose input (active low). See
description of CTS0# pin.
DTR5#
55
O
UART channel 5 Data Terminal Ready or general purpose output (active low).
See description of DTR0# pin.
DSR5#
51
I
UART channel 5 Data Set Ready or general purpose input (active low). See
description of DSR0# pin.
CD5#
52
I
UART channel 5 Carrier Detect or general purpose input (active low).
RI5#
53
I
UART channel 5 Ring Indicator or general purpose input (active low).
TX6
46
O
UART channel 6 Transmit Data or infrared transmit data.
RX6
39
I
UART channel 6 Receive Data or infrared receive data. Normal RXD input
idles at logic 1 condition. The infrared pulses can be inverted internally prior
the decoder by FCTR[4].
RTS6#
44
O
UART channel 6 Request to Send or general purpose output (active low). See
description of RTS0# pin.
CTS6#
40
I
UART channel 6 Clear to Send or general purpose input (active low). See
description of CTS0# pin.
DTR6#
45
O
UART channel 6 Data Terminal Ready or general purpose output (active low).
See description of DTR0# pin.
DSR6#
41
I
UART channel 6 Data Set Ready or general purpose input (active low). See
description of DSR0# pin.
CD6#
42
I
UART channel 6 Carrier Detect or general purpose input (active low).
RI6#
43
I
UART channel 6 Ring Indicator or general purpose input (active low).
TX7
38
O
UART channel 7 Transmit Data or infrared transmit data.
RX7
31
I
UART channel 7 Receive Data or infrared receive data. Normal RXD input
idles at logic 1 condition. The infrared pulses can be inverted internally prior
the decoder by FCTR[4].
RTS7#
36
O
UART channel 7 Request to Send or general purpose output (active low). See
description of RTS0# pin.
CTS7#
32
I
UART channel 7 Clear to Send or general purpose input (active low). See
description of CTS0# pin.
DTR7#
37
O
UART channel 7 Data Terminal Ready or general purpose output (active low).
See description of DTR0# pin.
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XR16L788 OCTAL UART
REV. 1.1.4
NAME
PIN #
TYPE
DESCRIPTION
DSR7#
33
I
UART channel 7 Data Set Ready or general purpose input (active low). See
description of DSR0# pin.
CD7#
34
I
UART channel 7 Carrier Detect or general purpose input (active low).
RI7#
35
I
UART channel 7 Ring Indicator or general purpose input (active low).
ANCILLARY SIGNALS
XTAL1
82
I
Crystal or external clock input.
XTAL2
81
O
Crystal or buffered clock output.
TMRCK
14
I
16-bit timer/counter external clock input.
ENIR
15
I
Infrared mode enable (active high). This pin is sampled during power up, following a hardware reset (RST#) or soft-reset (register RESET). It can be used
to start up all 8 UARTs in the infrared mode. The sampled logic state is transferred to MCR bit-6 in the UART.
RST#
1
I
Reset (active low). The configuration and UART registers are reset to default
values, see Table-18.
16/68#
2
I
Intel or Motorola data bus interface select. Logic one selects Intel bus interface and logic zero selects Motorola interface. This input affects the functionality of IOR#, IOW# and CS# pins.
VCC
3,17,28,48,84
+3.3V supply with 5V tolerant inputs.
GND
4,18,29,47,83,
Power supply common, ground.
NOTE: Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.
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XR16L788 OCTAL UART
REV. 1.1.4
DESCRIPTION
or 3.125Mbps in the 16X rate. The XR16L788 is a 5V
and 3.3V device with 5 volt tolerant inputs.
The XR16L788 (788) integrates the functions of 8 enhanced 16550 UARTs, a general purpose 16-bit timer/counter and an on-chip oscillator. The device configuration registers include a set of four consecutive
interrupt source registers that provides interrupt-status for all 8 UARTs, timer/counter and a sleep wake
up indicator. Each UART channel has its own 16550
UART compatible configuration register set for individual channel control, status, and data transfer. Additionally, each UART channel has 64-byte of transmit
and receive FIFOs, automatic RTS/CTS or DTR/DSR
hardware flow control with hysteresis control, automatic Xon/Xoff and special character software flow
control, programmable transmit and receive FIFO
trigger levels, FIFO level counters, infrared encoder
and decoder (IrDA ver. 1.0), programmable baud rate
generator with a prescaler of divide by 1 or 4, and data rate up to 6.25 Mbps with 8X sampling clock rate
1.0 XR16L788 REGISTERS
The XR16L788 octal UART register set consists of
the Device Configuration Registers that are accessible directly from the data bus for programming general operating conditions of the UARTs and monitoring
the status of various functions. These functions include all 8 channel UART’s interrupt control and status, 16-bit general purpose timer control and status,
sleep mode, soft-reset, and device identification and
revision. Also, each UART channel has its own set of
internal UART Configuration Registers for its own operation control, status reporting and data transfer.
These registers are mapped into a 256-byte of the
data memory address space. The following paragraphs describe all the registers in detail.
FIGURE 3. THE XR16L788 REGISTERS
0 x0 0 -0 F
C hannel 0
0 x1 0 -1 F
C hannel 1
0 x2 0 -2 F
C hannel 2
0 x3 0 -3 F
C hannel 3
8 -b it D a ta
Bus
In te rfa ce
0 x4 0 -4 F
C hannel 4
U A R T [7 :0 ] C o n fig u ra tio n
R e g iste rs
1 6 5 5 0 C o m p a tib le a n d E X A R
E n h a n ce d R e g iste rs
0 x5 0 -5 F
C hannel 5
0 x6 0 -6 F
C hannel 6
0 x7 0 -7 F
C hannel 7
IN T 0 , IN T 1 , IN T 2 ,
IN T 3 , T IM E R ,
SLEEP, R ESET
0 x8 0 -8 F
D e vice C o n fig u ra tio n R e g iste rs
8 ch a n n e l In te rru p ts,
1 6 -b it T im e r/C o u n te r,
S le e p , R e se t, D V ID , D R E V
7 5 8R E G S -1
1.1 DEVICE CONFIGURATION REGISTER SET
The device configuration registers are directly accessible from the bus. This provides easy programming
of general operating parameters to the 788 UART
and for monitoring the status of various functions.
The device configuration registers are mapped onto
address 0x80-8F as shown on the register map in
Table 2 and Figure 3. These registers provide global
controls and status of all 8 channel UARTs that include interrupt status, 16-bit general purpose timer
control and status, 8X or 16X sampling clock, sleep
mode control, soft-reset control, simultaneous UART initialization, and device identification and revision.
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XR16L788 OCTAL UART
REV. 1.1.4
.
TABLE 1: XR16L788 REGISTER SETS
ADDRESS [A7:A0]
UART CHANNEL SPACE
REFERENCE
COMMENT
0x00 - 0x0F
UART channel 0 Registers
(Table 7 & 8)
First 8 registers are 16550 compatible
0x10 - 0x1F
UART channel 1 Registers
(Table 7 & 8)
0x20 - 0x2F
UART channel 2 Registers
(Table 7 & 8)
0x30 - 0x3F
UART channel 3 Registers
(Table 7 & 8)
0x40 - 0x4F
UART channel 4 Registers
(Table 7 & 8)
0x50 - 0x5F
UART channel 5 Registers
(Table 7 & 8)
0x60 - 0x6F
UART channel 6 Registers
(Table 7 & 8)
0x70 - 0x7F
UART channel 7 Registers
(Table 7 & 8)
0x80 - 0x8F
Device Configuration Registers
(Table 2)
Interrupt registers and global controls
TABLE 2: DEVICE CONFIGURATION REGISTERS
ADDRESS READ/
REGISTER
[A7:A0] WRITE
0x80
R
INT Source
0x81
R
INT 1
0x82
R
INT 2
0x83
R
INT 3
0x84
0x85
R/W TIMER CTRL
R
TIMER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UART 7
UART 6
UART 5
UART 4
UART 3
UART 2
UART 1
UART 0
UART 2 source
bit 1
bit 0
UART 5
bit 0
UART 1 interrupt source
bit 2
bit 1
bit 0
UART 4 interrupt source
bit 2
bit 1
bit 0
UART 7 interrupt source
bit 2
bit 1
bit 0
UART 0 interrupt source
bit 2
bit 1
bit 0
UART 3 interrupt source
bit 2
bit 1
bit 0
UART 6 interrupt source
bit 2
bit 1
bit 0
UART 2
bit 2
UART 5 source
bit 2
bit 1
0
0
0
0
clock
source
function
select
start timer
enable
timer INT
0
0
0
0
0
0
0
0
0x86
R/W TIMER LSB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0x87
R/W TIMER MSB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0x88
R/W
8X MODE
UART 7
UART 6
UART 5
UART 4
UART 3
UART 2
UART 1
UART 0
0x89
R
REG 1
0
0
0
0
0
0
0
0
0x8A
W
RESET
Reset
UART 7
Reset
UART 6
Reset
UART 5
Reset
UART 4
Reset
UART 3
Reset
UART 2
Reset
UART 1
Reset
UART 0
0x8B
R/W
SLEEP
Enable
sleep
UART 7
Enable
sleep
UART 6
Enable
sleep
UART 5
Enable
sleep
UART 4
Enable
sleep
UART 3
Enable
sleep
UART 2
Enable
sleep
UART 1
Enable
sleep
UART 0
0x8C
R
DREV
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0x8D
R
DVID
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0x8E
R/W
REG 2
0
0
0
0
0
0
0
write to all
UARTs
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XR16L788 OCTAL UART
REV. 1.1.4
INT0 CHANNEL INTERRUPT INDICATOR:
1.1.1 The Global Interrupt Source Registers
The XR16L788 has a global interrupt source register
set that consists of 4 consecutive registers [INT0,
INT1, INT2 and INT3]. The four registers are in the
device configuration register address space.
INT3
[0x00]
INT2
[0x00]
INT1
[0x00]
IN T0 Register
In d ivid u a l U A R T C h a n n e l In te rru p t S ta tu s
INT0
[0x00]
All four registers default to logic zero (as indicated in
square braces) for no interrupt pending. All 8 channel
interrupts are enabled or disabled in each channel’s
IER register. INT0 shows individual status for each
channel while INT1, INT2 and INT3 show the details
of the source of each channel’s interrupt with its
unique 3-bit encoding. Figure 4 shows the 4 interrupt
registers in sequence for clarity. The 16-bit timer and
sleep wake-up interrupts are masked in the device
configuration registers, TIMERCNTL and SLEEP. An interrupt is generated (if enabled) by the 788 when
awakened from sleep if all 8 channels were placed in
the sleep mode previously.
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C h -7
C h -6
C h -5
C h -4
C h -3
C h -2
C h -1
C h -0
requested for service. For example, bit-0 represents
channel 0 and bit-7 indicates channel 7. Logic one indicates the channel N [7:0] has called for service. The
interrupt bit clears after reading the appropriate register of the interrupting UART channel register (ISR,
LSR and MSR). See Table 9 for interrupt clearing details.
INT1, INT2 AND INT3 INTERRUPT SOURCE LOCATOR
INT3, INT2 and INT1 provide a 24-bit (3 bits per
channel) encoded interrupt indicator. Table 3 shows
the 3 bit encoding and their priority order. The 16-bit
Timer time-out interrupt will show up only as a channel 0 interrupt. For other channels, interrupt 7 is reserved.
Each bit gives an indication of the channel that has
.
FIGURE 4. THE GLOBAL INTERRUPT REGISTERS, INT0, INT1, INT2 AND INT3
Interrupt Registers,
INT0, INT1, INT2 and INT3
INT3 Register
C h a n n e l-7
B it
2
B it
1
INT2 Register
C h a n n e l-6
B it
0
B it
2
B it
1
C h a n n e l-5
B it
0
B it
2
B it
1
C h a n n e l-4
B it
0
B it
2
B it
1
INT1 Register
C h a n n e l-3
B it
0
B it
2
B it
1
C h a n n e l-2
B it
0
B it
2
B it
1
C h a n n e l-1
B it
0
B it
2
C h -7 C h -6 C h -5
B it-7
9
B it-6
B it-5
B it
1
C h a n n e l-0
B it
0
B it
2
INT0 Register
Ch- ChC h -4
3
2
B it-4
B it-3
B it-2
B it
1
B it
0
C h -1 C h -0
B it-1
B it-0
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XR16L788 OCTAL UART
REV. 1.1.4
TABLE 3: UART CHANNEL [7:0] INTERRUPT SOURCE ENCODING AND CLEARING
PRIORITY BIT2BIT1 BIT0
INTERRUPT SOURCE(S) AND CLEARING
x
0
0
0
None
1
0
0
1
RXRDY & RX Line Status (logic OR of LSR[4:1]). RXRDY INT clears by reading data in the RX
FIFO until it falls below the trigger level; RX Line Status INT cleared after reading LSR register.
2
0
1
0
RXRDY Time-out: Cleared same way as RXRDY INT.
3
0
1
1
TXRDY, THR or TSR (auto RS485 mode) empty, clears after reading ISR register.
4
1
0
0
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon or special character detected. The first two clears
after reading MSR register; Xoff/Xon or special char. detect INT clears after reading ISR register.
5
1
0
1
Reserved.
6
1
1
0
Reserved.
7
1
1
1
TIMER Time-out, shows up as a channel 0 INT. It clears after reading the TIMERCNTL register.
Reserved in other channels.
1.1.2 General Purpose 16-bit Timer/Counter.
[TIMERMSB, TIMELSB, TIMER, TIMECNTL]
(DEFAULT 0XXX-XX-00-00)
A 16-bit down-count timer for general purpose timer
or counter. Its clock source may be selected from internal crystal oscillator or externally on pin TMRCK.
The timer can be set to be a single-shot for a onetime event or re-triggerable for a periodic event. An
interrupt may be generated in the INT Register when
the timer times out. It is controlled through 4 configuration registers [TIMERCNTL, TIMER, TIMELSB,
TIMERMSB]. These registers provide start/stop and
re-triggerable or one-shot operation. The time-out
output of the Timer can be set to generate an interrupt for system or event alarm.
FIGURE 5. TIMER/COUNTER CIRCUIT.
T IM E R M S B a n d T IM E R L S B
(1 6 -b it V a lu e )
TMRCK
O SC. CLO C K
T IM E R C N T L [3 ]
T IM E R C N T L [1 ]
T IM E R C N T L [2 ]
T IM E R C N T L [0 ]
1
0
T im e -o u t
1 6 -B it
T im e r/C o u n te r
C lo c k
S e le c t
1
0
T im e r In te rru p t, C h -0 IN T = 7
N o In te rru p t
R e -trig g e r
0
S ta rt/S to p
1
S in g le /R e -trig g e ra b le
S in g le -s h o t
T im e r In te rru p t E n a b le
TABLE 4: TIMER CONTROL REGISTER
TIMERCNTL [0]
Logic zero (default) disables Timer-Counter interrupt and logic one enables the interrupt, reading the
TIMERCNTL clears the interrupt.
TIMERCNLT [1]
Logic zero (default) stops/pauses the timer and logic one starts/re-starts the timer/counter.
TIMERCNTL [2]
Logic zero (default) selects re-trigger timer function and logic one selects one-shot (timer function.
TIMERCNTL [3]
Logic zero (default) selects internal and logic one selects external clock to the timer/counter.
TIMERCNTL [7:4]
Reserved (defaults to zero).
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XR16L788 OCTAL UART
REV. 1.1.4
TIM E R C N TL R egister
B it-7 B it-6
R svd
R svd
B it-5
B it-4
B it-3
R svd
R svd
C lo c k
S in g le /
S e le c t R e -trig g e r
TIMER [7:0] (default 0x00): Reserved.
B it-2
B it-1
S ta rt/
S to p
B it-0
IN T
E n a b le
TIMERLSB with most-significant-bit being bit [7] in
TIMERMSB. Reading the TIMERCNTL register will
clear its interrupt. Default value is zero upon powerup and reset.
TIMERMSB [7:0] and TIMERLSB [7:0]
TIMERMSB and TIMERLSB form a 16-bit value. The
least-significant bit of the timer is being bit [0] of the
1 6 -B it T im e r/C o u n te r P ro g ra m m a b le R e g iste rs
TIM ERM SB Register
B it-15
B it-14
B it-13
B it-12
B it-11
B it-10
TIM ERLSB Register
B it-9
B it-8
B it-7
1.1.3 8XMODE [7:0] (default 0x00)
Each bit selects 8X or 16X sampling rate for that
UART channel, bit-0 is channel 0. Logic 0 (default)
selects normal 16X sampling with logic one selects
8X sampling rate. Transmit and receive data rates will
double by selecting 8X.
B it-4
B it-3
B it-2
B it-1
B it-0
1.1.6 SLEEP [7:0] (default 0x00)
The 8-bit Sleep register enables each UART separately to enter Sleep mode. Sleep mode reduces
power consumption when the system needs to put
the UART(s) to idle. The UART enters sleep mode
when there is no interrupt pending. When all 8 UARTs
are put to sleep, the on-chip oscillator shuts off to further conserve power. In this case, the octal UART is
awaken by any of the UART channel on from a receive data byte or a change on the serial port. The
UART is ready after 32 crystal clocks to ensure full
functionality. Also, a special interrupt is generated
with an indication of no pending interrupt. Logic 0 (default) and logic 1 disable and enable sleep mode respectively.
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Ch-7 Ch-6 Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
REGA [15:8] is reserved (default 0x00)
REGA [7:0] IS RESERVED
(default 0x00)
1.1.5
B it-5
logic 1 to perform a reset to that channel. All registers
in that channel will be reset to the default condition,
see Table 15 for details. As an example, bit-0 =1 resets UART channel 0 with bit-7=1 resets channel 7.
8XMODE Register
Individual UART Channel 8X Clock Mode Enabl e
1.1.4
B it-6
RESET [7:0] (default 0x00)
S LE EP Register
Individual U AR T C hannel S leep Enable
RESET Register
Individual UART Channel Reset Enable
C h-7 C h-6 C h-5 C h-4 C h-3 C h-2 C h-1 C h-0
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0
Ch-7 Ch-6 Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
1.1.7 Device Identification and Revision
There are 2 internal registers that provide device
identification and revision, DVID and DREV registers.
The 8-bit content in the DVID register provides device
The 8-bit Reset register [RESET] provides the software with the ability to reset the UART(s) when there
is a need. Each bit is self-resetting after it is written a
11
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XR16L788 OCTAL UART
REV. 1.1.4
externally between the XTAL1 and XTAL2 pins (see
identification. A return value of 0x28 from this register
indicates the device is a XR16L788. The DREV register returns a 8-bit value of 0x01 for revision A, 0x02
for revision B and so on. This information is very useful to the software driver for identifying which device it
is communicating with and to keep up with revision
changes.
DVID [7:0] default 0x28)
Figure 6). Alternatively, an external clock can be con-
nected to the XTAL1 pin to clock the internal 8 baud
rate generators for standard or custom rates. Typically, the oscillator connections are shown in Figure 6.
For further reading on oscillator circuit please see application note DAN108 on EXAR’s web site.
FIGURE 6. TYPICAL OSCILLATOR CONNECTIONS
Device identification for the type of UART. The upper
nibble indicates it is a XR16L78x series with lower
nibble indicating the number of channels.
Examples:
R =3 0 0 K to 40 0 K
XR16L788 = 0x28
XR16L784 = 0x24
XTAL1
DREV [7:0] (default (0x01)
Revision number of the XR16L788. A 0x01 represents "revision-A" with 0x02 for rev-B and so forth.
C1
2 2-4 7 pF
1.1.8 REGB [7:0] (default 0x00)
REGB register provides a control for simultaneous
write to all 8 UARTs configuration registers or individually. This is very useful for device initialization in the
power up and reset routines.
REGB[0]
XTAL2
C2
2 2-4 7 pF
3.0 TRANSMIT AND RECEIVE DATA
Each UART channel has a transmit holding register
(THR) and a receive holding register (RHR). The
THR and RHR registers are 16550 compatible so
their access is limited to 8-bit format. The software
driver must separately read the LSR content for the
associated error flags before reading the data byte.
Logic 0 (default) write to each UART
configuration registers individually.
Logic 1 enables simultaneous write to
all 8 UARTs configuration register. Useful during device initialization.
REGB[7:1]
1 4.7 45 6
MHz
3.1 FIFO DATA LOADING AND UNLOADING
THROUGH THE UART CHANNEL REGISTERS, THR AND RHR.
The THR and RHR register addresses for channel 0
to channel 7 is shown in Table 5 below. The THR and
RHR for channels 0 to 7 are located at address 0x00,
0x10, 0x20, 0x30, 0x40, 0x50, 0x60 and 0x70 respectively. Transmit data byte is loaded to the THR when
writing to that address and receive data is unloaded
from the RHR register when reading that address.
Both THR and RHR registers are 16C550 compatible
in 8-bit format, so each bus operation can only write
or read in bytes.
Reserved
2.0 CRYSTAL OSCILLATOR / BUFFER
The 788 includes an on-chip oscillator (XTAL1 and
XTAL2). The crystal oscillator provides the system
clock to the Baud Rate Generators (BRG) in each of
the 8 UARTs, the 16-bit general purpose timer/
counter and internal logics. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin
being the output. For programming details, see “Programmable Baud Rate Generator” on page 13.
The on-chip oscillator is designed to use an industry
standard microprocessor crystal (parallel resonant
with 10-22 pF capacitance load, 100ppm) connected
12
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XR16L788 OCTAL UART
REV. 1.1.4
.
TABLE 5: TRANSMIT AND RECEIVE DATA REGISTER, 16C550 COMPATIBLE
TH R and R H R A dd ress Locations F or C H0 to C H 7 (16C 550 Co m patib le)
C H 0 0 x0 0 W rite T H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C H 0 0 x0 0 R e a d R H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C H 1 0 x1 0 W rite T H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C H 1 0 x1 0 R e a d R H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C H 2 0 x2 0 W rite T H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C H 2 0 x2 0 R e a d R H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C H 3 0 x3 0 W rite T H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C H 3 0 x3 0 R e a d R H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C H 4 0 x4 0 W rite T H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C H 4 0 x4 0 R e a d R H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C H 5 0 x5 0 W rite T H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C H 5 0 x5 0 R e a d R H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C H 6 0 x6 0 W rite T H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C H 6 0 x6 0 R e a d R H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C H 7 0 x7 0 W rite T H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C H 7 0 x7 0 R e a d R H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
TH R R H R 1
4.0 UART
There are 8 UARTs [channel 7:0] in the 788. Each
has its own 64-byte of transmit and receive FIFO, a
set of 16550 compatible control and status registers,
and a baud rate generator for individual channel data
rate setting. Eight additional registers per UART were
added for the EXAR enhanced features.
register. The MCR register bit-7 sets the prescaler to
divide the input crystal or external clock by 1 or 4. The
output of the prescaler clocks to the BRG. The BRG
further divides this clock by a programmable divisor
between 1 and (216 -1) to obtain a 16X or 8X sampling clock of the serial data rate. The sampling clock
is used by the transmitter for data bit shifting and receiver for data sampling. The BRG divisor (DLL and
DLM registers) defaults to a random value upon power up. Therefore, the BRG must be programmed during initialization to the operating data rate.
4.1 PROGRAMMABLE BAUD RATE GENERATOR
Each UART has its own Baud Rate Generator (BRG)
with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR
13
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XR16L788 OCTAL UART
REV. 1.1.4
FIGURE 7. BAUD RATE GENERATOR
T o O ther
C hannels
D LL and D LM
R egisters
Prescaler
D ivide by 1
M C R Bit-7=0
(default)
C rystal
O sc/
Buffer
XT A L1
XT A L2
Baud R ate
G enerator
Logic
Prescaler
D ivide by 4
16X or 8X
Sam pling
R ate C lock to
T ransm itter
and R eceiver
M C R Bit-7=1
data rates would double. When using a non-standard
data rate crystal or external clock, the divisor value
can be calculated for channel ‘N’ with the following
equation(s).
Programming the Baud Rate Generator Registers
DLM and DLL provides the capability of selecting the
operating data rate. Table 6 shows the standard data
rates available with a 14.7456 MHz crystal or external
clock at 16X clock rate. At 8X sampling rate, these
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), WHEN 8XMODE-BIT N IS 0
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 8), WHEN 8XMODE-BIT N IS 1
TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING
OUTPUT Data Rate OUTPUT Data Rate DIVISOR FOR 16x DIVISOR FOR 16x DLM PROGRAM DLL PROGRAM DATA RATE
MCR Bit-7=1
MCR Bit-7=0
Clock (Decimal) Clock (HEX)
VALUE (HEX) VALUE (HEX) ERROR (%)
100
400
2304
900
09
00
0
600
2400
384
180
01
80
0
1200
4800
192
C0
00
C0
0
2400
9600
96
60
00
60
0
4800
19.2k
48
30
00
30
0
9600
38.4k
24
18
00
18
0
19.2k
76.8k
12
0C
00
0C
0
38.4k
153.6k
6
06
00
06
0
57.6k
230.4k
4
04
00
04
0
115.2k
460.8k
2
02
00
02
0
230.4k
921.6k
1
01
00
01
0
4.2 AUTOMATIC RTS/DTR HARDWARE FLOW CONTROL OPERATION
Automatic RTS/DTR flow control is used to prevent
data overrun to the local receiver FIFO. The RTS#/
DTR# output pin is used to request remote unit to
suspend/resume data transmission. The flow control
features are individually selected to fit specific application requirement (see Figure 8):
- Select RTS (and CTS) or DTR (and DSR) through
MCR bit-2.
- Enable auto RTS/DTR flow control using EFR bit-6.
- The auto RTS/DTR function must be started by asserting RTS/DTR# output pin (MCR bit-0 or 1 to
logic 1 after it is enabled.
14
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XR16L788 OCTAL UART
REV. 1.1.4
- Select CTS (and RTS) or DSR (and DTR) through
MCR bit-2.
- Enable RTS/DTR interrupt through IER bit-6 (after
setting EFR bit-4). The UART issues an interrupt
when the RTS#/DTR# pin makes a transition: ISR
bit-5 will be set to 1.
- Enable auto CTS/DSR flow control using EFR bit-7.
- Enable CTS/DSR interrupt through IER bit-7 (after
setting EFR bit-4). The UART issues an interrupt
when the CTS#/DSR# pin makes a transition: ISR
bit-5 will be set to 1, and UART will suspend TX
transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS#/DSR# input returns to logic
0, indicating more data may be sent.
- Select Hysteresis values when used with programmable RX FIFO trigger levels
4.2.1 Auto CTS/DSR Flow Control
Automatic CTS/DSR flow control is used to prevent
data overrun to the remote receiver FIFO. The CTS/
DSR pin is monitored to suspend/restart local transmitter. The flow control features are individually selected to fit specific application requirement (see
Figure 8):
FIGURE 8. AUTO RTS/DTR AND CTS/DSR FLOW CONTROL OPERATION
Local UART
UARTA
Remote UART
UARTB
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
TXB
RTSA#
CTSB#
Auto CTS
Monitor
RXB
Receiver FIFO
Trigger Reached
TXA
Transmitter
CTSA#
Auto CTS
Monitor
RTSA#
RXA
RTSB#
Assert RTS# to Begin
Transmission
1
ON
Auto RTS
Trigger Level
10
OFF
ON
7
2
ON
CTSB#
Transmitter
8
3
11
OFF
ON
TXB
Data Starts
6
Suspend
Restart
9
4
RXA FIFO
INTA
(RXA FIFO
Interrupt)
Receive
Data
RX FIFO
Trigger Level
5
RTS High
Threshold
RTS Low
Threshold
12
RX FIFO
Trigger Level
RTSCTS1
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and continues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its transmit
shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9), UARTA
re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB with RTSB#
and CTSA# controlling the data flow.
15
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XR16L788 OCTAL UART
REV. 1.1.4
4.3 INFRARED MODE
Each UART in the 788 includes the infrared encoder
and decoder compatible to the IrDA (Infrared Data
Association) version 1.0. The input pin ENIR conveniently activates all 8 UART channels to start up in
the infrared mode. This global control pin enables the
MCR bit-6 function in every UART channel register.
After power up or a reset, the software can overwrite
MCR bit-6 if so desired. ENIR and MCR bit-6 also disable the receiver while the transmitter is sending data. This prevents echoed data from reaching the receiver. The global activation ENIR pin prevents the infrared emitter from turning on and drawing large
amount of current while the system is starting up.
When the infrared feature is enabled, the transmit data outputs, TX[7:0], would idle at logic zero level.
Likewise, the RX [7:0] inputs assume an idle level of
logic zero.
The infrared encoder sends out a 3/16 of a bit wide
HIGH-pulse for each “0” bit in the transmit data
stream. This signal encoding reduces the on-time of
the infrared LED, hence reduces the power consumption. See Figure 9 below.
The infrared decoder receives the input pulse from
the infrared sensing diode on RX pin. Each time it
senses a light pulse, it returns a logic zero to the data
bit stream. The decoder also accepts (when FCTR
bit-4 = 1) an inverted IR-encoded input signal. This
option supports active low instead of normal active
high pulse from some infrared modules on the market.
FIGURE 9. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING
D ata B its
Start
T X D ata
0
Stop
C haracter
1
0
1
0
1
0
1
1
0
T ransm it
IR P ulse
(T X P in)
1/2 B it T im e
B it T im e
3/16 B it T im e
IrE ncoder-1
Receive
IR Pulse
(RX pin)
Bit Time
1/16 Clock Delay
1
0
1
0
0
Data Bits
1
1
0
1
Stop
0
Start
RX Data
Character
IRdecoder-1
4.4 INTERNAL LOOPBACK
Each UART channel provides an internal loopback
capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate
normally. Figure 10 shows how the modem port signals are re-configured. Transmit data from the trans-
mit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending. The TX pin
is held at logic 1 or mark condition while RTS# and
DTR# are de-asserted, and CTS#, DSR# CD# and
RI# inputs are ignored.
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XR16L788 OCTAL UART
REV. 1.1.4
FIGURE 10. INTERNAL LOOP BACK
VCC
T X [7 :0 ]
T ra n sm it S h ift
R e g iste r
R e ce ive S h ift
R e g iste r
R X [7 :0 ]
VCC
R T S # [7 :0 ]
RTS#
Modem / General Purpose Control
Logic
Internal Bus Lines and Control Signals
M C R b it-4 = 1
CTS#
C T S # [7 :0 ]
VCC
D T R # [7 :0 ]
DTR#
DSR#
D S R # [7 :0 ]
O P1#
R I#
R I# [7 :0 ]
O P2#
CD#
4.5 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING.
The 8 sets of UART configuration registers are decoded using address lines A4 to A7 as show below.
Address lines A0 to A3 select the 16 registers in each
channel.
The first 8 registers are 16550 compatible with EXAR
enhanced feature registers located on the upper 8
addresses.
17
C D # [7 :0 ]
A7
A6
A5
A4
UART CHANNEL
SELECTION
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
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XR16L788 OCTAL UART
REV. 1.1.4
.
TABLE 7: UART CHANNEL CONFIGURATION REGISTERS.
ADDRESS
REGISTER
READ/WRITE
COMMENTS
A3 A2 A1 A0
16550 COMPATIBLE
0
0
0 0
RHR - Receive Holding Reg
THR - Transmit Holding Register
Read-only
Write-only
LCR[7] = 0
0
0
0 0
DLL - Div Latch Low
Read/Write
LCR[7] = 1
0
0
0 1
DLM - Div Latch High
Read/Write
LCR[7] = 1
0
0
0 1
IER - Interrupt Enable Reg
Read/Write
LCR[7] = 0
0
0
1 0
ISR - Interrupt Status Reg
FCR - FIFO Control Reg
Read-only
Write-only
0
0
1 1
LCR - Line Control Reg
Read/Write
0
1
0 0
MCR - Modem Control Reg
Read/Write
0
1
0 1
LSR - Line Status Reg
reserved
Read-only
Write-only
0
1
1 0
MSR - Modem Status Reg
reserved
Read-only
Write-only
0
1
1 1
SPR - Scratch Pad Reg
Read/Write
ENHANCED REGISTER
1
0
0 0
FCTR
Read/Write
1
0
0 1
EFR - Enhanced Function Reg
Read/Write
1
0
1 0
TXCNT - Transmit FIFO Level Counter
TXTRG - Transmit FIFO Trigger Level
Read-only
Write-only
1
0
1 1
RXCNT - Receive FIFO Level Counter
RXTRG - Receive FIFO Trigger Level
Read-only
Write-only
1
1
0 0
Xoff-1 - Xoff Character 1
Xchar
Write-only
Read-only
1
1
0 1
Xoff-2 - Xoff Character 2
reserved
Write-only
Read-only
1
1
1 0
Xon-1 - Xon Character 1
reserved
Write-only
Read-only
1
1
1 1
Xon-2 - Xon Character 2
reserved
Write-only
Read-only
18
Xon,Xoff Rcvd.
Flags
áç
XR16L788 OCTAL UART
REV. 1.1.4
TABLE 8: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4.
ADDRESS
A3-A0
REG
NAME
0000
RHR
0000
THR
0000
DLL
0001
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
R
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=0
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=0
R/W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=1
DLM
R/W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=1
0001
IER
R/W
0010
ISR
R
0010
FCR
W
0011
LCR
R/W
0100
MCR
R/W
0/
0/
BRG
IR
Prescaler Enable
0101
LSR
R/W
RX FIFO
ERROR
TSR
Empty
0110
MSR
R
CD
RI
DSR
MSR
W
0/
RS485
DLY-3
0/
RS485
DLY-2
0/
RS485
DLY-1
0111
SPR
R/W
Bit-7
Bit-6
Bit-5
1000
FCTR
R/W
TRG
Table
Bit-1
TRG
Table
Bit-0
1001
EFR
R/W
1010
TFCNT
R
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1010
TFTRG
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1011
RFCNT
R
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1011
RFTRG
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1100
XCHAR
R
1100
XOFF1
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1101
XOFF2
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1110
XON1
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1111
XON2
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0
0/
0/
0/
CTS/DSR# RTS/DTR# Xon/Xoff/
Int. Enable Int. Enable Sp. Char.
Int. Enable
0/
FIFOs
Enable
0/
0/
INT
0/
Delta- Xoff/spe- Source
FIFOs
Bit-3
Enable Flow Cntl cial char
0/
0/
0/
0/
RX FIFO RX FIFO TX FIFO TX FIFO
Trigger Trigger Trigger Trigger
Divisor
Enable
Modem RX Line TX Empty RX Data
Status Int. Status Int.
Int.
Int.
Enable Enable Enable Enable
Set TX Set Parity
Break
Even
Parity
0/
Internal
XonAny Lopback
Enable
DMA
Mode
INT
Source
Bit-2
INT
Source
Bit-1
TX FIFO RX FIFO FIFOs
Reset
Reset
Enable
Parity Stop Bits Word
Enable
Length
Bit-1
OP22
INT
Source
Bit-0
Word
Length
Bit-0
OP12/ RTS# Pin DTR# Pin
RTS/DTR Control Control
Flow Sel
THR RX Break RX Fram- RX Parity RX Over- RX Data
Empty
ing Error Error
run
Ready
CTS
Delta
CD#
Delta
RI#
Delta
DSR#
Delta
CTS#
0/
Reserved Reserved Reserved Reserved
RS485
DLY-0
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
User Data
Auto
Invert IR RTS/DTR RTS/DTR RTS/DTR RTS/DTR
RS485 RX Input Hyst Bit-3 Hyst Bit-2 Hyst Bit-1 Hyst Bit-0
Enable
Auto
Auto
Special
CTS/DSR RTS/DTR Char
Enable Enable
Select
Enable
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5]
MSR[7:4]
Software Software Software Software
Flow Cntl Flow Cntl Flow Cntl Flow Cntl
Bit-3
Bit-2
Bit-1
Bit-0
Xon Det. Xoff Det. Self-clear
Indicator Indicator after read
19
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XR16L788 OCTAL UART
REV. 1.1.4
NOTE 2: MCR bits 2 and 3 (OP1 and OP2 outputs) are not
available in the XR16L788. They are present for 16C550
compatibility during Internal loopback, see Figure 10.
writes transmit data byte to the THR to be converted
into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit0) becomes first data bit to go out. The THR is also
the input register to the transmit FIFO of 64 bytes
when FIFO operation is enabled by FCR bit-0. Every
time a write operation is made to the transmit holding
register, its FIFO data pointer is automatically
bumped to the next sequential data location. A THR
empty interrupt can be generated when IER bit-1 is
set to logical 1.
4.6 TRANSMITTER
The transmitter section comprises of 64 bytes of
FIFO, a byte-wide Transmit Holding Register (THR)
and an 8-bit Transmit Shift Register (TSR). THR receives a data byte from the host (non-FIFO mode) or
a data byte from the FIFO when the FIFO is enabled
by FCR bit-0. TSR shifts out every data bit with the
16X or 8X internal clock. A bit time is 16 or 8 clock periods. The transmitter sends the start bit followed by
the number of data bits, inserts the proper parity bit if
enabled, and adds the stop bit(s). The status of the
THR and TSR are reported in the Line Status Register (LSR bit-5 and bit-6).
4.6.2 Transmitter Operation in non-FIFO
The host loads transmit data to THR one character at
a time. The THR empty flag (LSR bit-5) is set when
the data byte is transferred to TSR. THR flag can
generate a transmit empty interrupt (ISR bit-1) when
it is enabled by IER bit-1. The TSR flag (LSR bit-6) is
set when TSR becomes completely empty.
4.6.1 Transmit Holding Register (THR)
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
FIGURE 11. TRANSMITTER OPERATION IN NON-FIFO MODE
Data
Byte
16X or 8X
Clock
(8XMODE
Register)
Transmit
Holding
Register
(THR)
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
Transmit Shift Register (TSR)
M
S
B
L
S
B
TXNOFIFO1
4.6.4 Auto RS485 Operation
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by
FCTR bit-5. It de-asserts RTS# or DTR# after a specified delay indicated in MSR[7:4] following the last
stop bit of the last character that has been transmitted. This helps in turning around the transceiver to receive the remote station’s response. The delay optimizes the time needed for the last transmission to
reach the farthest station on a long cable network before switching off the line driver. This delay prevents
undesirable line signal disturbance that causes signal
degradation. The auto RS485 half-duplex direction
control also changes the transmitter empty interrupt
to TSR empty instead of THR empty.
4.6.3 Transmitter Operation in FIFO
The host may fill the transmit FIFO with up to 64
bytes of transmit data. The THR empty flag (LSR bit5) is set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR
bit-1) when the amount of data in the FIFO falls below
its programmed trigger level (see TXTRG register).
The transmit empty interrupt is enabled by IER bit-1.
The TSR flag (LSR bit-6) is set when TSR becomes
completely empty. Furthermore, with the RS485 halfduplex direction control enabled (FCTR bit-5=1), the
source of the transmit empty interrupt changes to
TSR empty instead of THR empty. This is to ensure
the RTS# output is not changed until the last stop bit
of the last character is shifted out.
20
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XR16L788 OCTAL UART
REV. 1.1.4
FIGURE 12. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
T ransm it
D ata Byte
T ransm it
F IF O
(64-B yte)
F low C ontrol C haracters
(X off1/2 and X on1/2 R eg.
T H R Interrupt (IS R bit-1) falls
below P rogram m ed T rigger
Level (T X T R G ) and then
w hen becom es em pty. F IF O
is E nabled by F C R bit-0=1
A uto S oftw are F low C ontrol
16X or 8X C lock
(8X M O D E R egister)
T ransm it D ata S hift R egister
(T S R )
A uto C T S F low C ontrol (C T S # pin)
T X F IF O 1
4.8 REGISTERS
4.7 RECEIVER
The receiver section contains an 8-bit Receive Shift
Register (RSR) and a byte-wide Receive Holding
Register (RHR). The RSR uses the 16X or 8X clock
for timing. It verifies and validates every bit on the incoming character in the middle of each data bit. On
the falling edge of a start or false start bit, an internal
receiver counter starts counting at the 16X (or 8X)
clock rate. After 8 (or 4) clocks the start bit period
should be at the center of the start bit. At this time the
start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents
the receiver from assembling a false character. The
rest of the data bits and stop bits are sampled and
validated in this same manner to prevent false framing. If there were any error(s), they are reported in the
LSR register bits 1- 4. Upon unloading the receive data byte from RHR, the receive FIFO pointer is
bumped and the error flags are immediately updated
to reflect the status of the data byte in RHR register.
RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the
FIFO trigger level. Furthermore, data delivery to the
host is guaranteed by a receive data ready time-out
function when receive data does not reach the receive FIFO trigger level. This time-out delay is 4 word
lengths as defined by LCR[1,0] plus 12 bits time. The
RHR interrupt is enabled by IER bit-0.
4.8.1 Receive Holding Register (RHR)
The receive holding register is a 8-bit register that
holds a receive data byte from the receive shift register (RSR). It provides the receive data interface to the
host processor. The host reads the receive data byte
on this register whenever a data byte is transferred
from the RSR. RHR also part of the receive FIFO of
64 bytes by 11-bit wide, 3 extra bits are for the error
flags to be in LSR register. When the FIFO is enabled
by FCR bit-0, it acts as the first-out register of the
FIFO as new data are put over the first-in register. Every time a read operation is made to the receive holding register, its FIFO data pointer is automatically
bumped to the next sequential data location. Also, the
error flags associated with the data byte are immediately updated onto the line status register (LSR) bits
1-4.
4.8.2 Baud Rate Generator Divisors (DLL and
DLM)
The Baud Rate Generator (BRG) is a 16-bit counter
that generates the data rate for the transmitter and receiver. The rate is programmed through registers DLL
and DLM which are only accessible when LCR bit-7 is
set to logic 1. See Programmable Baud Rate Generator section for more detail.
21
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XR16L788 OCTAL UART
REV. 1.1.4
FIGURE 13. RECEIVER OPERATION IN NON-FIFO MODE
1 6 X o r 8 X C lo c k
(8 X M O D E R e g is te r)
R e c e iv e
D a ta B y te
a n d E rro rs
R e c e iv e D a ta S h ift
R e g is te r (R S R )
E rror
F la g s in
LS R bits
4:2
D a ta B it
V a lid a tio n
R e c e iv e D a ta
H o ld in g R e g is te r
(R H R )
R e c e iv e D a ta C h a ra c te rs
R H R In te rru p t (IS R b it-2 )
R X F IF O 1
FIGURE 14. RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE
1 6 X o r 8 X S a m p lin g
C lo ck (8 X M O D E R e g .)
R e ce ive D a ta S h ift
R e g iste r (R S R )
D a ta B it
V a lid a tio n
R e ce ive D a ta C ha ra cte rs
E xa m p le :
- F IF O trig g e r le ve l se t a t 4 8 b yte s
- R T S /D T R h ya ste re sis se t a t +/-8 ch a rs.
6 4 b yte s b y 1 1 b it w id e F IF O
Error Flags
(64-sets)
D a ta fa lls to 4 0
R e ce ive D a ta
F IF O
(6 4 -b yte )
F IF O T rig g e r= 4 8
R e ce ive D a ta
B yte a n d E rro rs
Error Flags in
LSR bits 4:2
D a ta fills to 5 6
R T S # /D T R # re -a s se rts w h e n d a ta fa lls b e lo w
th e trig g e r le v e l to re sta rt re m o te tra n sm itte r.
E n a b le b y E F R b it-6 = 1 , M C R b it-2 .
R H R In te rru p t (IS R b it-2 ) is p ro g ra m m e d
a t F IF O trig g e r le ve l (R X T R G ).
F IF O is E n a b le b y F C R b it-0 = 1
R T S # /D T R # d e -a sse rts w h e n d a ta fills a b o ve
th e trig g e r le v e l to su sp e n d re m o te tra n sm itte r.
E n a b le b y E F R b it-6 = 1 , M C R b it-2 .
R e c e ive
D a ta
R X F IF O 1
4.9 IER VERSUS RECEIVE FIFO INTERRUPT MODE
OPERATION
When the receive FIFO (FCR BIT-0 = a logic 1) and
receive interrupts (IER BIT-0 = logic 1) are enabled,
the RHR interrupts (see ISR bits 3 and 4) status will
reflect the following:
A. The receive data available interrupts are issued
to the host when the FIFO has reached the pro-
4.8.3 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line
status and modem status registers. These interrupts
are reported in the Interrupt Status Register (ISR)
register and also encoded in INT (INT0-INT3) register
in the Device Configuration Registers.
22
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XR16L788 OCTAL UART
REV. 1.1.4
troller about the error status of the current data byte
in FIFO.
grammed trigger level. It will be cleared when the
FIFO drops below the programmed trigger level.
Logic 0 = Disable the receiver line status interrupt.
(default)
B. FIFO level will be reflected in the ISR register
when the FIFO trigger level is reached. Both the
ISR register status bit and the interrupt will be
cleared when the FIFO drops below the trigger
level.
Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
Logic 0 = Disable the modem status register interrupt.
(default)
C. The receive data ready bit (LSR BIT-0) is set as
soon as a character is transferred from the shift
register to the receive FIFO. It is reset when the
FIFO is empty.
Logic 1 = Enable the modem status register interrupt.
IER[4]: Reserved.
IER[5]: Xoff Interrupt Enable (requires EFR bit4=1)
4.10 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED
MODE OPERATION
When FCR BIT-0 equals a logic 1 for FIFO enable;
resetting IER bits 0-3 enables the XR16L788 in the
FIFO polled mode of operation. Since the receiver
and transmitter have separate bits in the LSR either
or both can be used in the polled mode by selecting
respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX
FIFO.
Logic 0 = Disable the software flow control, receive
Xoff interrupt. (default)
Logic 1 = Enable the software flow control, receive
Xoff interrupt. See Software Flow Control section for
details.
IER[6]: RTS# Output Interrupt Enable (requires
EFR bit-4=1)
Logic 0 = Disable the RTS# interrupt. (default).
B. LSR BIT 1-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition.
IER[7]: CTS# Input Interrupt Enable (requires EFR
bit-4=1)
C. LSR BIT-5 indicates THR is empty.
D. LSR BIT-6 indicates when both the transmit FIFO
and TSR are empty.
E. LSR BIT-7 indicates the Or’ed function of errors
in the RX FIFO.
Logic 0 = Disable the CTS# interrupt. (default).
Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when
RHR has a data character in the non-FIFO mode or
when the receive FIFO has reached the programmed
trigger level in the FIFO mode.
4.11 INTERRUPT STATUS REGISTER (ISR)
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with
six interrupt status bits. Performing a read cycle on
the ISR will give the user the current highest pending
interrupt level to be serviced, others queue up for
next service. No other interrupts are acknowledged
until the pending interrupt is serviced. The Interrupt
Source Table, Table 9, shows the data values (bit 0-5)
for the six prioritized interrupt levels and the interrupt
sources associated with each of these interrupt levels.
Logic 0 = Disable the receive data ready interrupt.
(default)
Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This interrupt is associated with bit-5 in the LSR register. An interrupt is issued whenever the THR becomes empty or when data in the FIFO falls below
the programmed trigger level.
Logic 0 = Disable Transmit Holding Register empty
interrupt. (default)
4.11.1 Interrupt Generation:
• LSR is by any of the LSR bits 1, 2, 3 and 4.
• RXRDY is by RX trigger level.
Logic 1 = Enable Transmit Holding Register empty interrupt.
IER[2]: Receive Line Status Interrupt Enable
• RXRDY Time-out is by the a 4-char plus 12 bits
delay timer if data doesn’t reach FIFO trigger level.
• TXRDY is by LSR bit-5 (or bit-6 in auto RS485 control).
Any of the LSR register bits 1,2,3 or 4 becomes active will generate an interrupt to inform the host con-
23
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XR16L788 OCTAL UART
REV. 1.1.4
• RXRDY and RXRDY Time-out are cleared by reading data until FIFO falls below the trigger level.
• TXRDY interrupt is cleared by a read to the ISR
register.
• MSR interrupt is cleared by a read to the MSR register.
• Xon, Xoff or Special character interrupt is cleared
by a read to ISR.
• RTS#/DTR# and CTS#/DSR# status change interrupts are cleared by a read to the MSR register.
• MSR is by any of the MSR bits, 0, 1, 2 and 3.
• Receive Xon/Xoff/Special character is by detection
of a Xon, Xoff or Special character.
• CTS#/DSR# is by a change of state on the input pin
with auto flow control enabled, EFR bit-7, and
depending on selection on MCR bit-2.
• RTS#/DTR# is when its receiver changes the state
of the output pin during auto RTS/DTR flow control
enabled by EFR bit-6 and selection of MCR bit-2.
4.11.2 Interrupt Clearing:
• LSR interrupt is cleared by a read to the LSR register.
]
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF THE INTERRUPT+
LEVEL
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1
0
0
0
1
1
0
LSR (Receiver Line Status Register)
2
0
0
0
1
0
0
RXRDY (Received Data Ready)
3
0
0
1
1
0
0
RXRDY (Receive Data Time-out)
4
0
0
0
0
1
0
TXRDY (Transmitter Holding Register Empty)
5
0
0
0
0
0
0
MSR (Modem Status Register)
6
0
1
0
0
0
0
RXRDY (Received Xon/Xoff or Special character)
7
1
0
0
0
0
0
CTS#/DSR#, RTS#/DTR# change of state
X
0
0
0
0
0
1
None (default)
ISR[0]: Interrupt Status
FIFO Control Register (FCR)
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine.
This register is used to enable the FIFOs, clear the
FIFOs, set the transmit/receive FIFO trigger levels,
and select the DMA mode. The DMA, and FIFO
modes are defined as follows:
FCR BIT-0: TX and RX FIFO Enable
Logic 1 = No interrupt pending. (default condition)
ISR[3:1]: Interrupt Status
Logic 0 = Disable the transmit and receive FIFO. (default).
These bits indicate the source for a pending interrupt
at interrupt priority levels 1, 2, 3 and 4 (See Interrupt
Source Table 9).
ISR[5:4]: Interrupt Status
Logic 1 = Enable the transmit and receive FIFOs.
This bit must be set to logic 1 when other FCR bits
are written or they will not be programmed.
FCR[1]: RX FIFO Reset
These bits are enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a
data match of the Xon or Xoff character(s).
This bit is only active when FCR bit-0 is active.
NOTE: Note that once set to a logic 1, the ISR bit-4 will stay
a logic 1 until a Xon character is received. ISR bit-5 indicates that CTS#/DSR# or RTS#/DTR# has changed state.
Logic 0 = No receive FIFO reset. (default)
Logic 1 = Reset the receive FIFO pointers and FIFO
level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after
resetting the FIFO.
FCR[2]: TX FIFO Reset
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are
disabled. They are set to a logic 1 when the FIFOs
are enabled.
This bit is only active when FCR bit-0 is active.
Logic 0 = No transmit FIFO reset. (default)
24
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XR16L788 OCTAL UART
REV. 1.1.4
trigger levels in 4 tables are supported for compatibility reasons. These 2 bits set the trigger level for the
transmit FIFO interrupt. The UART will issue a transmit interrupt when the number of characters in the
FIFO falls below the selected trigger level, or when it
gets empty in case that the FIFO did not get filled
over the trigger level on last re-load. Table 10 below
shows the selections.
FCR[7:6]: Receive FIFO Trigger Select
Logic 1 = Reset the transmit FIFO pointers and FIFO
level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after
resetting the FIFO.
FCR[3]: DMA Mode Select
This bit has no effect since TXRDY and RXRDY pins
are not available in this device. It is provided for legacy software.
Logic 0 = Set DMA to mode 0. (default)
(logic 0 = default, RX trigger level =1)
Logic 1 = Set DMA to mode 1.
FCR[5:4]: Transmit FIFO Trigger Select
The FCTR Bits 6-7 are associated with these 2 bits.
These 2 bits are used to set the trigger level for the
receiver FIFO interrupt. Table 10 shows the complete
selections.
(logic 0 = default, TX trigger level = one)
The FCTR Bits 6-7 are associated with these 2 bits by
selecting one of the four tables. The 4 user selectable
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION
FCTR
BIT-7
FCTR
BIT-6
0
0
0
FCR
BIT-7
FCR
BIT-6
0
0
1
1
0
1
0
1
1
FCR
0
0
RECEIVE
TRANSMIT
TRIGGER LEVEL TRIGGER LEVEL
1 (default)
0
1
0
1
0
1
0
1
X
X
16
8
24
30
Table-B. 16C650A compatible.
8
16
32
56
Table-C. 16C654 compatible.
8
16
24
28
0
0
1
1
0
0
1
1
COMPATIBILITY
Table-A. 16C550, 16C2550,
16C2552, 16C554, 16C580
compatible.
1 (default)
4
8
14
0
1
0
1
0
1
BIT-4
0
0
1
1
1
0
0
1
1
1
FCR
BIT-5
0
1
0
1
8
16
56
60
X
X
Programmable Programmable Table-D. 16C850, 16c2850,
16C2852, 16C854, 16C864,
16C872 compatible.
Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1-0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
25
BIT-1
BIT-0
WORD LENGTH
0
0
5 (default)
0
1
6
1
0
7
1
1
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XR16L788 OCTAL UART
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LCR[2]: TX and RX Stop-bit Length Select
LCR[6]: Transmit Break Enable
The length of stop bit is specified by this bit in conjunction with the programmed word length.
• When enabled the Break control bit it causes a
break condition to be transmitted (the TX output is
forced to a “space’, logic 0, state). This condition
remains until disabled by setting LCR bit-6 to a
logic 0.
• Logic 0 = No TX break condition. (default)
BIT-2
WORD LENGTH
STOP BIT LENGTH
(BIT TIME(S))
0
5,6,7,8
1 (default)
1
5
1-1/2
1
6,7,8
2
• Logic 1 = Forces the transmitter output (TX) to a
“space”, logic 0, for alerting the remote receiver of a
line break condition.
LCR[7]: Baud Rate Divisors Enable
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The
parity bit is a simple way used in communications for
data integrity check. See Table 11 for parity selection
summary below.
• Logic 0 = No parity.
Baud rate generator divisor (DLL/DLM) enable.
• Logic 0 = Data registers are selected. (default)
• Logic 1 = Divisor latch registers are selected.
Modem Control Register (MCR) or General Purpose Outputs Control.
• Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of
the data character received.
LCR[4]: TX and RX Parity Select
This register controls the serial interface signals with
the modem or a peripheral device.
Modem Control Register (MCR)
If the parity bit is enabled with LCR bit-3 set to a logic
1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd
number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format. (default).
• Logic 1 = EVEN Parity is generated by forcing an
even the number of logic 1’s in the transmitted
character. The receiver must be programmed to
check the same format.
LCR[5]: TX and RX Parity Select
The MCR register is used for controlling the modem
interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Pins
The DTR# pin may be used for automatic hardware
flow control enabled by EFR bit-6 and MCR bit-2=1. If
the modem interface is not used, this output may be
used for general purpose.
• Logic 0 = Force DTR# output to a logic 1. (default)
• Logic 1 = Force DTR# output to a logic 0.
MCR[1]: RTS# Pins
If the parity bit is enabled, LCR BIT-5 selects the
forced parity format.
• LCR BIT-5 = logic 0, parity is not forced. (default)
The RTS# pin may be used for automatic hardware
flow control by enabled by EFR bit-6 and MCR bit2=0. If the modem interface is not used, this output
may be used for general purpose.
• Logic 0 = Force RTS# output to a logic 1. (default)
• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity
bit is forced to a logical 1 for the transmit and
receive data.
• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity
bit is forced to a logical 0 for the transmit and
receive data.
• Logic 1 = Force RTS# output to a logic 0.
MCR[2]: RTS/CTS or DTR/DSR for Auto Flow Control
TABLE 11: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3
DTR# or RTS# auto hardware flow control select.
This bit is in effect only when auto RTS/DTR is enabled by EFR bit-6.
PARITY SELECTION
X
X
0
No parity
0
0
1
Odd parity
0
1
1
Even parity
1
0
1
Force parity to mark, “1”
1
1
1
Forced parity to space,
“0”
• Logic 0 = RTS# (RX side) and CTS# (TX side) pins
are used for auto hardware flow control.
• Logic 1 = DTR# (RX side) and DSR# (TX side) pins
are used for auto hardware flow control.
MCR[3]:
Reserved. Logic zero is default.
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XR16L788 OCTAL UART
REV. 1.1.4
MCR[4]: Internal Loopback Enable
full. In this case the previous data in the receive
shift register is overwritten. Note that under this
condition the data byte in the receive shift register
is not transferred into the FIFO, therefore the data
in the FIFO is not corrupted by the error.
LSR[2]: Receive Data Parity Error Flag
• Logic 0 = Disable loopback mode. (default)
• Logic 1 = Enable local loopback mode, see loopback section and Figure 10.
MCR[5]: Xon-Any Enable
• Logic 0 = Disable Xon-Any function (for 16C550
compatibility). (default).
• Logic 1 = Enable Xon-Any function. In this mode
any RX character received will enable Xon, resume
data transmission.
MCR[6]: Infrared Encoder/Decoder Enable
• Logic 0 = No parity error. (default)
• Logic 1 = Parity error. The receive character in
RHR does not have correct parity information and
is suspect. This error is associated with the character available for reading in RHR.
LSR[3]: Receive Data Framing Error Flag
The state of this bit depends on the sampled logic
level of pin ENIR during power up, following a hardware reset or a soft-reset. Afterward user can override this bit for desired operation.
• Logic 0 = No framing error. (default)
• Logic 1 = Framing error. The receive character did
not have a valid stop bit(s). This error is associated
with the character available for reading in RHR.
LSR[4]: Receive Break Flag
• Logic 0 = Enable the standard modem receive and
transmit character interface.
• Logic 1 = Enable infrared IrDA receive and transmit
inputs/outputs. While in this mode, the TX/RX output/input are routed to the infrared encoder/
decoder. The data input and output levels will conform to the IrDA infrared interface requirement. As
such, while in this mode the infrared TX output will
be a logic 0 during idle data conditions. FCTR bit-4
may be selected to invert the RX input signal level
going to the decoder for infrared modules that provide rather an inverted output.
MCR[7]: Clock Prescaler Select
• Logic 0 = No break condition. (default)
• Logic 1 = The receiver received a break signal (RX
was a logic 0 for one character frame time). In the
FIFO mode, only one break character is loaded into
the FIFO. The break indication remains until the RX
input returns to the idle condition, “mark” or logic 1.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. This bit indicates that the transmitter is ready to
accept a new character for transmission. In addition,
this bit causes the UART to issue an interrupt to the
host when the THR interrupt enable is set. The THR
bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set when
the transmit FIFO is empty; it is cleared when at least
1 byte is written to the transmit FIFO.
LSR[6]: Transmit Shift Register Empty Flag
• Logic 0 = Divide by one. The input clock from the
crystal or external clock is fed directly to the Programmable Baud Rate Generator without further
modification, i.e., divide by one. (default).
• Logic 1 = Divide by four. The prescaler divides the
input clock from the crystal or external clock by four
and feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
Line Status Register (LSR)
This bit is the Transmit Shift Register Empty indicator.
This bit is set to a logic 1 whenever the transmitter
goes idle. It is set to logic 0 whenever either the THR
or TSR contains a data character. In the FIFO mode
this bit is set to one whenever the transmit FIFO and
transmit shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
This register provides the status of data transfers between the UART and the host.
LSR[0]: Receive Data Ready Indicator
• Logic 0 = No data in receive holding register or
FIFO. (default).
• Logic 1 = Data has been received and is saved in
the receive holding register or FIFO.
LSR[1]: Receiver Overrun Flag
• Logic 0 = No FIFO error. (default)
• Logic 1 = An indicator for the sum of all error bits in
the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit
clears when there is no more error(s) in the FIFO.
• Logic 0 = No overrun error. (default)
• Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens when additional data arrives while the FIFO is
27
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XR16L788 OCTAL UART
REV. 1.1.4
Modem Status Register (MSR) - Read Only
character has finished transmission, and a logic 0 will
resume data transmission. Normally MSR bit-4 bit is
the compliment of the CTS# input. However in the
loopback mode, this bit is equivalent to the RTS# bit
in the MCR register. The CTS# input may be used as
a general purpose input when the modem interface is
not used.
This register provides the current state of the modem
interface signals, or other peripheral device that the
UART is connected. Lower four bits of this register
are used to indicate the changed information. These
bits are set to a logic 1 whenever a signal from the
modem changes state. These bits may be used as
general purpose inputs/outputs when they are not
used with modem signals.
MSR[0]: Delta CTS# Input Flag
MSR[5]: DSR Input Status
DSR# (active high, logical 1). This input may be used
for auto DTR/DSR flow control function, see auto
\hardware flow control section. Normally this bit is the
compliment of the DSR# input. In the loopback mode,
this bit is equivalent to the DTR# bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is not used.
MSR[6]: RI Input Status
• Logic 0 = No change on CTS# input (default).
• Logic 1 = The CTS# input has changed state since
the last time it was monitored. A modem status
interrupt will be generated if MSR interrupt is
enabled (IER bit-3.
MSR[1]: Delta DSR# Input Flag
• Logic 0 = No change on DSR# input (default).
• Logic 1 = The DSR# input has changed state since
the last time it was monitored. A modem status
interrupt will be generated if MSR interrupt is
enabled (IER bit-3.
MSR[2]: Delta RI# Input Flag
RI# (active high, logical 1). Normally this bit is the
compliment of the RI# input. In the loopback mode
this bit is equivalent to bit-2 in the MCR register. The
RI# input may be used as a general purpose input
when the modem interface is not used.
MSR[7]: CD Input Status
• Logic 0 = No change on RI# input (default).
• Logic 1 = The RI# input has changed from a logic 0
to a logic 1, ending of the ringing signal. A modem
status interrupt will be generated if MSR interrupt is
enabled (IER bit-3.
MSR[3]: Delta CD# Input Flag
CD# (active high, logical 1). Normally this bit is the
compliment of the CD# input. In the loopback mode
this bit is equivalent to bit-3 in the MCR register. The
CD# input may be used as a general purpose input
when the modem interface is not used.
Modem Status Register (MSR) - Write Only
• Logic 0 = No change on CD# input (default).
• Logic 1 = Indicates that the CD# input has changed
state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is
enabled (IER bit-3.
MSR[4]: CTS Input Status
The upper four bits 4-7 of this register sets the delay
in number of bits time for the auto RS485 turn around
from transmit to receive.
MSR [7:4]
When Auto RS485 feature is enabled (FCTR bit-5=1)
and RTS# output is connected to the enable input of
a RS-485 transceiver. These 4 bits select from 0 to 15
bit-time delay after the end of the last stop-bit of the
last transmitted character. This delay controls when
to change the state of RTS# output. This delay is very
useful in long-cable networks. Table 12 shows the selection. The bits are enabled by EFR bit-4.
CTS# pin may function as automatic hardware flow
control signal input if it is enabled and selected by Auto CTS (EFR bit-7) and RTS/CTS flow control select
(MCR bit-2). Auto CTS flow control allows starting
and stopping of local data transmissions based on
the modem CTS# signal. A logic 1 on the CTS# pin
will stop UART transmitter as soon as the current
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XR16L788 OCTAL UART
REV. 1.1.4
TABLE 12: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE
MSR[7]
MSR[6]
MSR[5]
MSR[4]
DELAY IN DATA BIT(S) TIME
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
9
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1
0
1
0
10
1
0
1
1
11
1
1
0
0
12
1
1
0
1
13
1
1
1
0
14
1
1
1
1
15
FCTR [3:0] - Auto RTS/DTR Flow Control Hysteresis Select
SCRATCH PAD REGISTER (SPR)
This is a 8-bit general purpose register for the user to
store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
These bits select the auto RTS/DTR flow control hysteresis and only valid when TX and RX Trigger TableD is selected (FCTR bit-6 and 7 are set to logic 1).
The RTS/DTR hysteresis is referenced to the RX
FIFO trigger level. After reset, these bits are set to
logic 0 selecting the next FIFO trigger level for hardware flow control. Table 13 below shows the 16 selectable hysteresis levels.
FEATURE CONTROL REGISTER (FCTR)
This register controls the UART enhanced functions
that are not available on ST16C554 or ST16C654.
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XR16L788 OCTAL UART
REV. 1.1.4
TABLE 13: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED
FCTR BIT3
FCTR BIT2
FCTR BIT1
FCTR BIT0
RTS/DTR HYSTERESIS
(CHARACTERS)
0
0
0
0
0
0
0
0
1
+/- 4
0
0
1
0
+/- 6
0
0
1
1
+/- 8
0
1
0
0
+/- 8
0
1
0
1
+/- 16
0
1
1
0
+/- 24
0
1
1
1
+/- 32
1
1
0
0
+/- 12
1
1
0
1
+/- 20
1
1
1
0
+/- 28
1
1
1
1
+/- 36
1
0
0
0
+/- 40
1
0
0
1
+/- 44
1
0
1
0
+/- 48
1
0
1
1
+/- 52
FCTR[4]: Infrared RX Input Logic Select
FCTR[7:6]: TX and RX FIFO Trigger Table Select
0 = Select RX input as active high encoded IrDA data,
normal, (default).
These 2 bits select the transmit and receive FIFO trigger level table A, B, C or D. When table A, B, or C is
selected the auto RTS flow control trigger level is set
to "next FIFO trigger level" for compatibility to
ST16C550 and ST16C650 series. RTS/DTR# triggers on the next level of the RX FIFO trigger level, in
another word, one FIFO level above and one FIFO
level below. See in Table 10 for complete selection
with FCR bit 4-5 and FCTR bit 6-7, i.e. if Table C is
used on the receiver with RX FIFO trigger level set to
56 bytes, RTS/DTR# output will de-assert at 60 and
re-assert at 16.
Enhanced Feature Register (EFR)
1 = Select RX input as active low encoded IrDA data,
inverted.
FCTR[5]: Auto RS485 Enable
Auto RS485 half duplex control enable/disable.
• 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
(THR) becomes empty. Transmit Shift Register
(TSR) may still be shifting data bit out.
• 1 = Enable Auto RS485 half duplex direction control. RTS# output changes its logic level from 1 to 0
when finished sending the last stop bit of the last
character out of the TSR register. It changes back
to logic level 1 from 0 when a data byte is loaded
into the THR or transmit FIFO. The change to logic
1 occurs prior sending the start-bit. It also changes
the transmitter interrupt from transmit holding to
transmit shift register (TSR) empty.
Enhanced features are enabled or disabled using this
register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see
Table 14). When the Xon1 and Xon2 and Xoff1 and
Xoff2 modes are selected, the double 8-bit words are
concatenated into two sequential characters. Caution: note that whenever changing the TX or RX flow
control bits, always reset all bits back to logic 0 (disable) before programming a new setting.
30
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XR16L788 OCTAL UART
REV. 1.1.4
TABLE 14: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3
CONT-3
EFR BIT-2
CONT-2
EFR BIT-1
CONT-1
EFR BIT-0
CONT-0
0
0
0
0
No TX and RX flow control (default and reset)
0
0
X
X
No transmit flow control
1
0
X
X
Transmit Xon1/Xoff1
0
1
X
X
Transmit Xon2/Xoff2
TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
1
1
X
X
Transmit Xon1 and Xon2/Xoff1 and Xoff2
X
X
0
0
No receive flow control
X
X
1
0
Receiver compares Xon1/Xoff1
X
X
0
1
Receiver compares Xon2/Xoff2
1
0
1
1
Transmit Xon1/ Xoff1,
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
1
1
Transmit Xon2/Xoff2,
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
1
1
1
Transmit Xon1 and Xon2/Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
0
0
1
1
No transmit flow control,
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
EFR BIT 0-3: Software Flow Control Select
bit-4 will be set to indicate detection of the special
character. Bit-0 corresponds with the LSB bit for the
receive character. If flow control is set for comparing Xon1, Xoff1 (EFR [1:0]=10) then flow control
and special character work normally. However, if
flow control is set for comparing Xon2, Xoff2
(EFR[1:0]=01) then flow control works normally, but
Xoff2 will not go to the FIFO, and will generate an
Xoff interrupt and a special character interrupt.
Combinations of software flow control can be selected by programming these bits.
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables the
functions in IER bits 4-7, ISR bits 4-5, FCR bits 4-5,
and MCR bits 5-7 to be modified. After modifying any
enhanced bits, EFR bit-4 can be set to a logic 0 to
latch the new values. This feature prevents legacy
software from altering or overwriting the enhanced
functions once set. Normally, it is recommended to
leave it enabled, logic 1.
• Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 are saved to retain the user settings.
After a reset, the IER bits 4-7, ISR bits 4-5, FCR
bits 4-5, and MCR bits 5-7 are set to a logic 0 to be
compatible with ST16C554 mode. (default).
• Logic 1 = Enables the enhanced functions. When
this bit is set to a logic 1 all enhanced features are
enabled.
EFR[5]: Special Character Detect Enable
EFR[6]: AUTO RTS OR DTR FLOW CONTROL
ENABLE
RTS#/DTR# output may be used for hardware flow
control by setting EFR bit-6 to logic 1. When Auto
RTS/DTR is selected, an interrupt will be generated
when the receive FIFO is filled to the programmed
trigger level and RTS/DTR# will de-assert to a logic 1
at the next upper trigger or selected hysteresis level.
RTS/DTR# will return to a logic 0 when FIFO data
falls below the next lower trigger or selected hysteresis level (see FCTR bits 4-7). The RTS# or DTR# output must be asserted (logic 0) before the auto RTS/
DTR can take effect. The selection for RTS# or DTR#
is through MCR bit-2. RTS/DTR# pin will function as a
general purpose output when hardware flow control is
disabled.
• Logic 0 = Automatic RTS/DTR flow control is disabled. (default)
• Logic 1 = Enable Automatic RTS/DTR flow control.
• Logic 0 = Special Character Detect Disabled.
(default)
• Logic 1 = Special Character Detect Enabled. The
UART compares each incoming receive character
with data in Xoff-2 register. If a match exists, the
received data will be transferred to FIFO and ISR
EFR[7]: Auto CTS Flow Control Enable
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XR16L788 OCTAL UART
REV. 1.1.4
Automatic CTS or DSR Flow Control.
• Logic 0 = Automatic CTS/DSR flow control is disabled. (default)
• Logic 1 = Enable Automatic CTS/DSR flow control.
Transmission stops when CTS/DSR# pin deasserts to logic 1. Transmission resumes when
CTS/DRS# pin returns to a logic 0. The selection
for CTS# or DSR# is through MCR bit-2.
TFCNT[7:0]: Transmit FIFO Level Counter, readonly
TABLE 15: UART RESET CONDITIONS
Transmit FIFO level byte count from 0x00 (zero) to
0x40 (64). This 8-bit register gives an indication of the
number of characters in the transmit FIFO. The FIFO
level Byte count register is read only. The user can
take advantage of the FIFO level byte counter for
faster data loading to the transmit FIFO., which reduces CPU bandwidth requirements.
TXTRG [7:0]: Transmit FIFO Trigger Level, write
only.
An 8-bit value written to this register sets the TX FIFO
trigger level from 0x00 (zero) to 0x40 (64). The TX
FIFO trigger level generates an interrupt whenever
the data level in the transmit FIFO falls below this
preset trigger level.
RFCNT[7:0]: Receive FIFO Level Counter, read
only
Receive FIFO level byte count from 0x00 (zero) to
0x40 (64). It gives an indication of the number of
characters in the receive FIFO. The FIFO level byte
count register is read only. The user can take advantage of the FIFO level byte counter for faster data unloading from the receiver FIFO, which reduces CPU
bandwidth requirements.
RXTRG[7:0]: Receive FIFO Trigger Level, write
only
An 8-bit value written to this register, sets the RX
FIFO trigger level from 0x00 (zero) to 0x40 (64). The
RX FIFO trigger level generates an interrupt whenever the receive FIFO level rises to this preset trigger
level.
32
REGISTERS
RESET STATE
DLL
Bits 7-0 = 0xXX
DLM
Bits 7-0 = 0xXX
RHR
Bits 7-0 = 0xXX
THR
Bits 7-0 = 0xXX
IER
Bits 7-0 = 0x00
FCR
Bits 7-0 = 0x00
ISR
Bits 7-0 = 0x01
LCR
Bits 7-0 = 0x00
MCR
Bits 7-0 = 0x00
LSR
Bits 7-0 = 0x60
MSR
Bits 3-0 = logic 0
Bits 7-4 = logic levels of the inputs
SPR
Bits 7-0 = 0xFF
FCTR
Bits 7-0 = 0x00
EFR
Bits 7-0 = 0x00
TFCNT
Bits 7-0 = 0x00
TFTRG
Bits 7-0 = 0x00
RFCNT
Bits 7-0 = 0x00
RFTRG
Bits 7-0 = 0x00
XCHAR
Bits 7-0 = 0x00
XON1
Bits 7-0 = 0x00
XON2
Bits 7-0 = 0x00
XOFF1
Bits 7-0 = 0x00
XOFF2
Bits 7-0 = 0x00
I/O SIGNALS
RESET STATE
TX[ch-7:0]
Logic 1
IRTX[ch-7:0]
Logic 0
RTS#[ch-7:0]
Logic 1
DTR#[ch-7:0]
Logic 1
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XR16L788 OCTAL UART
REV. 1.1.4
ABSOLUTE MAXIMUM RATINGS
Power Supply Range
7 Volts
Voltage at Any Pin
-0.5 to 7V
Operating Temperature
-40o to +85o C
Storage Temperature
-65o to +150o C
Package Dissipation
500 mW
θ-ja = 34°C/W , θ-jc = 9°C/W
Thermal Resistance (14x20x3.0mm 100-QFP)
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc-3.3V and 5V +/-10% unless specified
PARAMETER
3.3V
MIN
MAX
5V
MIN
5V
MAX
UNITS
VIL
Input Low Voltage
-0.3
0.7
-0.5
0.8
V
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
SYMBOL
3.3
2.4
0.4
2.0
CONDITION
V
0.55
2.4
V
Iout=6 mA
V
Iout=-2 mA
IIL
Input Low Leakage Current
-10
-10
uA
IIH
Input High Leakage Current
10
10
uA
X1
Crystal/Clock input low
level
-0.3
0.6
-0.5
0.6
V
X1
Crystal/Clock input high
level
2.4
6
3.0
6
V
CIN
Input Pin Capacitance
5
5
pF
ICC
Power Supply Current
5
5
mA
EXT Clock=2MHz
A7-A0 at GND, all
inputs at VCC or GND
and outputs unloaded
0.60
3.00
mA
Eight UARTs asleep.
A7-A0 at GND, all
inputs at VCC or GND
and outputs unloaded.
15K
Ohms
ISLEEP
RIN
Sleep Current
Internal pull-up or pulldown resistance
3K
15K
3K
33
NOTES
20uA Typ.
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XR16L788 OCTAL UART
REV. 1.1.4
AC ELECTRICAL CHARACTERISTICS
TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc-3.3V and 5V +/-10% unless specified.
SYMBOL
3,3V
MIN
PARAMETER
TC1,TC2 Clock Pulse Period
3.3V
MAX
10
5V
MIN
5V
MAX
8
UNITS
ns
TOSC
Oscillator Frequency
16
24
MHz
TECK
External Clock Frequency
33
50
MHz
TAS
Address Setup (16 Mode)
5
5
ns
TAH
Address Hold (16 Mode)
10
10
ns
TCS
Chip Select Width (16 Mode)
50
50
ns
TDY
Delay between CS# Active Cycles (16 Mode)
50
50
ns
TRD
Read Strobe Width (16 Mode)
50
50
ns
TWR
Write Strobe Width (16 Mode)
40
30
ns
TRDV
Read Data Valid (16 Mode)
35
25
ns
TWDS
Write Data Setup (16 Mode)
15
10
ns
TRDH
Read Data Hold (16 Mode)
TWDH
Write Data Hold (16 Mode)
15
10
ns
TADS
Address Setup (68 Mode)
10
5
ns
TADH
Address Hold (68 Mode)
10
10
ns
TRWS
R/W# Setup to CS# (68 Mode)
10
10
ns
TRDA
Read Data Access (68 mode)
35
25
ns
TRDH
Read Data Hold (68 mode)
TWDS
Write Data Setup (68 mode)
10
10
ns
TWDH
Write Data Hold (68 Mode)
10
10
ns
TRWH
CS# De-asserted to R/W# De-asserted (68 Mode)
10
10
ns
TCSL
CS# Width (68 Mode)
50
40
ns
TCSD
CS# Cycle Delay (68 Mode)
50
40
ns
15
10
15
10
ns
ns
ns
T17D
Delay from IOW# to Modem Output
50
50
ns
T18D
Delay to set Interrupt from Modem Input
50
35
ns
T19D
Delay to reset Interrupt from IOR#
50
35
ns
TRST
Reset Pulse
40
34
40
ns
NOTES
áç
XR16L788 OCTAL UART
REV. 1.1.4
FIGURE 15. 16 MODE (INTEL) DATA BUS READ AND WRITE TIMING
A0-A7
Valid Address
T AS
Valid Address
TAS
T AH
T AH
T CS
CS#
T DY
T RD
IO R #
T RDH
T RDV
T RDH
T RDV
Valid D ata
D 0-D 7
Valid D ata
16Read
16 M ode (Intel) D ata Bus R ead Tim ing
A0-A7
Valid Address
T AS
Valid Address
TAS
T AH
T AH
T CS
CS#
T DY
TWR
IO W #
T W DS
D 0-D 7
T W DH
Valid D ata
T W DS
T W DH
Valid D ata
16W rite
16 M ode (Intel) D ata Bus W rite T im ing
35
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XR16L788 OCTAL UART
REV. 1.1.4
FIGURE 16. 68 MODE (MOTOROLA) DATA BUS READ AND WRITE TIMING
A0-A7
Valid Address
T AD S
T CS L
Valid Address
T AD H
C S#
T CS D
T RW S
T RW H
R /W #
T RD H
T RD A
D 0-D 7
Valid D ata
Valid D ata
68R ead
68 M ode (M otorola) D ata B us R ead Tim ing
A0-A7
Valid Address
T AD S
T CS L
Valid Address
T AD H
C S#
T CS D
T RW S
T RW H
R /W #
T W DS
D 0-D 7
T W DH
Valid D ata
Valid D ata
68W rite
68 M ode (M otorola) D ata B us W rite Tim ing
36
áç
XR16L788 OCTAL UART
REV. 1.1.4
FIGURE 17. MODEM INPUT/OUTPUT PORT DELAY
IO W #
A ctiv e
T 17D
RTS#
DTR#
C h an ge of
S ta te
C h an ge of
S ta te
CD#
CTS#
DSR#
C h an ge of
S ta te
C h an ge of
S ta te
T18D
T 18D
A ctiv e
IN T
A ctiv e
A ctiv e
T19D
A ctiv e
A ctiv e
IO R #
A ctiv e
T 18D
C h an ge of
S ta te
R I#
M o d e m -1
FIGURE 18. TRANSMIT DATA INTERRUPT AT TRIGGER LEVEL
START
BIT
TX Data
STOP
BIT
DATA BITS (5-8)
D0
D1
D2
D3
D4
D5
D6
D7
PARITY
BIT
5 DATA BITS
6 DATA BITS
NEXT
DATA
START
BIT
7 DATA BITS
TX Interrupt at
Transmit Trigger Level
Clear at
Above
Trigger Level
Set at Below
Trigger Level
BAUD RATE CLOCK of 16X or 8X
TXNOFIFO-1
37
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XR16L788 OCTAL UART
REV. 1.1.4
FIGURE 19. RECEIVE DATA READY INTERRUPT AT TRIGGER LEVEL
START
BIT
RX Data Input
STOP
BIT
DATA BITS (5-8)
D0
D1
D2
D3
D4
D5
D6
D7
PARITY First byte that
reaches the
BIT
trigger level
RX Data Ready Interrupt at
Receive Trigger Level
De-asserted at
below trigger level
Asserted at
above trigger
level
RXFIFO1
38
áç
XR16L788 OCTAL UART
REV. 1.1.4
PACKAGE DIMENSIONS
100 LEAD PLASTIC QUAD FLAT PACK
(14 mm x 20 mm, QFP)
Rev. 2.00
D
D1
80
51
81
50
E1 E
100
31
1
30
B
A2
e
C
A
Seating Plane
α
A1
L
SYMBOL
A
A1
A2
B
C
D
D1
E
E1
e
L
α
1.95 mm Form
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.102
0.134
2.60
3.40
0.002
0.014
0.05
0.35
0.100
0.120
2.55
3.05
0.009
0.015
0.22
0.38
0.005
0.009
0.13
0.23
0.931
0.951
23.65
24.15
0.783
0.791
19.90
20.10
0.695
0.715
17.65
18.15
0.547
0.555
13.90
14.10
0.0256 BSC
0.65 BSC
0.026
0.037
0.65
0.95
0°
7°
0°
7°
Note: The control dimension is the millimeter column
39
XR16L788
áç
OCTAL UART
REV. 1.1.4
REVISION HISTORY
P1.0.0
Preliminary
P1.0.1
Corrected figure 2 pin diagram on pins 16 to 30 and 39.
P1.0.2
Corrected pins description (pin number) for TX3, RX6, DSR6# and 16/68#.
P1.0.3
Changed part number to XR16L788, added 5V spec and target timing, and corrected RX6 pin to be 39.
P1.0.4
Changed Icc to 5mA max. and Isleep current to 400uA max, clarified ENIR pin and MCR bits 2 and 6.
1.1.0
Updated Electrical Specification Tables. Added θ-ja and θ-jc values. Removed Preliminary designation.
1.1.1
changed VIL ( 0.8 to 0.7 max) and VIH (2.2 to 2.4 min) in electrical characteristics tables.
1.1.2
Changed Isleep max @ 3.3V from 0.40mA to 0.60 mA and @ 5V from 0.40 to 3.00mA
1.1.3
Deleted VOH @ Iout =6mA. Changed condition on ICC from CLK=35MHz to “EXT Clock=2Mhz”. Changed
TRDA from min =30ns to 35ns. Changed max VOL @5V from 0.4 to 0.55V. Changed min VOH @5V from
4.0 to 2.4V.
1.1.4
Updated values of AC Electrical Characteristics (TAS, TAH, TCS, TRD, TADS, TADH, TWDS, TWDH). Added
Exar’s UART Technical Support E-mail address to first and last page.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order
to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of
any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for
illustration purposes and may vary depending upon a user’s specific application. While the information in
this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where
the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury
or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright 2001 EXAR Corporation
Datasheet December 2001
Send your UART technical inquiry with technical details to hotline: [email protected]
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
40
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XR17C158
PCI BUS OCTAL UART
REV. 1.1.4
TABLE OF CONTENTS
GENERAL DESCRIPTION ............................................................................................... 1
APPLICATIONS ...........................................................................................................................................
NEW FEATURES: ......................................................................................................................................
Figure 1. Block Diagram .........................................................................................................................
Figure 2. Pin Out of the Device ..............................................................................................................
ORDERING INFORMATION ............................................................................................................................
1
1
1
2
2
PIN DESCRIPTIONS ....................................................................................................... 3
DESCRIPTION .................................................................................................................. 7
1.0 XR16L788 REGISTERS .........................................................................................................................
Figure 3. The XR16L788 Registers ........................................................................................................
1.1 DEVICE CONFIGURATION REGISTER SET ...................................................................................
TABLE 1: XR16L788 REGISTER SETS .......................................................................................................
TABLE 2: DEVICE CONFIGURATION REGISTERS ..........................................................................................
7
7
7
8
8
INT0 Channel Interrupt Indicator: ....................................................................................... 9
INT1, INT2 and INT3 Interrupt Source Locator ................................................................. 9
Figure 4. The Global Interrupt Registers, INT0, INT1, INT2 and INT3 ................................................... 9
TABLE 3: UART CHANNEL [7:0] INTERRUPT SOURCE ENCODING AND CLEARING ...................................... 10
Figure 5. Timer/Counter circuit. ............................................................................................................ 10
TABLE 4: TIMER CONTROL REGISTER ................................................................................................. 10
2.0 CRYSTAL OSCILLATOR / BUFFER .................................................................................................... 12
3.0 TRANSMIT AND RECEIVE DATA ........................................................................................................ 12
3.1 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR. 12
Figure 6. Typical oscillator connections ................................................................................................ 12
TABLE 5: TRANSMIT AND RECEIVE DATA REGISTER, 16C550 COMPATIBLE ............................................... 13
4.0 UART ..................................................................................................................................................... 13
4.1 PROGRAMMABLE BAUD RATE GENERATOR ........................................................................................................... 13
Figure 7. Baud Rate Generator ............................................................................................................ 14
TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING ... 14
4.2 AUTOMATIC RTS/DTR HARDWARE FLOW CONTROL OPERATION ........................................................................... 14
Figure 8. Auto RTS/DTR and CTS/DSR Flow Control Operation ......................................................... 15
4.3 INFRARED MODE .................................................................................................................................................. 16
Figure 9. Infrared Transmit Data Encoding and Receive Data Decoding ............................................. 16
4.4 INTERNAL LOOPBACK ........................................................................................................................................... 16
Figure 10. Internal Loop Back .............................................................................................................. 17
4.5 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING. ......................................... 17
TABLE 7: UART CHANNEL CONFIGURATION REGISTERS. ............................................................. 18
TABLE 8: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY
EFR BIT-4. ............................................................................................................................................. 19
4.6 TRANSMITTER ...................................................................................................................................................... 20
Figure 11. Transmitter Operation in non-FIFO Mode ........................................................................... 20
Figure 12. Transmitter Operation in FIFO and Flow Control Mode ...................................................... 21
4.7 RECEIVER ........................................................................................................................................................... 21
4.8 REGISTERS .......................................................................................................................................................... 21
Figure 13. Receiver Operation in non-FIFO Mode ............................................................................... 22
Figure 14. Receiver Operation in FIFO and Flow Control Mode .......................................................... 22
4.9 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION .................................................................................. 22
4.10 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION ..................................................................... 23
4.11 INTERRUPT STATUS REGISTER (ISR) .................................................................................................................. 23
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ................................................................................ 24
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION ..................................................... 25
TABLE 11: PARITY SELECTION ................................................................................................................. 26
TABLE 12: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE .......... 29
I
áç
XR17C158
PCI BUS OCTAL UART
REV. 1.1.4
SCRATCH PAD REGISTER (SPR) ......................................................................................................
FEATURE CONTROL REGISTER (FCTR) ..........................................................................................
TABLE 13: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED .........................
TABLE 14: SOFTWARE FLOW CONTROL FUNCTIONS ................................................................................
EFR[6]: AUTO RTS OR DTR FLOW CONTROL ENABLE ............................................................................
TABLE 15: UART RESET CONDITIONS ..............................................................................................
29
29
30
31
31
32
ABSOLUTE MAXIMUM RATINGS ................................................................................ 33
ELECTRICAL CHARACTERISTICS .............................................................................. 33
DC ELECTRICAL CHARACTERISTICS ...............................................................................................
AC ELECTRICAL CHARACTERISTICS ...............................................................................................
Figure 15. 16 Mode (Intel) Data Bus Read and Write Timing ..............................................................
Figure 16. 68 Mode (Motorola) Data Bus Read and Write Timing .......................................................
Figure 17. Modem Input/Output Port Delay .........................................................................................
Figure 18. Transmit Data Interrupt at Trigger Level .............................................................................
Figure 19. Receive Data Ready Interrupt at Trigger Level ...................................................................
33
34
35
36
37
37
38
PACKAGE DIMENSIONS .............................................................................................. 39
REVISION HISTORY .................................................................................................................................. 40
TABLE OF CONTENTS .......................................................................................................................... I
II