EXAR XR17L154CV

áç
XR17L154
DISCONTINUED
3.3V PCI BUS QUAD UART
AUGUST 2003
REV. 1.1.0
FEATURES
GENERAL DESCRIPTION
The XR17L1541 (L154) is a quad PCI Bus Universal
Asynchronous Receiver and Transmitter (UART) with
same package and pin-out as the Exar XR17C158
octal UART. The device is designed to meet today’s
32-bit PCI Bus and high bandwidth requirement in
communication systems. The global interrupt source
register provides a complete interrupt status
indication for all 4 channels to speed up interrupt
parsing. Each UART is independently controlled and
has its own 16C550 compatible 5G register set,
transmit and receive FIFOs of 64 bytes, fully
programmable transmit and receive FIFO trigger
levels, transmit and receive FIFO level counters,
automatic hardware flow control with programmable
hysteresis, automatic software (Xon/Xoff) flow
control, IrDA (Infrared Data Association) encoder/
decoder, 8 multi-purpose definable inputs/outputs,
and a 16-bit general purpose timer/counter.
NOTE:
1 Covered by U.S. Patents #5,649,122, #5,949,787
APPLICATIONS
• Remote Access Servers
• Ethernet Network to Serial Ports
• Network Management
• Factory Automation and Process Control
• Point-of-Sale Systems
• Multi-port RS-232/RS-422/RS-485 Cards
• High Performance Quad UART
• PCI Bus 2.2 Target Interface Compliance
• 3.3 Volt PCI Bus Compliant up to 33 MHz Clock
• 5 Volt Tolerant Serial Inputs
• 32-bit PCI Bus Interface with EEPROM Interface
• A Global Interrupt Source Register for all 4 UARTs
• Data Transfer in Byte, Word and Double-word
• Data Read/Write Burst Operation
• Each UART is independently Controlled with:
•16C550 Compatible 5G (Fifth Gen) Register Set
•64-byte Transmit and Receive FIFOs
•Transmit and Receive FIFO Level Counters
•Automatic RTS/CTS or DTR/DSR Flow Control
•Automatic Xon/Xoff Software Flow Control
•Automatic RS485 Half-duplex Control Output with
Selectable Turn-around Delay (0 to 15 bit-times)
•Infrared (IrDA 1.0) Data Encoder/Decoder
•Programmable Data Rate with Prescaler
•Up to 4 Mbps Serial Data Rate at 8X
• Eight Multi-Purpose Inputs/outputs
• General Purpose 16-bit Timer/Counter
• Sleep Mode with Automatic Wake-up
• Same Package and Pin-out as the XR17C158,
XR17D158, XR17C154 and XR17D154 UARTs
FIGURE 1. BLOCK DIAGRAM
*5V Tolerance for non-PCI Inputs
CLK (33MHz)
RST#
AD[31:0]
C/BE[3:0]#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
INTA#
IDSEL
PERR#
SERR#
PAR
UART Channel 0
64 Byte TX FIFO
UART
Regs
TX & RX
PCI Local
Bus
Interface
Device
Configuration
Registers
ENIR
BRG
IR
ENDEC
TX0, RX0, DTR0#,
DSR0#, RTS0#,
CTS0#, CD0#, RI0#
64 Byte RX FIFO
UART Channel 1
UART Channel 2
Configuration
Space
Registers
EECK
EEDI
EEDO
EECS
3.3V VCC
GND
EEPROM
Interface
UART Channel 3
16-bit
Timer/Counter
Multi-purpose
.
Inputs/Outputs
Crystal Osc/Buffer
TX3, RX3, DTR3#,
DSR3#, RTS3#,
CTS3#, CD3#, RI3#
MPIO0- MPIO7
XTAL1
XTAL2
TMRCK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
NC
NC
NC
NC
NC
80
79
78
77
76
MPIO3
RX2
81
73
CTS2#
82
NC
DSR2#
83
MPIO2
CD2#
84
74
RI2#
85
75
RTS2#
86
87 DTR2#
GND
NC
92
TX2
NC
93
88
NC
94
89
NC
95
NC
NC
96
VCC
NC
97
90
NC
98
91
RX1
99
100 CTS1#
CD1#
101 DSR1#
103 RI1#
102
DTR1#
104 RTS1#
TX1
105
107 MPIO1
106
108 MPIO0
FIGURE 2. PIN OUT OF THE DEVICE
XTAL2
109
72
XTAL1
110
71
NC
TEST#
111
70
ENIR
TMRCK
NC
VCC
112
69
EEDO
113
68
MPIO4
EEDI
114
67
MPIO5
EECS
115
66
MPIO6
EECK
116
65
MPIO7
NC
117
64
VCC
NC
118
63
GND
NC
119
62
TX3
NC
120
61
DTR3#
NC
121
60
RTS3#
NC
122
59
RI3#
NC
123
58
CD3#
NC
124
57
DSR3#
TX0
125
56
CTS3#
DTR0#
126
RTS0#
127
XR17L154
144-TQFP
55
RX3
54
NC
28
29
30
31
32
33
34
35
36
AD12
AD11
AD10
AD9
AD8
VI/O
GND
CBE0
PAR
VI/O
AD13
AD7
27
AD6
37
AD14
38
144
26
143
AD25
AD15
AD26
CBE1 25
AD5
24
39
SERR# 23
142
PERR# 22
AD4
AD27
21
AD3
40
20
41
141
GND
140
AD28
STOP#
AD29
19
AD2
DEVSEL# 18
42
17
139
TRDY#
AD1
AD30
16
43
IRDY#
138
FRAME# 15
AD0
AD31
CBE2 14
VI/O
44
13
45
137
AD16
136
VI/O
12
GND
AD17
GND
11
46
AD18
135
9
NC
CLK
10
47
AD20
134
AD19
NC
RST#
8
48
AD21
133
6
NC
INTA#
7
49
AD23
132
AD22
NC
RX0
5
50
GND
131
4
NC
CTS0#
VI/O
51
3
130
IDSEL
NC
DSR0#
2
NC
52
1
53
CBE3
128
129
AD24
RI0#
CD0#
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING
TEMPERATURE
RANGE
DEVICE STATUS
XR17L154CV
144-Lead TQFP
0°C to +70°C
Discontinued. See XR17D154CV for a replacement.
XR17L154IV
144-Lead TQFP
-40°C to +85°C
Discontinued. See XR17D154IV for a replacement.
2
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
PIN DESCRIPTIONS
NAME
PIN #
TYPE
DESCRIPTION
PCI LOCAL BUS INTERFACE
RST#
134
I
Bus reset input (active low). It resets the PCI local bus configuration space
registers, device configuration registers and UART channel registers to the
default condition, see Table 18 .
CLK
135
I
Bus clock input of up to 33MHz at 3.3V.
AD31-AD0
138-144,
1, 6-13
26-33
37-44
IO
Address data lines [31:0] (bidirectional).
FRAME#
15
I
Bus transaction cycle frame (active low). It indicates the beginning and duration of an access.
C/BE3#C/BE0#
2,14,25,36
I
Bus Command/Byte Enable [3:0] (active low). This line is multiplexed for bus
Command during the address phase and Byte Enable during the data phase.
IRDY#
16
I
Initiator Ready (active low). During a write, it indicates valid data is present on
data bus. During a read, it indicates the master is ready to accept data.
TRDY#
17
O
Target Ready (active low).
STOP#
21
O
Target request to stop current transaction (active low). 5
IDSEL
3
I
Initialization device select (active high).
DEVSEL#
18
O
Device select to the XR17L154 (active low).
INTA#
133
OD
Device interrupt from XR17L154 (open drain, active low).
PAR
24
IO
Parity is even across AD[31:0] and C/BE[3:0]# (bidirectional, active high).
PERR#
22
O
Parity error indicator to host (active low). Optional in bus target application.
SERR#
23
OD
System error indicator to host (open drain, active low). Optional in bus target
application.
MODEM OR SERIAL I/O INTERFACE
TX0
125
O
UART channel 0 Transmit Data or infrared transmit data.
RX0
132
I
UART channel 0 Receive Data or infrared receive data. Normal RXD input
idles at logic 1 condition. The infrared pulses can be inverted internally prior
the decoder by FCTR[4].
RTS0#
127
O
UART channel 0 Request to Send or general purpose output (active low).
CTS0#
131
I
UART channel 0 Clear to Send or general purpose input (active low).
DTR0#
126
O
UART channel 0 Data Terminal Ready or general purpose output (active low).
DSR0#
130
I
UART channel 0 Data Set Ready or general purpose input (active low).
CD0#
129
I
UART channel 0 Carrier Detect or general purpose input (active low).
RI0#
128
I
UART channel 0 Ring Indicator or general purpose input (active low).
TX1
106
O
UART channel 1 Transmit Data or infrared transmit data.
3
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
PIN DESCRIPTIONS
NAME
PIN #
TYPE
DESCRIPTION
RX1
99
I
UART channel 1 Receive Data or infrared receive data. Normal RXD input
idles at logic 1 condition. The infrared pulses can be inverted internally prior
the decoder by FCTR[4].
RTS1#
104
O
UART channel 1 Request to Send or general purpose output (active low).
CTS1#
100
I
UART channel 1 Clear to Send or general purpose input (active low).
DTR1#
105
O
UART channel 1 Data Terminal Ready or general purpose output (active low).
DSR1#
101
I
UART channel 1 Data Set Ready or general purpose input (active low).
CD1#
102
I
UART channel 1 Carrier Detect or general purpose input (active low).
RI1#
103
I
UART channel 1 Ring Indicator or general purpose input (active low).
TX2
88
O
UART channel 2 Transmit Data or infrared transmit data.
RX2
81
I
UART channel 2 Receive Data or infrared receive data. Normal RXD input
idles at logic 1 condition. The infrared pulses can be inverted internally prior
the decoder by FCTR[4].
RTS2#
86
O
UART channel 2 Request to Send or general purpose output (active low).
CTS2#
82
I
UART channel 2 Clear to Send or general purpose input (active low).
DTR2#
87
O
UART channel 2 Data Terminal Ready or general purpose output (active low).
DSR2#
83
I
UART channel 2 Data Set Ready or general purpose input (active low).
CD2#
84
I
UART channel 2 Carrier Detect or general purpose input (active low).
RI2#
85
I
UART channel 2 Ring Indicator or general purpose input (active low).
TX3
62
O
UART channel 3 Transmit Data or infrared transmit data.
RX3
55
I
UART channel 3 Receive Data or infrared receive data. Normal RXD input
idles at logic 1 condition. The infrared pulses can be inverted internally prior
the decoder by FCTR[4].
RTS3#
60
O
UART channel 3 Request to Send or general purpose output (active low).
CTS3#
56
I
UART channel 3 Clear to Send or general purpose input (active low).d.
DTR3#
61
O
UART channel 3 Data Terminal Ready or general purpose output (active low).
DSR3#
57
I
UART channel 3 Data Set Ready or general purpose input (active low).
CD3#
58
I
UART channel 3 Carrier Detect or general purpose input (active low).
RI3#
59
I
UART channel 3 Ring Indicator or general purpose input (active low).
ANCILLARY SIGNALS
MPIO0
108
I/O
Multi-purpose input/output 0. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT
MPIO1
107
I/O
Multi-purpose input/output 1. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO2
74
I/O
Multi-purpose input/output 2. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
4
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
PIN DESCRIPTIONS
NAME
PIN #
TYPE
DESCRIPTION
MPIO3
73
I/O
Multi-purpose input/output 3. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO4
68
I/O
Multi-purpose input/output 4. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO5
67
I/O
Multi-purpose input/output 5. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO6
66
I/O
Multi-purpose input/output 6. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO7
65
I/O
Multi-purpose input/output 7. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
EECK
116
O
Serial clock to EEPROM. Pin has a weak internal pull-down resistor and
requires an external 10K resistor to operate correctly with the EEPROM. An
internal clock of CLK divide by 256 is used for reading the vendor and subvendor ID and model number during power up or reset. However, it can be
manually clocked thru the Configuration Register REGB.
EECS
115
O
Chip select to a EEPROM device like 93C46. It is manually selectable thru the
Configuration Register REGB. Requires a pull-up 4.7KΩ resistor for external
sensing of EEPROM during power up. See DAN112 for further details.
EEDI
114
O
Write data to EEPROM device. It is manually accessible thru the Configuration Register REGB. The L154 auto-configuration register interface logic uses
the 16-bit format.
EEDO
113
I
Read data from EEPROM device. It is manually accessible thru the Configuration Register REGB.
XTAL1
110
I
Crystal or external clock input of up to 33MHz for 2Mbps at 3.3V. Caution:
This input is not 5V tolerant.
XTAL2
109
O
Crystal or buffered clock output.
TMRCK
69
I
16-bit timer/counter external clock input.
ENIR
70
I
Infrared mode enable (active high). Start up all 4 UARTs in infrared mode
upon power up or reset.
TEST#
111
I
Factory Test. Connect to VCC for normal operation.
VCC
64, 90, 112
PWR
5V or 3.3V power supply for the core logic.
VI/O
4, 19, 34, 45, 137
PWR
PCI bus I/O power supply. 3.3V ONLY (PCI 2.2 Compliance).
GND
5,20,35,46,63,
89,136
PWR
Power supply common, ground.
NC
47-54, 71, 72,
75-80, 91-98,
117-124
No Connection. These pins are reserved and used by the octal PCI UART
XR17C158.
NOTE: Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.
5
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
FUNCTIONAL DESCRIPTION
The XR17L154 (L154) integrates the functions of 4 enhanced 16550 UARTs with the PCI Local Bus interface
and a non-volatile memory interface for PCI bus’s plug-and-play auto-configuration, a 16-bit timer/counter, 8
multi-purpose inputs/outputs, and an on-chip oscillator. The PCI local bus is a synchronous timing bus where
all bus transactions are associated to the bus clock of up to 33 MHz. The L154 supports 32-bit wide read and
write data transfer operations including data burst mode through the PCI Local Bus interface. Read and write
data operations maybe in byte, word or double-word (DWORD) format. The data transfer rate in a DWORD
operation is 4 times faster than the single byte operation with 8-bit ISA bus. A single 32-bit interrupt status
register provides interrupts status for all 4 UARTs, timer/counter, multipurpose inputs/outputs, and a special
sleep wake up indicator. There are three sets of register in the device. First, the PCI local bus configuration
registers for PCI auto configuration. A set of device configuration registers for overall control, 32-bit wide
transmit and receive data transfer, and monitoring of the 4 UART channels. Lastly, each UART channel has its
own 16550 UART compatible configuration register set for individual channel control, status, and byte wide
data transfer.
Each UART has the improved fifth generation (5G) register set, 64-byte FIFOs, automatic RTS/CTS or DTR/
DSR hardware flow control with hysteresis control, automatic Xon/Xoff and special character software flow
control, programmable transmit and receive FIFO trigger level, FIFO level counters, infrared encoder and
decoder (IrDA ver 1.0), programmable baud rate generator with a prescaler of 1X or 4X, and data rate up to 2
Mbps. The XR17L154 bus timing and drive capability meets the PCI local bus specification revision 2.2 for 3.3V
33 MHz operation over the temperature range. The XR17L154 is available in the same thin 144-pin TQFP
(20x20x1.4mm) package and pin-out as the XR17C154 and XR17C158 in commercial and industrial
temperature ranges.
PCI LOCAL BUS INTERFACE
This is the host interface and it meets the PCI Local Bus Specification revision 2.2. The PCI local bus
operations are synchronous meaning each transaction is associated to the bus clock. The XR17L154 can
operate with the bus clock of up to a 33 MHz. Data transfers operation can be formatted in 8-bit, 16-bit, 24-bit
or 32-bit wide. With 32-bit data operations, it pushes the data transfer rate on the bus up to 132 MByte/sec.
This increases the overall system’s communication performance up to 16 times better than the 8-bit ISA bus.
See PCI local bus specification revision 2.2 for bus operation details.
PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
A set of PCI local bus configuration space register is provided. These registers provide the PCI local bus
operating system with the card’s vendor ID, device ID, sub-vendor ID, product model number, and resources
and capabilities. The PCI local bus operating system collects this data from all the cards on the bus during the
auto configuration phase that follows immediately after a power up or system reset/reboot. After it has sorted
out all devices on the bus, it defines and download the operating conditions to the cards. One of the definitions
is the base address loaded into the Base Address Register (BAR) where the card will be operating in the PCI
local bus memory space.
EEPROM INTERFACE
An external 93C46 EEPROM is only used to store the vendor’s ID and model number, and the sub-vendor’s ID
and product model number. This information is only used with the plug-and-play auto configuration of the PCI
local bus. These data provide automatic hardware installation onto the PCI bus. The EEPROM interface
consists of 4 signals, EEDI, EEDO, EECS, and EECK. The EEPROM is not needed when auto configuration is
not required in the application. However, If your design requires non-volatile memory for other purpose. It is
possible to store and retrieve data on the EEPROM through a special PCI device configuration register. See
application note DAN112 for its programming details.
6
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
1.0 XR17L154 REGISTERS
The XR17L154 UART has three different sets of registers as shown in Figure 3. The PCI local bus
configuration space registers are for plug-and-play auto-configuration when connecting the device to the PCI
bus. This auto-configuration feature makes installation very easy into a PCI system and it is part of the PCI
local bus specification. The second register set is the device configuration registers that are accessible directly
from the PCI bus for programming general operating conditions of the device and monitoring the status of
various functions. These registers are mapped into 2K of the PCI bus memory address space. These functions
include all 4 channel UART’s interrupt control and status, 16-bit general purpose timer control and status,
multipurpose inputs/outputs control and status, sleep mode, soft-reset, and device identification and revision.
And lastly, each UART channel has its own set of 5G internal UART configuration registers for its own operation
control and status reporting. All 4 sets of channel registers are embedded inside the device configuration
registers space, which provides faster access. The following paragraphs describe all 3 sets of registers in
detail.
FIGURE 3. THE XR17L154 REGISTER SETS
Device Configuration and
UART[3:0] Configuration
Registers are mapped on
to the Base Address
Register (BAR) in a 2Kbyte of memory address
space
PCI Local Bus
Configuration Space
Registers for Plugand-Play Auto
Configuration
Channel 0
INT, MPIO,
TIMER, REG
Vendor and Sub-vendor ID
and Product Model Number
in External EEPROM
0x0000
0x0080
0x0100
PCI Local Bus
Target
Interface
Channel 0
Channel 1
Channel 2
Channel 3
0x0200
0x0400
0x0600
0x07FF
Device Configuration Registers
4 channel Interrupts,
Multipurpose I/Os,
16-bit Timer/Counter,
Sleep, Reset, DVID, DREV
UART[3:0] Configuration
Registers
16550 Compatible and EXAR
Enhanced Registers
PCIREGS-1
1.1
PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
The PCI local bus configuration space registers are responsible for setting up the device’s operating
environment in the PCI local bus. The pre-defined operating parameters of the device are read by the PCI bus
plug-and-play auto-configuration manager in the operating system. After the PCI bus has collected all data
from every device/card on the bus, it defines and downloads the memory mapping information to each device/
card about their individual operation memory address location and conditions. The operating memory mapped
address location is downloaded into the Base Address Register (BAR) register, 0x10. The plug-and-play auto
configuration feature is only available when an external 93C46 EEPROM is used. The EEPROM contains the
device vendor and sub-vendor data required by the auto-configuration setup.
7
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
ADDRESS
0x00
0x04
TYPE
31:16
RWR1
Device ID (Exar device ID number or from EEPROM)
0x0154
15:0
RWR1
Vendor ID (Exar ID or from EEPROM) specified by PCISIG
0x13A8
31:28
RO
27
R-Reset
DESCRIPTION
RESET VALUE
(HEX)
BITS
Status bits (error reporting bits)
0000
Target Abort. Set whenever L154 terminates with a target abort.
0
26:25
RO
DEVSEL# timing.
00
24
RO
Unimplemented bus master error reporting bit
0
23
RO
Fast back to back transactions are supported
1
22:16
RO
Reserved Status bits
15:9,7,
5,4,3,2
RO
Command bits (reserved)
8
WO
SERR# driver enable. Logic 1=enable driver and 0=disable driver
0
6
WO
Parity error enable. Logic 1=respond to parity error and 0=ignore
0
1
RWR
Command controls a device’s response to mem space accesses:
0=disable mem space accesses, 1=enable mem space accesses
0
0
RO
Command controls a device’s response to I/O space accesses:
0 = disable I/O space accesses 1 = enable I/O space accesses
0
31:8
RO
Class Code (Simple 550 Communication Controller).
7:0
RO
Revision ID (Exar device revision number)
0x01
31:24
RO
BIST (Built-in Self Test)
0x00
23:16
RO
Header Type (a single function device with one BAR)
0x00
15:8
RO
Unimplemented Latency Timer (needed only for bus master)
0x00
7:0
RO
Unimplemented Cache Line Size
0x00
31:11
RW
Memory Base Address Register (BAR)
0x00
10:0
RO
Claims a 2K address space for the memory mapped UARTs
0x14
31:0
RO
Unimplemented Base Address Register (returns zeros)
0x00000000
0x18h
31:0
RO
Unimplemented Base Address Register (returns zeros)
0x00000000
0x1C
31:0
RO
Unimplemented Base Address Register (returns zeros)
0x00000000
0x20
31:0
RO
Unimplemented Base Address Register (returns zeros)
0x00000000
0x24
31:0
RO
Unimplemented Base Address Register (returns zeros)
0x00000000
0x28
31:0
RO
Reserved
0x00000000
0x2C
31:16
RWR1
0x08
0x0C
0x10
000 0000
Subsystem ID (write from external EEPROM by customer)
8
0x0000
0x070002
0xX000
0x0000
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
ADDRESS
BITS
TYPE
DESCRIPTION
RESET VALUE
(HEX)
15:0
RWR1
0x30
31:0
RO
Expansion ROM Base Address (Unimplemented)
0x00000000
0x34
31:0
RO
Reserved (returns zeros)
0x00000000
0x38
31:0
RO
Reserved (returns zeros)
0x00000000
0x3C
31:24
RO
Unimplemented MAXLAT
0x00
23:16
RO
Unimplemented MINGNT
0x00
15:8
RO
Interrupt Pin, use INTA#.
0x01
7:0
RWR
Interrupt Line.
0xXX
Subsystem Vendor ID (write from external EEPROM by customer)
0x0000
NOTE: RWR1=Read/Write from external EEPROM. RWR=Read/Write from AD[31:0]. RO= Read Only. WO=Write Only.
1.2
Device configuration Register Set
The device configuration registers and a special way to access each of the UART’s transmit and receive data
FIFOs are accessible directly from the PCI data bus. This provides easy programming of general operating
parameters to the L154 UART and for monitoring the status of various functions. The registers occupy 2K of
PCI bus memory address space. These addresses are offset onto the basic memory address, a value loaded
into the Memory Base Address Register (BAR) in the PCI local bus configuration register set. These registers
control or report on all 4 channel UARTs functions that include interrupt control and status, 16-bit general
purpose timer control and status, multipurpose inputs/outputs control and status, sleep mode control, softreset control, and device identification and revision, and others.
The registers set is mapped into 4 address blocks where each UART channel occupies 512 bytes memory
space for its own 16550 compatible configuration registers. The device configuration and control registers are
embedded inside the UART channel zero’s address space between 0x0080 to 0x0093. All these registers can
be accessed in 8, 16, 24 or 32 bit width depending on the starting address given by the host at beginning of the
bus cycle. Transmit and receive data may be loaded or unloaded in 8, 16, 24 or 32 bit format to the register’s
address. Every time a read or write operation is made to the transmit or receive register, its FIFO data pointer
is automatically bumped to the next sequential data location either in byte, word or dword. One special case
applies to the receive data unloading when reading the receive data together with its LSR register content. The
host must read them in 16 or 32 bits format in order to maintain integrity of the data byte with its associated
error flags.
9
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
TABLE 2: XR17L154 DEVICE CONFIGURATION REGISTERS
OFFSET ADDRESS
MEMORY SPACE
READ/WRITE
DATA WIDTH
COMMENT
( Table 10 &
Table 11)
8/16/24/32
First 8 regs are 16550 compatible
( Table 3)
8/16/24/32
0x000 - 0x00F
UART channel 0 Regs
0x010 - 0x07F
Reserved
0x080 - 0x093
DEVICE CONFIG. REGISTERS
0x094 - 0x0FF
Reserved
Read/Write
0x100
UART 0 – Read FIFO
Read-Only
8/16/24/32
64 bytes of RX FIFO data
0x100
UART 0 – Write FIFO
Write-Only
8/16/24/32
64 bytes of TX FIFO data
0x140 - 0x17F
Reserved
0x180 - 0x1FF
UART 0 – Read FIFO with errors
Read-Only
16/32
64 bytes of RX FIFO data + LSR
0x200 - 0x20F
UART channel 1 Regs
( Table 10 &
Table 11)
8/16//24/32
First 8 regs are 16550 compatible
0x210 - 0x2FF
Reserved
Read/Write
0x300
UART 1 – Read FIFO
Read-Only
8/16/24/32
64 bytes of RX FIFO data
0x300
UART 1 – Write FIFO
Write-Only
8/16/24/32
64 bytes of TX FIFO data
0x340 - 0x37F
Reserved
0x380 - 0x3FF
UART 1 – Read FIFO with errors
Read-Only
16/32
64 bytes of RX FIFO data + LSR
0x400 - 0x40F
UART channel 2 Regs
( Table 10 &
Table 11)
8/16/24/32
First 8 regs are 16550 compatible
0x410 - 0x4FF
Reserved
Read/Write
0x500
UART 2 – Read FIFO
Read-Only
8/16/24/32
64 bytes of RX FIFO data
0x500
UART 2 – Write FIFO
Write-Only
8/16/24/32
64 bytes of TX FIFO data
0x540 - 0x57F
Reserved
0x580 - 0x5FF
UART 2 – Read FIFO with errors
Read-Only
16/32
64 bytes of RX FIFO data + LSR
0x600 - 0x60F
UART channel 3 Regs
( Table 10 &
Table 11)
8/16/24/32
First 8 regs are 16550 compatible
0x610 - 0x6FF
Reserved
Read/Write
0x700
UART 3 – Read FIFO
Read-Only
8/16/24/32
64 bytes of RX FIFO data
0x700
UART 3 – Write FIFO
Write-Only
8/16/24/32
64 bytes of TX FIFO data
0x740 - 0x77F
Reserved
0x780 - 0x7FF
UART 3 – Read FIFO with errors
Read-Only
16/32
10
64 bytes of RX FIFO data + LSR
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
TABLE 3: DEVICE CONFIGURATION REGISTERS SHOWN IN BYTE ALIGNMENT
ADDRESS
[A7:A0]
REGISTER
Ox080
INT0 [7:0]
Read-only Interrupt [3:0], Reserved [7:4]
Bits 7-0 = 0x00
Ox081
INT1 [15:8]
Read-only
Bits 7-0 = 0x00
Ox082
INT2 [23:16]
Read-only [3:0], Reserved [7:4]
Bits 7-0 = 0x00
Ox083
INT3 [31:24]
Reserved [7:0]
Bits 7-0 = 0x00
Ox084
TIMERCNTL
Read/Write Timer Control
Bits 7-0 = 0x00
Ox085
TIMER
Reserved
Bits 7-0 = 0x00
Ox086
TIMERLSB
Read/Write Timer LSB
Bits 7-0 = 0x00
Ox087
TIMERMSB
Read/Write Timer MSB
Bits 7-0 = 0x00
Ox088
8XMODE
Read/Write
Bits 7-0 = 0x00
Ox089
REGA
Reserved
Bits 7-0 = 0x00
Ox08A
RESET
Write-only Self clear bits after executing Reset [3:0]
Bits 7-0 = 0x00
Ox08B
SLEEP
Read/Write Sleep mode [3:0]
Bits 7-0 = 0x00
Ox08C
DREV
Read-only Device revision
Bits 7-0 = 0x01
Ox08D
DVID
Read-only Device identification
Bits 7-0 = 0x24
Ox08E
REGB
Read/Write
Bits 7-0 = 0x00
Ox08F
MPIOINT
Read/Write MPIO interrupt mask
Bits 7-0 = 0x00
Ox090
MPIOLVL
Read/Write MPIO level control
Bits 7-0 = 0x00
Ox091
MPIO3T
Read/Write MPIO output control
Bits 7-0 = 0x00
Ox092
MPIOINV
Read/Write MPIO input polarity select
Bits 7-0 = 0x00
Ox093
MPIOSEL
Read/Write MPIO select
Bits 7-0 = 0xFF
READ/WRITE COMMENT
11
RESET STATE
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
TABLE 4: DEVICE CONFIGURATION REGISTERS SHOWN IN DWORD ALIGNMENT
ADDRESS
REGISTER
BYTE 3 [31:24]
BYTE 2 [23:16]
BYTE 1 [15:8]
BYTE 0 [7:0]
0x080-083
INTERRUPT (read-only)
INT3
INT2
INT1
INT0
0x084-087
TIMER (read/write)
TIMERMSB
TIMERLSB
TIMER
(reserved)
TIMERCNTL
0x088-08B
ANCILLARY1 (read/write)
SLEEP
RESET
REGA
(reserved)
8XMODE
0x08C-08F
ANCILLARY2 (read-only)
MPIOINT
REGB
DVID
DREV
0x090-093
MPIO (read/write)
MPIOSEL
MPIOINV
MPIO3T
MPIOLVL
1.2.1
The Interrupt Status Register
The XR17L154 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and
supports two interrupt schemes. The first scheme is a 4-bit indicator in INT0 register representing the 4
channels with the first 4 bits representing each channel from 0 to 3. This permits the interrupt routine to quickly
vector and serve that UART channel and determine the source(s) in each individual routines. INT0 bit-0
represents the interrupt status for UART channel 0 when its transmitter, receiver, line status, or modem port
status requires service. Other bits in the INT0 register provide indication for the other channels with bit-3
representing UART channel 4 respectively, bits 4 to 7 are reserved and remain at logic zero.
The second scheme provides detail about the source of the interrupts for each UART channel. All the interrupts
are encoded into a 3-bit code. This 3-bit code represents 7 interrupts corresponding to individual UART’s
transmitter, receiver, line status, modem port status. INT1 and INT2 registers provide the 12-bit interrupt status
for all 4 channels. Bits 8, 9 and 10 representing channel 0 and bits 17,18 and 19 representing channel 3
respectively. Bits 20 to 31 are reserved and remain at logic zero. All 4 channel interrupts status are available
with a single DWORD read operation. This feature allows the host quickly vectors and serves the interrupts,
reducing service interval, hence, reduce host bandwidth requirement.
GLOBAL INTERRUPT REGISTER (DWORD) - [default 0x00-00-00-00]
INT3 [31:24]
INT2 [23:16]
INT1 [15:8]
INT0 [7:0]
All bits start up zero. A special interrupt condition is generated by the L154 upon awakening from sleep after all
4 channels were put to sleep mode earlier. Figure 4 shows the 4-byte interrupt register and its make up.
INT0 [7:0] Channel Interrupt Indicator
Each bit gives an indication of the channel that has requested for service. Bit-0 represents channel 0 and bit-3
indicates channel 3. Logic one indicates the channel N [3:0] has called for service. Bits 4 to 7 are reserved and
remain at logic zero The interrupt bit clears after reading the appropriate register of the interrupting channel
register, see Interrupt Clearing section.
INT0 register provides status for each channel
IN T0 R egister
Individual U A R T C hannel Interrupt S tatus
R s vd R s vd R s vd R s vd C h-3 C h-2 C h-1 C h-0
B it-7 B it-6
B it-5
B it-4
B it-3
12
B it-2
B it-1
B it-0
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
Registers INT3, INT2 and INT1 [32:8]
Twenty four bit encoded interrupt indicator. Each channel’s interrupt is encoded into 3 bits for receive, transmit,
and status. Bit [10:8] represent channel 0 and go up to channel 3 with bits [19:17]. The 3 bit encoding and their
priority order are shown below in Table 5 . The Timer and MPIO interrupts are for the device and therefore they
exist within channel 0 space and not in other channel interrupt.
.
FIGURE 4. THE GLOBAL INTERRUPT REGISTER, INT0, INT1, INT2 AND INT3
Interrup t Reg isters,
INT0, IN T1, INT 2 and INT3
INT3 Register
R svd
Bit
N+2
Bit
N+1
INT2 Register
R svd
Bit
N
Bit
N+2
Bit
N+1
R svd
Bit
N
Bit
N+2
Bit
N+1
C h an ne l-3
R svd
Bit
N
Bit
N+2
Bit
N+1
INT1 Register
Bit
N
Bit
N+2
Bit
N+1
C h an ne l-2
Bit
N
Bit
N+2
Bit
N+1
C h an ne l-1
Bit
N
Bit
N+2
Bit
N+1
C h an ne l-0
Bit
N
Bit
N+2
Bit
N+1
Bit
N
INT0 Register
R svd
Bit-7
R svd R svd
Bit-6
R svd
Bit-5 Bit-4
C h -3 C h -2 C h -1 C h -0
Bit-3
Bit-2
Bit-1
Bit-0
TABLE 5: UART CHANNEL [3:0] INTERRUPT SOURCE ENCODING
PRIORITY
BIT[N+2]
BIT[N+1]
BIT[N]
INTERRUPT SOURCE(S)
x
0
0
0
None
1
0
0
1
RXRDY and RX Line Status (logic OR of LSR[4:1])
2
0
1
0
RXRDY Time-out
3
0
1
1
TXRDY, THR or TSR (auto RS485 mode) empty
4
1
0
0
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon det. or special char. detected
5
1
0
1
Reserved.
6
1
1
0
MPIO pin(s). Available only within channel 0, reserved in other channels.
7
1
1
1
TIMER Time-out. Available only within channel 0, reserved in other channels.
13
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
TABLE 6: UART CHANNEL [3:0] INTERRUPT CLEARING:
RXRDY is clear by reading data in the RX FIFO until it falls below the trigger level.
RXRDY Time-out interrupt is cleared when the RX FIFO becomes empty.
RX Line Status interrupt clears after reading the LSR register.
TXRDY interrupt clears after reading ISR register that is in the UART channel register set.
Modem Status Register interrupt clears after reading MSR register that is in the UART channel register set.
RTS/CTS or DTR/DSR delta interrupt clears after reading MSR register that is in the UART channel register set.
Xoff/Xon delta and special character detect interrupt clears after reading the ISR register in the UART channel register set.
TIMER Time-out interrupt clears after reading the TIMERCNTL register that is in the Device Configuration register set.
MPIO interrupt clears after reading the MPIOLVL register that is in the Device Configuration register set.
1.2.2
General Purpose 16-bit Timer/Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT
0XXX-XX-00-00)
A 16-bit down-count timer for general purpose timer or counter. Its clock source may be selected from internal
crystal oscillator or externally on pin TMRCK. The timer can be set to be a single-shot for a one-time event or
re-triggerable for continue interval. An interrupt may be generated in the INT Register when the timer times out.
It is controlled through 4 configuration registers [TIMERCNTL, TIMER, TIMELSB, TIMERMSB]. These
registers provide start/stop and re-triggerable or one-shot operation. The time-out output of the Timer can be
set to generate an interrupt for system or event alarm.
FIGURE 5. TIMER/COUNTER CIRCUIT.
T IM E R M S B a n d T IM E R L S B
(1 6 -b it V a lu e )
TMRCK
OSC. CLOCK
T IM E R C N T L [3 ]
T IM E R C N T L [1 ]
T IM E R C N T L [2 ]
T IM E R C N T L [0 ]
T im e -o u t
1 6 -B it
T im er/C ou n te r
1
0
C lo ck
S e le ct
1
0
T im er In te rru p t, C h-0 IN T = 7
N o In te rru p t
R e -trig g e r
0
1
S ta rt/S to p
S in g le /R e -trig g e ra b le
S in g le -sh o t
1
0
M P IO [0 ]
M P IO LV L [0 ]
T im e r In te rru p t E n a b le
T IM E R C N T L [4 ]
TABLE 7: TIMER CONTROL REGISTERS
TIMERCNTL [0]
Logic zero (default) disables Timer-Counter interrupt and logic one enables the interrupt, reading the
TIMERCNTL clears the interrupt.
TIMERCNLT [1]
Logic zero (default) stops/pauses the timer and logic one starts/re-starts the timer/counter.
TIMERCNTL [2]
Logic zero (default) selects re-trigger timer function and logic one selects one-shot (timer function.
TIMERCNTL [3]
Logic zero (default) selects internal and logic one selects external clock to the timer/counter.
TIMERCNTL [4]
Routes the Timer-Counter interrupt to MPIO[0] if MPIOSEL[0]=0 for external event control.
TIMERCNTL [7:5]
Reserved (defaults to zero)
14
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
T IM E R C N T L R eg ister
B it-7 B it-6
R s vd
B it-5
R s vd
R s vd
B it-4
B it-3
B it-2
M P IO [0 ] C lo c k
S in g le /
C o n tro l S e le c t R e -trig g e r
B it-1
B it-0
S ta rt/
S to p
IN T
E n a b le
TIMER [15:8] - (default 0x00)
Reserved.
TIMERMSB [31:24] and TIMERLSB [23:16]
TIMERMSB and TIMERLSB form a 16-bit value. The least-significant bit of the timer is being bit [0] of the
TIMERLSB with most-significant-bit being bit [7] in TIMERMSB. Notice that these registers do not hold the
current counter value when read. Reading the TIMERCNTL register will clear its interrupt. Default value is zero
(timer disabled) upon powerup and reset.
1 6 -B it T im e r/C o u n te r P ro g ra m m a b le R e g iste rs
TIM E RM S B R eg ister
B it-1 5
B it-1 4
1.2.3
B it-1 3
B it-1 2
B it-1 1
TIM E RL SB R eg ister
B it-1 0
B it-9
B it-7
B it-8
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1 B it-0
8XMODE [7:0] - (default 0x00)
Each bit selects 8X or 16X sampling rate for that UART channel, bit-0 is channel 0. Logic 0 (default) selects
normal 16X sampling with logic one selects 8X sampling rate. Transmit and receive data rates will double by
selecting 8X.
8XM O D E R egister
Individual UA R T Channel 8X C lock M ode E nable
B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0
R svd R svd R svd R svd C h-3 C h-2 C h-1 C h-0
1.2.4
REGA [15:8] - (default 0x00)
Reserved.
1.2.5
RESET [23:16] - (default 0x00)
The 8-bit Reset register [RESET] provides the software with the ability to reset the UART(s) when there is a
need. Each bit is self-resetting after it is written a logic 1 to perform a reset to that channel. All registers in that
channel will be reset to the default condition, see Table 18 for details. Bit-0 =1 resets UART channel 0 with bit3=1 resets channel 3..
RES ET Register
Individual U A RT C hannel R eset E nable
B it-7 B it-6 B it-5 B it-4 B it-3 Bit-2 Bit-1 Bit-0
R svd R svd R svd R svd C h-3 C h-2 C h-1 C h-0
15
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
1.2.6
REV. 1.1.0
SLEEP [31:24] - (default 0x00)
The first four bits of the Sleep register enables each UART channel separately to enter Sleep mode. The upper
bits 4 to 7 are reserved. Sleep mode reduces power consumption when the system needs to put the UART(s)
to idle. The UART enters Sleep mode when there is no interrupt pending. When all 4 UARTs are put to sleep,
the on-chip oscillator shuts off to further conserve power. In this case, the quad UART is awaken by any of the
UART channel on from a receive data byte or a change on the serial port. The UART is ready after 32 crystal
clocks to ensure full functionality. Also, a special interrupt is generated with an indication of no pending
interrupt. Logic 0 (default) is disable and logic 1 is enable to Sleep mode.
SLEEP Register
Individual U A R T C hannel S leep E nable
B it-7 Bit-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0
R svd R svd R svd R svd C h-3 C h-2 C h-1 C h-0
1.2.7
Device Identification and Revision
There are 2 internal registers that provide device identification and revision, DVID and DREV registers. The 8bit content in the DVID register provides device identification. A return value of 0x24 from this register indicates
the device is an XR17L154 or an XR17C154. The DREV register returns an 8-bit value of 0x01 for revision A
with 0x02 equals to revision B and so forth. This information is very useful to the software driver for identifying
which device it is communicating with and to keep up with revision changes.
DVID [15:8] - (default 0x24)
Device identification for the type of UART. The upper nibble indicates it is a XR17Cxxx series with lower nibble
indicating the number of channels.
Examples:
XR17C158 = 0x28
XR17L154 or XR17L154 = 0x24
XR17C152 or XR17L152 = 0x22
DREV [7:0] - (default (0x01)
Revision number of the XR17L154. A 0x01 represents "revision-A" with 0x02 for rev-B and so forth.
REGB [23:16] - (default 0x00)
REGB register provides a control for simultaneous write to all 4 UARTs configuration register or individually.
This is very useful for device initialization in the power up and reset routines. Also, the register provides a
facility to interface to the non-volatile memory device such as a 93C46 EEPROM. In embedded applications,
the user can use this facility to store proprietary data.
1.2.8
RGEB Register
REGB[16] (Read/Write)
Logic 0 (default) write to each UART configuration registers individually.
Logic 1 enables simultaneous write to all 4 UARTs configuration register.
REGB[19:17]
Reserved
REGB[20] (Write-Only)
Control the EECK, clock, output (pin 116) on the EEPROM interface.
REGB[21] (Write-Only)
Control the EECS, chips select, output (pin 115) to the EEPROM device.
REGB[22] (Write-Only)
EEDI (pin 114) data input. Write data to the EEPROM device.
REGB[23] (Read-Only)
EEDO (pin 113) data output. Read data from the EEPROM device.
16
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
1.2.9
Multi-Purpose Inputs and Outputs
The L154 provides 8 multi-purpose inputs/outputs [MPIO7:0] for general use. Each pin can be programmed to
be an input or output function. The input logic state can be set for normal or inverted level, and optionally set to
generate an interrupt. The outputs can be set to be normal logic 1 or 0 state, or tri-state. Their functions and
definitions are programmed through 5 registers: MPIOINT, MPIOLVL, MPIO3T, MPIOINV and MPIOSEL. If all 8
pins are set for inputs, all 8 interrupts would be or’ed together. The Or’ed interrupt is reported in the channel 0
UART interrupt status, see Interrupt Status Register. The pins may also be programmed to be outputs and to
the tri-state condition for signal sharing.
1.2.10
MPIO REGISTER
Bit 7 represents MPIO7 pin and bit 0 represents MPIO0 pin. There are 5 registers that select, control and
monitor the 8 multipurpose inputs and outputs pins. Figure 6 shows the internal circuitry.
FIGURE 6. MULTIPURPOSE INPUT/OUTPUT INTERNAL CIRCUIT
M PIO IN T [7:0]
IN T
AND
R ising Edge
D etection
AND
1
M PIO
Pin [7:0]
M PIO LVL [7:0]
R ea d Inp ut Le vel
0
M PIO IN V [7:0]
(Inp ut In versio n E na ble =1 )
M PIO LVL [7:0]
(O utp ut Level)
M PIO 3T [7:0]
(3-sta te En ab le =1 )
OR
M PIO SE L [7:0]
(S elect Inp ut=1 , O u tp ut= 0 )
M P IO C KT
17
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
MPIOINT [7:0] - (default 0x00)
Enable multipurpose input pin interrupt. If the pin is selected by MPIOSEL as input then bit-0 enables input pin
0 for interrupt, and bit-7 enables input pin 7. No interrupt is enable if the pin is selected to be an output. The
interrupt is edge sensing and determined by MPIOINV and MPIOLVL registers. The MPIO interrupt clears after
a read to register MPIOLVL. The combination of MPIOLVL and MPIOINV determines the interrupt being active
low or active high, it’s level trigger. Logic 0 (default) disables the pin’s interrupt and logic 1 enables it.
M PIO IN T R egister
M ultipu rpo se Inp ut/O u tpu t In terrup t E n ab le
B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0
M P IO 7 M P IO 6 M P IO 5 M P IO 4 M P IO 3 M P IO 2 M P IO 1 M P IO 0
MPIOLVL [7:0] - (default 0x00)
Output pin level control and input level status. The status of the input pin(s) is read on this register and output
pins are controlled on this register. A logic 0 (default) sets the output to low and a logic 1 sets the output pin to
high. The MPIO interrupt will clear upon reading this register.
M PIO L VL R egister
M ultipurpose O utput Level C ontrol
B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0
M P IO 7 M P IO 6 M P IO 5 M P IO 4 M P IO 3 M P IO 2 M P IO 1 M P IO 0
MPIO3T [7:0] - (default 0x00)
Output pin tri-state control. A logic 0 (default) sets the output to active level per register MPIOBIT settling, a
logic 1 sets the output pin to tri-state.
M PIO 3T Register
M ultipurpose O utput 3-state E n able
B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0
M P IO 7 M P IO 6 M P IO 5 M P IO 4 M P IO 3 M P IO 2 M P IO 1 M P IO 0
MPIOINV [7:0] - (default 0x00)
Input inversion control. A logic 0 (default) does not invert the input pin logic. A logic 1 inverts the input logic
level.
M PIO INV Register
M ultipurpose Input S ignal Inversion E nable
B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0
M P IO 7 M P IO 6 M P IO 5 M P IO 4 M P IO 3 M P IO 2 M P IO 1 M P IO 0
18
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
MPIOSEL [7:0] - (default 0xFF)
Multipurpose input/output pin select. This register defines the functions of the pins. A logic 1 (default) defines
the pin for input and a logic "0" for output.
MPIOSEL Register
Multipurpose Input/Output Selection
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO7 MPIO6 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
2.0 CRYSTAL OSCILLATOR / BUFFER
The L154 includes an on-chip oscillator (XTAL1 and XTAL2). The crystal oscillator provides the system clock to
the Baud Rate Generators (BRG) in each of the 4 UARTs, the 16-bit general purpose timer/counter and
internal logics. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the output.
Caution: The XTAL1 input is not 5V tolerant. See Programmable Baud Rate Generator in the UART section for
programming details.
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant with
10-22 pF capacitance load, 100ppm) connected externally between the XTAL1 and XTAL2 pins (see Figure 7).
Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal 8 baud rate generators
for standard or custom rates. Typically, the oscillator connections are shown in Figure 7. For further reading on
oscillator circuit please see application note DAN108 on EXAR’s web site.
FIGURE 7. TYPICAL OSCILLATOR CONNECTIONS
R =3 0 0 K to 4 00 K
X T A L1
1 4 .7 45 6
MHz
X T A L2
C2
2 2 -4 7 pF
C1
2 2 -4 7 pF
3.0 TRANSMIT AND RECEIVE DATA
There are two methods to load transmit data and unload receive data from each UART channel. First, there is
a transmit data register and receive data register for each UART channel in the device configuration register set
to ease programming. These registers support 8, 16, 24 and 32 bits wide format. In the 32-bit format, it
increases the data transfer rate on the PCI bus. Additionally, a special register location provides receive data
byte with its associated error flags. This is a 16-bit or 32-bit read operation where the Line Status Register
(LSR) content in the UART channel register is paired along with the data byte. This operation further facilitates
data unloading with the error flags without having to read the LSR register separately. Furthermore, the
XR17L154 supports PCI burst mode for read/write operation of up to 64 bytes of data.
The second method is through each UART channel’s transmit holding register (THR) and receive holding
register (RHR). The THR and RHR registers are 16550 compatible so their access is limited to 8-bit format.
The software driver must separately read the LSR content for the associated error flags before reading the data
byte.
19
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
3.1
REV. 1.1.0
FIFO DATA LOADING AND UNLOADING THROUGH THE DEVICE CONFIGURATION REGISTERS
IN 32-BIT FORMAT.
The transmit and receive data registers are defined for channel 0 to channel 3 with each channel having it’s
own address as shown in Table 2 for faster loading and unloading. The following paragraphs illustrate the
receive and transmit data registers in more detail.
Each Channel Normal Receive Data FIFO Address for channels 0 to 3 are at 0x0100, 0x0300, 0x0500 and
0x0700.
READ RX FIFO,
WITH NO ERRORS
BYTE 3
BYTE 2
BYTE 1
BYTE 0
Read n+0 to n+3
FIFO Data n+3
FIFO Data n+2
FIFO Data n+1
FIFO Data n+0
Read n+4 to n+7
FIFO Data n+7
FIFO Data n+6
FIFO Data n+5
FIFO Data n+4
Etc.
Channel 0 to 3 ReceiveData in 32-bit alignm ent through the Configuration Register A ddress
0x0100, 0x0300, 0x0500 and 0x0700
R e ce ive D a ta B yte n + 3
B7
B6
B5
B4
B3
B2
B1
R e ce ive D a ta B yte n + 2
B0
B7
B6
B5
B4
B3
B2
B1
R e ce ive D a ta B yte n + 1
B0
B7
B6
B5
B4
B3
B2
B1
R e ce ive D a ta B yte n + 0
B0
B7
B6
B5
PCI Bus
D a ta B it-31
B4
B3
B2
B1
B0
PCI Bus
D a ta B it-0
Each Channel Normal Transmit Data FIFO Address for Channel 0 to 3 are at 0x0100, 0x0300, 0x0500 and
0x0700.
WRITE TX FIFO
BYTE 3
BYTE 2
BYTE 1
BYTE 0
Write n+0 to n+3
FIFO Data n+3
FIFO Data n+2
FIFO Data n+1
FIFO Data n+0
Write n+4 to n+7
FIFO Data n+7
FIFO Data n+6
FIFO Data n+5
FIFO Data n+4
Etc.
Channel 0 to 3 Transmit Data in 32-bit alignment through the Configuration Register Address
0x0100, 0x0300, 0x0500 and 0x0700
Transmit Data Byte n+3
Transmit Data Byte n+2
Transmit Data Byte n+1
Transmit Data Byte n+0
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
PCI Bus
Data Bit-31
PCI Bus
Data Bit-0
Each Channel Special Receive FIFO Data Address for channel 0 to 3 are at 0x0180 0x380, 0x0580 and
0x0780. The Status and Data bytes must be read in 16 or 32 bits format to maintain data integrity.
20
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
READ RX FIFO,
WITH LSR ERRORS
BYTE 3
BYTE 2
BYTE 1
BYTE 0
Read n+0 to n+1
FIFO Data n+1
LSR n+1
FIFO Data n+0
LSR n+0
Read n+2 to n+3
FIFO Data n+3
LSR n+3
FIFO Data n+2
LSR n+2
Etc
Channel 0 to 3 Receive Data with Line Status Register in a 32-bit alignm ent through
the Configuration Register Address 0x0180, 0x0380, 0x0580 and 0x0780
R e ce ive D a ta B yte n + 1
B7
B6
B5
B4
B3
B2
B1
L in e S ta tu s R e g iste r n + 1
B0
B7
B6
B5
B4
B3
B2
B1
R e ce ive D a ta B yte n + 0
B0
B7
B6
B5
B4
B3
B2
B1
L in e S ta tu s R e g iste r n + 0
B0
B7
B6
B5
B4
B3
B2
PCI Bus
D a ta B it-3 1
3.2
B1
B0
PCI Bus
D a ta B it-0
FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR
AND RHR IN 8-BIT FORMAT.
The THR and RHR register address for channel 0 to channel 3 is shown in Table 8 below. The THR and RHR
for each channel 0 to 3 are located sequentially at address 0x0000, 0x0200, 0x0400 and 0x0600. Transmit
data byte is loaded to the THR when writing to that address and receive data is unloaded from the RHR
register when reading that address. Both THR and RHR registers are 16C550 compatible in 8-bit format, so
each bus operation can only write or read in bytes.
TABLE 8: TRANSMIT AND RECEIVE DATA REGISTER IN BYTE FORMAT, 16C550 COMPATIBLE
THR and RHR Address Locations For CH0 to CH3 (16C550 Com patible)
C H 0 0x00 0 W rite T H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C H 0 0x00 0 R ead R H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C H 1 0x20 0 W rite T H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C H 1 0x20 0 R ead R H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C H 2 0x40 0 W rite T H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C H 2 0x40 0 R ead R H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C H 3 0x60 0 W rite T H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
C H 3 0x60 0 R ead R H R
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
78 4T H R R H R 1
4.0 UART
There are 4 UARTs [channels 3:0] in the L154. Each has its own 64-byte of transmit and receive FIFO, a set of
16550 compatible control and status registers, and a baud rate generator for individual channel data rate
setting. Eight additional registers per UART were added for the EXAR enhanced features.
21
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
4.1
REV. 1.1.0
Programmable Baud Rate Generator
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide
the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further
divides this clock by a programmable divisor between 1 and (216 -1) to obtain a 16X or 8X sampling clock of the
serial data rate. The sampling clock is used by the transmitter for data bit shifting and receiver for data
sampling. The BRG divisor (DLL and DLM registers) defaults to a random value upon power up. Therefore, the
BRG must be programmed during initialization to the operating data rate.
FIGURE 8. BAUD RATE GENERATOR
To O ther
C hannels
D LL and D LM
R egisters
Prescaler
D ivide by 1
XTAL1
XTAL2
C rystal
O sc/
Buffer
M C R Bit-7=0
(default)
Baud R ate
G enerator
Logic
Prescaler
D ivide by 4
16X or 8X
Sam pling
R ate C lock to
Transm itter
and R eceiver
M C R Bit-7=1
Programming the Baud Rate Generator Registers DLM and DLL provides the capability for selecting the
operating data rate. Table 9 shows the standard data rates available with a 14.7456 MHz crystal or external
clock at 16X clock rate. At 8X sampling rate, these data rates would double. When using a non-standard data
rate crystal or external clock, the divisor value can be calculated with the following equation(s).
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), WITH 8XMODE [3:0] IS 0
divisor (decimal) = (XTAL1 clock frequency / prescaler / (serial data rate x 8), WITH 8XMODE [3:0] IS 1
22
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
TABLE 9: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING
OUTPUT Data Rate OUTPUT Data Rate DIVISOR FOR 16x DIVISOR FOR 16x DLM PROGRAM DLL PROGRAM DATA RATE
MCR Bit-7=1
MCR Bit-7=0
Clock (Decimal) Clock (HEX)
VALUE (HEX) VALUE (HEX) ERROR (%)
4.2
100
400
2304
900
09
00
0
600
2400
384
180
01
80
0
1200
4800
192
C0
00
C0
0
2400
9600
96
60
00
60
0
4800
19.2k
48
30
00
30
0
9600
38.4k
24
18
00
18
0
19.2k
76.8k
12
0C
00
0C
0
38.4k
153.6k
6
06
00
06
0
57.6k
230.4k
4
04
00
04
0
115.2k
460.8k
2
02
00
02
0
230.4k
921.6k
1
01
00
01
0
Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Operation
Automatic RTS/DTR and CTS/DSR flow control, also known as hardware flow control, is used to prevent data
overrun to the local receiver FIFO and remote receiver FIFO. The RTS#/DTR# output pin is used to request
remote unit to suspend/restart data transmission while the CTS#/DSR# input pin is monitored to suspend/
restart local transmitter. The auto RTS/DTR and auto CTS/DSR flow control features are individually selected
to fit specific application requirement and enabled through EFR bit-6 and 7 and MCR bit-2 for either RTS/CTS
or DTR/DSR control signals. The auto RTS/DTR function must be started by asserting RTS/DTR# output pin
(MCR bit-0 or 1 to logic 1 after it is enabled. Figure 9 below explains how it works.
Two interrupts associated with RTS/DTR and CTS/DSR flow control have been added to give indication when
RTS/DTR# pin or CTS/DSR# pin is de-asserted during operation. The RTS/DTR and CTS/DSR interrupts must
be first enabled by EFR bit-4, and then enabled individually by IER bit-6 and 7, and chosen with MCR bit-2.
Automatic hardware flow control is selected by setting bits 6 (RTS) and 7 (CTS) of the EFR register to logic 1.
If CTS# pin transitions from logic 0 to logic 1 indicting a flow control request, ISR bit-5 will be set to logic 1, (if
enabled via IER bit 6-7), and the UART will suspend TX transmissions as soon as the stop bit of the character
in process is shifted out. Transmission is resumed after the CTS# input returns to logic 0, indicating more data
may be sent.
23
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
FIGURE 9. AUTO RTS/DTR AND CTS/DSR FLOW CONTROL OPERATION
Local UART
UARTA
Remote UART
UARTB
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
TXB
RTSA#
CTSB#
Auto CTS
Monitor
RXB
Receiver FIFO
Trigger Reached
TXA
Transmitter
CTSA#
Auto CTS
Monitor
RTSA#
RXA
RTSB#
Assert RTS# to Begin
Transmission
1
ON
Auto RTS
Trigger Level
10
OFF
ON
7
2
ON
CTSB#
Transmitter
8
3
11
OFF
ON
TXB
Data Starts
6
Suspend
Restart
9
4
RXA FIFO
INTA
(RXA FIFO
Interrupt)
Receive
Data
RX FIFO
Trigger Level
5
RTS High
Threshold
RTS Low
Threshold
12
RX FIFO
Trigger Level
RTSCTS1
The local UART (UARTA) starts data transfer by asserting -RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and continues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its transmit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
24
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
4.3
Infrared Mode
Each UART in the L154 includes the infrared encoder and decoder compatible to the IrDA (Infrared Data
Association) version 1.0. The input pin ENIR conveniently activates all 4 UART channels to start up in the
infrared mode. This global control pin enables the MCR bit-6 function in every UART channel register. After
power up or a reset, the software can overwrite MCR bit-6 if so desired. ENIR and MCR bit-6 also disable its
receiver while the transmitter is sending data. This prevents the echoed data from going to the receiver. The
global activation ENIR pin prevents the infrared emitter from turning on and drawing large amount of current
while the system is starting up. When the infrared feature is enabled, the transmit data outputs, TX[3:0], would
idle at logic zero level. Likewise, the RX[3:0] inputs assume an idle level of logic zero.
The infrared encoder sends out a 3/16 of a bit wide pulse for each “0” bit in the transmit data stream. This
signal encoding reduces the on-time of the infrared LED, hence reduces the power consumption. See
Figure 10 below.
The infrared decoder receives the input pulse from the infrared sensing diode on RX pin. Each time it senses a
light pulse, it returns a logic zero to the data bit stream. The RX input signal may be inverted prior delivered to
the input of the decoder. This option supports active low instead of normal active high pulse from some infrared
modules on the market.
FIGURE 10. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING
TX Data
0
Stop
Start
Character
Data Bits
1
1
0
0
1
0
1
1
0
Transmit
IR Pulse
(TX Pin)
1/2 Bit Time
Bit Time
3/16 Bit Time
IrEncoder-1
Receive
IR Pulse
(RX pin)
Bit Time
1/16 Clock Delay
1
0
1
0
0
Data Bits
1
1
0
1
Stop
0
Start
RX Data
Character
IRdecoder-1
25
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
4.4
REV. 1.1.0
Internal Loopback
Each UART channel provides an internal loopback capability for system diagnostic. The internal loopback
mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 11 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored.
FIGURE 11. INTERNAL LOOP BACK
VCC
TX[3:0]
TransmitShif t
Register
Internal Bus Lines and ControlSignals
MC R bit-4=1
Receive Shif t
Register
RX [3:0]
VCC
Modem / G eneral Purpose Control
Logic
RTS# [3:0]
RTS#
CTS#
CTS# [3:0]
VCC
DTR# [3:0]
DTR#
DSR#
DSR# [3:0]
OP1#
RI#
RI# [3:0]
OP2#
CD#
4.5
CD# [3:0]
UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING.
The 4 sets of UART configuration registers are decoded using address lines A9 to A11 as shown below:
A11
A10
A9
UART CHANNEL
SELECTION
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
26
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
Address lines A0 to A3 select the 16 registers in each channel. The first 8 registers are 16550 compatible with
the EXAR enhanced feature registers located on next 8 addresses locations. Addresses 0x080 to 0x093
comprise the Device Configuration Registers and they reside in Channel 0’s space.
.
TABLE 10: UART CHANNEL CONFIGURATION REGISTERS.
ADDRESS
REGISTER
READ/WRITE
COMMENTS
A3 A2 A1 A0
16550 COMPATIBLE
0
0
0 0
RHR - Receive Holding Register
THR - Transmit Holding Register
Read-only
Write-only
LCR[7] = 0
0
0
0 0
DLL - Div Latch Low
Read/Write
LCR[7] = 1
0
0
0 1
DLM - Div Latch High
Read/Write
LCR[7] = 1
0
0
0 1
IER - Interrupt Enable Register
Read/Write
LCR[7] = 0
0
0
1 0
ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
0
0
1 1
LCR - Line Control Register
Read/Write
0
1
0 0
MCR - Modem Control Register
Read/Write
0
1
0 1
LSR - Line Status Register
reserved
Read-only
Write-only
0
1
1 0
MSR - Modem Status Register
- Auto RS485 Delay
Read-only
Write-only
0
1
1 1
SPR - Scratch Pad Reg
Read/Write
ENHANCED REGISTER
1
0
0 0
FCTR
Read/Write
1
0
0 1
EFR - Enhanced Function Register
Read/Write
1
0
1 0
TXCNT - Transmit FIFO Level Counter
TXTRG - Transmit FIFO Trigger Level
Read-only
Write-only
1
0
1 1
RXCNT - Receive FIFO Level Counter
RXTRG - Receive FIFO Trigger Level
Read-only
Write-only
1
1
0 0
Xoff-1 - Xoff Character 1
Xchar
Write-only
Read-only
1
1
0 1
Xoff-2 - Xoff Character 2
reserved
Write-only
Read-only
1
1
1 0
Xon-1 - Xon Character 1
reserved
Write-only
Read-only
1
1
1 1
Xon-2 - Xon Character 2
reserved
Write-only
Read-only
27
Xon,Xoff Rcvd.
Flags
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
TABLE 11: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4.
ADDRESS
REG
READ/
A3-A0
NAME
WRITE
0000
RHR
0000
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
R
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=0
THR
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=0
0000
DLL
R/W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=1
0001
DLM
R/W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=1
0001
IER
R/W
0/
0/
0/
0
CTS/
RTS/
Xon/Xoff/
DSR# Int. DTR# Int. Sp. Char.
Enable
Enable
Int.
Enable
0010
0010
0011
0100
ISR
FCR
LCR
MCR
R
W
R/W
R/W
FIFOs
Enable
RX FIFO
Trigger
Divisor
Enable
FIFOs
Enable
RX FIFO
Trigger
Set TX
Break
0/
0/
DeltaFlow Cntl
Xoff/special char
0/
0/
TX FIFO
Trigger
TX FIFO
Trigger
Set Parity Even Parity
0/
0/
0/
BRG
Prescaler
IR
XonAny
Enable
Internal
Lopback
Enable
0101
LSR
R/W
RX FIFO
ERROR
TSR
Empty
THR
Empty
RX Break
0110
MSR
R
CD
RI
DSR
CTS
Modem
RX Line TX Empty
Status Int. Status Int.
Int.
Enable
Enable
Enable
RX Data
Int.
Enable
INT
Source
Bit-3
INT
Source
Bit-2
INT
Source
Bit-1
INT
Source
Bit-0
DMA
Mode
TX FIFO
Reset
RX FIFO
Reset
FIFOs
Enable
Parity
Enable
Stop Bits
Word
Length
Word
Length
Bit-1
Bit-0
(OP2)1
(OP1)1
RTS# Pin DTR# Pin
Control
Control
RTS/DTR
Flow Sel
RX Fram- RX Parity RX Overing Error
Error
run
Delta
CD#
Delta
RI#
Delta
DSR#
RX Data
Ready
Delta
CTS#
MSR
W
RS485
DLY-3
RS485
DLY-2
RS485
DLY-1
0111
SPR
R/W
Bit-7
Bit-6
Bit-5
Bit-4
1000
FCTR
R/W
TRG
Table
TRG
Table
Invert IR
RX Input
RTS/DTR RTS/DTR RTS/DTR RTS/DTR
Hyst Bit-3 Hyst Bit-2 Hyst Bit-1 Hyst Bit-0
Bit-1
Bit-0
Auto
RS485
Enable
Enable
Software Software Software Software
Flow Cntl Flow Cntl Flow Cntl Flow Cntl
1001
EFR
R/W
Auto CTS/ Auto RTS/
DSR
DTR
Enable
Enable
Special
Char
Select
RS485 DLY- Reserved Reserved Reserved Reserved
0
IER [7:5],
ISR [5:4],
FCR[5:4],
Bit-3
Bit-2
Bit-1
Bit-0
Bit-3
Bit-2
Bit-1
Bit-0
MCR[7:5,2]
MSR[7:4]
1010
TXCNT
R
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1010
TXTRG
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1011
RXCNT
R
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1011
RXTRG
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
28
User Data
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
TABLE 11: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4.
ADDRESS
REG
READ/
A3-A0
NAME
WRITE
1100
XCHAR
1100
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
R
0
0
0
0
0
0
Xon Det.
Indicator
XOFF1
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1101
XOFF2
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1110
XON1
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1111
XON2
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
COMMENT
Xoff Det. Self-clear
Indicator after read
NOTE: MCR bits 2 and 3 (OP1 and OP2 outputs) are not available in the XR17L154. They are present for 16C550
compatibility during Internal loopback, see Figure 11.
4.6
Transmitter
The transmitter section comprises of a 64 bytes of FIFO, a byte-wide Transmit Holding Register (THR) and an
8-bit Transmit Shift Register (TSR). THR receives a data byte from the host (non-FIFO mode) or a data byte
from the FIFO when the FIFO is enabled by FCR bit-0. TSR shifts out every data bit with the 16X or 8X internal
clock. A bit time is 16 or 8 clock periods. The transmitter sends the start bit followed by the number of data bits,
inserts the proper parity bit if enable, and adds the stop bit(s). The status of the THR and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
4.6.1
Transmit Holding Register (THR)
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is also the
input register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. A THR empty
interrupt can be generated when it is enabled in IER bit-1.
4.6.2
Transmitter Operation in non-FIFO
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
FIGURE 12. TRANSMITTER OPERATION IN NON-FIFO MODE
D a ta
B y te
T ra n s m it
H o ld in g
R e g is te r
(T H R )
T H R In te rru p t (IS R b it-1 )
E n a b le d b y IE R b it-1
16X or 8X
C lo c k
(8 X M O D E
R e g is te r)
T ra n s m it S h ift R e g is te r (T S R )
M
S
B
L
S
B
T X N O F IF O 1
29
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
4.6.3
REV. 1.1.0
Transmitter Operation in FIFO
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level (see TXTRG register). The transmit empty
interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
Furthermore, with the RS485 half-duplex direction control enabled (FCTR bit-5=1) the source of the transmit
empty interrupt changes to TSR empty instead of THR empty. This is to ensure the RTS# output is not
changed until the last stop bit of the last character is shifted out.
4.6.4
Auto RS485 Operation
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR
bit-5. It de-asserts RTS# or DTR# after a specified delay indicated in MSR[7:4] following the last stop bit of the
last character that has been transmitted. This helps in turning around the transceiver to receive the remote
station’s response. The delay optimizes the time needed for the last transmission to reach the farthest station
on a long cable network before switching off the line driver. This delay prevents undesirable line signal
disturbance that causes signal degradation. It also changes the transmitter empty interrupt to TSR empty
instead of THR empty.
FIGURE 13. TRANSMIITTER OPERATION IN FIFO AND FLOW CONTROL MODE
T ra n sm it
D ata B yte
T ra n sm it
F IF O
(64 -B yte )
F lo w C on tro l C h a racters
(X o ff1 /2 a nd X o n 1 /2 R e g .
T H R In te rru p t (IS R b it-1 ) fa lls
b e lo w P ro gra m m e d T rig g e r
L e ve l (T X T R G ) an d th e n
w he n b e co m es em p ty. F IF O
is E n a b le d b y F C R b it-0 = 1
A u to S o ftw are F low C o n trol
1 6 X or 8 X C lo ck
(8X M O D E R e g iste r)
T ra n sm it D a ta S h ift R e g iste r
(T S R )
A u to C T S F lo w C o n tro l (C T S # p in)
4.7
T X F IF O 1
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and Receive Holding Register (RHR). The
RSR uses the 16X or 8X clock for timing. It verifies and validates every bit on the incoming character in the
middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts
counting at the 16X or 8X clock rate. After 8 or 4 clocks the start bit period should be at the center of the start
bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this
manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there were any error(s), they are
reported in the LSR register bits 1- 4 and an LSR interrupt is generated immediately if IER bit-2 is enabled.
Upon unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are
immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data
ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data
delivery to the host is guaranteed by a receive data ready time-out function when receive data does not reach
the receive FIFO trigger level. This time-out delay is 4 word lengths as defined by LCR[1:0] plus 12 bits time.
The RHR interrupt is enabled by IER bit-0.
30
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
4.7.1
Receiver Operation in non-FIFO Mode
FIGURE 14. RECEIVER OPERATION IN NON-FIFO MODE
1 6 X o r 8 X C lo c k
( 8 X M O D E R e g is t e r )
R e c e iv e
D a ta B y t e
a n d E rro rs
R e c e iv e D a t a S h if t
R e g is t e r ( R S R )
E rro r
F la g s in
L S R b it s
4 :1
D a ta B it
V a lid a t io n
R e c e iv e D a t a
H o ld in g R e g is t e r
(R H R )
R e c e iv e D a t a C h a r a c t e r s
R H R In te r r u p t ( I S R b it - 2 )
R X F IF O
4.7.2
Receiver Operation with FIFO
FIGURE 15. RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE
16X or 8X Sampling
Clock (8XMODE Reg.)
Receive Data Shift
Register (RSR)
Data Bit
Validation
64 bytes by 11bit wide FIFO
Error Flags
(64-sets)
Data falls to 40
Receive Data
FIFO
(64-byte)
FIFO Trigger=48
Error Tags in
LSR bits 4:1
Data fills to 56
Receive Data
Byte and Errors
Receive Data Characters
Example:
- FIFO trigger level set at 48 bytes
- RTS/DTR hyasteresis set at +/-8 chars.
RTS#/DTR# re-asserts when data falls below the
trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RHR Interrupt (ISR bit-2) is programmed at
FIFO trigger level (RXTRG).
FIFO is Enable by FCR bit-0=1
RTS#/DTR# de-asserts when data fills above
the trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
Receive
Data
RXFIFO1
4.8
Registers
Receive Holding Register (RHR)
The receive holding register is an 8-bit register that holds a receive data byte from the receive shift register
(RSR). It provides the receive data interface to the host processor. The host reads the receive data byte on this
register whenever a data byte is transferred from the RSR. RHR also part of the receive FIFO of 64 bytes by
11-bit wide, 4 extra bits are for the error tags to be in LSR register. When the FIFO is enabled by FCR bit-0, it
acts as the first-out register of the FIFO as new data are put over the first-in register. The receive FIFO pointer
is bumped after the RHR register is read. Also, the error tags associated with the data byte are immediately
updated onto the line status register (LSR) bits 1-4.
31
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
Baud Rate Generator Divisors (DLL and DLM)
The Baud Rate Generator (BRG) is a 16-bit counter that generates the data rate for the transmitter and
receiver. The rate is programmed through registers DLL and DLM which are only accessible when LCR bit-7 is
set to logic 1. See Programmable Baud Rate Generator section for more detail.
Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR) register and
also encoded in INT (INT0-INT3) register in the Device Configuration Registers.
IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = logic 1) and receive interrupts (IER BIT-0 = logic 1) are enabled, the RHR
interrupts (see ISR bits 3 and 4) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the FIFO is empty.
IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the L154 in the FIFO polled
mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used
in the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX FIFO.
B. LSR BIT 1-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
C. LSR BIT-5 indicates THR is empty.
D. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
E. LSR BIT-7 indicates the or’ed function of errors in the RX FIFO.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
• Logic 0 = Disable the receive data ready interrupt (default).
• Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This interrupt is associated with bit-5 in the LSR register. An interrupt is issued whenever the THR becomes
empty (non-FIFO mode) or when data in the FIFO falls below the programmed trigger level in the 64-byte FIFO
mode.
• Logic 0 = Disable Transmit Holding Register empty interrupt (default).
• Logic 1 = Enable Transmit Holding Register empty interrupt.
IER[2]: Receive Line Status Interrupt Enable
Any of the LSR register bits 1,2,3 or 4 becomes active will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO.
• Logic 0 = Disable the receiver line status interrupt (default).
• Logic 1 = Enable the receiver line status interrupt.
32
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
IER[3]: Modem Status Interrupt Enable
• Logic 0 = Disable the modem status register interrupt (default).
• Logic 1 = Enable the modem status register interrupt.
IER[4]: Reserved.
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the software flow control, receive Xoff interrupt. (default)
• Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the RTS# interrupt. (default).
• Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# output pin makes a
transition.
IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the CTS# interrupt. (default).
• Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# input pin makes a transition.
Interrupt Status Register (ISR)
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others queue up for next
service. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source
Table, Table 12, shows the data values (bit 0-5) for the six prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels.
Interrupt Generation:
• LSR is by any of the LSR bits 1, 2, 3 and 4.
• RXRDY is by RX trigger level.
• RXRDY Time-out is by the a 4-char plus 12 bits delay timer if data doesn’t reach FIFO trigger level.
• TXRDY is by LSR bit-5 in the non-FIFO mode, TX trigger level setting in the FIFO mode (or bit-6 in auto
RS485 control).
• MSR is by any of the MSR bits, 0, 1, 2 and 3.
• Receive Xon/Xoff/Special character is by detection of a Xon, Xoff or Special character.
• CTS#/DSR# is by a change of state on the input pin with auto flow control enabled, EFR bit-7, and depending
on selection on MCR bit-2.
• RTS#/DTR# is when its receiver changes the state of the output pin during auto RTS/DTR flow control
enabled by EFR bit-6 and selection of MCR bit-2.
Interrupt Clearing:
• LSR interrupt is cleared by a read to the LSR register.
• RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
• RXRDY Time-out interrupt is cleared by emptying the RX FIFO.
• TXRDY interrupt is cleared by a read to the ISR register.
• MSR interrupt is cleared by a read to the MSR register.
• Xon, Xoff or Special character interrupt is cleared by a read to ISR register.
33
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
• RTS#/DTR# output status change interrupt is cleared by a read to the ISR register.
• CTS#/DSR# input status change interrupt is cleared by a read to the MSR register.
]
TABLE 12: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF THE INTERRUPT+
LEVEL
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1
0
0
0
1
1
0
LSR (Receiver Line Status Register)
2
0
0
0
1
0
0
RXRDY (Received Data Ready)
3
0
0
1
1
0
0
RXRDY (Receive Data Time-out)
4
0
0
0
0
1
0
TXRDY (Transmitter Holding Register Empty)
5
0
0
0
0
0
0
MSR (Modem Status Register)
6
0
1
0
0
0
0
RXRDY (Received Xon/Xoff or Special character)
7
1
0
0
0
0
0
CTS#/DSR#, RTS#/DTR# change of state
X
0
0
0
0
0
1
None (default)
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, 3 and 4 (See Interrupt
Source Table 12).
ISR[5:4]: Interrupt Status
These bits are enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data
match of the Xon or Xoff character(s). Note that once set to a logic 1, the ISR bit-4 will stay a logic 1 until a Xon
character is received. ISR bit-5 indicates that CTS#/DSR# or RTS#/DTR# has changed state.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is active.
Logic 0 = No receive FIFO reset (default).
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not cleared
or altered). This bit will return to a logic 0 after resetting the FIFO.
34
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is active.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
This bit has no effect since TXRDY and RXRDY pins are not available in this device. It is provided for legacy
software.
Logic 0 = Set DMA to mode 0. (default)
Logic 1 = Set DMA to mode 1.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = one)
The FCTR Bits 6-7 are associated with these 2 bits by selecting one of the four tables. The 4 user selectable
trigger levels in 4 tables are supported for compatibility reasons. These 2 bits set the trigger level for the
transmit FIFO interrupt. The UART will issue a transmit interrupt when the number of characters in the FIFO
falls below the selected trigger level, or when it gets empty in case that the FIFO did not get filled over the
trigger level on last re-load. Table 13 below shows the selections.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
The FCTR Bits 6-7 are associated with these 2 bits. These 2 bits are used to set the trigger level for the
receiver FIFO interrupt. Table 13 shows the complete selections.
35
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
TABLE 13: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION
FCTR
BIT-7
FCTR
BIT-6
0
0
0
FCR
BIT-7
FCR
BIT-6
0
0
1
1
0
1
0
1
1
BIT-4
0
0
0
0
1
1
RECEIVE
TRIGGER LEVEL
0
1
0
1
0
1
0
1
X
X
COMPATIBILITY
Table-A. 16C550, 16C2550,
16C2552, 16C554, 16C580
compatible.
16
8
24
30
Table-B. 16C650A compatible.
8
16
32
56
Table-C. 16C654 compatible.
8
16
24
28
0
0
1
1
0
0
1
1
TRANSMIT
TRIGGER LEVEL
1 (default)
0
1
0
1
0
1
FCR
1 (default)
4
8
14
1
0
0
1
1
1
FCR
BIT-5
0
1
0
1
8
16
56
60
X
X
Programmable Programmable Table-D. 16C850, 16c2850,
via RXTRG
via TXTRG reg- 16C2852, 16C854, 16C864,
register
ister
16C872 compatible.
Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
BIT-1
BIT-0
WORD LENGTH
0
0
5 (default)
0
1
6
1
0
7
1
1
8
36
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
BIT-2
WORD LENGTH
STOP BIT LENGTH
(BIT TIME(S))
0
5,6,7,8
1 (default)
1
5
1-1/2
1
6,7,8
2
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 14 for parity selection summary below.
• Logic 0 = No parity.
• Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format. Logic
0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The receiver
must be programmed to check the same format (default).
• Logic 1 = EVEN Parity is generated by forcing an even the number of logic 1’s in the transmitted character.
The receiver must be programmed to check the same format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
• LCR BIT-5 = logic 0, parity is not forced (default).
• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
TABLE 14: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3
PARITY SELECTION
X
X
0
No parity
0
0
1
Odd parity
0
1
1
Even parity
1
0
1
Force parity to mark, “1”
1
1
1
Forced parity to space, “0”
LCR[6]: Transmit Break Enable
When enabled the Break control bit it causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains until disabled by setting LCR bit-6 to a logic 0.
• Logic 0 = No TX break condition. (default)
• Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
37
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
• Logic 0 = Data registers are selected. (default)
• Logic 1 = Divisor latch registers are selected.
Modem Control Register (MCR)
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Pins
The DTR# pin may be used for automatic hardware flow control enabled by EFR bit-6 and MCR bit-2=1. If the
modem interface is not used, this output may be used for general purpose.
• Logic 0 = Force DTR# output to a logic 1 (default).
• Logic 1 = Force DTR# output to a logic 0.
MCR[1]: RTS# Pins
The RTS# pin may be used for automatic hardware flow control by enabled by EFR bit-6 and MCR bit-2=0. If
the modem interface is not used, this output may be used for general purpose.
• Logic 0 = Force RTS# output to a logic 1 (default).
• Logic 1 = Force RTS# output to a logic 0.
MCR[2]: DTR# or RTS# for Auto Flow Control
The OP1 output is not available in the XR17L152. It is present for 16C550 compatibility during internal
loopback. See Figure 11. Logic zero is default.
DTR# or RTS# auto hardware flow control select. This bit is in effect only when auto RTS/DTR is enabled by
EFR bit-6.
• Logic 0 = Uses RTS#/CTS# pins for auto hardware flow control.
• Logic 1 = Uses DTR#/DSR# pin is used for auto hardware flow control.
MCR[3]: (OP2)
The OP2 output is not available in the XR17L154. It is present for 16C550 compatibility during internal
loopback. See Figure 11. Logic zero is default.
MCR[4]: Internal Loopback Enable
• Logic 0 = Disable loopback mode (default).
• Logic 1 = Enable local loopback mode, see loopback section and Figure 11.
MCR[5]: Xon-Any Enable
• Logic 0 = Disable Xon-Any function (for 16C550 compatibility) (default).
• Logic 1 = Enable Xon-Any function. In this mode any RX character received will enable Xon, resume data
transmission.
MCR[6]: Infrared Encoder/Decoder Enable
This bit overrides the ENIR pin selection.
• Logic 0 = Disable the infrared mode (default).
• Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. While in this mode, the TX/RX output/
input are routed to the infrared encoder/decoder. The data input and output levels will conform to the IrDA
infrared interface requirement. As such, while in this mode the infrared TX output will be a logic 0 during idle
data conditions. FCTR bit-4 may be selected to invert the RX input signal level going to the decoder for
infrared modules that provide rather an inverted output.
38
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
MCR[7]: Clock Prescaler Select
• Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
• Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
Line Status Register (LSR)
This register provides the status of data transfers between the UART and the host. If IER bit-2 is enabled, an
LSR interrupt is generated when a received data error occurs due to Overrrun, Parity or Framing. If LSR[0] =
logic 0, then LSR bits 1-4 are invalid.
LSR[0]: Receive Data Ready Indicator
• Logic 0 = No data in receive holding register or FIFO (default).
• Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
LSR[1]: Receiver Overrun Error Tag
• Logic 0 = No overrun error (default).
• Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register is
overwritten. Note that under this condition the data byte in the receive shift register is not transferred into the
FIFO, therefore the data in the FIFO is not corrupted by the error. Automatic Hardware (RTS/CTS) or
Software (Xon/Xoff) Flow Control should be considered if this condition persists.
LSR[2]: Receive Data Parity Error Tag
• Logic 0 = No parity error (default).
• Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR.
LSR[3]: Receive Data Framing Error Tag
• Logic 0 = No framing error (default).
• Logic 1 = Framing error tag. The receive character did not have a valid stop bit(s). This error tag is associated
with the character available for reading in RHR.
LSR[4]: Receive Break Tag
• Logic 0 = No break condition (default).
• Logic 1 = The receiver received a break signal (RX was a logic 0 for one character frame time). In the FIFO
mode, only one break character is loaded into the FIFO. The break indication remains until the RX input
returns to the idle condition, “mark” or logic 1.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. This bit indicates that the transmitter is ready to
accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to the host
when the THR interrupt enable is set. The THR bit is set to a logic 1 when the last data byte is transferred from
the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently with the data
loading to the transmit holding register by the host. In the FIFO mode this bit is set when the transmit FIFO is
empty; it is cleared when at least 1 byte is written to the transmit FIFO.
LSR[6]: Transmit Shift Register Empty Flag
This bit is the Transmit Shift Register Empty indicator. This bit is set to a logic 1 whenever the transmitter goes
idle. It is set to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is
set to one whenever the transmit FIFO and transmit shift register are both empty.
39
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
LSR[7]: Receive FIFO Data Error Flag
• Logic 0 = No FIFO error (default).
• Logic 1 = An indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error or
break indication is in the FIFO data. This bit clears when there is no more error(s) in the FIFO.
Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface signals, or other peripheral device that the
UART is connected. Lower four bits of this register are used to indicate the changed information. These bits are
set to a logic 1 whenever a signal from the modem changes state. These bits may be used as general purpose
inputs/outputs when they are not used with modem signals.
MSR[0]: Delta CTS# Input Flag
• Logic 0 = No change on CTS# input (default).
• Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3.
MSR[1]: Delta DSR# Input Flag
• Logic 0 = No change on DSR# input (default).
• Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3.
MSR[2]: Delta RI# Input Flag
• Logic 0 = No change on RI# input (default).
• Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3.
MSR[3]: Delta CD# Input Flag
• Logic 0 = No change on CD# input (default).
• Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3.
MSR[4]: CTS Input Status
CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto
CTS (EFR bit-7) and RTS/CTS flow control select (MCR bit-2). Auto CTS flow control allows starting and
stopping of local data transmissions based on the modem CTS# signal. A logic 1 on the CTS# pin will stop
UART transmitter as soon as the current character has finished transmission, and a logic 0 will resume data
transmission. Normally MSR bit-4 bit is the compliment of the CTS# input. However in the loopback mode, this
bit is equivalent to the RTS# bit in the MCR register. The CTS# input may be used as a general purpose input
when the modem interface is not used.
MSR[5]: DSR Input Status
DSR# (active high, logical 1). This input may be used for auto DTR/DSR flow control function, see auto
\hardware flow control section. Normally this bit is the compliment of the DSR# input. In the loopback mode,
this bit is equivalent to the DTR# bit in the MCR register. The DSR# input may be used as a general purpose
input when the modem interface is not used.
MSR[6]: RI Input Status
RI# (active high, logical 1). Normally this bit is the compliment of the RI# input. In the loopback mode this bit is
equivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose input when the
modem interface is not used.
40
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
MSR[7]: CD Input Status
CD# (active high, logical 1). Normally this bit is the compliment of the CD# input. In the loopback mode this bit
is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input
when the modem interface is not used.
Modem Status Register (MSR) - Write Only
The upper four bits 4-7 of this register sets the delay in number of bits time for the auto RS485 turn around from
transmit to receive.
MSR [7:4]: Programmable RS485 Turn-around Delay
When Auto RS485 feature is enabled (FCTR bit-5=1) and RTS# output is connected to the enable input of a
RS-485 transceiver. These 4 bits select from 0 to 15 bit-time delay after the end of the last stop-bit of the last
transmitted character. This delay controls when to change the state of RTS# output. This delay is very useful in
long-cable networks. Table 15 shows the selection. The bits are enabled by EFR bit-4.
TABLE 15: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE
MSR[7]
MSR[6]
MSR[5]
MSR[4]
DELAY IN DATA BIT(S) TIME
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
9
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1
0
1
0
10
1
0
1
1
11
1
1
0
0
12
1
1
0
1
13
1
1
1
0
14
1
1
1
1
15
Scratch Pad Register (SPR)
This is an 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
Feature Control Register (FCTR)
This register controls the UART enhanced functions that are not available on ST16C554 or ST16C654.
41
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
FCTR [3:0] - Auto RTS/DTR Flow Control Hysteresis Select
These bits select the auto RTS/DTR flow control hysteresis and only valid when TX and RX Trigger Table-D is
selected (FCTR bit-6 and 7 are set to logic 1). The RTS/DTR hysteresis is referenced to the RX FIFO trigger
level. After reset, these bits are set to logic 0 selecting the next FIFO trigger level for hardware flow control.
Table 16 below shows the 16 selectable hysteresis levels.
TABLE 16: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED
FCTR BIT-3 FCTR BIT-2 FCTR BIT-1 FCTR BIT-0
RTS/DTR HYSTERESIS
(CHARACTERS)
0
0
0
0
0
0
0
0
1
+/- 4
0
0
1
0
+/- 6
0
0
1
1
+/- 8
0
1
0
0
+/- 8
0
1
0
1
+/- 16
0
1
1
0
+/- 24
0
1
1
1
+/- 32
1
1
0
0
+/- 12
1
1
0
1
+/- 20
1
1
1
0
+/- 28
1
1
1
1
+/- 36
1
0
0
0
+/- 40
1
0
0
1
+/- 44
1
0
1
0
+/- 48
1
0
1
1
+/- 52
FCTR[4]: Infrared RX Input Logic Select
• Logic 0 = Select RX input as active high encoded IrDA data, normal, (default).
• Logic 1 = Select RX input as active low encoded IrDA data, inverted.
FCTR[5]: Auto RS485 Enable
Auto RS485 half duplex control enable/disable.
• Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
(THR) becomes empty. Transmit Shift Register (TSR) may still be shifting data bit out.
• Logic 1 = Enable Auto RS485 half duplex direction control. RTS# output changes its logic level from 1 to 0
when finished sending the last stop bit of the last character out of the TSR register. It changes back to logic
level 1 from 0 when a data byte is loaded into the THR or transmit FIFO. The change to logic 1 occurs prior
sending the start-bit. It also changes the transmitter interrupt from transmit holding to transmit shift register
(TSR) empty.
42
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
FCTR[7:6]: TX and RX FIFO Trigger Table Select
These 2 bits select the transmit and receive FIFO trigger level table A, B, C or D. When table A, B, or C is
selected the auto RTS flow control trigger level is set to "next FIFO trigger level" for compatibility to ST16C550
and ST16C650 series. RTS/DTR# triggers on the next level of the RX FIFO trigger level, in another word, one
FIFO level above and one FIFO level below. See Table 13 for complete selection with FCR bit 4-5 and FCTR
bit 6-7, i.e. if Table C is used on the receiver with RX FIFO trigger level set to 56 bytes, RTS/DTR# output will
de-asserts at 60 and re-asserts at 16.
Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 17). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Combinations of software flow control can be selected by programming these bits (see Table 17).
TABLE 17: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3
CONT-3
EFR BIT-2
CONT-2
EFR BIT-1
CONT-1
EFR BIT-0
CONT-0
0
0
0
0
No TX and RX flow control (default and reset)
0
0
X
X
No transmit flow control
1
0
X
X
Transmit Xon1/Xoff1
0
1
X
X
Transmit Xon2/Xoff2
1
1
X
X
Transmit Xon1 and Xon2/Xoff1 and Xoff2
X
X
0
0
No receive flow control
X
X
1
0
Receiver compares Xon1/Xoff1
X
X
0
1
Receiver compares Xon2/Xoff2
1
0
1
1
Transmit Xon1/ Xoff1,
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
1
1
Transmit Xon2/Xoff2,
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
1
1
1
Transmit Xon1 and Xon2/Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
0
0
1
1
No transmit flow control,
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
43
TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables the functions in IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the
new values. This feature prevents legacy software from altering or overwriting the enhanced functions once
set. Normally, it is recommended to leave it enabled, logic 1.
• Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR
bits 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 are set to a logic 0 to be compatible with ST16C554 mode (default).
• Logic 1 = Enables the enhanced functions. When this bit is set to a logic 1 all enhanced features are enabled.
EFR[5]: Special Character Detect Enable
• Logic 0 = Special Character Detect Disabled. (default)
• Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the received data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit for the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]=10) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]=01) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt.
EFR[6]: Auto RTS or DTR Flow Control Enable
RTS#/DTR# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS/DTR
is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS/DTR# will de-assert to a logic 1 at the next upper trigger or selected hysteresis level. RTS/DTR# will
return to a logic 0 when FIFO data falls below the next lower trigger or selected hysteresis level (see FCTR bits
4-7). The RTS# or DTR# output must be asserted (logic 0) before the auto RTS/DTR can take effect. The
selection for RTS# or DTR# is through MCR bit-2. RTS/DTR# pin will function as a general purpose output
when hardware flow control is disabled.
• Logic 0 = Automatic RTS/DTR flow control is disabled. (default)
• Logic 1 = Enable Automatic RTS/DTR flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS or DSR Flow Control.
• Logic 0 = Automatic CTS/DSR flow control is disabled. (default)
• Logic 1 = Enable Automatic CTS/DSR flow control. Transmission stops when CTS/DSR# pin de-asserts to
logic 1. Transmission resumes when CTS/DSR# pin returns to a logic 0. The selection for CTS# or DSR# is
through MCR bit-2.
44
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
TXCNT[7:0]: Transmit FIFO Level Counter, read-only
Transmit FIFO level byte count from 0x00 (zero) to 0x40 (64). This 8-bit register gives an indication of the
number of characters in the transmit FIFO. The FIFO level Byte count register is read only. The user can take
advantage of the FIFO level byte counter for faster data loading to the transmit FIFO, which reduces CPU
bandwidth requirements.
TXTRG [7:0]: Transmit FIFO Trigger Level, write only
An 8-bit value written to this register sets the TX FIFO trigger level from 0x00 (zero) to 0x40 (64). The TX FIFO
trigger level generates an interrupt whenever the data level in the transmit FIFO falls below this preset trigger
level.
RXCNT[7:0]: Receive FIFO Level Counter, read-only
Receive FIFO level byte count from 0x00 (zero) to 0x40 (64). It gives an indication of the number of characters
in the receive FIFO. The FIFO level byte count register is read only. The user can take advantage of the FIFO
level byte counter for faster data unloading from the receiver FIFO, which reduces CPU bandwidth
requirements.
RXTRG[7:0]: Receive FIFO Trigger Level, write-only
An 8-bit value written to this register, sets the RX FIFO trigger level from 0x00 (zero) to 0x40 (64). The RX
FIFO trigger level generates an interrupt whenever the receive FIFO level rises to this preset trigger level.
45
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
TABLE 18: UART[3:0] RESET CONDITIONS
REGISTERS
RESET STATE
DLL
Bits 7-0 = 0xXX
DLM
Bits 7-0 = 0xXX
RHR
Bits 7-0 = 0xXX
THR
Bits 7-0 = 0xXX
IER
Bits 7-0 = 0x00
FCR
Bits 7-0 = 0x00
ISR
Bits 7-0 = 0x01
LCR
Bits 7-0 = 0x00
MCR
Bits 7-0 = 0x00
LSR
Bits 7-0 = 0x60
MSR
Bits 3-0 = logic 0
Bits 7-4 = logic levels of the inputs
SPR
Bits 7-0 = 0xFF
FCTR
Bits 7-0 = 0x00
EFR
Bits 7-0 = 0x00
TXCNT
Bits 7-0 = 0x00
TXTRG
Bits 7-0 = 0x00
RXCNT
Bits 7-0 = 0x00
RXTRG
Bits 7-0 = 0x00
XCHAR
Bits 7-0 = 0x00
XON1
Bits 7-0 = 0x00
XON2
Bits 7-0 = 0x00
XOFF1
Bits 7-0 = 0x00
XOFF2
Bits 7-0 = 0x00
I/O SIGNALS
RESET STATE
TX[ch-3:0]
Logic 1
IRTX[ch-3:0]
Logic 0
RTS#[ch-3:0]
Logic 1
DTR#[ch-3:0]
Logic 1
EECK
Logic 0
EECS
Logic 0
EEDI
Logic 0
46
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
ABSOLUTE MAXIMUM RATINGS
Power Supply Range
4 Volts
Voltage at Any Pin
-0.5 to 4V
Operating Temperature
-40o to +85o C
Storage Temperature
-65o to +150o C
Package Dissipation
500 mW
Thermal Resistance (20x20x1.0mm 144-TQFP)
theta-ja = 42, theta-jc = 8 oC/W
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS FOR 3.3V SIGNALLING
TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc = 3.3V +/-10% unless otherwise specified.
SYMBOL
PARAMETER
MIN
MAX
UNITS
CONDITION
VIL
Input Low Voltage
-0.5
0.3Vcc
V
VIH
Input High Voltage
0.5Vcc
Vcc + 0.5
V
VOL
Output Low Voltage
0.4
V
IOL = 4mA
VOH
Output High Voltage
V
IOH = -0.5mA
IIL
Input Low Leakage Current
-10
µA
IIH
Input High Leakage Current
10
µA
ICL
Input Clock Leakage
+/-10
µA
CIN
Input Pin Capacitance
10
pF
CCLK
CLK Pin Capacitance
12
pF
CIDSEL
IDSEL Pin Capacitance
8
pF
ICC
Power Supply Current
2
mA
PCI CLK and Ext.
Clock=2MHz, all
inputs are at VCC or
GND and all outputs
are unloaded
ISLEEP
Sleep Current
20
µA
All four UARTs asleep.
AD[31:0] at GND, all
inputs at VCC or GND
0.9Vcc
47
NOTES
For PCI bus and exter- For other inputs, VIH
nal clock (XTAL1)
max = 6.0 V
inputs
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
AC ELECTRICAL CHARACTERISTICS FOR 3.3V SIGNALING
TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc = 3.3V +/-10% unless otherwise specified.
SYMBOL
PARAMETER
MIN
MAX
UNITS
NOTES
CLK
PCI Bus Clock
33
MHz
XTAL1
XTAL2
Crystal Oscillator
24
MHz
On-chip osc.
ECLK
External Clock
33
MHz
Ext. clock on XTAL1
IOH(AC)
Switching Current High
-12Vcc
mA
0 < Vout ≤ 0.3Vcc
IOL(AC)
Switching Current Low
16Vcc
mA
Vcc > Vout ≥ 0.6Vcc
ICH
Clamping Current High
25+(Vin-Vcc-1)/0.015
mA
Vcc+4 > Vin ≥ Vcc+1
ICL
Clamping Current Low
-25+(Vin+1)/0.015
mA
-3 < Vin ≤ -1
SlewR
Output Rise Slew Rate
1
4
V/ns
0.2Vcc - 0.6Vcc load
SlewF
Output Fall Slew Rate
1
4
V/ns
0.6Vcc - 0.2Vcc load
TCYC
CLK Cycle Time
30
∞
ns
THI
CLK High Time
11
ns
TLO
CLK Low Time
11
ns
CLK Slew Rate
1
4
V/ns
TVAL
CLK to Signal Valid Delay
2
11
ns
TON
Float to Active Delay
2
TOFF
Active to Float Delay
TSETUP
Input Setup Time to CLK bused signals
7
ns
THOLD
Input Hold Time from CLK
0
ns
TPRST
RST# Active Time After
Power Stable
1
ms
TCRST#
RST# Active Time After CLK
Stable
100
us
RST# Slew Rate
50
mV/ns
ns
28
48
ns
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
FIGURE 16. PCI BUS CONFIGURATION SPACE REGISTERS READ AND WRITE OPERATION
C LK
H ost
1
2
4
3
FR A M E#
H ost
ADDRESS
A D[31:0]
H ost
D A TA
Ta rg e t
C FG -R D
C /BE [3:0]#
B Y TE E N A B L E #
DATA TRANSFER
H ost
IR DY #
H ost
TR D Y#
Ta rg e t
D EV SEL #
Ta rg e t
P C IC FG _R D
C LK
H os t
1
2
4
3
FR A M E#
H os t
A D[31:0]
H os t
ADDRESS
W R IT E D A T A
T a rg e t
C /BE [3:0]#
C F G -W R
B Y TE E N A B L E #
DATA TRANSFER
H os t
IR DY #
H os t
TR D Y#
T a rg e t
D EV SEL #
T a rg e t
P C IC F G _W R
49
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
FIGURE 17. DEVICE CONFIGURATION AND UART REGISTERS READ OPERATION FOR A BYTE OR DWORD
CLK
Host
1
2
3
5
4
7
6
8
9
10
11
FRAME#
Host
Byte Enable# = DWORD
Byte Enable# = BYTE
IRDY#
WAIT
WAIT
WAIT
Host
DWORD TRANSFER
Bus
CMD
WAIT
Host
WAIT
C/BE[3:0]#
Data
WORD
Data
BYTE
Address
Target
BYTE TRANSFER
AD[31:0]
Host
TRDY#
Target
DEVSEL#
Target
PAR
Host
Target
Data
Parity
Address
Parity
Data
Parity
Active
PERR#
Active
Target
SERR#
Targe
Active
t
Note: PERR# and SERR are optional in a bus target application.
Even Parity is on AD[31:0], C/BE[3:0]#, and PAR
PCI_RD1
50
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
FIGURE 18. DEVICE CONFIGURATION REGISTERS, UART REGISTERS AND TRANSMIT DATA BURST WRITE OPERATION
CLK
H o st
1
2
3
5
4
7
6
8
9
10
11
FRAM E#
H o st
TRDY#
Ta rg e t
D ata
DWORD
D a ta D W O R D
B yte E nable# = D W O R D
DWORD TRANSFER
IRDY#
H o st
B us
CMD
D ata
DWORD
DWORD TRANSFER
H o st
D ata
DWORD
DWORD TRANSFER
C/BE[3:0]#
D ata
DWORD
DWORD TRANSFER
A ddress
Ta rg e t
DWORD TRANSFER
AD[31:0]
H o st
DEVSEL#
Ta rg e t
PAR
H o st
Ta rg e t
A ddress
P arity
D ata
P arity
PERR#
D ata
P arity
D ata
P arity
D ata
P arity
A ctive
A ctive
A ctive
D ata
P arity
A ctive
A ctive
Ta rg e t
SERR#
Ta rg e t
A ctive
N o te : P E R R # a n d S E R R a re o p tio n a l in a b u s ta rg e t a p p lica tio n .
E ve n P a rity is o n A D [3 1 :0 ], C /B E [3 :0 ]# , a n d P A R
P C I_B W R
51
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
FIGURE 19. DEVICE CONFIGURATION REGISTERS, UART REGISTERS AND RECEIVE DATA BURST READ OPERATION
CLK
H ost
1
18
13
8
23
FRAM E#
H ost
AD[31:0]
D ata
AD
D ata
D ata
D ata
Target
Bus
CMD
Byte Enab le# = D W O R D
DWORD TRANSFER
IRDY#
H ost
TRDY#
Target
DWORD TRANSFER
H ost
DWORD TRANSFER
C/BE[3:0]#
DWORD TRANSFER
H ost
DEVSEL#
Target
PAR
H ost
AD
D ata
D ata
D ata
D ata
Target
Active
PERR#
Active
Active
Active
Target
SERR#
Active
Target
N ote: PER R # and SER R are optional in a bus target application.
Even Parity is on AD [31:0], C /BE[3:0]#, and PAR
PC I_BR D
52
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
FIGURE 20. PCI BUS CLOCK (DC TO 33MHZ)
1.44 ns
(max)
11 ns
(min)
1.44 ns
(max)
11 ns
(min)
0.6 Vcc
0.4Vcc p-to-p
(minimum)
CLK
0.2 Vcc
Tvalid
(2-11 ns)
Bused
Signal
Output
Delay
Ton
(2 ns min)
Tri-State
Output
Toff
(28 ns max)
Tsetup
(7 ns min)
Thold
(0 ns)
Bused
Signal
Input
Inputs Valid
pci_clk
53
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
FIGURE 21. TRANSMIT DATA INTERRUPT AT TRIGGER LEVEL
START
BIT
TX Data
STOP
BIT
DATA BITS (5-8)
D0
D1
D2
D3
D4
D5
D6
D7
NEXT
DATA
START
BIT
PARITY
BIT
5 DATA BITS
6 DATA BITS
7 DATA BITS
TX Interrupt at
Transmit Trigger Level
Clear at
Above
Trigger Level
Set at Below
Trigger Level
BAUD RATE CLOCK of 16X or 8X
TXNOFIFO-1
FIGURE 22. RECEIVE DATA READY INTERRUPT AT TRIGGER LEVEL
START
BIT
RX Data Input
STOP
BIT
DATA BITS (5-8)
D0
D1
D2
D3
D4
D5
D6
D7
PARITY
BIT
RX Data Ready Interrupt at
Receive Trigger Level
De-asserted at
below trigger level
First byte that
reaches the
trigger level
Asserted at
above trigger
level
RXFIFO1
54
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
PACKAGE DIMENSIONS
55
áç
XR17L154
3.3V PCI BUS QUAD UART
DISCONTINUED
REV. 1.1.0
REVISION HISTORY
DATE
REVISION
DESCRIPTION
August 2002
Adv. Rev. 1.0.0
October 2002
Rev. 1.0.0
Release into production. Updated DC and AC Electrical Characteristics.
August 2003
Rev. 1.1.0
Added Device Status to Ordering Information. Changed status to "Discontinued." Please refer to the XR17D154 for new designs.
Advanced Datasheet
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order
to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of
any circuits described herein, conveys no license under any patent or other right, and makes no
representation that the circuits are free of patent infringement. Charts and schedules contained here in are
only for illustration purposes and may vary depending upon a user’s specific application. While the
information in this publication has been carefully checked; no responsibility, however, is assumed for
inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where
the failure or malfunction of the product can reasonably be expected to cause failure of the life support
system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of
injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR
Corporation is adequately protected under the circumstances.
Copyright 2003 EXAR Corporation
Datasheet August 2003.
Send your UART technical inquiry with technical details to hotline: [email protected].
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
56