SN74LVC2G34 DUAL BUFFER GATE www.ti.com FEATURES • • • • • • • • • • • Available in the Texas Instruments NanoStar™ and NanoFree™ Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 4.1 ns at 3.3 V Low Power Consumption, 10-µA Max ICC 24-mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25 C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25 C Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) SCES359F – AUGUST 2001 – REVISED APRIL 2005 DBV, DCK, OR DRL PACKAGE (TOP VIEW) 1A GND 2A 1 6 2 5 3 4 1Y VCC 2Y YEA, YEP, YZA, OR YZP PACKAGE (BOTTOM VIEW) 2A GND 1A 3 4 2 5 1 6 2Y VCC 1Y DESCRIPTION/ORDERING INFORMATION This dual buffer gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2G34 performs the Boolean function Y = A in positive logic. NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar, NanoFree are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2005, Texas Instruments Incorporated SN74LVC2G34 DUAL BUFFER GATE www.ti.com SCES359F – AUGUST 2001 – REVISED APRIL 2005 ORDERING INFORMATION PACKAGE (1) TA ORDERABLE PART NUMBER NanoStar™ – WCSP (DSBGA) 0.17-mm Small Bump – YEA SN74LVC2G34YEAR NanoFree™ – WCSP (DSBGA) 0.17-mm Small Bump – YZA (Pb-free) SN74LVC2G34YZAR Reel of 3000 NanoStar™ – WCSP (DSBGA) 0.23-mm Large Bump – YEP –40°C to 85°C NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) SN74LVC2G34YZPR SOT (SC-70) – DCK SOT (SOT-533) – DRL (2) _ _ _C9_ SN74LVC2G34YEPR SOT (SOT-23) – DBV (1) Reel of 3000 SN74LVC2G34DBVR Reel of 250 SN74LVC2G34DBVT Reel of 3000 SN74LVC2G34DCKR Reel of 250 SN74LVC2G34DCKT Reel of 4000 SN74LVC2G34DRLR C34_ C9_ PREVIEW Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ⋅ = Pb-free). FUNCTION TABLE (EACH GATE) INPUT A OUTPUT Y H H L L LOGIC DIAGRAM (POSITIVE LOGIC) 1A 2A 2 TOP-SIDE MARKING (2) 1 6 3 4 1Y 2Y SN74LVC2G34 DUAL BUFFER GATE www.ti.com SCES359F – AUGUST 2001 – REVISED APRIL 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current 50 mA 100 mA Continuous current through VCC or GND θJA Package thermal impedance (4) DBV package 165 DCK package 259 DRL package 142 YEA/YZA package 143 YEP/YZP package Tstg (1) (2) (3) (4) Storage temperature range V C/W 123 –65 150 C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. 3 SN74LVC2G34 DUAL BUFFER GATE www.ti.com SCES359F – AUGUST 2001 – REVISED APRIL 2005 Recommended Operating Conditions (1) VCC Supply voltage Operating Data retention only High-level input voltage MAX 1.65 5.5 0.65 VCC = 2.3 V to 2.7 V VCC VCC = 1.65 V to 1.95 V Low-level input voltage V 2 0.7 V VCC 1.7 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VIL UNIT 1.5 VCC = 1.65 V to 1.95 V VIH MIN 0.35 VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VCC = 4.5 V to 5.5 V 0.3 V VCC VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VCC = 1.65 V –4 VCC = 2.3 V IOH High-level output current –8 –16 VCC = 3 V VCC = 4.5 V –32 VCC = 1.65 V 4 VCC = 2.3 V IOL Low-level output current 8 16 VCC = 3 V ?t/?v Input transition rise or fall rate VCC = 3.3 V VCC = 5 V TA (1) 4 Operating free-air temperature mA 24 VCC = 4.5 V VCC = 1.8 V mA –24 32 0.15 V, 2.5 V 0.2 V 20 0.3 V 10 0.5 V ns/V 5 –40 85 All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. C SN74LVC2G34 DUAL BUFFER GATE www.ti.com SCES359F – AUGUST 2001 – REVISED APRIL 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VOH 1.65 V to 5.5 V 1.65 V 1.2 IOH = –8 mA 2.3 V 1.9 4.5 V IOL = 100 µA 1.65 V to 5.5 V 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 3.8 0.4 3V IOL = 24 mA IOL = 32 mA A inputs 2.3 IOH = –32 mA IOL = 16 mA II V 2.4 3V IOH = –24 mA ICC VI = 5.5 V or GND, IO = 0 ?ICC One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND (1) All typical values are at VCC = 3.3 V, TA = 25 C. 0.55 0 to 5.5 V 5 µA 0 10 µA 1.65 V to 5.5 V 10 µA 500 µA VI = 5.5 V or GND VI or VO = 5.5 V V 0.55 4.5 V Ioff UNIT VCC – 0.1 IOH = –4 mA IOH = –16 mA VOL MIN TYP (1) MAX VCC 3 V to 5.5 V 3.3 V 3.5 pF Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A Y VCC = 1.8 V 0.15 V VCC = 2.5 V 0.2 V VCC = 3.3 V 0.3 V VCC = 5 V 0.5 V MIN MAX MIN MAX MIN MAX MIN MAX 3.2 8.6 1.5 4.4 1.4 4.1 1 3.2 UNIT ns Operating Characteristics TA = 25 C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 14 14 15 17 UNIT pF 5 SN74LVC2G34 DUAL BUFFER GATE www.ti.com SCES359F – AUGUST 2001 – REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VM VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 PACKAGE OPTION ADDENDUM www.ti.com 5-Dec-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LVC2G34DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC2G34DBVRE4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC2G34DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC2G34DCKRE4 ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC2G34DCKRG4 ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC2G34DRLR ACTIVE SOP DRL 6 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC2G34DRLRG4 ACTIVE SOP DRL 6 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC2G34YEAR ACTIVE WCSP YEA 6 3000 TBD SNPB Level-1-260C-UNLIM SN74LVC2G34YEPR ACTIVE WCSP YEP 6 3000 TBD SNPB Level-1-260C-UNLIM SN74LVC2G34YZAR ACTIVE WCSP YZA 6 3000 Pb-Free (RoHS) SNAGCU Level-1-260C-UNLIM SN74LVC2G34YZPR ACTIVE WCSP YZP 6 3000 Pb-Free (RoHS) SNAGCU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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