SN74AUC2G34 DUAL BUFFER GATE www.ti.com SCES514A – NOVEMBER 2003 – REVISED MARCH 2006 FEATURES • • • • • • • • Available in the Texas Instruments NanoStar™ and NanoFree™ Packages Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub-1-V Operable Max tpd of 1.6 ns at 1.8 V Low Power Consumption, 10 µA at 1.8 V DBV PACKAGE (TOP VIEW) 1A GND 2A 1 2 3 6 5 4 • DCK PACKAGE (TOP VIEW) ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DRL PACKAGE (TOP VIEW) YEP PACKAGE (BOTTOM VIEW) 1Y VCC 1A 1 6 1Y 1A 1 6 1Y GND 2 5 VCC GND 2 5 VCC 2Y 2A 3 4 2Y 2A 3 4 2Y 2A GND 1A 3 4 2Y 2 5 1 6 VCC 1Y DESCRIPTION/ORDERING INFORMATION This dual buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC2G34 performs the Boolean function Y = A in positive logic. NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION PACKAGE (1) TA NanoStar™ – WCSP (DSBGA) 0.23-mm Large Bump – YEP –40°C to 85°C (1) (2) NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) ORDERABLE PART NUMBER TOP-SIDE MARKING (2) SN74AUC2G34YEPR Tape and reel _ _ _U9_ SN74AUC2G34YZPR SOT-563 – DRL Tape and reel SN74AUC2G34DRLR U9_ SOT-23 – DBV Tape and reel SN74AUC2G34DBVR U34_ SC-70 – DCK Tape and reel SN74AUC2G34DCKR U9_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar, NanoFree are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2006, Texas Instruments Incorporated SN74AUC2G34 DUAL BUFFER GATE www.ti.com SCES514A – NOVEMBER 2003 – REVISED MARCH 2006 FUNCTION TABLE (EACH GATE) INPUT A OUTPUT Y H H L L LOGIC DIAGRAM (POSITIVE LOGIC) 1A 2A 1 6 3 4 1Y 2Y Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 3.6 V VI Input voltage range (2) –0.5 4.1 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 4.1 V –0.5 VCC + 0.5 range (2) UNIT VO Output voltage IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±20 mA ±100 mA Continuous current through VCC or GND θJA Package thermal impedance (3) Tstg Storage temperature range DBV package 165 DCK package 259 DRL package 142 YEP/YZP package (1) (2) (3) 2 V °C/W 123 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback SN74AUC2G34 DUAL BUFFER GATE www.ti.com SCES514A – NOVEMBER 2003 – REVISED MARCH 2006 Recommended Operating Conditions VCC (1) Supply voltage VCC = 0.8 V VIH High-level input voltage VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V MIN MAX 0.8 2.7 UNIT V VCC 0.65 × VCC V 1.7 VCC = 0.8 V 0 VIL Low-level input voltage VCC = 1.1 V to 1.95 V 0.35 × VCC VI Input voltage 0 3.6 V VO Output voltage 0 VCC V VCC = 2.3 V to 2.7 V IOH High-level output current IOL Low-level output current 0.7 VCC = 0.8 V –0.7 VCC = 1.1 V –3 VCC = 1.4 V –5 VCC = 1.65 V –8 VCC = 2.3 V –9 VCC = 0.8 V 0.7 VCC = 1.1 V 3 VCC = 1.4 V 5 VCC = 1.65 V 8 VCC = 2.3 V ∆t/∆v TA (1) (2) (3) Input transition rise or fall rate mA mA 9 VCC = 0.8 V to 1.65 V (2) 20 VCC = 1.65 V to 1.95 V (3) 20 VCC = 2.3 V to 2.7 V (3) 10 Operating free-air temperature V –40 85 ns/V °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. The data was taken at CL = 15 pF, RL = 2 kΩ (see Figure 1). The data was taken at CL = 30 pF, RL = 500 Ω (see Figure 1). Submit Documentation Feedback 3 SN74AUC2G34 DUAL BUFFER GATE www.ti.com SCES514A – NOVEMBER 2003 – REVISED MARCH 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VOH VOL VCC TYP (1) MIN MAX IOH = –100 µA 0.8 V to 2.7 V IOH = –0.7 mA 0.8 V IOH = –3 mA 1.1 V 0.8 IOH = –5 mA 1.4 V 1 IOH = –8 mA 1.65 V 1.2 IOH = –9 mA 2.3 V 1.8 IOL = 100 µA 0.8 V to 2.7 V IOL = 0.7 mA 0.8 V IOL = 3 mA 1.1 V 0.3 IOL = 5 mA 1.4 V 0.4 IOL = 8 mA 1.65 V 0.45 IOL = 9 mA 2.3 V 0.6 UNIT VCC – 0.1 0.55 V 0.2 0.25 V VI = VCC or GND 0 to 2.7 V ±5 µA Ioff VI or VO = 2.7 V 0 ±10 µA ICC VI = VCC or GND, 0.8 V to 2.7 V 10 µA Ci VI = VCC or GND II (1) A inputs IO = 0 2.5 V 2 pF All typical values are at TA = 25°C. Switching Characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) PARAMETER VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V FROM (INPUT) TO (OUTPUT) VCC = 0.8 V TYP MIN MAX MIN MAX MIN TYP MAX MIN MAX A Y 6.4 0.7 3.4 0.6 2.3 0.6 1 1.6 0.5 1.2 tpd UNIT ns Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A Y VCC = 1.8 V ± 0.15 V MIN 0.7 VCC = 2.5 V ± 0.2 V TYP MAX 1.3 2.4 UNIT MIN MAX 0.6 1.8 ns Operating Characteristics TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance TEST CONDITIONS VCC = 0.8 V VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V TYP TYP TYP TYP TYP f = 10 MHz 12 12 12 13 14 Submit Documentation Feedback UNIT pF SN74AUC2G34 DUAL BUFFER GATE www.ti.com SCES514A – NOVEMBER 2003 – REVISED MARCH 2006 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND RL LOAD CIRCUIT VCC CL RL V∆ 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 15 pF 15 pF 15 pF 15 pF 15 pF 30 pF 30 pF 2 kΩ 2 kΩ 2 kΩ 2 kΩ 2 kΩ 1 kΩ 500 Ω 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V 0.15 V 0.15 V VCC Timing Input VCC/2 0V tw tsu th VCC VCC/2 Input VCC/2 VCC VCC/2 Data Input VCC/2 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 Input VCC/2 0V tPHL tPLH VOH VCC/2 Output VCC/2 VOL tPHL VCC/2 VCC/2 VOL tPZL tPLZ VCC VCC/2 Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VCC/2 0V tPZH VOH Output Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH VCC/2 VCC Output Control VOL + V∆ VOL tPHZ VCC/2 VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback 5 PACKAGE OPTION ADDENDUM www.ti.com 8-Apr-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74AUC2G34DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC2G34DBVRE4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC2G34DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC2G34DCKRE4 ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC2G34DRLR ACTIVE SOP DRL 6 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC2G34DRLRG4 ACTIVE SOP DRL 6 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUC2G34YEPR NRND WCSP YEP 6 3000 TBD SNPB Level-1-260C-UNLIM SN74AUC2G34YZPR ACTIVE WCSP YZP 6 3000 Pb-Free (RoHS) SNAGCU Level-1-260C-UNLIM SN74AUC2G34YZTR ACTIVE DSBGA YZT 6 3000 Pb-Free (RoHS) SNAGCU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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