TI TFP403PZP

PanelBus SLDS125A – DECEMBER 2000 – REVISED OCTOBER 2002
D
D
D
D
D
9
D
81
D
D
51
D
Rates and Better Performance Over Longer
Cables
Reduced Power Consumption—1.8-V Core
Operation With 3.3 V I/Os and Supplies3
Reduced Ground Bounce Using Time
Staggered Pixel Outputs
Lowest Noise and Best Power Dissipation
Using PowerPAD Packaging
Advanced Technology Using TI 0.18-µm
EPIC-5 CMOS Process
Supports Hot Plug Detection
71
D
D 4x Over-Sampling for Reduced Bit-Error
Rates up to 165 MHz)
Digital Visual Interface (DVI 1.0)
Specification Compliant1
Pin-for-Pin Compatible With TFP501 for
Simple Upgrade Path to HDCP2
True-Color, 24 Bit/Pixel, 16.7M Colors at
1 or 2-Pixels per Clock
Laser Trimmed (50 Ω) Input Stage for
Optimum Fixed Impedance Matching
Skew Tolerant up to One Pixel Clock Cycle
(High Clock and Data Jitter Tolerance)
44
D Supports UXGA Resolution (Output Pixel
：
description
85
，
QQ
The Texas Instruments TFP403 is a PanelBus flat panel display products, part of a comprehensive family of
end-to-end DVI 1.0 compliant solutions. Targeted primarily at desktop LCD monitors and digital projectors, the
TFP403 finds applications in any design requiring high-speed digital interface.
43
41
5
The TFP403 supports display resolutions up to UXGA in 24-bit true color pixel format. The TFP403 offers design
flexibility to drive one or two pixels per clock, supports TFT or DSTN panels, and provides an option for time
staggered pixel outputs for reduced ground bounce.
18
66
PowerPAD advanced packaging technology results in best of class power dissipation, footprint, and ultralow
ground inductance.
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The TFP403 combines PanelBus circuit innovation with TIs advanced 0.18-µm EPIC-5 CMOS process
technology, along with PowerPAD package technology to achieve a reliable, low-powered, low-noise,
high-speed digital interface solution.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1.
The Digital Visual Interface Specification (DVI) is an industry standard developed by the Digital Display Working Group (DDWG) for
high-speed digital connection to digital displays. The TFP403 is compliant with the DVI Specification Rev. 1.0.
2.
High-bandwidth digital content protection (HDCP) is the system used for protecting DVI outputs from being copied. The TFP501 is
TI’s DVI receiver with HDCP functionality.
The TFP403 has an internal voltage regulator that provides the 1.8-V core power supply from the externally supplied 3.3-V supplies.
3.
PanelBus, PowerPAD, and EPIC-5 are trademarks of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
!" #$
# % & ## '($ # ) # "( "#
) "" $
POST OFFICE BOX 655303
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1
TFP403
TI PanelBus DIGITAL RECEIVER
SLDS125A – DECEMBER 2000 – REVISED OCTOBER 2002
51
81
QO1
QO0
HSYNC
VSYNC
DE
OGND
ODCK
OVDD
RSVD
CLT2
CLT1
DGND
DVDD
QE23
QE22
QE21
QE20
QE19
QE18
QE17
QE16
OVDD
OGND
QE15
QE14
71
：
QQ
85
，
43
41
5
18
66
，
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有
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公
DFO
PD
ST
PIXS
DGND
DVDD
STAG
SCDT
PDO
QE0
QE1
QE2
QE3
QE4
QE5
QE6
QE7
OVDD
OGND
QE8
QE9
QE10
QE11
QE12
QE13
技
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50
49
48
47
46
45
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27
26
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91
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95
96
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98
99
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
OGND
QO23
OVDD
AGND
Rx2+
Rx2–
AVDD
Rx1+
Rx1–
AVDD
Rx0+
Rx0–
AVDD
RxC+
RxC–
AVDD
RSVD
RSVD
RSVD
RSVD
RSVD
PVDD
PGND
PVDD
OCK_INV
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9
75
74
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72
71
70
69
68
67
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65
64
63
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59
58
57
56
55
54
53
52
51
QO22
QO21
QO20
QO19
QO18
QO17
QO16
DGND
CAP
QO15
QO14
QO13
QO12
QO11
QO10
QO9
QO8
OGND
OVDD
QO7
QO6
QO5
QO4
QO3
QO2
PZP PACKAGE
(TOP VIEW)
TFP403
TI PanelBus DIGITAL RECEIVER
SLDS125A – DECEMBER 2000 – REVISED OCTOBER 2002
functional block diagram
3.3 V
3.3 V
1.8 V
Regulator
Internal 50-Ω
Termination
9
3.3 V
Latch
CTL2
+
_
Rx0+
Rx0-
+
_
Latch
RxC+
RxC-
+
_
PLL
Latch
GRN(0-7)
Data Recovery CH1(0-9)
TMDS
and
Decoder
Synchronization
CTL1
BLUE(0-7)
VSYNC
HSYNC
CH0(0-9)
ODCK
DE
SCDT
CTL2
CTL1
VSYNC
HSYNC
43
41
5
85
，
QQ
：
Channel 0
Panel
Interface
44
Channel 1
Rx1+
Rx1-
QE(0-23)
QO(0-23)
CTL3
71
+
_
CH2(0-9)
51
Channel 2
81
RED(0-7)
Rx2+
Rx2-
Terminal Functions
TERMINAL
I/O
NO.
DESCRIPTION
18
66
NAME
79
GND
Analog ground—Ground reference and current return for analog circuitry
AVDD
82,85,88,
91
VDD
Analog VDD—Power supply for analog circuitry. Nominally 3.3 V
67
VDD
Bypass capacitor—4.7 µF tantalum and 0.01 µF ceramic connected to ground. This capacitor is optional for
the TFP403, but is required for the TFP501.
41,40
DO
General-purpose control signals—Used for user defined control. In normal mode CTL1 is not powered down
via PDO.
46
DO
Output data enable—Used to indicate time of active video display versus nonactive display or blank time.
During blank, only HSYNC, VSYNC, and CTL1-2 are transmitted. During times of active display, or nonblank,
only pixel data, QE[23:0] and QO[23:0], is transmitted.
司
技
有
DE
公
CTL[2:1]
限
CAP
，
AGND
1
DI
5,39,68
GND
Digital ground—Ground reference and current return for digital core
Digital VDD—Power supply for digital core. Nominally 3.3 V
6,38
HSYNC
48
VDD
DO
OCK_INV
100
DI
深
DVDD
Output clock data format—Controls the output clock (ODCK) format for either TFT or DSTN panel support. For
TFT support ODCK clock runs continuously. For DSTN support ODCK only clocks when DE is high; otherwise
ODCK is held low when DE is low.
High : DSTN support/ODCK held low when DE = low
Low: TFT support/ODCK runs continuously.
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DGND
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High : Active display time
Low: Blank time
Horizontal sync output
ODCK polarity—Selects ODCK edge on which pixel data (QE[23:0] and QO[23:0]) and control signals
(HSYNC, VSYNC, DE, CTL1-2 ) are latched
Normal mode:
High : Latches output data on rising ODCK edge
Low : Latches output data on falling ODCK edge
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TFP403
TI PanelBus DIGITAL RECEIVER
SLDS125A – DECEMBER 2000 – REVISED OCTOBER 2002
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
Output data clock—Pixel clock. All pixel outputs QE[23:0] and QO[23:0] (if in 2-pixel/clock mode) along with
DE, HSYNC, VSYNC, and CTL[2:1] are synchronized to this clock.
44
DO
OGND
19,28,45,
58,76
GND
Output driver ground—Ground reference and current return for digital output drivers
OVDD
18,29,43,
57,78
VDD
Output driver VDD—Power supply for output drivers. Nominally 3.3 V
2
DI
81
51
Power down—An active low signal that controls the TFP403 power-down state. During power down all output
buffers are switched to a high impedance state. All analog circuits are powered down and all inputs are
disabled, except for PD.
44
PD
9
ODCK
71
If PD is left unconnected an internal pullup will default the TFP403 to normal operation.
9
DI
Output drive power down—An active low signal that controls the power-down state of the output drivers.
During output drive powerdown, the output drivers (except SCDT and CTL1) are driven to a high impedance
state. A weak pulldown will slowly pull these outputs to a low level. When PDO is left unconnected, an internal
pullup defaults the TFP403 to normal operation.
85
，
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PDO
：
High : Normal operation
Low: Power down
High : Normal operation/output drivers on
Low: Output drive power down.
GND
4
DI
PLL GND—Ground reference and current return for internal PLL
43
41
5
98
PIXS
Pixel select—Selects between one or two pixels per clock output modes. During the 2-pixel/clock mode, both
even pixels, QE[23:0], and odd pixels, QO[23:0], are output in tandem on a given clock cycle. During
1-pixel/clock, even and odd pixels are output sequentially, one at a time, with the even pixel first, on the even
pixel bus, QE[23:0]. (The first pixel per line is pixel-0, the even pixel. The second pixel per line is pixel-1, the
odd pixel.)
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66
PGND
VDD
DO
10-17
PLL VDD—Power supply for internal PLL. Nominally 3.3 V
司
97
Even blue pixel output—Output for even and odd blue pixels when in 1-pixel/clock mode. Output for even only
blue pixel when in 2-pixel per clock mode. Output data is synchronized to the output data clock, ODCK.
DO
Even green pixel output—Output for even and odd green pixels when in 1-pixel/clock mode. Output for even
only green pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
有
20-27
技
QE[8:15]
限
LSB: QE0/pin 10
MSB: QE7/pin 17
公
PVDD
QE[0:7]
，
High : 2-pixel/clock
Low: 1-pixel/clock
30-37
DO
DO
59-66
DO
49-56
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QO[0:7]
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QE[16:23]
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LSB: QE8/pin 20
MSB: QE15/pin 27
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QO[8:15]
Even red pixel output—Output for even and odd red pixels when in 1-pixel/clock mode. Output for even only
red pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE16/pin 30
MSB: QE23/pin 37
Odd blue pixel output—Output for odd only blue pixel when in 2-pixel/clock mode. Not used, and held low,
when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO0/pin 49
MSB: QO7/pin 56
Odd green pixel output—Output for odd only green pixel when in 2-pixel/clock mode. Not used, and held low,
when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO8/pin 59
MSB: QO15/pin 66
QO[16:23]
69-75,77
DO
Odd red pixel output—Output for odd only red pixel when in 2-pixel/clock mode. Not used, and held low, when
in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO16/pin 69
MSB: QO23/pin 77
4
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TFP403
TI PanelBus DIGITAL RECEIVER
SLDS125A – DECEMBER 2000 – REVISED OCTOBER 2002
Terminal Functions (Continued)
TERMINAL
NAME
RSVD
I/O
NO.
DESCRIPTION
42
DO
Reserved. Must be tied high for normal operation
AI
Reserved. See TFP501 data sheet for intended future use.
89
AI
Clock positive receiver input—Positive side of reference clock. TMDS low voltage signal differential input pair
RxC–
90
AI
Clock negative receiver input—Negative side of reference clock. TMDS low voltage signal differential input
pair
Rx0+
86
AI
Channel-0 positive receiver input—Positive side of channel-0. TMDS low voltage signal differential input pair.
Channel-0 receives blue pixel data in active display and HSYNC, VSYNC control signals in blank.
Rx0–
87
AI
Channel-0 negative receiver input—Negative side of channel-0. TMDS low voltage signal differential input
pair.
Rx1+
83
AI
Channel-1 positive receiver input—Positive side of channel-1 TMDS low voltage signal differential input pair.
Channel-1 receives green pixel data in active display and CTL1 control signals in blank.
Rx1–
84
AI
Channel-1 negative receiver input—Negative side of channel-1 TMDS low voltage signal differential input pair
Rx2+
80
AI
Channel-2 positive receiver input—Positive side of channel-2 TMDS low voltage signal differential input pair.
Channel-2 receives red pixel data in active display and CTL2 control signals in blank.
Rx2–
81
AI
Channel-2 negative receiver input—Negative side of channel-2 TMDS low voltage signal differential input
pair.
SCDT
8
DO
Sync detect—Output to signal when the link is active or inactive. The link is considered to be active when DE is
actively switching. The TFP403 monitors the state DE to determine link activity. SCDT can be tied externally to
PDO to power down the output drivers when the link is inactive.
43
41
5
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：
71
44
51
81
9
92–96
RxC+
18
66
High: Active link
Low: Inactive link
3
DI
Output drive strength select—Selects output drive strength for high or low current drive. (See dc specifications
for IOH and IOL vs ST state.)
High : High drive strength
Low : Low drive strength
STAG
7
DI
Staggered pixel select—An active low signal used in the 2-pixel/clock pixel mode (PIXS = high). Time staggers
the even and odd pixel outputs to reduce ground bounce. Normal operation outputs the odd and even pixels
simultaneously.
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ST
47
DO
Vertical sync output
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VSYNC
有
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High : Normal simultaneous even/odd pixel output
Low: Time staggered even/odd pixel output
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5
TFP403
TI PanelBus DIGITAL RECEIVER
SLDS125A – DECEMBER 2000 – REVISED OCTOBER 2002
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
44
51
81
9
Supply voltage range, DVDD, AVDD, OVDD, PVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Input voltage range, logic/analog signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Operating ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -–65°C to 150°C
Case temperature for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Package power dissipation/PowerPAD: Soldered (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 W
Not soldered (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 W
ESD Protection, all pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 KV Human Body Model
JEDEC latch up (EIA/JESD78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
85
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71
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Specified with PowerPAD bond pad on the backside of the package soldered to a 2 oz. Cu plate PCB thermal plane. Specified at
maximum allowed operating temperature, 70°C.
2. PowerPAD bond pad on the backside of the package is not soldered to a thermal plane. Specified at maximum allowed operating
temperature, 70°C.
43
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5
recommended operating conditions
Supply voltage, VDD (DVDD, AVDD, PVDD, OVDD)
Pixel time, tpix‡
18
66
Single ended analog input termination resistance, Rt
MIN
TYP
MAX
3
3.3
3.6
V
40
ns
55
Ω
6.06
45
50
UNIT
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Operating free-air temperature, TA
0
25
70
°C
‡ tpix is the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK is equal to tpix when in 1-pixel/clock mode
and 2tpix when in 2-pixel/clock mode.
6
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TFP403
TI PanelBus DIGITAL RECEIVER
SLDS125A – DECEMBER 2000 – REVISED OCTOBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
dc digital I/O specifications
TEST CONDITIONS
MIN
Low level digital input voltage†
ST = High,
ST = Low,
10
3
6
12
VOL = 0.8 V
VOL = 0.8 V
10
13
19
7
11
VI(OC)
Open circuit analog input voltage
43
41
5
Analog input common mode voltage (see Note 3)
–1
QQ
TEST CONDITIONS
85
，
PARAMETER
5
18
9
5
dc specifications
Analog input differential voltage (see Note 3)
V
VOH = 2.4 V
VOH = 2.4 V
IOZ
Hi-Z output leakage current
PD = Low or PDO = Low
† Digital inputs are labeled DI in I/O column of Terminal Functions Table.
‡ Digital outputs are labeled DO in I/O column of Terminal Functions Table.
VID
VIC
V
0.8
81
Low level output drive current‡
DVDD
0
51
IOL
ST = Low,
UNIT
2
44
High level output drive current‡
MAX
1
mA
mA
µA
71
IOH
ST = High,
TYP
：
VIH
VIL
PARAMETER
High level digital input voltage†
MIN
TYP
MAX
UNIT
75
1200
mv
AVDD-300
AVDD-10
AVDD-37
AVDD+10
mv
400
mA
mv
Normal 2-pix/clock power supply current (see Note 4)
I(PD)
Power down current (see Note 5)
PD = Low
10
mA
Output drive power down current (see Note 5)
PDO = Low
45
mA
，
Specified as dc characteristic with no overshoot or undershoot.
Alternating 2-pixel black/2-pixel white pattern. ST = high, STAG = high, QE[23:0] and QO[23:0] CL = 10 pF.
Analog inputs are open circuit (transmitter is disconnected from TFP403).
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I(PDO)
NOTES: 3.
4.
5.
18
66
IDD(2PIX)
PIXEL RATE = 82.5 MHz
2-pix/clock
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7
TFP403
TI PanelBus DIGITAL RECEIVER
SLDS125A – DECEMBER 2000 – REVISED OCTOBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
ac specifications
VID(2)
tps
TEST CONDITIONS
MIN
TYP
150
MAX
UNIT
1560
mVp-p
tbit‡
Analog input intra-pair (+ to -) differential skew (see Note 6)
0.4
Analog Input inter-pair or channel-to-channel skew
(see Note 6)
Analog Input inter-pair or channel-to-channel skew
(see Note 6)
Worse case differential input clock jitter tolerance¶
(see Note 6)
Worse case differential input clock jitter tolerance¶
(see Note 6)
81
ST = Low,
ST = High,
CL = 5 pF
CL = 10 pF
tr(1)
Rise time of data and control signals#, ||
ST = Low,
ST = High,
tr(2)
Rise time of ODCK clock#
ST = Low,
ST = High,
tf(2)
Fall time of ODCK clock#
ST = Low,
ST = High,
tsu(1)
Setup time, data, and control
signal to falling edge of ODCK
1 pixel, OCK_INV = low||,
PIXS = low
th(1)
Hold time,
time data,
data and control
signal to falling edge of ODCK
1 pixel
INV = low||,
ixel, OCK
OCK_INV
PIXS = low
tsu(2)
Setup time,
Setu
time data,
data and control
signal to rising edge of ODCK
th(2)
Hold time, data, and control
signal to rising edge of ODCK
f(ODCK)
ODCK frequency
ns
CL = 5 pF
CL = 10 pF
2.4
1.9
ns
CL = 5 pF
CL = 10 pF
2.4
1.9
ns
CL = 5 pF
CL = 10 pF
2.4
1.9
ns
85
，
43
41
5
1.0
ns
ST = Low,
Low
ST = High,
High
CL = 5 pF
F
CL = 10 pF
1.0
ns
1 pixel
ixel, OCK_INV
OCK INV = high||,
PIXS = low
ST = Low,
Low
ST = High,
High
CL = 5 pF
F
CL = 10 pF
1.0
ns
2 pixel and STAG
OCK_INV = high||
PIXS = high
ST = Low,
ST = High,
CL = 5 pF
CL = 10 pF
0.5
ns
有
限
公
司
，
18
66
CL = 5 pF
CL = 10 pF
PIX = Low (1-PIX/CLK)
25
165
PIX = High (2-PIX/CLK)
12.5
82.5
40%
50%
Propagation delay time from PD low to Hi-Z outputs
讯
科
tpd(PDL)
tpd(PDOL)
ST = Low,
ST = High,
ps
2.4
1.9
技
ODCK duty-cycle
tpix§
51
Fall time of data and control signals#, ||
QQ
tf(1)
44
50
71
t(ijit)
1
：
t(ccs)
9
PARAMETER
Differential input sensitivity†
Propagation delay time from PDO low to Hi-Z outputs
td
Delay time, ODCK latching edge to QE[23:0] data output
市
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tt(HSC)
tt(FSC)
Transition time between DE transition to SCDT lowk
Transition time between DE transition to SCDT highk
1e6
STAG = Low
Pixs = High
MHz
60%
9
ns
9
ns
1600
tpix
tpix
0.5
tpix
深
圳
† Specified as ac parameter to include sensitivity to overshoot, undershoot, and reflection.
‡ tbit is 1/10 the pixel time, tpix
§ tpix is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to tpix in 1-pixel/clock mode or 2tpix when in
2-pixel/clock mode.
¶ Measured differentially at 50% crossing using ODCK output clock as trigger.
# Rise and fall times measured as time between 20% and 80% of signal amplitude.
|| Data and control signals are : QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[2:1]
k Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity.
NOTE 6: By characterization
8
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TFP403
TI PanelBus DIGITAL RECEIVER
SLDS125A – DECEMBER 2000 – REVISED OCTOBER 2002
PARAMETER MEASUREMENT INFORMATION
tr(2)
tf(2)
80%
ODCK
80%
20%
20%
80%
QE(0-23), QO(0-23), DE
CTL(1-2), HSYNC, VSYNC
51
tf(1)
80%
20%
71
20%
44
tr(1)
81
9
Figure 1. Rise and Fall Time of ODCK
QQ
：
Figure 2. Rise and Fall Time of Data and Control Signals
85
，
f(ODCK)
ODCK
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41
5
Figure 3. ODCK Frequency
tsu(1)
tsu(2)
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66
th(1)
VOH
VOL
，
ODCK
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
公
司
QE(0-23), QO(0-23), DE
CTL(1-2), HSYNC, VSYNC
th(2)
限
OCK_INV
讯
科
技
有
Figure 4. Data Setup and Hold Time to Rising and Falling Edge of ODCK
VOH
ODCK
t(ps)
市
金
合
td
50%
Tx-
50%
Figure 5. ODCK High to QE[23:0]
Staggered Data Output
Figure 6. Analog Input Intra-Pair
Differential Skew
深
圳
QE(O-23)
Tx+
POST OFFICE BOX 655303
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9
TFP403
TI PanelBus DIGITAL RECEIVER
SLDS125A – DECEMBER 2000 – REVISED OCTOBER 2002
PARAMETER MEASUREMENT INFORMATION
PD
PDO
VIL
VIL
tpd(PDL)
tpd(PDOL)
9
QE(0-23), QO(0-23),
ODCK, DE, CTL2,
HSYNC, VSYNC
81
QE(0-23), QO(0-23),
ODCK, DE, CTL(1-2),
HSYNC, VSYNC, SCDT
Figure 8. Delay From PDO Low to Hi-Z Outputs
71
50%
：
TX2
44
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Figure 7. Delay From PD Low to Hi-Z Outputs
QQ
TX1
50%
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TX0
85
，
t(ccs)
Figure 9. Analog Input Channel-to-Channel Skew
tt(FSC)
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tt(HSC)
司
，
DE
限
公
SCDT
技
有
Figure 10. Time Between DE Transitions to SCDT Low and SCDT High
t(DEH)
DE
Figure 11. Minimum DE Low and Maximum DE High
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t(DEL)
10
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TFP403
TI PanelBus DIGITAL RECEIVER
SLDS125A – DECEMBER 2000 – REVISED OCTOBER 2002
detailed description
fundamental operation
71
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The TFP403 is a digital visual interface (DVI) compliant TMDS digital receiver that is used in digital flat panel
display systems to receive and decode TMDS encoded RGB pixel data streams. In a digital display system a
host, usually a PC or workstation, contains a DVI compatible transmitter that receives 24 bit pixel data along
with appropriate control signals. The transmitter encodes them into a high-speed low-voltage differential serial
bit stream optimized for transmission over a twisted-pair cable to a display device. The display device, usually
a flat-panel monitor, will require a DVI compatible receiver like the TI TFP403 to decode the serial bit stream
back to the same 24 bit pixel data and control signals that originated at the host. This decoded data can then
be applied directly to the flat panel drive circuitry to produce an image on the display. Since the host and display
can be separated by distances up to 5 meters or more, serial transmission of the pixel data is preferred. To
support modern display resolutions up to UXGA a high bandwidth receiver with good jitter and skew tolerance
is required.
QQ
：
TMDS pixel data and control signal encoding
85
，
TMDS stands for transition minimized differential signaling. Only one of two possible TMDS characters for a
given pixel will be transmitted at a given time. The transmitter keeps a running count of the number of ones and
zeros previously sent and transmits the character that will minimize the number of transitions and approximate
a dc balance of the transmission line.
RECEIVED PIXEL DATA
ACTIVE DISPLAY DE = HIGH
INPUT CHANNEL
司
Green[7:0]
公
Blue[7:0]
限
RECEIVED CONTROL DATA
BLANKING DE = LOW
OUTPUT PINS
(VALID FOR DE = HIGH)
Channel – 2 (Rx2 ±)
QE[23:16] QO[23:16]
Channel – 1 (Rx1 ±)
QE[15:8] QO[15:8]
Channel – 0 (Rx0 ±)
QE[7:0] QO[7:0]
，
Red[7:0]
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Three TMDS channels are used to receive RGB pixel data during active display time, DE = high. The same three
channels also receive control signals, HSYNC, VSYNC, and user defined control signals CTL[2:1]. These
control signals are received during inactive display or blanking-time. Blanking-time is when DE = low. The
following table maps the received input data to appropriate TMDS input channel in a DVI compliant system.
INPUT CHANNEL
OUTPUT PINS
(VALID FOR DE = LOW)
Channel – 2 (Rx2 ±)
CTL2
CTL[1: 0] (see Note 7)
Channel – 1 (Rx1 ±)
CTL1
Channel – 0 (Rx0 ±)
HSYNC, VSYNC
技
有
CTL[3:2] (see Note 7)
讯
科
HSYNC, VSYNC
合
NOTE 7: Some TMDS transmitters transmit a CTL0 signal. The TFP403 decodes and
transfers CTL[2:1] and ignores CTL0 characters. CTL3 is used internally to enable
HDCP decryption. CTL3 and CTL0 are not available as TFP501 outputs.
深
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金
The TFP403 discriminates between valid pixel TMDS characters and control TMDS characters to determine
the state of active display versus blanking, i.e., state of DE.
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11
TFP403
TI PanelBus DIGITAL RECEIVER
SLDS125A – DECEMBER 2000 – REVISED OCTOBER 2002
detailed description (continued)
TFP403 clocking and data synchronization
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The TFP403 receives a clock reference from the DVI transmitter that has a period equal to the pixel time, Tpix.
The frequency of this clock is also referred to as the pixel rate. Since the TMDS encoded data on Rx[2:0]
contains 10 bits per 8 bit pixel it follows that the Rx[2:0] serial bit rate is 10 times the pixel rate. For example,
the required pixel rate to support an UXGA resolution with 60 Hz refresh rate is 165 MHz. The TMDS serial bit
rate is 10x the pixel rate or 1.65 Gb/s. Due to the transmission of this high-speed digital bit stream, on three
separate channels (or twisted-pair wires) of long distances (3-5 meters), phase synchronization between the
data steams and the input reference clock is not guaranteed. In addition, skew between the three data channels
is common. The TFP403 uses a 4x oversampling scheme of the input data streams to achieve reliable
synchronization with up to 1-Tpix channel-to-channel skew tolerance. Accumulated jitter on the clock and data
lines due to reflections and external noise sources is also typical of high speed serial data transmission, hence
the TFP403s design for high jitter tolerance.
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The input clock to the TFP403 is conditioned by a phase-locked-loop (PLL) to remove high frequency jitter from
the clock. The PLL provides four 10x clock outputs of different phase to locate and sync the TMDS data streams
(4x oversampling). During active display the pixel data is encoded to be transition minimized, whereas in blank,
the control data is encoded to be transition maximized. A DVI compliant transmitter is required to transmit in
blank for a minimum period of time, 128-Tpix, to ensure sufficient time for data synchronization when the
receiver sees a transition maximized code. Synchronization during blank, when the data is transition
maximized, ensures reliable data bit boundary detection. Phase synchronization to the data streams is unique
for each of the three input channels and is maintained as long as the link remains active.
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TFP403 TMDS input levels and input impedance matching
司
，
The TMDS inputs to the TFP403 receiver have a fixed single-ended termination to AVDD The TFP403 is
internally optimized using a laser trim process to precisely fix the impedance at 50 Ω. The device will function
normally with or without a resistor on the EXT_RES pin, so it remains drop-in compatible with current sockets.
The fixed impedance eliminates the need for an external resistor while providing optimum impedance matching
to standard 50-Ω DVI cables.
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合
讯
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技
有
限
公
Figure 12 shows a conceptual schematic of a DVI transmitter and TFP403 receiver connection. A transmitter
drives the twisted pair cable via a current source, usually achieved with an open drain type output driver. The
internal resistor, which is matched to the cable impedance, at the TFP403 input provides a pullup to AVDD.
Naturally, when the transmitter is disconnected and the TFP403 DVI inputs are left unconnected, the TFP403
receiver inputs pullup to AVDD. The single ended differential signal and full differential signal is shown in
Figure 13. The TFP403 is designed to respond to differential signal swings ranging from 150 mV to 1.56 V with
common mode voltages ranging from (AVDD-300 mV) to (AVDD-37 mV).
12
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TFP403
TI PanelBus DIGITAL RECEIVER
SLDS125A – DECEMBER 2000 – REVISED OCTOBER 2002
TFP403 TMDS input levels and input impedance matching (continued)
DVI
Transmitter
TI TFP403
Receiver
AVDD
DATA
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Internal
Termination at 50 Ω
9
DVI Compliant Cable
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DATA
85
，
QQ
：
Current
Source
+
_
Figure 12. TMDS Differential Input and Transmitter Connection
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1/2 VID
AVCC
–1/2 VID
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66
AVCC –1/2 VID
VID
+ 1/2 VID
b) Differential Input Signal
，
a ) Single-Ended Input Signal
司
Figure 13. TMDS Inputs
公
TFP403 modes of operation
技
有
限
The TFP403 provides systems design flexibility and value by providing the system designer with configurable
options or modes of operation to support varying system architectures. The following table outlines the various
panel modes that can be supported along with appropriate external control pin settings.
PIXEL RATE
ODCK LATCH
EDGE
ODCK
DFO
PIXS
OCK_INV
TFT or 16-bit DSTN
1 pix/clock
Falling
Free run
0
0
0
TFT or 16-bit DSTN
讯
科
PANEL
Rising
Free run
0
0
1
2 pix/clock
Falling
Free run
0
1
0
TFT
2 pix/clock
Rising
Free run
0
1
1
24-bit DSTN
1 pix/clock
Falling
Gated low
1
0
0
NONE
1 pix/clock
Rising
Gated low
1
0
1
24-bit DSTN
2 pix/clock
Falling
Gated low
1
1
0
24-bit DSTN
2 pix/clock
Rising
Gated low
1
1
1
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1 pix/clock
TFT
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13
TFP403
TI PanelBus DIGITAL RECEIVER
SLDS125A – DECEMBER 2000 – REVISED OCTOBER 2002
detailed description (continued)
TFP403 output driver configurations
The TFP403 provides flexibility by offering various output driver features that can be used to optimize power
consumption, ground-bounce, and power-supply noise. The following sections outline the output driver features
and their effects.
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Output driver power down (PDO = low), Pulling PDO low will place all the output drivers, except CTL1 and
SCDT, into a high-impedance state. The SCDT output which indicates link-disabled or link-inactive can be tied
directly to the PDO input to disable the output drivers when the link is inactive or when the cable is disconnected.
An internal pullup on the PDO pin will default the TFP403 to the normal nonpower down output drive mode if
left unconnected.
QQ
：
71
Drive Strength (ST = high for high drive strength, ST=low for low drive strength.) The TFP403 allows for
selectable output drive strength on the data, control and ODCK outputs. See the dc specifications table for the
values of IOH and IOL current drives for a given ST state. The high output strength offers approximately two times
the drive as the low output drive strength.
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85
，
Time Staggered Pixel Output. This option works only in conjunction with the 2-pixel/clock mode (PIXS = high).
Setting STAG = low will time stagger the even and odd pixel output so as to reduce the amount of instantaneous
current surge from the power supply. Depending on the PCB layout and design this can help reduce the amount
of system ground bounce and power supply noise. The time stagger is such that in 2-pixel/clock mode the even
pixel is delayed from the latching edge of ODCK by 0.25 Tcip. (Tcip is the period of ODCK. The ODCK period
is 2Tpix when in 2-pixel/clock mode.)
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66
Depending on system constraints of output load, pixel rate, panel input architecture and board cost the TFP403
drive strength and staggered pixel options allow flexibility to reduce system power-supply noise, ground bounce
and EMI.
，
Power Management. The TFP403 offers several system power management features.
公
司
The output driver power down (PDO = low) is an intermediate mode which offers several uses. During this mode,
all output drivers except SCDT and CTL1 are driven to a high impedance state while the rest of the device
circuitry remains active
技
有
限
The TFP403 power down (PD = low) is a complete power down in that it powers down the digital core, the analog
circuitry, and output drivers. All output drivers are placed into a Hi-Z state. All inputs are disabled except for the
PD input. The TFP403 will not respond to any digital or analog inputs until PD is pulled high.
讯
科
Both PDO and PD have internal pullup so if left unconnected they will default the TFP403 to normal operating
modes.
市
金
合
Sync Detect. The TFP403 offers an output, SCDT to indicate link activity. The TFP403 monitors activity on DE
to determine if the link is active. When 1 million (1e6) pixel clock periods pass without a transition on DE, the
TFP403 considers the link inactive and SCDT is driven low. The SCDT goes high immediately after the first
transition on DE. The SCDT again becomes low when no more transitions are seen after 218 ocillator clocks.
深
圳
SCDT can be used to signal a system power management circuit to initiate a system power down when the link
is considered inactive. The SCDT can also be tied directly to the TFP403 PDO input to power down the output
drivers when the link is inactive. It is not recommended to use the SCDT to drive the PD input since, once in
complete power down, the analog inputs are ignored and the SCDT state does not change. An external system
power management circuit to drive PD is preferred.
14
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TFP403
TI PanelBus DIGITAL RECEIVER
SLDS125A – DECEMBER 2000 – REVISED OCTOBER 2002
detailed description (continued)
PowerPAD 100-TQFP package
81
9
The TFP403 is packaged in TI’s thermally enhanced PowerPAD 100TQFP packaging. The PowerPAD package
is a 14 mm × 14 mm × 1 mm TQFP outline with 0.5 mm lead-pitch. The PowerPAD package has a specially
designed die mount pad that offers improved thermal capability over typical TQFP packages of the same outline.
The TI 100-TQFP PowerPAD package offers a back-side solder plane that connects directly to the die mount
pad for enhanced thermal conduction. Soldering the back side of the TFP403 to the application board is not
required thermally, as the device power dissipation is well within the package capability when not soldered.
71
44
51
Soldering the back side of the device to the PCB ground plane is recommended for electrical considerations.
Since the die pad is electrically connected to the chip substrate and hence chip ground, connection of the
PowerPAD back side to a PCB ground plane will help to improve EMI, ground bounce, and power supply noise
performance.
QQ
：
Table 1 outlines the thermal properties of the TI 100-TQFP PowerPAD package. The 100-TQFP non-PowerPAD
package is included only for reference.
Theta-JA†,‡
Theta-JC†,‡
PowerPAD
NOT CONNECTED TO PCB
THERMAL PLANE
PowerPAD
CONNECTED TO PCB
THERMAL PLANE†
27.3°C/W
17.3°C/W
0.12°C/W
0.12°C/W
2.7 W
4.3 W
45°C/W
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限
公
司
，
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3.11°C/W
Maximum power dissipation†,‡,§
1.6 W
† Specified with 2 oz. Cu PCB plating.
‡ Airflow is at 0 LFM (no airflow)
§ Measured at ambient temperature, TA = 70°C.
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WITHOUT
PowerPAD
PARAMETER
85
，
Table 1. TI 100-TQFP (14 × 14 × 1 mm)/0.5 mm Lead Pitch
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15
THERMAL PAD MECHANICAL DATA
PowerPAD™ PLASTIC QUAD FLATPACK
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，
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PZP (S-PQFP-G100)
www.ti.com
TFP403
TI PanelBus DIGITAL RECEIVER
SLDS125A – DECEMBER 2000 – REVISED OCTOBER 2002
MECHANICAL DATA
PZP (S-PQFP-G100)
PowerPAD PLASTIC QUAD FLATPACK
0,27
0,17
0,50
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75
0,08 M
50
：
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85
，
QQ
Thermal Pad
(see Note D)
71
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76
26
1
25
0,25
公
16,20
SQ
15,80
Gage Plane
司
14,20
SQ
13,80
，
12,00 TYP
限
0,15
0,05
技
有
1,05
0,95
0°- 7°
0,75
0,45
讯
科
Seating Plane
0,08
合
1,20 MAX
市
金
4146929/A 04/99
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MS-026
深
圳
NOTES: A.
B.
C.
D.
0,13 NOM
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100
PowerPAD is a trademark of Texas Instruments.
16
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• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
51
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
：
71
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
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，
QQ
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third–party products or services
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Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
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Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
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Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
深
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市
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合
讯
科
技
有
限
公
司
，
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Copyright  2002, Texas Instruments Incorporated