Product Profile SmartMPEGTM MB87M2141 January 2003 Edition 1.00 MPEG-2 Decoder for Set-Top-Boxes FME/MM/PP/0103 INTRODUCTION: FEATURES The SmartMPEGTM is an integrated set-top-box decoder. As a major component of a digital video broadcast (DVB) set-top-box or IDTV this device uses Fujitsu’s industry-leading Cx81 CMOS technology (0.18µm). It incorporates an ARC Tangent A4 RISC core (@130MHz), two transport stream demultiplexers with integrated DVB descramblers, a PAL/NTSC digital video encoder and a display controller, which overlays up to four layers of OSD. This set-top-box decoder consists of a shared memory interface for CPU and for MPEG decoding. The universal processor interface allows connection to FLASH, hard disk drives and other asynchronous devices. The minimum SDRAM required is one 64Mbit device using 16bit data bus. The SmartMPEGTM is the 3rd generation of Fujitsu’s MPEG decoder, the successor to the MB87L2250. With the MB87L2250, Fujitsu offered a set-top-box chip, which enabled very low end product cost. Its successor, the SmartMPEGTM incorporates all the features which are required for standard set-top-boxes. This high level of integration makes it ideally suited for todays interactive set-top-box applications. Furthermore the Fujitsu Application Programming Interface (FAPI) ensures a short time-to-market by making the software development easier. The FAPI is the programming interface for Fujitsu DVB components as well as easing migration to future devices. • • • • • • S h a re d M e m o r y MPEG2 video ISO/IEC 13818-2 ([email protected]@ML) MPEG audio layer 1/2 32-bit RISC CPU (ARC Tangent A4 @130MHz) 4K I-cache / 2K D-cache Three timers / watchdog / power-down mode Shared memory interface (SDRAM, 16/32 bit data), 64Mbit...1Gbit Universal processor interface (IDE, NAND/NOR FLASH & Common Interface) Two transport stream decoders (decoding/recording) including DVB descrambler Flexible MPEG video resizing (factor 1/16 to 2) Display controller with up to four true colour graphic or CLUT layers Teletext / WSS / CC / VBID insertion PAL/NTSC digital encoder RGB De-matrix (RGB or YCrCb output) Control of brightness, contrast and colour saturation of RGB and YCrCb output 5 video DAC’s @ 10bit ITU-R 656 video input/output (shared with TS2 input) S/P DIF output for PCM/AC3/MPEG UART / Smart Card IF / I2C / GPIO 7-segment LED controller for 4 digits Infra Red receiver / transmitter PWM Output On-chip DPLL, requiring only 27.0MHz crystal Bootable from NOR Flash or I2C FPT-208P-M06 (LQFP-Package) Ambient Temperature Range (Std Pkg): 0oC to +70oC Advanced Technology: Fujitsu CMOS Cx81 (0.18µm) 1.8 volt device with 3.3 volt I/O Power consumption: typ. 800mW • • • • • • • • • • • • • • • • • • • • • • S /P -D IF (D o lb y D ig . B its tr e a m ) I2 S (A u d io ) SDRAM (6 4 M b it … 1 G b it) IT U -R 6 5 6 IT U -R 6 5 6 A n a lo g O /P : CVBS, YC, RGB Y C R C B , A u d io R /L 1 6 / 3 2 b it A R C @ 1 3 0 .5 M H z T a n g e n t-A 4 4K I-C a c h e 2K D -C a c h e W a tc h D og P o w e rD ow n IR Q C TR L 3 T im e rs S h a re d M em ory In te r fa c e M P E G -2 V id e o D e c o d e r M P E G A u d io D e c o d e r S /P -D IF O u tp u t U n it R e s iz in g T X T In s e r tio n D is p la y C o n tr o lle r (4 L a y e r ) D ig ita l E ncoder (P A L /N T S C ) W SS / VPS In s e r tio n C C /V B ID In s e r tio n A d ju s ta b le R G B D e -M a tr ix DAC1 DAC2 DAC3 DAC4 DAC5 IT U -R 6 5 6 O u tp u t S m a r tM P E G In te r n a l B u s @ 1 3 0 .5 M H z DPLL B u ffe r M g r D V B D e s c r a m b le r s TS3 in te rn T S D e m u ltip le x e r s TS1 TS2 P a r/S e r P a r/ S e r 2 7 .0 M H z H D D /ID E CTRL Boot ROM C h ip S e le c t CTRL U n iv e rs a l P ro c e s s o r In te rfa c e N O R / N A N D F la s h H D D / ID E / C I Copyright © 2003 Fujitsu Microelectronics Europe GmbH IR R x IR T x G P IO GPI GPO I2 C UART S m a rt C a rd PW M 7 -S e g CTRL IR Q / I2 C / S m a r t C a rd U A R T / IR In / IR O u t G P IO / 7 -S e g m e n t C tr l P W M / K e y B o a rd M o n Preliminary Page 1 of 2 Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise. January 2003 Edition 1.00 SmartMPEGTM FME/MM/PP/0103 MB87M2141 MPEG-2 Decoder for Set-Top-Boxes Worldwide Headquarters Japan Tel: +81 3 5322 3353 Fax: +81 3 5322 3386 Asia Fujitsu Limited Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg.7-1 Nishishinjuku 2-chome, Shinjuku-ku Tokyo 163-0721 Japan http://edevice.fujitsu.com/ Tel: +65 6281 0770 Fax: +65 6281 0220 Fujitsu Microelectronics Korea Ltd. 1702 Kosmo Tower, 1002 Daechi-Dong Kangnam-Gu, Seoul 135-280, Korea http://www.fmal.fujitsu.com/ http://www.fmk.fujitsu.com/ Tel: +82 2 3484 7100 Fax: +82 2 3484 7111 USA Europe Fujitsu Microelectronics America, Inc. 3545 North First Street San Jose, CA 95134-1804 USA Tel: +1 800 866 8608 Customer Response Center Fax: +1 408 922 9179 Mon-Fri: 7am-5pm (PST) http://www.fma.fujitsu.com/ Tel: +49 6103 690-0 Fax: +49 6103 690122 Tel: +1 408 922 9000 Fax: +1 408 922 9179 Fujitsu Microelectronics Asia PTE Limited #05-08, 151 Lorong Chuan New Tech Park, Singapore 556741 e-mail Fujitsu Microelectronics Europe GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany [email protected] http://www.fme.fujitsu.com/ All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Use of this product in any manner that complies with the MPEG-2 Standard is only permitted with a license under applicable patents in the MPEG-2 patent portfolio, which is available from MPEG LA, LLC, 250 Stelle Street, Suite 300, Denver, Colorado 80206, URL: www.mpegla.com. TM: SmartMPEG is a trademark of Fujitsu Microelectronics Europe GmbH 3 Copyright © 2003 Fujitsu Microelectronics Europe GmbH Preliminary Page 2 of 2 Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.