FUJITSU SEMICONDUCTOR CONTROLLER MANUAL F2MC-16LX 16-BIT MICROCONTROLLER MB90580 SERIES HARDWARE MANUAL PREFACE Thank you for selecting FUJITSU Semiconductor Devices. The FUJITSU MB90580 series has been developed as one general-application version of the F2MC®*16LX series of original 16-bit one-chip microcontrollers for ASIC (application specific IC) applications. This manual describes the functions and operations of the MB90580 series, and is intended for use by engineers actually designing products using these semiconductors. Please be sure to read it carefully. *: F2MC is an abbreviation for FUJITSU Flexible Microcontroller, and is a registered trademark of Fujitsu. This document is organized as follows. Chapter 1 OVERVIEW This section presents an overview of MB90580 series features and functions. Chapter 2 CPU This section describes the functions of the F2MC-16LX series CPU. Chapter 3 MEMORY This section describes the functions of the F2MC-16LX series memory. Chapter 4 CLOCK AND RESET This section describes the functions of the MB90580 series clocks and resets. Chapter 5 WATCHDOG TIMER, TIME BASE TIMER, AND WATCH TIMER FUNCTION This section describes the functions and operation of the MB90580 series watchdog timer, timebase timer and watch timer function. Chapter 6 LOW POWER CONTROL CIRCUIT This section describes the MB90580 series low power control circuits (CPU intermittent operation function, oscillator stabilization wait time, PLL clock multiplier function). Chapter 7 INTERRUPT This section describes the functions of each MB90580 each interrupt and interrupt source. Chapter 8 PARALLEL PORTS This section describes the functions of the MB90580 series parallel port. Chapter 9 DTP/EXTERNAL INTERRUPT This section describes the function and operation of the MB90580 series DTP and external interrupts. Chapter 10 DELAY INTERRUPT MODULE This section describes the functions and operation of the MB90580 series delay interrupt module. Chapter 11 iii Chapter 12 COMMUNICATION PRESCALER This section describes the MB90580 series communication prescaler. Chapter 13 UART This section describes the function and operation of the MB90580 UART. Chapter 14 IE BUS This section describes the functions and operation of the MB90580 series IE Bus. Chapter 15 8/16-BIT PPG This section describes the functions and operation of the MB90580 series 8/16-bit PPG. Chapter 16 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) This section describes the functions and operation of the MB90580 series 16-bit reload timer. Chapter 17 A/D CONVERTERr This section describes the functions and oeration of the MB90580 series A/D converter. Chapter 18 D/A CONVERTER This section describes the functions and oeration of the MB90580 series D/A converter Chapter 19 PULSE WIDTH COUNTER (PWC) TIMER This section describes the functions and oeration of the MB90580 series pulse width counter (PWC) timer. Chapter 20 CLOCK MONITOR FUNCTION This section describes the functions of the MB90580 series clock monitor function. Chapter 21 16-bit I/O Timers This section describes the functions and operation of the MB90580 series 16-bit I/O timers which consists of 16-bit free-run timer, 2 output compare regsiters and 4 input capture registers. Chapter 22 ROM CORRECTION module This section describes the function and operation of the MB90580 series rom correction module. Chapter 23 ROM MIRRORING MODULE This section describes the function of the MB90580 series ROM mirrorIing module. Appendix A I/O MAP The appendix A provides I/O maps, and low power mode status transition charts. Appendix B INSTRUCTION The appendix B describes addressing in the F2MC®*-16LX series, and provides instruction lists and instruction maps. Appendix C PROGRAMMING THE FLASH MEMORY ON THE MB90F584 The appendix C provides programming method of the flash memory on the MB90F584. iv CONTENTS Chapter 1 Overview ...........................................................................................................................................1 1.1 Features ..........................................................................................................................................1 1.2 Product Lineup ................................................................................................................................3 1.3 Block Diagram .................................................................................................................................4 1.4 Pin Assignment ...............................................................................................................................5 1.4.1 SQFP-100 Pin Assignment ....................................................................................................5 1.4.1 QFP-100 Pin Assignment ......................................................................................................6 1.5 Pin Functions ..................................................................................................................................7 1.6 Handling the Device ......................................................................................................................14 Chapter 2 CPU ..................................................................................................................................................15 2.1 CPU ...............................................................................................................................................15 2.1.1 Memory space .....................................................................................................................16 2.1.2 Registers .............................................................................................................................20 2.1.3 Prefix codes .........................................................................................................................28 Chapter 3 Memory ............................................................................................................................................31 3.1 Memory Access Modes .................................................................................................................31 3.1.1 Mode pins ............................................................................................................................32 3.1.2 Mode data ............................................................................................................................33 3.1.3 Bus Mode ............................................................................................................................34 3.2 External Memory Access ...............................................................................................................36 3.2.1 Block diagram ......................................................................................................................36 3.2.2 Registers and Register details .............................................................................................37 3.2.1 Operations ...........................................................................................................................42 Chapter 4 Clock and Reset ..............................................................................................................................47 4.1 Clock Generator ............................................................................................................................47 4.2 Reset Causes ................................................................................................................................48 4.3 Operation after reset release ........................................................................................................50 Chapter 5 Watchdog Timer, Timebase Timer, and Watch Timer Functions ...............................................51 5.1 Outline ...........................................................................................................................................51 5.2 Block diagram ...............................................................................................................................52 5.3 Registers and register details ........................................................................................................53 5.3.1 WDTC (Watch-Dog Timer Control Register) .......................................................................54 5.3.2 TBTC (Time Base Timer Control Register) .........................................................................56 5.3.3 Watch Timer Control Register (WTC) ..................................................................................57 5.4 Operation ......................................................................................................................................59 5.4.1 Watch-Dog Timer ................................................................................................................59 5.4.2 Time Base Timer .................................................................................................................60 5.4.3 Watch Timer ........................................................................................................................60 Chapter 6 Low Power Control Circuit .............................................................................................................61 6.1 Outline ...........................................................................................................................................61 6.2 Block Diagram ...............................................................................................................................62 6.3 Registers and register details ........................................................................................................63 6.3.1 LPMCR (Low power mode control register) ........................................................................63 6.3.2 CKSCR (Clock selection register) .......................................................................................65 6.4 Operations .....................................................................................................................................67 6.4.1 Sleep mode .........................................................................................................................68 6.4.2 Pseudo-watch mode ............................................................................................................68 MB90580 Series v 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.4.8 6.4.9 Watch mode ........................................................................................................................69 Stop mode ...........................................................................................................................69 Hardware standby mode .....................................................................................................70 CPU intermittent operation function .....................................................................................70 Setting the main clock oscillation stabilization waiting period ..............................................71 Switching the machine clock ...............................................................................................71 State transition .....................................................................................................................73 Chapter 7 Interrupt ...........................................................................................................................................81 7.1 Outline ...........................................................................................................................................81 7.2 Causes of Interrupt ........................................................................................................................82 7.3 Interrupt Vector .............................................................................................................................83 7.4 Hardware Interrupt ........................................................................................................................84 7.4.1 Overview ..............................................................................................................................84 7.4.2 Structure ..............................................................................................................................84 7.4.3 Operation .............................................................................................................................84 7.4.4 Hardware Interrupt Ocurrence When Internal Resource Is Being Accessed ......................87 7.4.5 Interrupt Inhibit Instruction ...................................................................................................87 7.4.6 Multiple Interrupts ................................................................................................................87 7.4.7 Register Saving In Stack Upon Interrupt .............................................................................87 7.4.8 Precaution in Using Hardware Interrupt ..............................................................................87 7.5 Software Interrupt ..........................................................................................................................88 7.5.1 Overview ..............................................................................................................................88 7.5.2 Structure ..............................................................................................................................88 7.5.3 Operation .............................................................................................................................89 7.5.4 Others ..................................................................................................................................89 7.6 Extended intelligent I/O service (EI2OS) .......................................................................................90 7.6.1 Overview ..............................................................................................................................90 7.6.2 Structure ..............................................................................................................................91 7.6.3 Operation .............................................................................................................................97 7.6.4 EI2OS Execution Time ........................................................................................................99 7.7 Exceptions ...................................................................................................................................100 7.7.1 Exception due to execution of an undefined instruction ....................................................100 Chapter 8 Parallel Ports .................................................................................................................................101 8.1 Outline .........................................................................................................................................101 8.2 Block Diagram .............................................................................................................................102 8.3 Registers and register details ......................................................................................................103 8.3.1 Port data register ...............................................................................................................104 8.3.2 Port direction registers .......................................................................................................105 8.3.3 Output pin register .............................................................................................................106 8.3.4 Input resistor register .........................................................................................................106 8.3.5 Analogue Input Enable Register ........................................................................................107 8.3.6 Low Noise Output Select Register .....................................................................................107 Chapter 9 DTP/External Interrupt ..................................................................................................................109 9.1 Outline .........................................................................................................................................109 9.2 Block Diagram .............................................................................................................................109 9.3 Registers and Register Details ....................................................................................................110 9.3.1 Interrupt/DTP enable register (ENIR: Enable interrupt request register) ...........................110 9.3.2 Interrupt/DTP cause register (EIRR: External interrupt request register) ..........................111 9.3.3 Request level setting register (ELVR: External level register) ...........................................111 vi MB90580 Series 9.4 Operations ...................................................................................................................................112 9.4.1 External interrupts .............................................................................................................112 9.4.2 DTP operation ...................................................................................................................113 9.4.3 Switching between external interrupt and DTP requests ...................................................114 9.5 Notes on use ...............................................................................................................................115 9.5.1 Conditions on the externally connected peripheral when DTP is used .............................115 9.5.2 Recovery from standby ......................................................................................................115 9.5.3 External interrupt/DTP operation procedure ......................................................................115 9.5.4 External interrupt request level ..........................................................................................115 Chapter 10 Delayed Interrupt Generation Module .......................................................................................117 10.1 Outline .......................................................................................................................................117 10.2 Block Diagram ...........................................................................................................................117 10.3 Registers and Register Details ..................................................................................................117 10.4 Operations .................................................................................................................................118 10.4.1 Delayed interrupt occurrence ..........................................................................................118 10.5 Notes on operation ....................................................................................................................118 10.5.1 Delayed interrupt request lock .........................................................................................118 Chapter 11 Communication Prescaler ..........................................................................................................119 11.1 Outline .......................................................................................................................................119 11.2 Block Diagram ...........................................................................................................................119 11.3 Register and Register Details ....................................................................................................120 11.3.1 Clock Division Control Registers .....................................................................................120 11.4 Operations .................................................................................................................................121 Chapter 12 UART ............................................................................................................................................123 12.1 Outline .......................................................................................................................................123 12.2 Block Diagram ...........................................................................................................................124 12.3 Register and Register Details ....................................................................................................125 12.3.1 Serial Mode Register (SMR0/1/2/3/4) ..............................................................................126 12.3.2 Serial Control Register (SCR0/1/2/3/4) ...........................................................................128 12.3.3 Serial Input Data Register (SIDR0/1/2/3/4)/ Serial Ouput Data Register (SODR0/1/2/3/4) 130 12.3.4 Serial Status Register (SSR0/1/2/3/4) .............................................................................130 12.4 Operations .................................................................................................................................132 12.4.1 Operation modes .............................................................................................................132 12.4.2 UART clock selection ......................................................................................................132 12.4.3 Asynchronous mode ........................................................................................................134 12.4.4 CLK synchronous mode ..................................................................................................135 12.4.5 Interrupt occurrence and flag set timing ..........................................................................137 12.4.6 I2OS (Intelligent I/O service) ...........................................................................................139 12.4.7 Notes on use ..................................................................................................................139 12.4.8 Application .......................................................................................................................139 Chapter 13 IE Bus ...........................................................................................................................................141 13.1 Outline .......................................................................................................................................141 13.2 Block Diagram ...........................................................................................................................142 13.3 Registers and Register Details ..................................................................................................143 13.3.1 Command register upper byte (CMRH) ...........................................................................146 13.3.2 Command register lower byte (CMRL) ............................................................................148 13.3.3 Unit address register (MAWH, MAWL) ............................................................................150 13.3.4 Slave address register (SAWH, SAWL) ..........................................................................150 13.3.5 Mutliaddress, control bit set register (DCWR) .................................................................151 MB90580 Series vii 13.3.6 Telegraph length set register (DEWR) ............................................................................152 13.3.7 Status register upper byte (STRH) ..................................................................................153 13.3.8 Status register lower byte (STRL) ...................................................................................155 13.3.9 Lock read register (LRRH, LRRL) ...................................................................................157 13.3.10 Master address read register (MARH, MARL) ...............................................................158 13.3.11 Multiaddress, control bit read register (DCRR) ..............................................................159 13.3.12 Telegraph length read register (DERR) .........................................................................160 13.3.13 Read data buffer (RDB) .................................................................................................161 13.3.14 Write data buffer (WDB) ................................................................................................162 13.4 IEBus Communication Protocol ................................................................................................163 13.4.1 Overview ..........................................................................................................................163 13.4.2 Determining bus mastership (arbitration) ........................................................................164 13.4.3 Communication mode ......................................................................................................164 13.4.4 Communication address ..................................................................................................165 13.4.5 Multiaddress communication ...........................................................................................165 13.4.6 Transfer protocol .............................................................................................................166 13.4.7 Transmit data ...................................................................................................................170 13.4.8 Bit format .........................................................................................................................173 13.5 Operation ..................................................................................................................................174 13.5.1 IEBus control ...................................................................................................................174 13.5.2 Communication status .....................................................................................................177 13.5.3 Program flow example for IEBus controller .....................................................................179 13.5.4 Timing Diagram of Multiple Frame Transmission ............................................................186 13.5.5 Timing diaram of transmission data when an error is generated .....................................188 Chapter 14 8/16-Bit PPG ................................................................................................................................191 14.1 Outline .......................................................................................................................................191 14.2 Block Diagram ...........................................................................................................................192 14.3 Registers and Register Details ..................................................................................................194 14.3.1 PPG0 operation mode control register (PPGC0) ............................................................195 14.3.2 PPG1 operation mode control register (PPGC1) .............................................................197 14.3.3 PPG0, 1 output pin control register (PPGOE) .................................................................199 14.3.4 Reload register (PRLL/PRLH ) ........................................................................................200 14.4 Operations .................................................................................................................................201 Chapter 15 16-Bit Reload Timer (with Event Count Function) ...................................................................207 15.1 Outline .......................................................................................................................................207 15.2 Block Diagram ...........................................................................................................................208 15.3 Registers and Register Details ..................................................................................................209 15.3.1 Timer control status register (TMCSR) ............................................................................210 15.3.2 TMR (16-bit timer register)/TMRLR (16-bit reload register) .............................................213 15.4 Operation ..................................................................................................................................214 15.4.1 Internal clock operation ...................................................................................................214 15.4.2 Underflow operation ........................................................................................................215 15.4.3 Input pin functions (for internal clock mode) ....................................................................216 15.4.4 External event counter .....................................................................................................216 15.4.5 Output pin functions .........................................................................................................217 15.4.6 Intelligent I/O service (I2OS) function and interrupts .......................................................217 15.4.7 Counter operation state ...................................................................................................218 Chapter 16 A/D Converter ..............................................................................................................................219 16.1 Outline .......................................................................................................................................219 16.2 Block Diagram ...........................................................................................................................220 viii MB90580 Series 16.3 Registers and Register Details ..................................................................................................221 16.3.1 Control status registers (ADCS1 and ADCS2) ................................................................222 16.3.2 ADCR1 and ADCR0 (Data registers) ..............................................................................226 16.4 Operations .................................................................................................................................228 16.5 Notes on use .............................................................................................................................234 16.5.1 Other considerations ......................................................................................................234 Chapter 17 D/A Converter ..............................................................................................................................235 17.1 Outline .......................................................................................................................................235 17.2 Block Diagram ...........................................................................................................................236 17.3 Registers and Register Details ..................................................................................................237 17.3.1 DAT0/1 ( D/A data register) .............................................................................................238 17.3.2 DACR0/1 ( D/A control register) ......................................................................................238 17.4 Operations .................................................................................................................................239 Chapter 18 Pulse Width Counter (PWC) Timer ............................................................................................241 18.1 Outline .......................................................................................................................................241 18.2 Block Diagram ...........................................................................................................................242 18.3 Regiaters and Register Details ..................................................................................................243 18.3.1 PWC control status register (PWCSR) ............................................................................244 18.3.2 PWC data buffer register (PWCR) ...................................................................................249 18.3.3 Divide Ratio Control Register (DIVR) ..............................................................................250 18.3.4 PWC noise cancelling register (RNCR) ...........................................................................251 18.4 Operations .................................................................................................................................252 18.5 Precautions ...............................................................................................................................265 Chapter 19 Clock Monitor Function ..............................................................................................................267 19.1 Outline .......................................................................................................................................267 19.2 Block Diagram ...........................................................................................................................267 19.3 Registers and Register Details ..................................................................................................268 19.3.1 Clock output enable register (CLKR) ...............................................................................268 Chapter 20 16-Bit I/O Timer ...........................................................................................................................269 20.1 Outline .......................................................................................................................................269 20.2 Block Diagram ...........................................................................................................................271 20.2.1 Overall Block Diagram of 16-bit I/O Timer .......................................................................271 20.2.2 Block Diagram of 16-bit free-run timer .............................................................................272 20.2.3 Block Diagram of Output Comparison .............................................................................272 20.2.4 Block Diagram of Input Capture ......................................................................................273 20.3 Registers and Register Details ..................................................................................................274 20.3.1 16-bit free-run timer .........................................................................................................274 20.3.2 Output comparison ..........................................................................................................278 20.3.3 Input capture ....................................................................................................................282 20.4 Operations .................................................................................................................................285 20.4.1 16-bit free-run timer .........................................................................................................285 20.4.2 16-bit output compare ......................................................................................................286 20.4.3 16-bit input capture ..........................................................................................................287 20.5 Timing .......................................................................................................................................288 20.5.1 16-bit free-run timer count timing .....................................................................................288 20.5.2 Output compare timing ....................................................................................................289 20.5.3 Input capture input timing ................................................................................................290 Chapter 21 ROM Correction Module .............................................................................................................291 21.1 Outline .......................................................................................................................................291 MB90580 Series ix 21.2 Block Diagram ...........................................................................................................................291 21.3 Registers and Register Details ..................................................................................................292 21.3.1 Program Address Detect Register 0/1 (PADR0/PADR1) ................................................292 21.3.2 Program Address detect Control Status Register (PACSR) ............................................293 21.4 Operations .................................................................................................................................294 21.5 Application Example ..................................................................................................................295 Chapter 22 ROM Mirroring Module ...............................................................................................................299 22.1 Outline .......................................................................................................................................299 22.2 Block Diagram ...........................................................................................................................299 22.3 Registers and Register Details ..................................................................................................300 22.3.1 ROM Mirror Function Select Register ..............................................................................300 Appendix A I/O Map........................................................................................................................................ 303 A.1 I/O Map .......................................................................................................................................303 Appendix B Instructions ................................................................................................................................ 309 B.1 Addressing ..................................................................................................................................309 B.1.1 Effective address field .......................................................................................................309 B.1.2 Addressing Details ............................................................................................................310 B.2 Instruction Set .............................................................................................................................314 B.2.1 F2MC-16LX Instruction Set (351 Instructions) ..................................................................320 B.3 Instruction Map ...........................................................................................................................334 B.3.1 Basic Page Map ................................................................................................................336 Appendix C The Flash Memory in the MB90F583........................................................................................ 357 C.1 Outline ........................................................................................................................................357 C.2 Sector Structure of 1M Bit Flash Memory ...................................................................................358 C.3 Flash Control Register (FMCS) ..................................................................................................359 C.4 Automatic Algorithm Initiation Method ........................................................................................361 C.5 Automatic Algorithm Execution Status .......................................................................................362 C.5.1 Data polling flag (DQ7) .....................................................................................................363 C.5.2 Toggle bit flag (DQ6) .........................................................................................................364 C.5.3 Exceeded timing limits flag (DQ5) .....................................................................................365 C.5.4 Sector erase timer flag (DQ3) ...........................................................................................366 C.6 Notes on Flash Memory Program/Erase ....................................................................................367 C.6.1 Read/reset status ..............................................................................................................367 C.6.2 Data Programming ............................................................................................................368 C.6.3 Chip Erase ........................................................................................................................370 C.6.4 Sector Erase .....................................................................................................................370 C.6.5 Suspend Sector Erase ......................................................................................................372 C.6.6 Resume Sector Erase .......................................................................................................372 x MB90580 Series FIGURES Chapter 1 Overview ............................................................................................................................................1 Figure 1.3a Block Diagram of MB90580 Series .................................................................................... 4 Figure 1.4a Pin Assignment of MB90580 (LQFP-100).......................................................................... 5 Figure 1.4b Pin Assignment of MB90580 (QFP-100)............................................................................ 6 Figure 1.6a Using external clock ......................................................................................................... 14 Figure 1.6b Connection of Power pins ................................................................................................ 14 Chapter 2 CPU ..................................................................................................................................................15 Figure 2.1.1a Sample relationship between F2MC-16LX system and memory map .......................... 16 Figure 2.1.1b Sample linear addressing.............................................................................................. 17 Figure 2.1.1c Physical addresses of each space ................................................................................ 18 Figure 2.1.1d Sample allocation of multi-byte data in memory ........................................................... 19 Figure 2.1.1e Execution of MOVW A, 080FFFFH ............................................................................... 19 Figure 2.1.2a Special registers............................................................................................................ 20 Figure 2.1.2b General-purpose registers ............................................................................................ 21 Figure 2.1.2c Program counter............................................................................................................ 21 Figure 2.1.2d 32-bit data transfer ........................................................................................................ 22 Figure 2.1.2e AL-AH transfer .............................................................................................................. 22 Figure 2.1.2f Stack manipulation instruction and stack pointer ........................................................... 23 Figure 2.1.2g PS structure .................................................................................................................. 24 Figure 2.1.2h Condition code register configuration............................................................................ 24 Figure 2.1.2i Register bank pointer ..................................................................................................... 25 Figure 2.1.2j Interrupt level register..................................................................................................... 25 Figure 2.1.2k Generating a physical address in direct addressing mode............................................ 27 Figure 2.1.3a Interrupt disable instruction ........................................................................................... 29 Figure 2.1.3b Interrupt disable instructions and prefix codes.............................................................. 30 Figure 2.1.3c Consecutive prefix codes .............................................................................................. 30 Chapter 3 Memory ............................................................................................................................................31 Figure 3.1.3a Access areas and physical addresses in each bus mode............................................. 34 Figure 3.2.1a External bus pin control circuit ...................................................................................... 36 Figure 3.2.1a External memory access timing chart ........................................................................... 42 Figure 3.2.1b External memory access timing chart ........................................................................... 43 Figure 3.2.1c Ready timing chart ........................................................................................................ 44 Figure 3.2.1d Hold timing .................................................................................................................... 45 Chapter 4 Clock and Reset ..............................................................................................................................47 Figure 4.1a Clock generator circuit block diagram .............................................................................. 47 Figure 4.2a Reset cause bit block diagram ......................................................................................... 49 Figure 4.2b WDTC (watch-dog timer control register)......................................................................... 49 Figure 4.3a Source and destination of reset vector and mode data.................................................... 50 MB90580 Series xi Chapter 5 Watchdog Timer, Timebase Timer, and Watch Timer Functions ...............................................51 Figure 5.2a Watchdog Timer, Timebase Timer, and Watch Timer Block Diagram ............................. 52 Figure 5.4.1a Watch-dog timer operation............................................................................................ 59 Chapter 6 Low Power Control Circuit .............................................................................................................61 Figure 6.2a Low-power consumption control circuit and clock generator ........................................... 62 Figure 6.4.8a Clock Selection State Transition Diagram (1) ............................................................... 72 Figure 6.4.8b Clock Selection State Transition Diagram (2) ............................................................... 73 Figure 6.4.9a Low Power Consumption Mode Transition Diagram A ................................................. 77 Figure 6.4.9b Low Power Consumption Mode Transition Diagram B ................................................. 78 Figure 6.4.9c Low Power Consumption Mode Transition Diagram C ................................................. 79 Figure 6.4.9d Low Power Consumption Mode Transition Diagram D ................................................. 80 Chapter 7 Interrupt ...........................................................................................................................................81 Figure 7.4.3a Occurrence and release of hardware interrupt ............................................................. 85 Figure 7.4.3b Hardware interrupt operation flow ................................................................................. 86 Figure 7.4.7a Registers saved in stack ............................................................................................... 87 Figure 7.5.3a Occurrence and release of software interrupt .............................................................. 89 Figure 7.6.1a Outline of extended intelligent I/O service .................................................................... 90 Figure 7.6.2a Extended intelligent I/O service descriptor configuration ............................................ 94 Figure 7.6.3a EI2OS operation flow .................................................................................................... 97 Figure 7.6.3b EI2OS use flow ............................................................................................................. 98 Chapter 8 Parallel Ports .................................................................................................................................101 Figure 8.2a Block diagram of I/O port ............................................................................................... 102 Figure 8.2b Block diagram of input resistor register.......................................................................... 102 Figure 8.2c Block diagram of Output pin register .............................................................................. 102 Figure 8.3a Registers of Parallel Ports ............................................................................................. 103 Chapter 9 DTP/External Interrupt ..................................................................................................................109 Figure 9.2a Block diagram of DTP/External Interrupt ....................................................................... 109 Figure 9.4.1a External interrupt......................................................................................................... 112 Figure 9.4.2a Timing to cancel the external interrupt at the end of DTP operation........................... 113 Figure 9.4.2b Sample interface to the external peripheral ................................................................ 113 Figure 9.4.3a Switching between external interrupt and DTP requests ............................................ 114 Figure 9.5.4a Clearing the cause hold circuit upon level set............................................................. 115 Figure 9.5.4b Interrupt cause and interrupt request to the interrupt controller while interrupts are enabled ........................................................................................................................ 115 Chapter 10 Delayed Interrupt Generation Module .......................................................................................117 Figure 10.2a Block diagram of Delayed Interrupt Generation Module .............................................. 117 Figure 10.4.1a Delayed interrupt issuance ....................................................................................... 118 Chapter 11 Communication Prescaler ..........................................................................................................119 Figure 11.2a Block diagram of Communication Prescaler ................................................................ 119 xii MB90580 Series Chapter 12 UART ............................................................................................................................................123 Figure 12.2a Block diagram of UART................................................................................................ 124 Figure 12.3a Registers of UART ....................................................................................................... 125 Figure 12.4.3a Transfer data format (modes 0 and 1) ...................................................................... 134 Figure 12.4.4a Transfer data format (mode 2) .................................................................................. 135 Figure 12.4.5a Timing to set PE, ORE, FRE, and RDRF (mode 0) .................................................. 137 Figure 12.4.5b Timing to set ORE, FRE, and RDRF (mode 1) ......................................................... 137 Figure 12.4.5c Timing to set ORE and RDRF (mode 2).................................................................... 138 Figure 12.4.5d Timing to set TDRE (modes 0 and 1)........................................................................ 138 Figure 12.4.5e Timing to set TDRE (mode 2) ................................................................................... 138 Figure 12.4.8a Sample system configuration in mode 1 ................................................................... 139 Figure 12.4.8b Flow chart of communication in mode 1.................................................................... 140 Chapter 13 IE Bus ...........................................................................................................................................141 Figure 13.2a Block Diagram of IE Bus .............................................................................................. 142 Figure 13.3a Registers of IE BUS (1/3)............................................................................................ 143 Figure 13.3b Registers of IE BUS (2/3)............................................................................................. 144 Figure 13.3c Registers of IE BUS (3/3) ............................................................................................. 145 Figure 13.5.4a When setting ‘1’ on WDBC (Master side of master transmission) ............................ 186 Figure 13.5.4b When setting ‘0’ on WDBC (Master side of master transmission) ............................ 187 Figure 13.5.5a Error happened on the Slave side when master transmission.................................. 188 Figure 13.5.5b Error happened on the Master side when master transmission................................ 189 Chapter 14 8/16-Bit PPG ................................................................................................................................191 Figure 14.2a 8-bit PPG ch0 block diagram ....................................................................................... 192 Figure 14.2b 8-bit PPG ch1 block diagram ....................................................................................... 193 Figure 14.3a Registers of 8/16-bit PPG ............................................................................................ 194 Figure 14.4a PPG output operation, output waveform ...................................................................... 202 Figure 14.4b 8+8 PPG output operation waveform........................................................................... 203 Figure 14.4c Write timing chart ......................................................................................................... 205 Figure 14.4d PRL write operation block diagram .............................................................................. 205 Chapter 15 16-Bit Reload Timer (with Event Count Function) ...................................................................207 Figure 15.2a Block Diagram of 16-Bit Reload Timer......................................................................... 208 Figure 15.3a Registers of 16-Bit Reload Timer ................................................................................. 209 Figure 15.3.1a Timer Control Status Register................................................................................... 210 Figure 15.3.2a 16-Bit Timer Register and 16-Bit Reload Register .................................................... 213 Figure 15.4.1a Counter Activation and Operation ............................................................................. 214 Figure 15.4.2a Underflow Operation ................................................................................................. 215 Figure 15.4.3a Trigger Input Operation ............................................................................................. 216 Figure 15.4.3b Gate Input Operation ................................................................................................ 216 Figure 15.4.5a Output Pin Functions (1) ........................................................................................... 217 Figure 15.4.5b Output Pin Functions (2) ........................................................................................... 217 MB90580 Series xiii Figure 15.4.7a Counter State Transitions ......................................................................................... 218 Chapter 16 A/D Converter ..............................................................................................................................219 Figure 16.2a Block Diagram of A/D converter................................................................................... 220 Figure 16.3a Registers of A/D Converter .......................................................................................... 221 Figure 16.3.1a Control Status Registers ........................................................................................... 222 Figure 16.3.2a Data Registers .......................................................................................................... 226 Figure 16.4a Flow chart of A/D Conversion ...................................................................................... 229 Figure 16.4b Flow Chart of Data Protection Function ....................................................................... 233 Chapter 17 D/A Converter ..............................................................................................................................235 Figure 17.2a Block Diagram of D/A Cobverter .................................................................................. 236 Figure 17.3a Register of D/A Converter ............................................................................................ 237 Chapter 18 Pulse Width Counter (PWC) Timer ............................................................................................241 Figure 18.2a lock Diagram of Pulse Width Counter Timer ................................................................ 242 Figure 18.3a Register of Pulse Width Counter Timer ....................................................................... 243 Figure 18.4a Timer Operation (Single-Shot Mode) ........................................................................... 252 Figure 18.4b Timer Operation (Reload Mode) .................................................................................. 252 Figure 18.4c Pulse Width Count Operation (Single-Shot Count Mode, "H" Width Count Mode) ...... 253 Figure 18.4d Pulse Width Count Operation (Continuous Count Mode, "H" Width Count Mode) ...... 253 Figure 18.4e Operation Mode Selection ........................................................................................... 255 Figure 18.4f Flowchart of Timer Mode Operation ............................................................................. 259 Figure 18.4g Flowchart of Operation in Pulse Width Count Mode .................................................... 264 Chapter 19 Clock Monitor Function ..............................................................................................................267 Figure 19.2a Block Diagram of Clock Monitor Function ................................................................... 267 Figure 19.3a Registers of Clock Monitor Function ............................................................................ 268 Chapter 20 16-Bit I/O Timer ...........................................................................................................................269 Figure 20.2.1a Overall Block diagram of 16-bit I/O Timer ................................................................. 271 Figure 20.2.2a Block diagram of 16-bit free-run timer....................................................................... 272 Figure 20.2.3a Block diagram of Output Comparison ....................................................................... 272 Figure 20.2.4a Block diagram of Input Capture ................................................................................ 273 Figure 20.3.1a Registers of 16-bit free-run timer .............................................................................. 274 Figure 20.3.2a Registers of output comparsion ................................................................................ 278 Figure 20.3.3a Register of input capture ........................................................................................... 282 Chapter 21 ROM Correction Module .............................................................................................................291 Figure 21.2a Block Diagram of ROM Correction Module .................................................................. 291 Figure 21.3a Registers of ROM Correction Module .......................................................................... 292 Figure 21.5a System Structure Example ......................................................................................... 295 Figure 21.5b ROM Correction Processing Example ......................................................................... 296 Figure 21.5c ROM Correction Processing Flow Diagram ................................................................. 297 Chapter 22 ROM Mirroring Module ...............................................................................................................299 xiv MB90580 Series Figure 22.2a Block Diagram of ROM Mirroring Module .................................................................... 299 Figure 22.3a Register of ROM Mirroring Module .............................................................................. 300 Figure 22.3b Memory in Single Chip Mode ....................................................................................... 301 Figure 22.3c Memory in Internal ROM External Bus Mode............................................................... 301 Appendix A I/O Map ........................................................................................................................................303 Appendix B Instructions ................................................................................................................................309 Fig. B.1.2a Register List Configuration ..............................................................................................312 Fig. B.3a Structure of F2MC-16LX Instruction Map........................................................................... 334 Fig. B.3b Correspondence between Actual Instructions and the Instruction Maps ........................... 335 Appendix C The Flash Memory in the MB90F583 ........................................................................................357 Figure C.2a Sector structure of 1M bit flash memory....................................................................... 358 Figure C.3a Timing of RDYINT and RDY.......................................................................................... 360 Figure C.6.2a Example flowchart of progamming the flash memory .................................................369 Figure C.6.4a Example flowchart of erasing flash memory ...............................................................371 MB90580 Series xv xvi MB90580 Series TABLES Chapter 1 Overview ............................................................................................................................................1 Table 1.2a MB90580 series product lineup ....................................................................................3 Table 1.5a Pin functions (1/4) Table 1.5b Pin functions (2/4) .........................................................................................................8 Table 1.5c Pin functions (3/4) .........................................................................................................9 Table 1.5d Pin functions (4/4) .......................................................................................................10 Table 1.5e I/O circuit format (1) ....................................................................................................11 Table 1.5f I/O circuit format (2) ....................................................................................................12 Table 1.5g I/O circuit format (3) ....................................................................................................13 (STBC: With standby control) ......................................................7 Chapter 2 CPU ..................................................................................................................................................15 Table 2.1.1a Default space ..............................................................................................................18 Table 2.1.2a Levels indicated by the interrupt level mask (ILM) register .........................................25 Table 2.1.2b Register functions ......................................................................................................26 Table 2.1.2c Relationship between registers ...................................................................................26 Table 2.1.3a Bank select prefix .......................................................................................................28 Chapter 3 Memory ............................................................................................................................................31 Table 3.1a Memory Access Mode ................................................................................................31 Table 3.1.1a Mode pins and modes ................................................................................................32 Table 3.1.3a Sample recommended setting of mode pins and mode data .....................................35 Table 3.1.3b Modes and related external pin operations .................................................................35 Table 3.2.0a Selecting the high-order address bit output control ....................................................39 Chapter 4 Clock and Reset ..............................................................................................................................47 Table 4.2a Reset causes ..............................................................................................................48 Table 4.2b Reset cause bits .........................................................................................................49 Chapter 5 Watchdog Timer, Timebase Timer, and Watch Timer Functions ...............................................51 Table 5.3.1a Reset cause registers .................................................................................................54 Table 5.3.1b Watchdog Timer Interval Selection Bits ......................................................................55 Table 5.3.2a Selecting the time base timer interval .........................................................................56 Table 5.3.3a Watch Timer Interval Selection ...................................................................................58 Chapter 6 Low Power Control Circuit .............................................................................................................61 Table 6.3.1a CG Bit Setting .............................................................................................................64 Table 6.3.2a WS Bit Settings ...........................................................................................................65 Table 6.3.2b CS Bit Settings ............................................................................................................66 Table 6.4a Low Power Consumption Mode Operating Statuses ..................................................67 Table 6.4.9a List of Transition Conditions .......................................................................................74 Chapter 7 Interrupt ...........................................................................................................................................81 Table 7.2a MB90580 Series Interrupt causes, interrupt vectors, and interrupt control registers .............................82 xvii Table 7.3a MB90580 interrupt assignment table (1/2) ..................................................................83 Table 7.4.3a Compensation values for interrupt processing cycle count ........................................86 Table 7.6.2a ICS bits, channel numbers, and descriptor addresses ...............................................92 Table 7.6.2b S bits and end conditions ............................................................................................92 Table 7.6.2c Interrupt level setting bits and interrupt levels ............................................................93 Table 7.6.4a Execution time when the extended I2OS continues ...................................................99 Table 7.6.4b Data transfer compensation values for extended I2OS execution time ......................99 Chapter 8 Parallel Ports .................................................................................................................................101 Chapter 9 DTP/External Interrupt ..................................................................................................................109 Chapter 10 Delayed Interrupt Generation Module .......................................................................................117 Chapter 11 Communication Prescaler ..........................................................................................................119 Chapter 12 UART ............................................................................................................................................123 Table 12.4.1a UART operation modes ............................................................................................132 Table 12.4.2a Baud rate (f indicates the machine clock.) ................................................................132 Table 12.4.2b Baud rates and reload values ...................................................................................133 Chapter 13 IE Bus ...........................................................................................................................................141 Table 13.3.1a Transmission mode ..................................................................................................146 Table 13.3.1b Setting for GOTM and GOTS ...................................................................................147 Table 13.3.2a Interval for the occurrence of data transmit interrupt ................................................148 Table 13.3.2b Interval for the occurrence of data transmit interrupt ................................................148 Table 13.3.2c Interval for the occurrence of data transmit interrupt ................................................148 Table 13.3.2d Internal clock frequency ............................................................................................149 Table 13.3.5a Control bits setting ....................................................................................................151 Table 13.3.6a Number of transmit data bytes setting ......................................................................152 Table 13.3.8a Status flag .................................................................................................................156 Table 13.3.13a Time Required for next data receive after receive buffer full interrupt occurred ......161 Table 13.3.14a Data write time after WDB empty interrupt ...............................................................162 Table 13.4.1a IEBus transfer rates ..................................................................................................163 Table 13.4.3a Transfer rate and maximum number of transfer byte in each communication mode 164 Table 13.4.6a Number of transmit data bytes setting ......................................................................167 Table 13.4.7a Control bits setting ....................................................................................................170 Table 13.4.7b The control command that can be executed by a locked slave unit .........................170 Table 13.4.7c Meaning of Slave Status ...........................................................................................171 Table 13.5.1a Time required to write transmit data to WDB after transmit interrupt has occurred .175 Table 13.5.2a Meaning of status code ST3-0 for master, slave transmit ........................................177 Table 13.5.2b Meaning of status code ST3-0 for master receive ....................................................177 Table 13.5.2c Meaning of status code ST3-0 for slave receive .......................................................178 Table 13.5.2d Meaning of status code ST3-0 for multiaddress receive ...........................................178 Chapter 14 8/16-Bit PPG ................................................................................................................................191 xviii MB90580 Series Table 14.4a Reload operation and pulse output ...........................................................................201 Chapter 15 16-Bit Reload Timer (with Event Count Function) ...................................................................207 Chapter 16 A/D Converter ..............................................................................................................................219 Chapter 17 D/A Converter ..............................................................................................................................235 Table 17.4a Theoretical values of D/A converter output voltages ................................................239 Chapter 18 Pulse Width Counter (PWC) Timer ............................................................................................241 Table 18.4a Count Clock Selection ..............................................................................................254 Table 18.4b Start and Stop Bit Functions .....................................................................................256 Table 18.4c Operating State Indicator Bit Functions ....................................................................256 Table 18.4d Count Clock and Period ............................................................................................258 Table 18.4e Count Input Pin Selection (n = 3 to 0) .......................................................................260 Table 18.4f Count Modes ............................................................................................................261 Table 18.4g Pulse Width Count Range ........................................................................................263 Chapter 19 Clock Monitor Function ..............................................................................................................267 Chapter 20 16-Bit I/O Timer ...........................................................................................................................269 Chapter 21 ROM Correction Module .............................................................................................................291 Chapter 22 ROM Mirroring Module ...............................................................................................................299 Appendix A I/O Map ........................................................................................................................................303 Table A.1a I/O map ...........................................................................................................................303 Appendix B Instructions ................................................................................................................................309 Table B.1.1a Effective Address Field .............................................................................................309 Table B.2a Table B.2b Table B.2c Table B.2d Table B.2e Table B.2.1a Explanation of Items in Table of Instructions ............................................................314 Explanation of Symbols in Table of Instructions .......................................................316 Effective Address Fields ...........................................................................................317 Number of Execution Cycles for Each Form of Addressing ......................................318 Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles ............................................................................................................318 Compensation Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles ..............................................................................................319 Transfer Instructions (Byte) (41 Instructions) ............................................................320 Table B.2.1b Transfer Instructions (Word/Long-Word) (38 Instructions) .......................................321 Table B.2.1c Addition and Subtraction Instructions (Byte/Word/Long-Word) (42 Instructions) .....322 Table B.2.1d Increment and Decrement Instructions (Byte/Word/Long-Word) (12 Instructions) ...323 Table B.2.1e Compare Instructions (Byte/Word/Long-Word) (11 Instructions) ..............................323 Table B.2.1f Unsigned Multiplication and Division Instructions (Word/Long-Word) (11 Instructions) 324 Table B.2.1g Signed Multiplication and Division Instructions (Word/Long-Word) (11 Instructions) 325 Table B.2.1h Logical 1 Instructions (Byte/Word) (39 Instructions) .................................................326 Table B.2.1i Logical 2 Instructions (Long-Word) (6 Instructions) ..................................................327 Table B.2.1j Sign Inversion Instructions (Byte/Word) (6 Instructions) ...........................................327 Table B.2f MB90580 Series xix Table B.2.1k Normalize Instruction (Long-Word) (1 Instruction) ....................................................327 Table B.2.1l Shift Instructions (Byte/Word/Long-Word) (18 Instructions) .....................................328 Table B.2.1m Branch 1 Instructions (31 Instructions) .....................................................................329 Table B.2.1n Branch 2 Instructions (19 Instructions) .....................................................................330 Table B.2.1o Other Control Instructions (Byte/Word/Long-Word) (36 Instructions) .......................331 Table B.2.1p Bit Manipulation Instructions (22 Instructions) ..........................................................332 Table B.2.1q Accumulator Manipulation Instructions (Byte/Word) (6 Instructions) ........................333 Table B.2.1r String Instructions (10 Instructions) ..........................................................................333 Table B.3.1a Basic Page Map ........................................................................................................336 Table B.3.1b Bit Manipulation Instruction Map (First byte = 6 CH) ................................................337 Table B.3.1c Character String Manipulation Instruction Map (First byte = 6EH) ...........................338 Table B.3.1d Two-byte Instruction Map (First byte = 6FH) ............................................................339 Table B.3.1e “ea” Instructions 1 (First byte = 70H) ........................................................................340 Table B.3.1f “ea” Instructions 22 (First byte = 71H) ......................................................................341 Table B.3.1g “ea” Instructions 3 (First byte = 72H) ........................................................................342 Table B.3.1h “ea” Instructions 4 (First byte = 73H) ........................................................................343 Table B.3.1i “ea” Instructions 5 (First byte = 74H) ........................................................................344 Table B.3.1j “ea” Instructions 6 (First byte = 75H) ........................................................................345 Table B.3.1k “ea” Instructions 7 (First byte = 76H) ........................................................................346 Table B.3.1l “ea” Instructions 8 (First byte = 77H) ........................................................................347 Table B.3.1m “ea” Instructions 9 (First byte = 78H) .......................................................................348 Table B.3.1n MOVEA RWi, ea (First byte = 79H) ..........................................................................349 Table B.3.1o MOV Ri, ea (First byte = 7AH) ..................................................................................350 Table B.3.1p MOVW RWi, ea (First byte = 7BH) ...........................................................................351 Table B.3.1q MOV ea, Ri (First byte = 7CH) ..................................................................................352 Table B.3.1r MOVW ea, RWi (First byte = 7DH) ...........................................................................353 Table B.3.1s CH Ri, ea (First byte = 7EH) .....................................................................................354 Table B.3.1t XCHW RWi, ea (First byte = 7FH) ............................................................................355 Appendix C The Flash Memory in the MB90F583 ........................................................................................357 Table C.4a Command Sequence Definitions ....................................................................................361 Table C.5a Hardware sequence flag’s bit assignment ......................................................................362 Table C.5b Hardware Sequence Flag ...............................................................................................362 xx Table C.5.1a Status Change of data polling flag (DQ7) .................................................................363 Table C.5.2a Status Change of toggle bit flag (DQ6) .....................................................................364 Table C.5.3a Status Change of exceeded timing limits flag (DQ5) ................................................365 Table C.5.4a Status Change of sector erase tomer flag (DQ3) .....................................................366 MB90580 Series Chapter 1: Overview The MB90580 series 16-bit microcontrollers are designed for applications that require high-speed real-time processing. These microcontrollers feature functions that are suitable for controlling car audio and electronic appliances. 1.1 Features • Clock Embedded PLL Clock Multiplication Circuit Operating clock (PLL clock) can e selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz). Minimum instruction execution time of 83.3ns (at oscillation of 4 MHz, three times the PLL clock, operation at Vcc of 5.0 V) • CPU addressing space of 16 Mbytes Internal addressing of 24-bit External accessing can be performed by selecting 8/16-bit bus width (external bus mode) • Instruction set optimized for controller applications Rich data types (bit, byte, word, long word) Rich addressing mode (23 types) High code efficiency Enhanced precision calculation realized by the 32-bit accumulatorInstruction set designed for high level language (C) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions • Enhanced execution speed 4-byte instruction queue • Enhanced interrupt function 8 levels, 32 factors • Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI 2OS) • Low-power consumption (stand-by) mode Sleep mode (mode in which CPU operating clock is stopped) Timebase timer mode (mode in which other than oscillation and timebase timer are stopped) Stop mode (mode in which oscillation is stopped) CPU intermittent operation mode Hardware stand-by mode • I/O port Maximum of 77 ports • IE Bus :1 channels small scale two-line serial bus interface for automotive and general industrial application Maximium transfer rate is 27 Kbps 1.1 Features • Timers 18-bit Timebase counter/watchdog timer: 1 channel Watch-dog timer : 1 channel 15-bit Watch timer : 1 channel 8/16-bit PPG timer: 8-bit × 2 channels or 16-bit × 1 channel 16-bit re-load timer: 3 channels 16-bit PWC timer (with noise filter) : 1 channel 16-bit I/O timer (16-bit free-run timer): 1 channel • Input capture (ICU) : 4 channels Generates an interrupt request by latching a 16-bit free-run timer counter value upon detection of an edge input to the pin. • Output compare (OCU) : 2 channels Generates an interrupt request and reverse the output level upon detection of a match between the 16-bit free-run timer counter value and the compare setting value. • UART : 5 channels With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selectively used. • TP/external interrupt circuit : 8 channels A module for starting extended intelligent I/O service (EI2OS) and generating an external interrupt triggered by an external input. • Delayed interrupt generation module Generates an interrupt request for switching tasks. • Clock monitor function Output the clock to I/O port (Dividing the machine clock by 2 to 28. • ROM correction module Replace the internal ROM code by small external circuit. • ROM mirroring module Used to increase the coding efficiency. • 10-bit A/D converter : 8 channels 10-bit resolution can be selectively used. Starting by an external trigger input. • 8-bit D/A converter : 2 independent channels 8-bit resolution. R-2R typet. • Package LQFP-100, QFP-100 • Process CMOS technology 2 Chapter 1: Overview MB90580 series 1.2 Product Lineup 1.2 Product Lineup Internal Configuration Table 1.2a lists the product lineup of the MB90580 series. All products are functionally identical except for ROM and RAM sizes. Table 1.2a MB90580 series product lineup MB90V580 MB90583 MB90F583 ROM size ______ Mask ROM 128 Kbytes Flash ROM 128 Kbytes RAM size 6kByte 6kByte 6kByte Others Note: MB90V580 is the evaluation device of MB90580 series, that has no internal ROM incorporated. However it has 6Kbytes of internal RAM and the internal resources. The package of MB90V580 is PGA-256C-A02. MB90580 series Chapter 1: Overview 3 1.3 Block Diagram 1.3 Block Diagram X0,X1 X0A,X1A 4 TX P20-27/A16-23 P30/ALE P31/RDX P32/WRLX P33/WRHX P34/HRQ P35/HAKX P36/RDY P37/CLK Reset Circuit (Watch-dog timer) RSTX Hardware Standby circuit HSTX Timebase timer 8 CMOS I/O PORT 0, 1, 2, 3 P00-07/AD00-07 F2MC-16LX series core IEBUS™ Controller RX P10-17/AD08-15 CPU Clock control circuit 8 8 Delayed Interrupt generator Interrupt controller External Bus Interface 3 PA0-2 CMOS I/O PORT A I/O timer P90/TIN0/IN0 16-bit OCU x 2 channels P91/TIN1/IN1 P40/SIN0 P41/SOT0 P42/SCK0 Communication prescaler x 5 CMOS I/O PORT 4 and 5 P43/SIN1 P44/SOT1 P45/SCK1 P46/ADTG6 P47 P50/AN0/SIN3 P51/AN1/SOT3 P52/AN2/SCK3 P53/AN3 UART x 5 channels F2MC-16LX BUS 16-bit ICU x 4 channels P92/TIN2/IN2 16-bit free-run timer P93/TOT0/IN3 16-bit reload timer x 3 channels P94/TOT1/OUT0 P95/TOT2/OUT1 P96/PWC Noise Filter P97/POT 16-bit PWC Timer CMOS I/O PORT 9 P54/AN4/SIN4 A/D converter P55/AN5/SOT4 (10 bits) 8 P56/AN6/SCK4 8+8 PPG x 1 channel P63/PPG0 P64/PPG1 2 P57/AN7 AVCC AVRH,AVRL AVSS P65/CKOT Clock Monitor 2 RAM CMOS I/O PORT 6 ROM DTP/External interrupt ROM Correction ROM Mirroring Other pins Vss x 3, Vcc x 2, MD0-2 and C P60/SIN2 P61/SOT2 P62/SCK2 8 P80/IRQ0 P87/IRQ7 CMOS I/O PORT 8 CMOS I/O PORT 7 D/A converter (8 bits) x 2 channels P71 P72 P73/DA00 P74/DA01 DVRH DVSS Note: P00 to P07 (8 channels): With registers that can be used as input pull-up resistors P10 to P17 (8 channels): With registers that can be used as input pull-up resistors P60 to P65 (6 channels): With registers that can be used as input pull-up resistors P40 to P47 (8 channels): With registers that can be used as open drains Figure 1.3a Block Diagram of MB90580 Series 4 Chapter 1: Overview MB90580 series 1.4 Pin Assignment 1.4 Pin Assignment PA2 X0A X1A P10/AD08 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC X1 X0 VSS P13/AD11 P12/AD10 P11/AD09 P20/A16 P17/AD15 P16/AD14 P15/AD13 P14/AD12 P21/A17 1.4.1 LQFP-100 Pin Assignment 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P22/A18 1 P23/A19 2 P24/A20 3 P25/A21 4 P26/A22 5 P27/A23 6 P30/ALE 7 P31/RDX 8 VSS 9 P32/WRLX 10 P33/WRHX 11 P34/HR0 12 P35/HAKX 13 P36/RDY 14 P37/CLK 15 P40/SIN0 16 P41/SOT0 17 P42/SCK0 18 P43/SIN1 19 P44/SOT1 20 VCC 21 P45/SCK1 22 P46/ADTG 23 P47 24 C 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 LQFP - 100 MB90580 SERIES ( TOP VIEW) FPT-100P-M05 RSTX PA1 PA0 P97/POT P96/PWC P95/TOT2/OUT1 P94/TOT1/OUT0 P93/TOT0/IN3 P92/TIN2/IN2 P91/TIN1/IN1 P90/TIN0/IN0 RX TX P65/CKOT P64/PPG0 P63/PPG1 P62/SCK2 P61/SOT2 P60/SIN2 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 P82/IRQ2 HSTX P80/IRQ0 P81/IRQ1 MD0 MD1 MD2 P55/AN5/SOT4 P56/AN6/SCK4 P57/AN7 DVSS P73/DA00 P74/DA01 AVCC AVRH AVRL AVSS P50/AN0/SIN3 P51/AN1/SOT3 P52/AN2/SCK3 P53/AN3 VSS P54/AN4/SIN4 DVRH P71 P72 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Figure 1.4a Pin Assignment of MB90580 (LQFP-100) MB90580 series Chapter 1: Overview 5 1.4 Pin Assignment P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC X1 X0 VSS P11/AD09 P10/AD08 P07/AD07 P16/AD14 P15/AD13 P14/AD12 P13/AD11 P12/AD10 P17/AD15 1.4.1 QFP-100 Pin Assignment 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P20/A16 1 P21/A17 2 P22/A18 3 P23/A19 4 P24/A20 5 P25/A21 6 P26/A22 7 P27/A23 8 P30/ALE 9 P31/RDX 10 VSS 11 P32/WRLX 12 P33/WRHX 13 P34/HRQ 14 P35/HAKX 15 P36/RDY 16 P37/CLK 17 P40/SIN0 18 P41/SOT0 19 P42/SCK0 20 QFP - 100 MB90580 SERIES ( TOP VIEW) P43/SIN1 21 P44/SOT1 22 Vcc 23 P45/SCK1 24 P46/ADTG 25 FPT-100P-M06 P47 26 C 27 P71 28 P72 29 DVRH 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 X0A X1A PA2 RSTX PA1 PA0 P97/POT P96/PWC P95/TOT2/OUT1 P94TOT1/OUT0 P93/TOT0/IN3 P92/TIN2/IN2 P91/TIN1/IN1 P90/TIN0/IN0 RX TX P65/CKOT P64/PPG0 P63/PPG1 P62/SCK2 P61/SOT2 P60/SIN2 P87IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 P82/IRQ2 HSTX MD2 P50/AN0/SIN3 P51/AN1/SOT3 P52/AN2/SCK3 P53/AN3 VSS P54/AN4/SIN4 P55/AN5/SOT4 P56/AN6/SCK4 P57/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1 AVRH AVRL AVSS DVSS P73/DA00 P74/DA01 AVCC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Figure 1.4b Pin Assignment of MB90580 (QFP-100) 6 Chapter 1: Overview MB90580 series 1.5 Pin Functions 1.5 Pin Functions Table 1.5a to Table 1.5d lists the functions. Table 1.5e to Table 1.5g list the I/O circuit formats. Table 1.5a Pin functions (1/4) (STBC: With standby control) QFP LQFP Pin name I/O Circuit 82 80 X0 A Oscillator pin 83 81 X1 A Oscillator pin 52 50 HSTX C Hardware standby input pin 77 75 RSTX B Reset input pin D General-purpose I/O ports A pull-up resistor can be assigned (RD07-00=’1’) by using the pull-up resistor setting register (RDR0). (D07-00=’1’: Invalid when set as output) P00 to P07 85 to 92 83 to 90 AD00 to AD07 P10 to P17 93 to 100 91 to 98 AD08 to AD15 P20 to P27 1 to 8 (CMOS/H) D (CMOS/H) F 99 to 6 A16 to A23 P30 9 7 (CMOS/H) F (CMOS/H) ALE 10 12 General-purpose I/O port ALE pin in external bus mode (CMOS/H) Read strobe output (RDX) pin P32 F 10 11 (CMOS/H) F General-purpose I/O port WRX pin when the WRE bit is ’1’ in external bus mode Low-order data write strobe output (WRLX) pin General-purpose I/O port WRHX pin when the WRE bit of the EPCR register is ’1’ in external 16-bit bus mode (CMOS/H) 12 P35 13 High-order data write strobe output (WRHX) pin F (CMOS/H) F General-purpose I/O port HRQ pin when the HDE bit of the EPCR register is ’1’ in external bus mode Hold request input (HRQ) pin General-purpose I/O port HAKX pin when the HDE bit of the EPCR register is ’1’ in external bus mode (CMOS/H) HAKX P36 14 RDY P37 15 CLK P40 18 High-order address output (A16 to A19) when the corresponding bit of the HACR register is ’1’ in external bus mode RDX HRQ 17 General-purpose I/O ports Pins A16 to A19 when the corresponding bit of the HACR register is ’0’ in external bus mode General-purpose I/O port RDX pin in external bus mode P34 16 High-order data I/O or medium-order address output (AD08 to 15) in external 16-bit bus mode Address fetch enable signal pin WRHX 15 General-purpose I/O ports A pull-up resistor can be assigned (RD17-10=’1’) by using the pull-up resistor setting register (RDR1). (D17-10=’1’: Invalid when set as output) F P33 14 Low-order data I/O or low-order address output (AD00 to 07) in external bus mode P31 8 WRLX 13 Function Hold acknowledgment output (HAKX) pin F (CMOS/H) F (CMOS/H) E 16 General-purpose I/O port RDY pin when the RYE bit of the EPCR register is ’1’ in external bus mode External ready input (RDY) pin General-purpose I/O port CLK pin when the CKE bit of the EPCR register is ’1’ in external bus mode Machine cycle clock output (CLK) pin General-purpose I/O port Serial input (SIN0) during UART0 operation Open drain output port when OD40 of the open drain control setting register (ODR4) is set to ’1’ (D40=’0’: Invalid when set as input) (CMOS/H) SINO MB90580 series UART0 serial data input (SIN0) pin Chapter 1: Overview 7 1.5 Pin Functions Table 1.5b Pin functions (2/4) QFP LQFP Pin name P41 19 I/O Circuit Function E General-purpose I/O port SOT0 pin when the SOE bit of the UMC register is ’1’ Open drain output port when OD41 of the open drain control setting register (ODR4) is set to ’1’ (D41=’0’: Invalid when set as input) 17 (CMOS/H) SOT0 P42 20 UART0 serial data output (SOT0) pin E 18 General-purpose I/O port SOT0 pin when the SOE bit of the UMC register is ’1’ Open drain output port when OD41 of the open drain control setting register (ODR4) is set to ’1’ (D41=’0’: Invalid when set as input) (CMOS/H) SCK0 P43 21 UART0 serial clock I/O (SCK0) pin E 19 General-purpose I/O port Serial input (SIN1) during extended I/O serial operation Open drain output port when OD43 of the open drain control setting register (ODR4) is set to ’1’ (D43=’0’: Invalid when set as input) (CMOS/H) SIN1 P44 22 UART1 serial data input (SIN1) pin E 20 General-purpose I/O port SOT1 pin when the SOE bit of the UMC register is ’1’ Open drain output port when OD44 of the open drain control setting register (ODR4) is set to ’1’ (D44=’0’: Invalid when set as input) (CMOS/H) SOT1 P45 24 UART1 serial data output (SOT1) pin E 22 (CMOS/H) SCK1 P46 25 23 UART1 serial clock I/O (SCK1) pin E 24 P47 A/D converter external trigger input pin E (CMOS/H) P50 38 36 AN0 (CMOS/H) AN1 General-purpose I/O port G (CMOS/H) SOT3 38 AN2 General-purpose I/O port G (CMOS/H) SCK3 41 P53 G (CMOS/H) P54 43 44 41 42 AN4 General-purpose I/O port Analog input pins (AN3) during A/D converter operation General-purpose I/O port G (CMOS/H) Analog input pin (AN4) during A/D converter operation SIN4 UART4 serial data input (SIN4) pin P55 General-purpose I/O port AN5 SOT4 8 Analog input pin (AN2) during A/D converter operation UART3 serial data output (SOT3) pin AN3 39 Analog input pin (AN1) during A/D converter operation UART3 serial data output (SOT3) pin P52 40 Analog input pin (AN0) during A/D converter operation UART3 serial data input (SIN3) pin P51 37 General-purpose I/O port Open drain output port when OD47 of the open drain control setting register (ODR4) is set to ’1’ (D47=’0’: Invalid when set as input) General-purpose I/O port G SIN3 39 General-purpose I/O port Open drain output port when OD46 of the open drain control setting register (ODR4) is set to ’1’ (D46=’0’: Invalid when set as input) (CMOS/H) ADTG 26 General-purpose I/O port Clock input (SCK1) during extended I/O serial operation in external shift clock mode SCK1 pin when the SOE bit of the UMC register is ’1’ Open drain output port when OD45 of the open drain control setting register (ODR4) is set to ’1’ (D45=’0’: Invalid when set as input) Chapter 1: Overview G (CMOS/H) Analog input pin (AN5) during A/D converter operation UART4 serial data output (SOT4) pin MB90580 series 1.5 Pin Functions Table 1.5c Pin functions (3/4) QFP LQFP Pin name I/O Circuit P56 45 43 AN6 G (CMOS/H) SCK4 46 Analog input pin (AN6) during A/D converter operation UART4 serial data output (SOT4) pin P57 G AN7 (CMOS/H) 44 Function General-purpose I/O port General-purpose I/O port Analog input pins (AN7) during A/D converter operation 27 25 C 28 26 P71 F (CMOS/H) General-purpose I/O port SOT3 pin when the SOE bit of the UMC register is ’1’ 29 27 P72 F (CMOS/H) General-purpose I/O port Clock input (SCK3) during UART1 operation in external shift clock mode SCK3 pin when the SOE bit of the UMC register is ’1’ P73 32 30 H DAO0 P74 33 31 0.1uf capacitor connection pin for voltage supply stabilization. (CMOS/H) F (CMOS/H) DAO1 P80 47 45 IRQ0 P81 48 46 IRQ1 P82 53 51 IRQ2 P83 54 52 IRQ3 P84 55 53 IRQ4 P85 56 54 IRQ5 P86 57 55 P87 56 F (CMOS/H) F (CMOS/H) F (CMOS/H) F (CMOS/H) F (CMOS/H) F (CMOS/H) F (CMOS/H) P60 57 F (CMOS/H) General-purpose I/O port External interrupt request I/O 0 General-purpose I/O port External interrupt request I/O 1 General-purpose I/O port External interrupt request I/O 2 General-purpose I/O port External interrupt request I/O 3 General-purpose I/O port External interrupt request I/O 4 General-purpose I/O port External interrupt request I/O 5 General-purpose I/O port Always enabled (STBC) General-purpose I/O port Always enabled (STBC) External interrupt request I/O 7 D General-purpose I/O port A pull-up resistor can be assigned (RD60=’1’) by using the pull-up resistor setting register (RDR6). (D60=’1’: Invalid when set as output) (CMOS/H) SIN2 P61 60 General-purpose I/O port D/A output pin when the DAE1 bit of the D/A control register (DACR) is ’1’ External interrupt request I/O 6 IRQ7 59 D/A output ’0’ pin during D/A converter operation D/A output ’1’ pin during D/A converter operation IRQ6 58 General-purpose I/O port D/A output pin when the DAE0 bit of the D/A control register (DACR) is ’1’ UART2 serial data input (SIN2) pin D 58 General-purpose I/O port SOT1 pin when the SOE bit of the UMC register is ’1’ A pull-up resistor can be assigned (RD61=’1’) by using the pull-up resistor setting register (RDR6). (D61=’1’: Invalid when set as output) (CMOS/H) SOT2 P62 61 UART2 serial data output (SOUT2) pin D 59 (CMOS/H) SCK2 MB90580 series General-purpose I/O port Clock input (SCK2) during UART1 operation in external shift clock mode SCK1 pin when the SOE bit of the UMC register is ’1’ A pull-up resistor can be assigned (RD62=’1’) by using the pull-up resistor setting register (RDR6). (D62=’1’: Invalid when set as output) UART2 serial clock I/O (SCK2) pin Chapter 1: Overview 9 1.5 Pin Functions Table 1.5d Pin functions (4/4) QFP LQFP Pin name P63 62 60 I/O Circuit Function D General-purpose I/O port A pull-up resistor can be assigned (RD63=’1’) by using the pull-up resistor setting register (RDR6). (D63=’1’: Invalid when set as output) (CMOS/H) PPG00 P64 63 61 PPG00 output when PPG is enabled D (CMOS/H) PPG01 P65 64 62 PPG01 output when PPG is enabled D General-purpose I/O port A pull-up resistor can be assigned (RD65=’1’) by using the pull-up resistor setting register (RDR6). (D65=’1’: Invalid when set as output) (CMOS/H) CKOT CKOT output during CKOT operation 65 63 TX I IEBus output when IEBus is enabled 66 64 RX J IEBus input when IEBus is enabled P90 to P92 General-purpose I/O port F 67 to 69 65 to 67 TIN0 to TIN2 (CMOS/H) IN0 to IN2 70 68 TOT0 General-purpose I/O port F (CMOS/H) IN3 69 to 70 TOT1, TOT2 General-purpose I/O port F (CMOS/H) OUT0, OUT1 73 Output pins for reload timer 0. This function applies when the output for reload timers 0 is enabled. Input capture channel 3 trigger input P94 to P95 71 to 72 Event input pins for reload timers 0,1 and 2. As these inputs are used continuously during reload timer input operation, outputs to these pins from other functions must be avoided unless performed intentionally. Input capture channels 0 - 2 trigger inputs P93 10 General-purpose I/O port A pull-up resistor can be assigned (RD64=’1’) by using the pull-up resistor setting register (RDR6). (D64=’1’: Invalid when set as output) Output pins for reload timers 1 and 2. This function applies when the outputs for reload timers 1 and 2 are enabled. Output comparison channels 0 - 1 event outputs P96 F PWC (CMOS/H) PWC input 71 General-purpose I/O port 74 72 P97 F (CMOS/H) General-purpose I/O port 75, 76 73, 74 PA0, PA1 F (CMOS/H) General-purpose I/O port 78 76 PA2 F (CMOS/H) General-purpose I/O port 79 77 X1A A Oscillator input 80 78 X0A A Oscillator input 34 32 AVCC A/D converter power supply pin 37 35 AVSS A/D converter power supply pin 35 33 AVRH A/D converter external reference power supply pin 36 34 AVRL A/D converter external reference power supply pin 30 28 DVRH D/A converter external reference power supply pin 31 29 DVSS D/A converter power supply pin 49 to 51 47 to 49 MD0 to MD2 23, 84 21, 82 VCC Power supply (5 V) input pin 11, 42, 81 9, 40, 79 VSS Power supply (0 V) input pin Chapter 1: Overview C Operation mode specification input pin Connect directly to Vcc or Vss. MB90580 series 1.5 Pin Functions Table 1.5e I/O circuit format (1) Class A Circuit Remarks • Oscillation feedback resistor: 1 MΩ approx. X1 X0 Standby control signal • Hysteresis input with pull-up B Resistor: 50 kΩ approx. HYS • Hysteresis input port C HYS D CTL • With input pull-up resistor control • CMOS level output • Hysteresis input with standby control Resistor: 50 kΩ approx. HYS Standby control signal MB90580 series Chapter 1: Overview 11 1.5 Pin Functions Table 1.5f I/O circuit format (2) Class Circuit Remarks • CMOS level output • With open drain control • Hysteresis input with standby contro E Open drain control signal HYS Standby control signal • CMOS level output • Hysteresis input with standby control F HYS Standby control signal • CMOS level output • Hysteresis input with standby control • Analog input G Analog input HYS Standby control signal 12 Chapter 1: Overview MB90580 series 1.5 Pin Functions Table 1.5g I/O circuit format (3) Class Circuit Remarks • CMOS level output • Hysteresis input with standby control • Analog output • Shared with DA output H DA Output HYS Standby control signal I • CMOS level output J • Hysteresis input MB90580 series Chapter 1: Overview 13 1.6 Handling the Device 1.6 Handling the Device (1) Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions: A voltage higher than Vcc or lower than Vss is applied to an input or output pin. A voltage higher than the rated voltage is applied between Vcc and Vss. The AVcc power supply is applied before the Vcc voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. (2) Handling unused input pins Do not leave unused input pins open, as doing so may cause misoperation of the device. Use a pull-up or pull-down resistor. (3) Using external clock To use external clock, drive the X0 and X1 pins in reverse phase. Figure 1.6a is a diagram of how to use external clock.. MB90580 Series X0 X1 Figure 1.6a Using external clock (4) Power supply pins (Vcc/Vss) Ensure that all Vcc-level power supply pins are at the same potential. In addition, ensure the same for all Vss-level power supply pins. (See the figure below.) If there are more than one Vcc or Vss system, the device may operate incorrectly even within the guaranteed operating range. Vcc Vss Vcc Vss Vss Vcc MB90580 Series Vcc Vss Vss Vcc Figure 1.6b Connection of Power pins 14 Chapter 1: Overview MB90580 series Chapter 2: CPU 2.1 CPU The F2MC-16LX CPU core is a 16-bit CPU designed for applications that require high-speed real-time processing, such as home-use or vehicle-mounted electronic appliances. The F2MC-16LX instruction set is designed for controller applications, and is capable of high-speed, highly efficient control processing. In addition to 16-bit data, the F 2MC-16LX CPU core can process 32-bit data by using an internal 32-bit accumulator. (32-bit data can be processed with some instructions.) Up to 16 Mbytes of memory space (expandable) can be used, which can be accessed by either the linear pointer or bank method. The instruction system, based on the F2MC-8 A-T architecture, has been reinforced by adding instructions compatible with high-level languages, expanding addressing modes, reinforcing multiplication and division instructions, and enhancing bit processing. The features of the F2MC-16LX CPU are explained below. • Minimum instruction execution time: 62.5 ns (at 4-MHz oscillation, 4 times multiplication) • Maximum memory space: 16 Mbytes, accessed in linear or bank mode • Instruction set optimized for controller applications Rich data types: Bit, byte, word, long word Extended addressing modes: 23 types High-precision operation (32-bit length) based on 32-bit accumulator Signed multiply and division, enhanced RETI instruction • Powerful interrupt functions Eight priority levels (programmable) • CPU-independent automatic transfer Up to 16 channels of extended intelligent I/O service • Instruction set compatible with high-level language (C)/multitasking System stack pointer/instruction set symmetry/barrel-shift instructions • Improved execution speed: 4-byte queue 2.1 CPU 2.1.1 Memory space ■ Outline of CPU memory space An F2MC-16LX CPU has a 16-Mbyte memory space. All data program input and output managed by the F2MC-16LX CPU are located in this 16-Mbyte memory space. The CPU accesses the resources by indicating their addresses using a 24-bit address bus. (See Figure 2.1.1a.). F2MC-16LX CPU Program FFFFFFH FF8000H Data 810000H Interrupt 800000H Program area Data area Peripheral circuits [Device] Generalpurpose ports 0000C0H 0000B0H 000020H Interrupt controller Peripheral circuits General-purpose ports 000000H Figure 2.1.1a Sample relationship between F2MC-16LX system and memory map 16 Chapter 2: CPU MB90580 Series 2.1 CPU ■ Address generation types The F2MC-16LX CPU has two address generation methods. One is the linear method in which an entire 24-bit address is specified by an instruction. The other method is the bank method in which the high-order eight bits of an address is specified by an appropriate bank register while the low-order 16 bits of the same address is specified by an instruction. There are two types of linear method. One specifies a 24-bit address directly by using operands. The other method cites the low-order 24 bits of a 32-bit general-purpose register value as an address. (See Figure 2.1.1b.) Example 1 Linear method (24-bit operand specification) JMPP 123456H Old program counter + program bank 17 17452DH 452D 123456H New program counter + program bank 12 JMPP 123456H Next instruction 3456 Example 2 Linear method (32-bit register indirect specification) MOV A, @RL1+7 Old AL 090700H XXXX 3A +7 RL1 240906F9 (The high-order eight bits are ignored.) New AL 003A Figure 2.1.1b Sample linear addressing ■ Bank addressing types In the bank method, the 16-Mbyte space is divided into 256 64-Kbyte banks. The following five bank registers are used to specify the banks corresponding to each space: • Program bank register (PCB) • Data bank register (DTB) • User stack bank register (USB) • System stack bank register (SSB) • Additional bank register (ADB) MB90580 Series Chapter 2: CPU 17 2.1 CPU The 64-Kbyte bank specified by the PCB is called a program (PC) space. The PC space contains instruction codes, vector tables, and immediate value data, for example. The 64-Kbyte bank specified by the DTB is called a data (DT) space. The DT space contains readable/ writable data, and control/data registers for internal and external resources. The 64-Kbyte bank specified by the USP or SSP is called a stack (SP) space. The SP space is accessed when a stack access occurs during a push/pop instruction or interrupt register saving. The S flag in the condition code register determines the stack space to be accessed. The 64-Kbyte bank specified by the ADB is called an additional (AD) space. The AD space, for example, contains data that cannot fit into the DT space. Table 2.1.1a lists the default spaces used in each addressing mode, which are pre-determined to improve instruction coding efficiency. To use a non-default space for an addressing mode, specify a prefix code corresponding to a bank before the instruction. This enables access to the bank space corresponding to the specified prefix code. After reset, the DTB, USB, SSB, and ADB are initialized to 00H. The PCB is initialized to a value specified by the reset vector. After reset, the DT, SP, and AD spaces are allocated in bank 00H (000000H to 00FFFFH), and the PC space is allocated in the bank specified by the reset vector. Table 2.1.1a Default space Default space Addressing mode Program space PC indirect, program access, branch Data space Addressing mode using @RW0, @RW1, @RW4, or @RW5, @A, addr16, and dir Stack space Addressing mode using PUSHW, POPW, @RW3, or @RW7 Additional space Addressing mode using @RW2 or @RW6 Figure 2.1.1c is an example of a memory space divided into register banks. FFFFFFH FF0000H Program space FFH : PCB (Program bank register) B3H : ADB (Additional bank register) 92H : USB (User stack bank register) 68H : DTB (Data bank register) 4BH : SSB (System stack bank register) B3FFFFH Physical address Additional space B30000H 92FFFFH 920000H User stack space 68FFFFH 680000H Data space 4BFFFFH 4B0000H System stack space 000000H Figure 2.1.1c Physical addresses of each space 18 Chapter 2: CPU MB90580 Series 2.1 CPU ■ Multi-byte data allocation in memory space Figure 2.1.1d is a diagram of multi-byte data configuration in memory. The low-order eight bits of a data item are stored at address n, then address n+1, address n+2, address n+3, etc. MSB 01010101 H 11001100 11111111 LSB 00010100 01010101 11001100 11111111 Address n 00010100 L Figure 2.1.1d Sample allocation of multi-byte data in memory Data is written to memory from the low-order addresses. Therefore, for a 32-bit data item, the low-order 16 bits are transferred before the high-order 16 bits. If a reset signal is input immediately after the low-order bits are written, the high-order bits might not be written. ■ Accessing multi-byte data Fundamentally, accesses are made within a bank. For an instruction accessing a multi-byte data item, address FFFFH is followed by address 0000H of the same bank. Figure 2.1.1e is an example of an instruction accessing multi-byte data. H 80FFFFH AL before execution ?? ?? AL after execution 23H 01H 01H • • • 23H 800000H L Figure 2.1.1e Execution of MOVW A, 080FFFFH MB90580 Series Chapter 2: CPU 19 2.1 CPU 2.1.2 Registers The F2MC-16LX registers are largely classified into two types: special registers in the CPU and general-purpose registers in memory. The special registers are dedicated internal hardware of the CPU, and their applications are limited by the CPU architecture. The general-purpose registers share the CPU address space with RAM. The general-purpose registers are the same as the special registers in that they can be accessed without using an address. The applications of the general-purpose registers can be specified by the user however, as is ordinary memory space. ■ Special registers The F2MC-16LX has the following 13 special registers: • Accumulator (A=AH:AL): Two 16-bit accumulators (Can be used as a single 32-bit accumulator.) • User stack pointer (USP): 16-bit pointer indicating the user stack area • System stack pointer (SSP): 16-bit pointer indicating the system stack area • Processor status (PS): 16-bit register indicating the system status • Program counter: 16-bit register holding the address of the program • Program bank register: 8-bit register indicating the PC space • Data bank register: 8-bit register indicating the DT space • User stack bank register (USB): 8-bit register indicating the user stack space • System stack bank register (SSB): 8-bit register indicating the system stack space • Additional bank register (ADB): 8-bit register indicating the AD space • Direct page register (DPR): 8-bit register indicating a direct page AL Accumulator USP User stack pointer SSP System stack pointer AH PS Processor status PC Program counter DRP Direct page register PCB Program bank register DTB Data bank register USB User stack bank register SSB System stack bank register ADB Additional data bank register 8 bit 16 bit 32 bit Figure 2.1.2a Special registers 20 Chapter 2: CPU MB90580 Series 2.1 CPU ■ General-purpose registers The F2MC-16LX general-purpose registers are located from addresses 000180H to 00037FH (maximum configuration) of main storage. The register bank pointer (RP) indicates which of the above addresses are currently being used as a register bank. Each bank has the following three types of registers. These registers are mutually dependent as described in Figure 2.1.2b. • R0 to R7: 8-bit general-purpose register • RW0 to RW7: 16-bit general-purpose register • RL0 to RL3: 32-bit general-purpose register MSB LSB 16 bit 000180H + RP*10H RW0 Low-order First address of general-purpose register RL0 RW1 RW2 RL1 RW3 R1 R0 RW4 R3 R2 RW5 R5 R4 RW6 R7 R6 RW7 RL2 RL3 High-order Figure 2.1.2b General-purpose registers The relationship between the high-order and low-order bytes of a byte or word register is expressed as follows: RW (i+4) = R (i*2+1)*256+R (i*2) [i=0 to 3] The relationship between the high-order and low-order bytes of Rli and RW can be expressed as follows: RL (i) = RW (i*2+1)*65536+RW (i*2) [i=0 to 3] ■ Program counter (PC) The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory address of an instruction code to be executed by the CPU. The high-order eight bits of the address are indicated by the PCB. The PC register is updated by a conditional branch instruction, subroutine call instruction, interrupt, or reset. The PC register can also be used as a base pointer for operand access. PCB FEH PC A BCDH Next instruction to be executed FEABCDH Figure 2.1.2c Program counter MB90580 Series Chapter 2: CPU 21 2.1 CPU ■ Accumulator (A) The A register consists of two 16-bit arithmetic operation registers (AH and AL). The A register is used as a temporary storage for operation results and transfer data. During 32-bit data processing, AH and AL are used together. Only AL is used for word processing in 16-bit data processing mode or for byte processing in 8-bit data processing mode (see Figures 2.1.9 and 2.1.10). The data stored in the A register can be operated upon with the data in memory or registers (Ri, Rwi, or Rli). In the same manner as with the F2MC-8L, when a word or shorter data item is transferred to AL, the previous data item in AL is automatically sent to AH (data preservation function). The data preservation function and operation between AL and AH help improve processing efficiency. When a byte or shorter data item is transferred to AL, the data is sign-extended or zero-extended and stored as a 16-bit data item in AL. The data in AL can be handled either as word or byte long. When a byte-processing arithmetic operation instruction is executed on AL, the high-order eight bits of AL before operation are ignored. The high-order eight bits of the operation result all become zeroes. The A register is not initialized by a reset. The A register holds an undefined value immediately after a reset. MOVL A,@RW1+6 Old A XXXXH MSB XXXXH A6H DTB New A 8F74H 2B52H AH AL LSB A61540H 8FH 74H A6153EH 2BH 52H 15H 38H +6 RW1 Figure 2.1.2d 32-bit data transfer MSB MOVW A,@RW1+6 Old A XXXXH 1234H DTB New A 1234H A6H 2B52H LSB A61540H 8FH 74H A6153EH 2BH 52H RW1 15H 38H +6 Figure 2.1.2e AL-AH transfer 22 Chapter 2: CPU MB90580 Series 2.1 CPU ■ User stack pointer (USP) and system stack pointer (SSP) USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data in the event of a push/pop instruction or subroutine execution. The USP and SSP registers are used by stack instructions. The USP register is enabled when the S flag in the processor status register is ’0,’ and the SSP register is enabled when the S flag is ’1’ (see Figure 2.1.2f). Since the S flag is set when an interrupt is accepted, register values are always saved in the memory area indicated by SSP during interrupt processing. SSP is used for stack processing in an interrupt routine, while USP is used for stack processing outside an interrupt routine. If the stack space is not divided, use only the SSP. During stack processing, the high-order eight bits of an address are indicated by SSB (for SSP) or USB (for USP). USP and SSP are not initialized by a reset. Instead, they hold undefined values. Example 1 PUSHW A when the S flag is ’0’ Before execution AL S flag After execution AL MSB C6F326H LSB A624H USB C6H USP F328H 0 SSB 56H SSP 1234H A624H USB C6H USP F326H 0 SSB 56H SSP 1234H C6F326H A6H 24H 561232H XX XX 561232H A6H 24H XX XX User stack is used because the S flag is ’0.’ Example 2 PUSHW A when the S flag is ’1’ AL AL A624H USB C6H USP F328H 1 SSB 56H SSP 1234H A624H USB C6H USP F328H 1 SSB 56H SSP 1232H System stack is used because the S flag is ’1.’ Figure 2.1.2f Stack manipulation instruction and stack pointer Note: Specify an even-numbered address in the stack pointer whenever possible. MB90580 Series Chapter 2: CPU 23 2.1 CPU ■ Processor status (PS) The PS register consists of the bits controlling the CPU Operation and the bits indicating the CPU status. As shown in Figure 2.1.2g, the high-order byte of the PS register consists of a register bank pointer (RP) and an interrupt level mask register (ILM). The RP indicates the start address of a register bank. The low-order byte of the PS register is a condition code register (CCR), containing the flags to be set or reset depending on the results of instruction execution or interruptoccurrences. 15 13 12 PS 0 8 7 ILM RP CCR Figure 2.1.2g PS structure (1)Condition code register (CCR) Initial value 7 6 5 4 3 2 1 0 - I S T N Z V C : CCR - 0 1 * * * * * *: Undefined Figure 2.1.2h Condition code register configuration I:Interrupt enable flag: Interrupts other than software interrupts are enabled when the I flag is 1 and are masked when the I flag is 0. The I flag is cleared by a reset. 24 S:Stack flag: When the S flag is 0, USP is enabled as the stack manipulation pointer. When the S flag is 1, SSP is enabled as the stack manipulation pointer. The S flag is set by an interrupt reception or a reset. T:Sticky bit flag: 1 is set in the T flag when there is at least one ’1’ in the data shifted out from the carry after execution of a logical right/arithmetic right shift instruction. Otherwise, 0 is set in the T flag. In addition, ’0’ is set in the T flag when the shift amount is zero. N:Negative flag: The N flag is set when the MSB of the operation result is ’1,’ and is otherwise cleared. Z:Zero flag: The Z flag is set when the operation result is all zeroes, and is otherwise cleared. V:Overflow flag: The V flag is set when an overflow of a signed value occurs as a result of operation execution and is otherwise cleared. C:Carry flag: The C flag is set when a carry-up or carry-down from the MSB occurs as a result of operation execution and is otherwise cleared. Chapter 2: CPU MB90580 Series 2.1 CPU (2) Register bank pointer (RP) The RP register indicates the relationship between the general-purpose registers of the F2MC-16LX and the internal RAM addresses. Specifically, the RP register indicates the first memory address of the currently used register bank in the following conversion expression: [00180H + (RP)*10H] (see Figure 2.1.2i). The RP register consists of five bits, and can take a value between 00H and 1FH. Register banks can be allocated at addresses from 000180H to 000370H in memory. Even within that range, however, the register banks cannot be used as general-purpose registers if the banks are not in internal RAM. The RP register is initialized to all zeroes by a reset. An instruction may transfer an eight-bit immediate value to the RP register; however, only the low-order five bits of that data are used. Initial value B4 B3 B2 B1 0 0 0 0 : RP B0 0 Figure 2.1.2i Register bank pointer (3) Interrupt level mask register (ILM) The ILM register consists of three bits, indicating the CPU interrupt masking level. An interrupt request is accepted only when the level of the interrupt is higher than that indicated by these three bits. Level 0 is the highest priority interrupt, and level 7 is the lowest priority interrupt (see Table 2.1.2a). Therefore, for an interrupt to be accepted, its level value must be smaller than the current ILM value. When an interrupt is accepted, the level value of that interrupt is set in ILM. Thus, an interrupt of the same or lower level cannot be accepted subsequently. ILM is initialized to all zeroes by a reset. An instruction may transfer an eight-bit immediate value to the ILM register, but only the low-order three bits of that data are used. Initial value ILM2 ILM1 ILM0 0 0 0 : ILM Figure 2.1.2j Interrupt level register Table 2.1.2a Levels indicated by the interrupt level mask (ILM) register ILM2 ILM1 ILM0 Level value Acceptable interrupt level 0 0 0 0 Interrupt disabled 0 0 1 1 0 only 0 1 0 2 Level value smaller than 1 0 1 1 3 Level value smaller than 2 1 0 0 4 Level value smaller than 3 1 0 1 5 Level value smaller than 4 1 1 0 6 Level value smaller than 5 1 1 1 7 Level value smaller than 6 MB90580 Series Chapter 2: CPU 25 2.1 CPU ■ Register bank A register bank consists of eight words. The register bank can be used as the following general-purpose registers for arithmetic operations: byte registers R0 to R7, word registers RW0 to RW7, and long word registers RL0 to RL3. In addition, the register bank can be used as instruction pointers. Table 2.1.2b lists the functions of the registers. Table 2.1.2c indicates the relationship between the registers. In the same manner as for an ordinary RAM area, the register bank values are not initialized by a reset. The status before a reset is maintained. When the power is turned on, however, the register bank will have an undefined value. Table 2.1.2b Register functions R0 to R7 RW0 to RW7 RL0 to RL3 Used as operands of instructions. Note: R0 is also used as a counter for barrel shift or normalization instructions. Used as pointers. Used as operands of instructions. Note: RW0 is used as a counter for string instructions. Used as long pointers. Used as operands of instructions. Table 2.1.2c Relationship between registers RW0 RW1 RW2 RW3 R0 R1 R2 R3 R4 R5 R6 R7 26 Chapter 2: CPU RL0 RL1 RW4 RL2 RW5 RW6 RL3 RW7 MB90580 Series 2.1 CPU ■ Program counter bank register (PCB) <Initial value: Value in reset vector> Data bank register(DTB) <Initial value: 00H> User stack bank register(USB) <Initial value: 00H> System stack bank register(SSB) <Initial value: 00H> Additional data bank register(ADB) <Initial value: 00H> Each bank register indicates the memory bank where the PC, DT, SP (user), SP (system), or AD space is allocated. All bank registers are one byte long. PCB is initialized to 00H by a reset. Bank registers other than PCB can be read or written to. PCB can be read but cannot be written to. PCB is updated when the JMPP, CALLP, RETP, RETI, or RETF instruction branching to the entire 16-Mbyte space is executed or when an interrupt occurs. For operation of each register, see Chapter 2, Section 2.1.1, "Memory space." ■ Direct page register (DPR) <Initial value: 01H> DPR specifies addr8 to addr15 of the instruction operands in direct addressing mode as shown in Figure 2.1.2k. DPR is eight bits long, and is initialized to 01H by a reset. DPR can be read or written to by an instruction. DTB register DPR register αααααααα ββββββββ Direct address during instruction LSB MSB 24-bit physical address γγγγγγγγ ααααααααββββββββγγγγγγγγ Figure 2.1.2k Generating a physical address in direct addressing mode MB90580 Series Chapter 2: CPU 27 2.1 CPU 2.1.3 Prefix codes Placing a prefix code before an instruction partially changes the operation of the instruction. Three types of prefix codes can be used: bank select prefix, common register bank prefix, and flag change disable prefix. ■ Bank select prefix The memory space used for accessing data is determined for each addressing mode. When a bank select prefix is placed before an instruction, the memory space used for accessing data by that instruction can be selected regardless of the addressing mode. Table 2.1.3a Bank select prefix Bank select prefix Space selected PCB PC space DTB Data space ADB AD space SPB Either the SSP or USP space is used according to the stack flag value. Use the following instructions with care: (1) String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) The bank register specified by an operand is used regardless of the prefix. (2)Stack manipulation instructions (PUSHW, POPW) SSB or USB is used according to the S flag regardless of the prefix. (3)I/O access instructions MOV A, io / MOV io, A /MOVX A, io / MOVW A, io /MOVW io, A / MOV io, #imm8 MOVW io, #imm16 / MOVB A, io:bp / MOVB io:bp, A /SETB io:bp / CLRB io:bp BBC io:bp, rel / BBS io:bp, rel WBTC, WBTS The IO space of the bank is used regardless of the prefix. (4)Flag change instructions (AND CCR,#imm8, OR CCR,#imm8) The instruction is executed normally, but the prefix affects the next instruction. (5)POPW PS SSB or USB is used according to the S flag regardless of the prefix. The prefix affects the next instruction. (6)MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction. (7)RETI SSB is used regardless of the prefix. 28 Chapter 2: CPU MB90580 Series 2.1 CPU ■ Common register bank prefix (CMR) To simplify data exchange between multiple tasks, the same register bank must be accessed relatively easily regardless of the RP value. When CMR is placed before an instruction that accesses a register bank, that instruction accesses the common bank (the register bank selected when RP=0) at addresses from 000180H to 00018FH regardless of the current RP value. Use the following instructions with care: (1)String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) If an interrupt request occurs during execution of a string instruction with a prefix code, the prefix code becomes invalid when the string instruction is resumed after the interrupt is processed. Thus, the string instruction is executed falsely after the interrupt is processed. Do not prefix any of the above string instructions with CMR. (2)Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS) The instruction is executed normally, but the prefix affects the next instruction. (3)MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction. ■ Flag change disable prefix To disable flag changes, use the flag change disable prefix code (NCC). Placing NCC before an instruction disables flag changes associated with that instruction. Use the following instructions with care: (1) String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) If an interrupt request occurs during execution of a string instruction with a prefix code, the prefix code becomes invalid when the string instruction is resumed after the interrupt is processed. Thus, the string instruction is executed incorrectly after the interrupt is processed. Do not prefix any of the above string instructions with NCC. (2) Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS) The instruction is executed normally, but the prefix affects the next instruction. (3)Interrupt instructions (INT #vct8, INT9, INT addr16, INTP addr24, RETI) CCR changes according to the instruction specifications regardless of the prefix. (4)JCTX @A CCR changes according to the instruction specifications regardless of the prefix. (5)MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction. ■ Interrupt disable instructions Interrupt requests are not sampled for the following ten instructions: • MOV ILM,#imm8 • PCB • SPB • OR CCR,#imm8 • AND CCR,#imm8 • ADB • CMR •POPW PS • NCC • DTB If a valid interrupt request occurs during execution of any of the above instructions, the interrupt can be processed only when an instruction other than the above is executed. For details, see Figure 2.1.3a. Interrupt disable instruction •••••••• (a) ••• (a) Ordinary instruction Interrupt request Interrupt acceptance Figure 2.1.3a Interrupt disable instruction MB90580 Series Chapter 2: CPU 29 2.1 CPU ■ Restrictions on interrupt disable instructions and prefix instructions When a prefix code is placed before an interrupt disable instruction, the prefix code affects the first instruction after the code other than the interrupt disable instruction. Interrupt disable instruction MOV A, FFH NCC •••• MOV ILM,#imm8 ADD A,01H CCR:XXX10XX CCR:XXX10XX CCR does not change with NCC. Figure 2.1.3b Interrupt disable instructions and prefix codes ■ Consecutive prefix codes When competitive prefix codes are placed consecutively, the latter becomes valid. Prefix code ••••• ADB DTB PCB ADD A,01H •••• PCB is valid as the prefix code Figure 2.1.3c Consecutive prefix codes In the figure above, competitive prefix codes are PCB, ADB, DTB, and SPB. 30 Chapter 2: CPU MB90580 Series Chapter 3: Memory 3.1 Memory Access Modes In the F2MC-16LX, there are several modes for access methods, access areas, and test methods. In this module, the following classifications apply: Table 3.1a Memory Access Mode Operation Mode Bus Mode Access Mode (External data bus width) Single Chip ——— 8 bit Internal ROM, external bus 16 bit RUN 8 bit External ROM, external bus 16 bit EPROM Write ——— ——— Test Functions ——— ——— ■ Operation mode Operation mode means the mode for controlling the device operation status. The operation mode is specified by the MDx mode setting pin and the Ex bit in mode data. By selecting an operation mode, normal operation, internal test program activation, or special test function activation can be performed. ■ Bus mode Bus mode means the mode for controlling the internal ROM operation and external access function. The bus mode is specified by the MDx mode setting pin and the Mx bit in mode data. The MDx mode setting pin specifies the bus mode for reading the reset vector and mode data, and the Mx bit in mode data specifies the bus mode for normal operation. ■ Access mode Access mode means the mode for controlling the external data bus width. The access mode is specified by the MDx mode setting pin and the Sx bit in mode data. By selecting an access mode, an 8- or 16-bit external data bus is specified. 3.1 Memory Access Modes 3.1.1 Mode pins Table 3.1.1a describes the operations specified by combinations of the MD2 to MD0 external pins. Table 3.1.1a Mode pins and modes Mode pin setting MD2 MD1 MD0 000 001 Mode name External vector mode 0 External vector mode 1 010 (Specification inhibited) 011 Internal vector mode Reset vector access area External data bus width External 8 bits External 16 bits Reset vector, 16-bit bus width access Internal (Mode data) Reset sequence are based on mode data. —— —— Remarks 100 101 (Specification inhibited) 110 111 EPROM write Note: When using internal vector mode 0, the initial value of IOBS and LMBS are ‘0’. If IOBS and LMBS are set afterwards, the address range 0000C0H..0000FFH and 002000H..7FFFFFH will use 16-bit data bus. 32 Chapter 3: Memory MB90580 Series 3.1 Memory Access Modes 3.1.2 Mode data Mode data is stored at FFFFDFH of main memory and used for controlling the CPU operation. This data is fetched during a reset sequence and stored in the mode register inside the device. The mode register value can be changed only by a reset sequence. The setting of this register is valid after the reset sequence. Always set the reserved bits to ’0.’ Here is a diagram of the setting of the bits. Mode data Address: FFFFDFH 7 6 5 4 3 2 1 0 M1 M0 — — S0 — — — Bit No. [bit 7, 6] : Bus mode setting bits These bits are used to specify the operation mode after the reset sequence is completed. Here shows the relationship between the bits and the functions. M1 M0 Function 0 0 Single chip mode 0 1 Internal ROM and external bus mode 1 0 External ROM and external bus mode 1 1 (Inhibited) Remarks [bit 3] : Mode setting bits These bits are used to specify the bus mode or access mode after the reset sequence is completed. The following table shows the relationship between the bits and the functions. S0 MB90580 Series Function 0 External data bus, 8-bit mode 1 External data bus, 16-bit mode Remarks Chapter 3: Memory 33 3.1 Memory Access Modes 3.1.3 Bus Mode Figure 3.1.3a shows correspondence between the access areas and physical addresses for each bus mode. FFFFFFH ROM ROM ROM (FF bank image) ROM (FF bank image) Address #1 FE0000H 010000H Address #2 004000H 002000H Address #3 : No access RAM RAM RAM I/O I/O I/O Single chip (with ROM mirror function) Internal ROM, external bus (with ROM mirror function) External ROM, external bus 000100H 0000C0H 000000H . : Internal access : External access Device Address #1 Address #2 Address #3 MB90583 FE0000H 004000H 001900H MB90F583 FE0000H 004000H 001900H MB90V580 (FE0000H) 004000H 001900H Note: If ROM mirroring function is not wanted, please refer to Chapter 22, ROM Mirroring Module. Note: The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without using the far specification in the pointer declaration.For example, an attempt to access 00C000H accesses the value at FFC000H in ROM. Note: The ROM area in bank FF exceeds 48 Kbytes, and its entire image cannot be shown in bank 00. Note: With the MB90F583 and MB90583, the image between FF4000H and FFFFFF H is visible in bank 00, while the image between FE0000H and FF3FFFH is visible only in bank FE or FF Figure 3.1.3a Access areas and physical addresses in each bus mode 34 Chapter 3: Memory MB90580 Series 3.1 Memory Access Modes ■ Recommended setting Table 3.1.3a lists a sample recommended setting of mode pins and mode data. Table 3.1.3a Sample recommended setting of mode pins and mode data Sample setting MD2 MD1 MD0 M1 M0 S0 Single chip 0 1 1 0 0 × Internal ROM and external bus mode, 16-bit bus 0 1 1 0 1 1 Internal ROM and external bus mode, 8-bit bus 0 1 1 0 1 0 External ROM and external bus mode, 16-bit bus, vector 16 bus width 0 0 1 1 0 1 External ROM and external bus mode, 8-bit bus 0 0 0 1 0 0 Note: I/O signals appearing on an external pin connected to this module vary with the mode. Table 3.1.3b lists the external pin function in each modes Table 3.1.3b Modes and related external pin operations Function Pin name Single chip P07 to P00 External bus extension 8 bits 16 bits AD07 to 00 P17 to P10 A15 to 08 AD15 to 08 EPROM write D07 to 00 A15 to 08 P27 to P20 A23 to 16 A07 to 00 P30 ALE A16 P31 RDX CEX P32 P33 Port WRX WRLX OEX Port WRHX PGMX P34 HRQ P35 HAKX P36 RDY P37 CLK Unused Note: The high-order bits of an address and WRX, WRLX, WRHX, HAKX, HRQ, RDY, and CLK can be used as ports depending on function selection. MB90580 Series Chapter 3: Memory 35 3.2 External Memory Access 3.2 External Memory Access To access external memory and peripherals, the F 2MC-16LX supplies the following address, data, and control signals: CLK (P37) : Machine cycle clock (KBP) RDY (P36) : External ready input pin WRHX (P33) : Write signal for high-order 8 bits of data bus WRLX (P32) : Write signal for low-order 8 bits of data bus RDX (P31) : Read signal ALE (P30) : Address latch enable signal The external bus pin control circuit controls the external bus pins for externally extending the CPU address/data bus. 3.2.1 Block diagram P3 P2 P3 P1 P0 P0 data P0 P0 direction RB Data control Address control Access control Access control Figure 3.2.1a External bus pin control circuit 36 Chapter 3: Memory MB90580 Series 3.2 External Memory Access 3.2.2 Registers and Register details Automatic ready function selection register Address: 0000A5H Read/write Initial value 15 14 13 12 IOR1 IOR0 HMR1 HMR0 (W) (0) (W) (0) (W) (1) (W) (1) 11 9 8 — LMR1 LMR0 (-) (-) (-) (-) (W) (0) (W) (0) — 10 Bit No. ARSR External address output control register 7 6 5 4 3 2 1 0 E23 E22 E21 E20 E19 E18 E17 E16 (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) 15 14 13 12 11 10 9 8 Address: 0000A7H CKE RYE HDE IOBS HMBS WRE LMBS — Read/write Initial value (W) (0) (W) (0) (W) (0) (W) (0) (W) (1/0) (W) (0) (W) (0) (-) (-) Address: 0000A6H Read/write Initial value Bit No. HACR Bus control signal selection register MB90580 Series Bit No. ECSR Chapter 3: Memory 37 3.2 External Memory Access 3.2.2.1 Automatic ready function selection register Address: 0000A5H Read/write Initial value 15 14 13 12 11 10 9 8 IOR1 IOR0 HMR1 HMR0 - - LMR1 LMR0 (W) (0) (W) (0) (W) (1) (W) (1) (-) (-) (-) (-) (W) (0) (W) (0) Bit No. ARSR [bits 15 and 14]: IOR1 and IOR0 These bits specify the automatic wait function for external access to the area between 000000H and 0000FFH. IOR1 IOR0 Setting 0 0 Automatic wait disabled 0 1 One machine cycle of automatic wait for external access 1 0 Two machine cycles of automatic wait for external access 1 1 Three machine cycles of automatic wait for external access The initial value is ’00B.’ [bits 13 and 12]: HMR1 and HMR0 These bits specify the automatic wait function for external access to the area between 800000H and FFFFFFH. HMR1 HMR0 Setting 0 0 Automatic wait disabled 0 1 One machine cycle of automatic wait for external access 1 0 Two machine cycles of automatic wait for external access 1 1 Three machine cycles of automatic wait for external access The initial value is ’11B.’ [bits 9 and 8]: LMR1 and LMR0 These bits specify the automatic wait function for external access to the area between 002000H and 7FFFFFH. LMR1 LMR0 Setting 0 0 Automatic wait disabled 0 1 One machine cycle of automatic wait for external access 1 0 Two machine cycles of automatic wait for external access 1 1 Three machine cycles of automatic wait for external access The initial value is ’00B.’ 38 Chapter 3: Memory MB90580 Series 3.2 External Memory Access 3.2.2.2 External address output control register Address: 0000A6H Read/write Initial value 7 6 5 4 3 2 1 0 E23 E22 E21 E20 E19 E18 E17 E16 (W) (W) (W) (W) (W) (W) (W) (W) (0) (0) (0) (0) (0) (0) (0) (0) Bit No. HACR This register controls the external output of addresses (A19 to A16). The bits corresponds to addresses A19 to A16, controlling the address output pins as described below. Table 3.2.0a Selecting the high-order address bit output control 0 The corresponding pin is used as an address output (Axx). 1 The corresponding pin is used as an I/O port (Pxx). This register cannot be accessed when the device is in single chip mode. In that case, all pins are used as I/O ports regardless of the value of this register. All bits of this register are write-only bits. ’1’ is always read from these bits. These bits are initialized to ’0’ upon a reset. MB90580 Series Chapter 3: Memory 39 3.2 External Memory Access 3.2.2.3 Bus control signal selection register Bus control signal selection register 15 14 13 12 11 10 9 8 Address: 0000A7H CKE RYE HDE IOBS HMBS WRE LMBS — Read/write Initial value (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (-) (-) Bit No. ECSR This register is used to set the bus control function in external bus mode. This register cannot be accessed when the device is in single chip mode. In that case, all pins are used as I/O ports regardless of the value of this register. All bits of this register are write-only bits. ’1’ is always read from these bits. [bit 15]: CKE This bit controls the external clock (CLK) output as described below. 0 I/O port (P37) operation (clock output disabled) 1 Clock signal (CLK) output enabled This bit is initialized to ’0’ upon a reset. [bit 14]: RYE This bit controls the external ready (RDY) input as described below. 0 I/O port (P36) operation (external RDY input disabled) [default] 1 External ready (RDY) input enabled This bit is initialized to ’0’ upon a reset. [bit 13]: HDE This bit specifies whether to enable I/O of hold-related pins. This bit controls the hold request input (HRQ) and hold acknowledge output (HAKX) pins as described below. 0 I/O port (P35 and P34) operation (Hold function I/O disabled) [default] 1 Hold request (HRQ) input/hold acknowledge (HAKX) output enabled This bit is initialized to ’0’ upon a reset. [bit 12]: IOBS This bit specifies the bus size when an area between 0000C0H and 0000FFH is externally accessed in 16-bit external data bus mode. The size is controlled as described below. 0 16-bit bus size access [default] 1 8-bit bus size access This bit is initialized to ’0’ upon a reset. 40 Chapter 3: Memory MB90580 Series 3.2 External Memory Access [bit 11]: HMBS This bit specifies the bus size when an area between 800000H and FFFFFFH is externally accessed in 16-bit external data bus mode. The size is controlled as described below. 0 16-bit bus size access [default in mode other than external vector mode 2] 1 8-bit bus size access [default in external vector mode 2] This bit is initialized to ’1’ upon a reset in external vector mode 2. In any other mode, this bit is initialized to ’0’ upon a reset. [bit 10]: WRE This bit controls the output of the external write signal pin (WRHX and WRLX pins in 16-bit bus mode and WRX pin in 8-bit bus mode) as described below. 0 I/O port (P33 and P32) operation (write signal output disabled) [default] 1 Write strobe signal (WRHX/WRLX or WRX) output enabled In 8-bit external data bus mode, P33 is used as an I/O port regardless of the value of this register. This bit is initialized to ’0’ upon a reset. [bit 9]: LMBS This bit specifies the bus size when an area between 002000H and 7FFFFFH is externally accessed in 16-bit external data bus mode. The size is controlled as described below. 0 16-bit bus size access [default] 1 8-bit bus size access This bit is initialized to ’1’ upon a reset. Note: In 16-bit bus mode, set P33 and P32 in input mode (set ’0’ in bits 3 and 2 of DDR3) when enabling the WRHX and WRLX functions by the WRE bit. In 8-bit bus mode, set P32 in input mode (set ’0’ in bit 2 of DDR3) when enabling the WRX function by the WRE bit. Even if RDY or HRQ input is enabled by the RYE or HDE bit, the I/O port function of the port is valid. Therefore, ensure that ’0’ (input mode) is written to the DDR3 bit corresponding to the port. MB90580 Series Chapter 3: Memory 41 3.2 External Memory Access 3.2.1 Operations MB90580 has a variety of access method and access area modes. See Section 3.1 ,“Memory Access Modes” (1) External memory access control signals External memory is accessed in three cycles while the ready function is not used. Figure 3.2.4 shows the concept of external access timing. The 8-bit bus width access in external 16-bit bus mode is used to read or write to an 8-bit peripheral chip when both 8- and 16-bit peripheral chips are connected to the external bus. Sine the 8-bit bus width access is executed using the low-order 8 bits of the data bus, ensure that the 8-bit peripheral chips are connected to the low-order 8 bits of the data bus. Use the HMBS, LMBS, and IOBS bits of EPCR to specify whether to perform 16- or 8-bit bus width access in external 16-bit bus mode. If only an address and ALE assert signal are output and RDX, WRX, WRLX, and WRHX are not asserted, the bus operation may not be actually performed. Ensure that a peripheral chip is not accessed by only an ALE signal. ■ External 8-bit bus mode Write Read Read P37/CLK P33 (Port data) P32/WRX P31/RDX P30/ALE P27 to 20/A23 to 16 Read address Write address Read address P17 to 10/A15 to 08 Read address Write address Read address Write address Read address P07 to 00/AD07 to 00 Read address Read data Write data Figure 3.2.1a External memory access timing chart 42 Chapter 3: Memory MB90580 Series 3.2 External Memory Access ■ External 16-bit bus mode 8-bit bus width byte read Even-number address byte read 8-bit bus width byte write Even-number address byte write P37/CLK P33/WRHX P32/WRLX P31/RDX P30/ALE Read address P27 to 20/A23 to16 P17 to 10/AD15 to 08 Read address P07 to 00/AD07 to 00 Read address Read address Write address Invalid Write address Read data Odd-number address byte read Read address Write address Read address Undefined Write data Odd-number address byte write P37/CLK P33/WRHX P32/WRLX P31/RDX P30/ALE P27 to 20/A23 to 16 Read address P17 to 10/AD15 to 08 Read address P07 to 00/AD07 to 00 Read address Read address Write address Read address Write address Invalid Write address Read data Even-number address word read Read address Undefined Write data Even-number address word write P37/CLK P33/WRHX P32/WRLX P31/RDX P30/ALE P27 to 20/A23 to 16 Read address Read address Write address P17 to 10/AD15 to 08 Read address Write address Read address P07 to 00/AD07 to 00 Read address Write address Read address Read data Write data * Design the external circuit so that data is always read in word mode. Low-speed memory or peripheral circuit can be accessed depending on the setting of the P36/RDY pin or the automatic ready function selection register (ARSR). Figure 3.2.1b External memory access timing chart MB90580 Series Chapter 3: Memory 43 3.2 External Memory Access (2) Ready function When the RYE bit of the bus control signal selection register (EPCR) is set to ’1,’ a wait cycle is inserted while an L level signal appears at the R36/RDY pin in the event of an access to an external area. Thus, the access cycle can be extended. Even-number address word read Even-number address word write P37/CLK P33/WRHX P32/WRLX P31/RDX P30/ALE P27 to 20/A23 to 16 Read address Write address P17 to 10/AD15 to 08 Read address Write address P07 to 00/AD07 to 00 Read address Write address P36/RDY Read data RDY pin fetch Even-number address word read Write data Even-number address word write P37/CLK P33/WRHX P32/WRLX P31/RDX P30/ALE P27-20/A23-16 Write address Read address P17-10/AD15-08 Write address Read address P07-00/AD07-00 Write address Read address Write data Cycle extended by automatic ready Figure 3.2.1c Ready timing chart The F2MC-16LX has two types of automatic ready functions for external memory. The automatic ready function automatically inserts one to three wait cycles without an external circuit under the following conditions. The function inserts the wait cycles when an access is made to a low-order address external area located between addresses 002000H and 7FFFFFH or to a high-order address external area located between addresses 800000H and FFFFFFH. This function extends the access cycle. The automatic ready function is activated by setting the LMR1/LMR0 bits (low-order address external area) or the HMR1/HMR0 bits (high-order address external area) of ARSR. In addition, the F2MC-16LX has another built-in automatic ready function for external I/O. This automatic ready function automatically inserts one to three wait cycles without an external circuit when an access is made to an external area located between addresses 0000C0H and 0000FFH. This function extends the access cycle. This automatic ready function is activated by setting the IOR1/IOR0 bits of ARSR. 44 Chapter 3: Memory MB90580 Series 3.2 External Memory Access When the RYE bit of EPCR is set to ’1,’ the wait cycle continues if an L level signal appears at the R36/RDY pin at the end of either automatic ready cycle. (3) Hold function When the HDE bit of EPCR is set to ’1,’ the external bus hold function by the P34/HRQ and P35/HAKX pins is enabled. When an H level signal is input to the P34/HRQ pin, the hold state starts at the end of the CPU instruction (at the end of processing for one element data item in the case of a string instruction), an L level signal is output from the P35/HAKX pin, and the following pins are set to high impedance: • Address output • Address/data I/O • Bus control signal P27/A23 to P20/A16 P17/D15 to P00/D00 P30/ALE, P31/RDX, P32/WRLX, P33/WRHX The above function enables the use of an external bus by a device external circuit. When an L level signal is input to the P34/HRQ pin, an H level signal is output from the P35/HAKX pin, the external pin status is restored, and the CPU resumes operation. In the STOP state, no hold request input is accepted. ■ Hold timing (in external bus 16-bit mode) Read cycle Hold cycle Write cycle P37/CLK P34/HRQ P35/HAKX P33/WRHX P32/WRLX P31/RDX P30/ALE 23 to 20/A19 to 16 (Address) (Address) 17 to 10/AD15 to 08 (Address) 07 to 00/AD07 to 00 (Address) Read data Write data Figure 3.2.1d Hold timing MB90580 Series Chapter 3: Memory 45 Chapter 4: Clock and Reset 4.1 Clock Generator The clock generator controls internal clock operation, including such functions as sleep, timer, stop, and PLL multiplication. This internal clock is called the machine clock, and one cycle of the machine clock is called a machine cycle. A clock based on the source oscillation is called the main clock, and a clock based on the internal VCO oscillation is called the PLL clock. Note: When the operating voltage is 5 V, the OSC source oscillation can be between 3 MHz and 16 MHz. The highest operating frequency for the CPU and peripheral resource circuits is 16 MHz, however. Normal operation is not guaranteed if a multiplication factor resulting in a higher frequency than 16 MHz is specified. For example, if the source oscillation is 16 MHz, only 1 can be specified as the multiplication factor. The lowest operating frequency of the VCO oscillation is 4 MHz, and an oscillation below 4 MHz must not be specified. S Reset Interrupt HSTX Transition to stop mode Q Machine clock Transition to timer or sleep mode R S Q R S Selecting the machine clock Q 1 R 2 3 4 PLL multiplication Selecting the oscillation stabilization wait time Time base timer 1/2 X0 1/2048 1/4 1/4 1/8 XL Selecting the watch-dog timer interval Monitoring timer Watch-dog reset Figure 4.1a Clock generator circuit block diagram 4.2 Reset Causes 4.2 Reset Causes When a reset cause occurs, F2MC-16LX terminates the currently executing processing and waits for the release of reset signal. A reset can be caused by the following factors: ❍ Power-on reset ❍ Hardware standby release ❍ Watch-dog timer overflow ❍ External reset request via RSTX pin ❍ Reset request by software Right after stop mode release or power on reset, the MCU will wait for the stabilization time before resumption of any activities. When reset occurs, F2MC-16LX will stop all operation at once and wait for the release of reset. The content of watchdog timer control register will change according to the reset cause. Thus, the cause of previous reset can be known. Note: While an external bus is used, the address generated by the device is undefined when a reset cause occurs. All external bus access signals, including RDX and WRX, become inactive. Table 4.2a Reset causes Reset Cause Machine clock Watch-dog timer Oscillation stabilization wait Power-on When the power is turned on Main clock Stop Yes Hardware standby ’L’ level input to HSTX pin Main clock Stop Yes Watch-dog timer Watch-dog timer overflow Main clock Stop Yes External pin ’L’ level input to RSTX pin Previous status maintained Previous status maintained No Software ’0’ written to RST bit of STBYC Previous status maintained Previous status maintained No * In stop or hardware standby mode, a reset input allows for oscillation stabilization time regardless of the reset cause. * The oscillation stabilization time for a power-on reset is fixed to 218 cycles of source oscillation. For other types of reset, the oscillation stabilization wait time is determined by CS1 and CS0 of the clock selection register. As shown in Figure 4.2a, each reset cause has a corresponding flip-flop. The contents of the flip-flop can be obtained by reading the watch-dog timer control register. If identifying the reset cause is required after the reset is released, ensure that the value read from the watch-dog timer control register is processed by software and processing branches to an appropriate program. 48 Chapter 4: Clock and Reset MB90580 Series 4.2 Reset Causes HSTX pin RSTX pin RSTX=L HSTX=LÆH Without periodic clear Power on RST bit set Hardware standby release detection circuit Power-on detection circuit S R F/F Q External reset request detection circuit S R F/F Q S R F/F Q Watch-dog timer reset detection circuit S R F/F Q S R F/F Q STBYC.RST bit write detection circuit Delay circuit WTC register WTC register read F2MC-16LX internal bus Figure 4.2a Reset cause bit block diagram Address: 0000A8H 7 6 5 4 3 2 1 0 PONR STBR WRST ERST SRST WTE WT1 WT0 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (W) (1) (W) (1) (W) (1) Read/write Initial value Bit No. WDTC Figure 4.2b WDTC (watch-dog timer control register) When there are multiple reset causes, the corresponding reset cause bits in the watch-dog timer control register are set. Therefore, if an external reset request and a watch-dog reset occur at the same time, both the ERST and WRST bits are set to 1. A power-on reset is an exception; while the PONR bit is 1, the values of other bits do not indicate the correct reset causes. Therefore, design software so that the other reset cause bit values are ignored while the PONR bit is set to 1. Table 4.2b Reset cause bits Reset cause PONR STBR WRST ERST SRST Power-on 1 Hardware standby * 1 * * * Watch-dog timer * * 1 * * External pin * * * 1 * RST bit * * * * 1 (An asterisk (*) in the table means that the previous value is maintained.) Note: A reset cause bit is cleared only by reading the watch-dog timer control register. Thus, once a reset occurs, the corresponding reset cause bit remains 1 even if another reset cause occurs. MB90580 Series Chapter 4: Clock and Reset 49 4.3 Operation after reset release 4.3 Operation after reset release When a reset cause is removed, the F2MC-16LX immediately outputs the address in which the reset vector is stored, then fetches the reset vector and mode data. The reset vector and mode data are assigned to the four bytes between FFFFDCH and FFFFDFH. After reset is released, the reset vector and mode data are transferred to the registers by the hardware as described in Figure 4.3a. Use the mode pin to specify whether to read the reset vector and mode data from internal ROM or from external memory. When the mode pin is set to external vector mode, the F2MC-16LX reads the reset vector and mode data from external memory. When using the F 2MC-16LX in single chip mode or internal ROM external bus mode, Fujitsu recommends specifying internal vector mode. The bus mode after the reset vector and mode data are read is specified by the mode data. F2MC-16LX CPU core Mode Memory space Register FFFFDFH Mode data FFFFDEH Reset vector bits 23 to 16 FFFFDDH Reset vector bits 15 to 8 FFFFDCH Reset vector bits 7 to 0 Micro ROM Reset sequence PCB PC Figure 4.3a Source and destination of reset vector and mode data 50 Chapter 4: Clock and Reset MB90580 Series Chapter 5: Watchdog Timer, Timebase Timer, and Watch Timer Functions 5.1 Outline Watch-Dog Timer The watchdog timer consists of 2-bit counter that uses to carry signal from the 18-bit timebase timer or the 15-bit watch timer as a clock source, a control register, and a watchdog reset controller. The watch-dog timer function enables detection of program surge. If the watch-dog timer is not accessed within the specified time due to, for example, a program surge, the watch-dog timer resets the system. Time Base Timer The timebase timer consists of 18-bit counter and a circuit that control interval interrupts. The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation stabilization time or the watchdog timer etc.it is counting up in synchronization to the internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from four types of 212/HCLK, 214/HCLK, 216/HCLK, and 219/HCLK. (HCLK is the main clock.) Note taht the timebase timer uses the main clock, regardless of the MCS bit and SCS bit in CKSCR. Watch Timer The watch timer consists of 15-bit counter and a circuit that controls interval interrupts. The watch timer functions as the clock source for the watchdog counter, as the timer for the subclock stabilization wait, and as an interval timer that generates interrupts at a given period. Note that the watch timer uses the sub clock, regardless of the MCS bit and SCS bit in CKSCR. 5.2 Block diagram 5.2 Block diagram Main clock TBTC TBC1 Selector TBC0 212 214 216 218 TBTRES Clock input Timebase timer TBR TBIE 214 216 217 218 S AND Q R F2MC-16 bus TBOF Timebase interrupt WDTC 2-bit counter WT1 Selector WT0 Watchdog reset generation circuit OF CLR CLR WTE To WDGRST internal reset generation circuit WTC WDCS SCE AND SCM Power-on reset /subclock stop S Q R WTC1 Selector WTC0 WTR WTIE 210 210 213 214 215 213 214 Watch timer 215 WTRES Clock input S AND Q R Subclock WTOF Clock interrupt WDTC generation STBR WRST From hardware standby control circuit ERST RSTX pin SRST From RST bit of STBYC register Figure 5.2a 52 From power-on PONR Watchdog Timer, Timebase Timer, and Watch Timer Block Diagram Chapter 5: Watchdog Timer, Timebase Timer, and Watch Timer Functions MB90580 Series 5.3 Registers and register details 5.3 Registers and register details Watch-Dog timer control register Address : 0000A8H 7 6 5 4 3 PONR STBR WRST ERST SRST WTE WT1 (R) (X) (R) (X) (R) (X) (W) (1) (W) (1) 13 12 Read/write Initial value (R) (X) (R) (X) 2 1 Bit number 0 WT0 WDTC (W) (1) Timer base timer control register 15 14 Address: 0000A9H Reserved Read/write Initial value (-) (1) TBIE (-) (-) (-) (-) (R/W) (0) 11 TBOF (R/W) (0) 10 9 TBR TBC1 (W) (1) (R/W) (0) 8 TBC0 Bit number TBTC (R/W) (0) Watch timer control register 7 6 5 4 3 2 1 Address: 0000AAH WDCS SCE WTIE WTOF WTR WTC2 WTC1 Read/write Initial value (R/W) (1) (R) (X) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) MB90580 Series 0 Bit number WTC0 WTC (R/W) (0) Chapter 5: Watchdog Timer, Timebase Timer, and Watch Timer Functions 53 5.3 Registers and register details 5.3.1 WDTC (Watch-Dog Timer Control Register) Watch-Dog timer control register Address : 0000A8H 7 6 5 4 3 PONR STBR WRST ERST SRST WTE WT1 (R) (X) (R) (X) (W) (1) (W) (1) Read/write Initial value (R) (X) (R) (X) (R) (X) 2 1 Bit number 0 WT0 WDTC (W) (1) Don’t use read-modify-write command to access this register, otherwise malfunction will occur. [bits 7 to 3] PONR, STBR, WRST, ERST, and SRST These flags indicate the reset causes. The flags are set upon a reset as described in Table 5.3.1a. All bits are cleared to '0' after the WDTC register is read. The WDTC register is a read-only register. This is a read-only register. Note that during power-on only, the contents of the bits that indicate sources other than power-on are not guaranteed. Therefore, software should be designed to ignore the other bits when the PONR bit is "1". Table 5.3.1a Reset cause registers Reset cause PONR STBR WRST ERST SRST Power-on 1 — — — — Hardware standby * 1 * * * Watch-dog timer * * 1 * * External pin * * * 1 * RST bit * * * * 1 (*: The previous value is maintained.) [bit 2] WTE While the watch-dog timer is stopped, writing '0' to this bit activates the watch-dog timer. Subsequently, writing '0' clears the watch-dog timer counter. Writing '1' has no effect. The watch-dog timer is stopped by power-on, hardware standby, or reset by watch-dog timer. '1' is always read from this bit. [Bits 1, 0] WT1, WT0 These bits select the watchdog interval time. Only the data written when the watchdog timer is started up is valid. Data written to these bits at any time other than watchdog startup is ignored. Note that the clock that is input to the watchdog timer is selected according to the result of ANDing the WDCS bit of the WTC and the SCM bit of the LPMCR. In other words, if WDCS is set to "1", then the timebase timer output can be selected if the main clock and the PLL clock are selected, and the watch timer output can be selected if the subclock is selected. The interval time settings are shown in Table 5.3.1a. These bits are write-only bits. 54 Chapter 5: Watchdog Timer, Timebase Timer, and Watch Timer Functions MB90580 Series 5.3 Registers and register details Table 5.3.1b Watchdog Timer Interval Selection Bits WDCS/ SCM WT1 WT0 Interval Time (Source oscillation: 4 MHz) Minimum Maximum 1 0 0 Approx. 3.58 ms Approx. 4.61 ms 1 0 1 Approx. 14.33 ms Approx. 18.43 ms 1 1 0 Approx. 57.23 ms Approx. 73.73 ms 1 1 1 Approx. 458.75 ms Approx. 589.82 ms 0 0 0 Approx. 0.109 s Approx. 0.141 s 0 0 1 Approx. 0.875 s Approx. 1.125 s 0 1 0 Approx. 1.75 s Approx. 2.25 s 0 1 1 Approx. 3.5 s Approx. 4.5 s Note: The maximum interval value is the value when the time base counter or the clock counter are not reset during watchdog operation. MB90580 Series Chapter 5: Watchdog Timer, Timebase Timer, and Watch Timer Functions 55 5.3 Registers and register details 5.3.2 TBTC (Time Base Timer Control Register) Timer base timer control register 15 Address: 0000A9H Reserved Read/write Initial value (-) (1) 14 13 12 TBIE (-) (-) (-) (-) 11 TBOF (R/W) (0) (R/W) (0) 10 9 TBR TBC1 (W) (1) (R/W) (0) Bit number 8 TBC0 TBTC (R/W) (0) Note: Don’t use read-modify-write command to access this register, otherwise malfunction will occur. [bit 15] Reserved This is a reserved bit. When writing data to this register, ensure that '1' is written to this bit. [bit 12] TBIE This bit is used to enable interval interrupts based on the time base timer. Writing '1' to this bit enables interrupts, and writing '0' disables interrupts. This bit is initialized to '0' upon a reset. This bit is readable and writable. [bit 11] TBOF This is an interrupt request flag for the time base timer. While the TBIE bit is '1,' an interrupt request is issued when '1' is written to TBOF. This bit is set to '1' for each interval specified with the TBC1 and TBC0 bits. This bit is cleared by writing '0,' by switching to stop or hardware standby mode, or by a reset. Writing '1' has no effect. 1' is always read by a read-modify-write instruction. [bit 10] TBR This bit clears all bits of the time base timer counter to '0.' Writing '0' clears the time base counter. Writing '1' has no effect. '1' is always read from this bit. Note: Time base timer interrupt should be masked by either TBIE bit or ILM bit of CPU before clearing the TBOF bit. [bits 9 and 8] TBC1 and TBC0 These bits are used to set the time base timer interval. Table 5.3.2a Selecting the time base timer interval 56 TBC1 TBC0 Interval at 4 MHz source oscillation Machine Clock Cycle 0 0 1.024 ms 212 cycle 0 1 4.096 ms 214 cycle 1 0 16.384 ms 216 cycle 1 1 131.072 ms 219 cycle Chapter 5: Watchdog Timer, Timebase Timer, and Watch Timer Functions MB90580 Series 5.3 Registers and register details 5.3.3 Watch Timer Control Register (WTC) Watch timer control register 7 6 5 4 3 2 1 Address: 0000AAH WDCS SCE WTIE WTOF WTR WTC2 WTC1 Read/write Initial value (R/W) (1) (R) (X) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) 0 Bit number WTC0 WTC (R/W) (0) [Bit 7] WDCS This bit selects whether to use the clock signal from the watch timer or from the timebase timer for the watchdog timer input clock when the main clock and PLL clock are selected. When this bit is "0", the clock signal from the watch timer is selected; when this bit is "1", the clock signal from the timebase timer is selected. In short, if WDCS is set to "1", then the timebase timer output can be selected if the main clock and the PLL clock are selected, and the watch timer output can be selected if the subclock is selected. This bit is initialized to "1" by a power-on reset. Note: When WDCS is set to "1", because the timebase timer output and the watch timer output are asynchronous, there is a possibility that the watchdog timer count may advance. Therefor, when WDCS is set to "1", it is necessary to clear the watchdog timer before and after changing the clock mode. [Bit 6] SCE This bit indicates that the subclock oscillation stabilization waiting period has elapsed. When this bit is "0", it indicates that the oscillation stabilization period is currently in progress. The oscillation stabilization period is fixed at 214cycles (subclock). This bit is initialized to "0" by a power-on reset and by stopping. [Bit 5] WTIE This bit enables interval interrupts by the watch timer. When this bit is set to "1", interrupts are enabled; when set to "0", interrupts are disabled. This bit is initialized to "0" by a reset. This bit can be read and written. [Bit 4] WTOF This bit is the watch timer interrupt request flag. When the WTIE bit is "1", an interrupt request is generated if WTOF is set to "1". This bit is set to "1" at the intervals set by the WTC1 and WTC0 bits. This bit is cleared by writing a "0", by switching to stop mode or hardware standby mode, and by a reset. Writing "1" to this bit has no meaning. When this bit is read by a read-modify-write instruction, a "1" is read. [Bit 3] WTR This bit clears all of the watch timer counter bits to "0". The clock counter is cleared by writing a "0" to this bit. Writing "1" to this bit has no meaning. Reading this bit returns a "1". [Bits 2, 1, 0] WTC2, WTC1, WTC0 These bits set the watch timer interval. The interval settings are shown in Table 5.3.3a. These bits are initialized to "000" by a reset. These bits can be read and written. When writing these bits, clear bit 4 (WTOF) at the same time. MB90580 Series Chapter 5: Watchdog Timer, Timebase Timer, and Watch Timer Functions 57 5.3 Registers and register details Table 5.3.3a Watch Timer Interval Selection 58 WTC2 WTC1 WTC0 Interval time when subclock is 32 kHz 0 0 0 15.625 ms 0 0 1 31.25 ms 0 1 0 62.5 ms 0 1 1 0.125 s 1 0 0 0.250 s 1 0 1 0.500 s 1 1 0 1.000 s 1 1 1 – Chapter 5: Watchdog Timer, Timebase Timer, and Watch Timer Functions MB90580 Series 5.4 Operation 5.4 Operation 5.4.1 Watch-Dog Timer The watch-dog timer function enables detection of program surge. If the watch-dog timer is not accessed within the specified time due to, for example, a program surge, the watch-dog timer resets the system. (1) Activation The watch-dog timer is activated by writing ’0’ to the WTE bit of the WTC register while the watch-dog timer is stopped. At the same time, the WT1 and WT0 bits are used to set the watch-dog timer reset interval. Only the interval setting specified during activation is valid. (2) Watch-dog counter Once the watch-dog timer is activated, the watch-dog timer counter must be periodically cleared within the program. Writing ’0’ to the WTE bit of the WTC register clears the watch-dog counter. The watch-dog counter consists of a two-bit counter which uses the carry signals of the time base counter as a clock source. Therefore, the watch-dog reset time may become shorter than the setting if the time base counter is cleared. Figure 5.4.1a is a diagram of the watch-dog timer operation. Time base Watch-dog 00 01 10 00 01 10 11 00 WTE write Watch-dog activation Watch-dog clear Watch-dog reset Figure 5.4.1a Watch-dog timer operation (3) Watch-dog stop Once activated, the watch-dog timer is initialized and stopped only by power-on, hardware standby, or reset by watch-dog. Reset by an external pin or software merely clears the watch-dog counter without stopping the watch-dog function. (4) Others The watch-dog counter is cleared by a reset, transition to sleep or stop mode, or hold acknowledgment signal in addition to writing the WTE bit. MB90580 Series Chapter 5: Watchdog Timer, Timebase Timer, and Watch Timer Functions 59 5.4.2 Time Base Timer The time base timer functions as a watch-dog timer clock source, timer for waiting for the oscillation to stabilize, and interval timer for generating interrupts at specified intervals. (1) Time base counter The time base counter consists of an 18-bit counter for a clock generated by dividing the source oscillation input by two. This clock is used to generate the machine clock. While the source oscillation is input, the time base counter keeps counting. The time base counter is cleared by a power-on reset, transition to stop or hardware standby mode, shifting from the main clock to the PLL clock through the setting of the MCS bit in the CKSCR register, shifting from the main clock to the subclock through the setting of the SCS bit in the CKSCR register, or writing ’0’ to the TBR bit of the TBTC register. (2) Interval interrupt function Interrupts are generated at specified intervals according to the carry signals of the time base counter. The TBOF flag is set at the intervals specified with the TBC1 and TBC0 bits of the TBTC register. The flag is written to reference to the time at which the time base timer is cleared last. If a shift is made from the main clock mode to the PLL clock mode, the timebase timer is cleared, since it is used as the timer for the PLL clock oscillation stabilization waiting period. In addition, if a shift is made from the main clock mode to the subclock mode, the timebase timer is cleared, since it is used as the timer for the main clock oscillation stabilization waiting period. Upon transition to stop or hardware standby mode, the time base timer is used as a timer for waiting for the oscillation to stabilize upon recovery. Therefore, the TBOF flag is immediately cleared upon mode transition. 5.4.3 Watch Timer The watch timer functions as the clock source for the watchdog counter, as the timer for the subclock stabilization wait, and as an interval timer that generates interrupts at a given period. (1) Watch timer The watch timer is a 15-bit counter that counts the source oscillation input which is used to generate the machine clock. The watch timer always continues its counting operation as long as the source oscillation is being input. The watch timer is cleared by: power-on reset, shifting to stop mode or hardware standby mode, and writing "0" to the WTR bit in the WTC register. The watchdog counter and the interval interrupts, both of which utilize the watch timer output, are affected by the watch timer being cleared. (2) Interval interrupt function This function generates interrupts at a given period based on the clock counter carry signal. This function sets the WTOF flag at a regular interval, which is set by the WTC1 and WTC0 bits in the WDTC register. The timing for the setting of this flag is based on the time when the watch timer was last cleared. If a shift is made to stop mode or hardware standby mode, the WTOF flag is cleared at the same time as the mode shift, since the watch timer is used for the oscillation stabilization waiting period during recovery. Chapter 6: Low Power Control Circuit 6.1 Outline The following are the operating modes: PLL clock mode, PLL sleep mode, PLL watch mode, pseudo-watch mode, main clock mode, main sleep mode, main watch mode, main stop mode, subclock mode, sub sleep mode, sub watch mode, sub stop mode, and hardware standby mode. Aside from the PLL clock mode, all of the other operating modes are low power consumption modes. In main clock mode and main sleep mode, only the main clock (main OSC oscillation clock) and the subclock (sub OSC oscillation clock) operate. In these modes, the main clock divided by two is used as the operation clock, the subclock (sub OSC oscillation clock) is used as the watch clock, and the PLL clock (VCO oscillation clock) is stopped. In subclock mode and sub sleep mode, only the subclock (sub OSC oscillation clock) operates. The subclock is used as the operation clock, and the main clock and the PLL clock are stopped. In PLL sleep mode and main sleep mode, only the CPU’s operation clock is stopped, all clocks other than the CPU clock operate. In pseudo-watch mode, only the watch timer and the timebase timer operate. In PLL watch mode, main watch mode, and sub-watch mode, only the watch timer operates. Only the subclock is in operation in this mode; the main clock and the PLL clock are stopped. (The difference among PLL watch mode, main watch mode, and sub-watch mode is that the operating mode upon recovery from an interrupt is PLL clock mode, main clock mode, or subclock mode, respectively. There are no differences in the watch mode operations.) The main stop mode, sub stop mode, and hardware standby mode stop oscillation, making it possible to retain data while consuming the least amount of power possible. (The difference between main stop mode and sub stop mode is that the operating mode upon recovery from an interrupt is main clock mode or subclock mode, respectively. There are no differences in the stop mode operations.) The CPU intermittent operation function intermittently runs the clock supplied to the CPU when accessing registers, on-chip memory, on-chip resources, and the external bus. Processing is possible with lower power consumption by reducing the execution speed of the CPU while supplying a high-speed clock to the on-chip resources. The PLL clock multiplier can be selected as either 2, 4, 6, or 8 by setting the CS1 and CS0 bits. The selected clock divided by two is used as the machine clock. The WS1 and WS0 bits can be used to set the main clock oscillation stabilization waiting period for when stop mode and hardware standby mode are released. 6.2 Block Diagram 6.2 Block Diagram CKSCR SCM SCS Subclock switching controller Subclock (OSC oscillation) PLL multiplier circuit Main clock (OSC oscillation) CKSCR F2MC-16LX Bus MCM MCS 1 2 3 CPU system clock generation 4 CPU clock CKSCR 0/9/17/33 intermittent cycle selection 1/2 S CS1 CPU clock selector CS0 LPMCR CG1 CPU intermittent operation function cycle number selection circuit CG0 LPMCR SLP SCM Peripheral system clock generation SLEEP Peripheral clock Standby MSTP Main OSC stop Control circuit STOP Sub OSC stop STP TMD RST Cancel HST start HSTX pin CKSCR WS1 Oscillation stabilization wait time selector WS0 LPMCR 24 213 215 218 Clock input Timebase timer SPL Pin high-impedance control circuit SSR Self-refresh control circuit LPMCR RST Internal reset generation circuit Interrupt request or RST 212 214 216 219 Pin HI-Z Self-refresh RSTX pin Internal RST To watchdog timer WDGRST Figure 6.2a Low-power consumption control circuit and clock generator 62 Chapter 6: Low Power Control Circuit MB90580 Series 6.3 Registers and register details 6.3 Registers and register details Clock selection register 15 14 13 Address: 0000A1H SCM MCM Read/write Initial value (R) (1) (R) (1) 12 11 10 9 8 WS1 WS0 SCS MCS CS1 CS0 (R/W) (1) (R/W) (1) (R/W) (1) (R/W) (1) (R/W) (0) (R/W) (0) 5 4 3 SPL RST (R/W) (0) (W) (1) Bit No. CKSCR Low power mode control register 7 Address: 0000A0H Read/write Initial value STP (W) (0) 6 SLP (W) (0) 2 1 0 TMD CG1 CG0 SSR (W) (1) (R/W) (0) (R/W) (0) (R/W) (0) Bit No. LPMCR 6.3.1 LPMCR (Low power mode control register) Low power mode control register 7 Address: 0000A0H Read/write Initial value STP (W) (0) 6 SLP (W) (0) 5 4 3 2 1 SPL RST (R/W) (0) (W) (1) 0 TMD CG1 CG0 SSR (W) (1) (R/W) (0) (R/W) (0) (R/W) (0) Bit No. LPMCR [Bit 7] STP Writing a "1" to this bit changes the mode to pseudo-watch mode (CKSCR. MCS = 0 and SCS = 1) or stop mode (CKSCR. MCS = 1 or SCS = 0). Writing a "0" to this bit has no effect. This bit is cleared to "0" by a reset, wake-up from watch or stop mode. This bit is a write-only bit. When this bit is read, "0" is always returned. [Bit 6] SLP Writing a "1’ to this bit changes the mode to sleep mode. Writing a "0" to this bit has no effect. This bit is cleared to "0" by a reset, wake-up from sleep or stop mode. If a "1’ is written to both the STP bit and the SLP bit simultaneously, the mode changes to either pseudo-watch mode or to stop mode. This bit is a write-only bit. When this bit is read, "0" is always returned. [Bit 5] SPL When this bit is "0", the level of external pins in watch mode or stop mode is retained. When this bit is "1", the external pins in watch mode or stop mode go to high-impedance. This bit is cleared to "0" by a reset. This bit can be read and written. MB90580 Series Chapter 6: Low Power Control Circuit 63 6.3 Registers and register details [Bit 4] RST Writing a "0" to this bit generates an internal reset signal in three machine cycles. Writing a "1’ to this bit has no effect. When this bit is read, a "1" is returned. [Bit 3] TMD Writing a "0" to this bit changes the mode to watch mode. Writing a "1" to this bit has no effect. This bit is set to "1" by a reset, wake-up from watch or stop mode. This bit is a write-only bit. When this bit is read, "1" is always returned. [Bits 2, 1] CG1, CG0 These bits set the number of clock pause cycles for the CPU intermittent operation function. These bits are initialized to "00" by a reset due to power-on, hardware standby, or a reset by the watchdog timer. These bits are not initialized by resets due to other sources. These bits can be read or written. Table 6.3.1a CG Bit Setting CG1 CG0 Number of CPU clock pause cycles 0 0 0 cycles (CPU clock = resource clock) 0 1 9 cycles (CPU clock: resource clock = 1: approximately 3 to 4) 1 0 17 cycles (CPU clock: resource clock = 1: approximately 5 to 6) 1 1 33 cycles (CPU clock: resource clock = 1: approximately 9 to 10) [Bit 0] SSR When this bit is set to "1", DRAMC self-refresh control is performed in sleep (main/PLL) mode, watch mode, and stop mode. This bit is cleared to "0" by a refresh. This bit can be read and written. Note: SSR has no function if there is no DRAMC on chip. 64 Chapter 6: Low Power Control Circuit MB90580 Series 6.3 Registers and register details 6.3.2 CKSCR (Clock selection register) Clock selection register 15 14 13 Address: 0000A1H SCM MCM Read/write Initial value (R) (1) (R) (1) 12 11 10 9 8 WS1 WS0 SCS MCS CS1 CS0 (R/W) (1) (R/W) (1) (R/W) (1) (R/W) (1) (R/W) (0) (R/W) (0) Bit No. CKSCR [Bit 15] SCM This bit indicates whether the main clock or the subclock is selected as the machine clock. When this bit is "0", it indicates that the subclock is selected; when this bit is "1", it indicates that the main clock is selected. If SCS = 0 and SCM = 1, it indicates that the main clock oscillation stabilization waiting period is in progress. [Bit 14] MCM This bit indicates whether the main clock or the PLL clock is selected as the machine clock. When this bit is "0", it indicates that the PLL clock is selected; when this bit is "1", it indicates that the main clock is selected. If MCS = 0 and MCM = 1, it indicates that the PLL clock oscillation stabilization waiting period is in progress. Note that the PLL clock oscillation stabilization waiting period is fixed at 212 main clock cycles. [Bits 13, 12] WS1, WS0 These bits set the main clock oscillation stabilization waiting period upon wake-up from stop mode or hardware standby mode is released. These bits are initialized to "11" by a power-on reset; these bits are not initialized by a reset due to other sources. These bits can be read and written. Table 6.3.2a WS Bit Settings WS1 WS0 Oscillation stabilization waiting period (source oscillation at 4 MHz) 0 0 No oscillation stabilization waiting period 0 1 Approx. 1.02 ms (count of 2 14 of the source oscillation) 1 0 Approx. 8.19 ms (count of 216 of the source oscillation) 1 1 Approx. 65.54 ms (count of 218 of the source oscillation) [Bit 11] SCS This bit selects either the main clock or the subclock as the machine clock. When a "0" is written to this bit, the subclock is selected; when a "1" is written to this bit, the main clock is selected. If a "1" is written to this bit while it is "0", the oscillation stabilization waiting period for the main clock is generated; therefore, the timebase timer is automatically cleared. In addition, the subclock (as is) is used for the operation clock when the subclock is selected. (When the source oscillation is 32 kHz, the operation clock is 32 KHz.) When SCS and MCS are both set to "0", SCS takes priority and the subclock is selected. This bit is initialized to "1" by a reset due to power-on, hardware standby, the watchdog timer, an external source, or software. MB90580 Series Chapter 6: Low Power Control Circuit 65 6.3 Registers and register details [Bit 10] MCS This bit selects either the main clock or the PLL clock as the machine clock. When a "0" is written to this bit, the PLL clock is selected; when a "1" is written to this bit, the main clock is selected. If a "0" is written to this bit while it is "1", the oscillation stabilization waiting period for the PLL clock is generated; therefore, the timebase timer is automatically cleared. Note that the PLL clock oscillation stabilization waiting period is fixed at 212 main clock cycles. In addition, the main clock divided by two is used for the operation clock when the main clock is selected. (When the source oscillation is 4 MHz, the operation clock is 2 MHz.) This bit is initialized to "1" by a reset due to power-on, hardware standby, or the watchdog timer. [Bits 9, 8] CS1, CS0 These bits select the PLL clock multiplier. These bits are not initialized by a reset initiated by an external pin or the RST bit. These bits are initialized to "00" by a reset due to power-on, hardware standby, and the watchdog timer. Writing to these bits is suppressed when the MCS bit is "0". Set the MCS bit to "1" (main clock mode) first and then overwrite the CS bits. These bits can be read and written. Table 6.3.2b CS Bit Settings 66 CS1 CS0 Machine clock (source oscillation at 4 MHz) 0 0 4 MHz (operation frequency = OSC oscillation frequency) 0 1 8 MHz (operation frequency = OSC oscillation frequency × 2) 1 0 12 MHz (operation frequency = OSC oscillation frequency × 3) 1 1 12 MHz (operation frequency = OSC (3 MHz) × 4) Chapter 6: Low Power Control Circuit MB90580 Series 6.4 Operations 6.4 Operations The status of each chip block in each operating mode is shown in Table 6.4a Table 6.4a Low Power Consumption Mode Operating Statuses Transition Sub Main condition oscillation oscillation Clock CPU Peripheral s Pins Exit method Subclock SCS=0 MCS=x Operating Stopped Operating Operating Operating Operating Reset Interrupt Sub sleep SCS=0 MCS=x SLP=1 Operating Stopped Operating Stopped Operating Operating Reset Interrupt Main sleep SCS=1 MCS=1 SLP=1 Operating Operating Operating Stopped Operating Operating Reset Interrupt PLL sleep SCS=1 MCS=0 SLP=1 Operating Operating Operating Stopped Operating Operating Reset Interrupt Pseudowatch (SPL=0) SCS=1 MCS=0 STP=1 Operating Operating Stopped Stopped Stopped Maintained Reset Interrupt Pseudowatch (SPL=1) SCS=1 MCS=0 STP=1 Operating Operating Stopped Stopped Stopped HI-Z Reset Interrupt Watch (SPL=0) SCS=x MCS=x TMD=0 Operating Stopped Stopped Stopped Stopped Maintained Reset Interrupt Watch (SPL=1) SCS=x MCS=x TMD=0 Operating Stopped Stopped Stopped Stopped HI-Z Reset Interrupt Stop (SPL=0) MCS=1 or SCS=0 STP=1 Stopped Stopped Stopped Stopped Stopped Maintained Reset Interrupt Stop (SPL=1) MCS=1 or SCS=0 STP=1 Stopped Stopped Stopped Stopped Stopped HI-Z Reset Interrupt Hardware standby HSTX=L Stopped Stopped Stopped Stopped Stopped HI-Z HSTX=H MB90580 Series Chapter 6: Low Power Control Circuit 67 6.4 Operations 6.4.1 Sleep mode ● Transition to sleep mode The standby control circuit is set to sleep mode by writing a "1" to the SLP bit, a "1’ to the TMD bit, and a "0" to the STP bit in the low power consumption mode control register. In sleep mode, only the clock supplied to the CPU is stopped; in this mode, the CPU stops, but the peripheral circuits continue to operate. If an interrupt request is generated when the "1" is written to the SLP bit, the standby control circuit does not go into sleep mode. In this case, if the CPU is not accepting interrupts, the next instruction is executed; if the CPU is accepting interrupts, processing branches immediately to the interrupt processing routine. The contents of the accumulator and other dedicated registers, as well as the contents of RAM, are maintained in sleep mode. ● Releasing sleep mode The standby control circuit is used for wake-up from sleep mode when a reset signal is input or when an interrupt is generated. If a wake-up from sleep mode was done by a reset source, the device enters the reset state after wake-up from sleep mode is completed. If an interrupt request higher than level 7 is generated by a peripheral circuit, etc., while the device is in sleep mode, the standby control circuit is used for wake-up from sleep mode. Once wake-up from sleep mode is completed, the interrupt is handled in the normal manner. If the settings of the I flag, ILM bits, and the interrupt control register (ICR) are all set so that the interrupt is accepted, then the CPU executes interrupt processing. If the settings do not permit the interrupt to be accepted, then processing resumes from the instruction that follows the instruction that put the device into sleep mode. 6.4.2 Pseudo-watch mode ● Transition to pseudo-watch mode The standby control circuit is set to pseudo-watch mode by writing a "1" to the SCS bit and a "0" to the MCS bit in the clock selection register, and a "1" to the TMD bit and a "1" to the STP bit in the low power consumption mode control register. In pseudo-watch mode, all clocks stop, except for the source oscillation (main and sub), the watch timer, and the timebase timer. Practically all chip functions cease. In addition, the SPL bit in the low power consumption mode control register can be used to control whether I/O pins maintain their previous states or go to high impedance state in pseudo-watch mode. If an interrupt request is generated when the "1" is written to the STP bit, the standby control circuit does not shift to pseudo-watch mode. The contents of the accumulator and other dedicated registers, as well as the contents of RAM, are hold in pseudo-watch mode. ● Exit from pseudo-watch mode The standby control circuit is used for exit from pseudo-watch mode when a reset signal is input or when an interrupt is generated. If an exit from pseudo-watch mode was performed by a reset source, the device enters the reset state after exit from pseudo-watch mode. When recovering from pseudo-watch mode, the standby control circuit is activated first for exit from pseudo-watch mode, and then begins waiting for the PLL clock oscillation stabilization wait time to elapse. Therefore, even if the exit from of pseudo-watch mode is due to a reset source, the main clock is used for the reset sequence. If an interrupt request higher than level 7 is generated by a peripheral circuit, etc., while the device is in pseudo-watch mode, the standby control circuit is activated for exit from pseudo-watch mode. Once exit from pseudo-watch mode is completed, the interrupt is handled in the normal manner. If the settings of the I flag, ILM bits, and the interrupt control register (ICR) are all set so that the interrupt is accepted, then the CPU executes interrupt processing. If the settings do not permit the interrupt to be accepted, then 68 Chapter 6: Low Power Control Circuit MB90580 Series 6.4 Operations processing resumes from the instruction that follows the last instruction that put the device into pseudo-watch mode. 6.4.3 Watch mode ● Transition to watch mode The standby control circuit is set to watch mode by writing a "0" to the TMD bit in the low power consumption mode control register. In watch mode, all clocks stop, except for the sub-source oscillation and the watch timer. Practically all chip functions cease. In addition, the SPL bit in the low power consumption mode control register can be used to control whether I/O pins maintain their previous states or go to high impedance state in watch mode. If an interrupt request is generated when the "1" is written to the TMD bit, the standby control circuit does not shift to watch mode. The contents of the accumulator and other dedicated registers, as well as the contents of RAM, are maintained in watch mode. ● Exit from watch mode The standby control circuit is used for exit from watch mode when a reset signal is input or when an interrupt is generated. If watch mode was released by a reset source, the device enters the reset state after exit from watch mode. When recovering from sub-watch mode, the standby control circuit is activated first for exit from watch mode, and then immediately enters subclock mode. Therefore, even if the wake-up from sub-watch mode is due to a reset source, the sub-clock is used for the reset sequence. When recovering from main watch mode or PLL watch mode, the standby control circuit is activated first for exit from watch mode, and then begins waiting for the main clock oscillation stabilization period to elapse. Therefore, even if the exit from watch mode is due to a reset source, the sub-clock is used for the reset sequence. If an interrupt request higher than level 7 is generated by a peripheral circuit, etc., while the device is in watch mode, the standby control circuit is activated for exit from watch mode. Once exit from watch mode is completed, the interrupt is handled in the normal manner. If the settings of the I flag, ILM bits, and the interrupt control register (ICR) are all set so that the interrupt is accepted, then the CPU executes interrupt processing. If the settings do not permit the interrupt to be accepted, then processing resumes from the instruction that follows the last instruction that put the device into watch mode. 6.4.4 Stop mode ● Transition to stop mode The standby control circuit is set to stop mode by writing a "0" to the SCS bit and a "1" to the MCS bit in the clock selection register, and a "1" to the STP bit in the low power consumption mode control register. In stop mode, all oscillation sources (sub and main) stop. All chip functions cease. As a result, data can be retained with the barest minimum of power consumption. In addition, the SPL bit in the LPMCR can be used to control whether I/O pins maintain their previous states or go to high impedance state in stop mode. If an interrupt request is generated when the "1" is written to the STP bit, the standby control circuit does not go into stop mode. The contents of the accumulator and other dedicated registers, as well as the contents of RAM, are maintained in stop mode. MB90580 Series Chapter 6: Low Power Control Circuit 69 6.4 Operations ● Exiting stop mode The standby control circuit releases stop mode when a reset signal is input or when an interrupt is generated. If stop mode was released by a reset source, the device enters the reset state after stop mode is released. When recovering from sub-stop mode, the standby control circuit first begins waiting for the sub-clock oscillation stabilization waiting period to elapse, and then exits stop mode. Therefore, even if the exit from stop mode is due to a reset source, the reset sequence is executed after the sub-clock oscillation stabilization waiting period elapses. When recovering from main stop mode, the standby control circuit first begins waiting for the main clock oscillation stabilization waiting period to elapse, and then exits stop mode. Therefore, even if the exit from stop mode is due to a reset source, the reset sequence is executed after the main clock oscillation stabilization waiting period elapses. If an interrupt request higher than level 7 is generated by a peripheral circuit, etc., while the device is in stop mode, the standby control circuit exits stop mode. After exit from sub-stop mode, and after the sub-clock oscillation stabilization waiting period has elapsed, the interrupt is handled in the normal manner. If the settings of the I flag, ILM bits, and the interrupt control register (ICR) are all set so that the interrupt is accepted, then the CPU executes interrupt processing. If the settings do not permit the interrupt to be accepted, then processing resumes from the instruction that follows the last instruction that put the device into stop mode. After exit from main stop mode, and after the main clock oscillation stabilization waiting period (specified by the WS1 and WS0 bits in the CKSCR) has elapsed, the interrupt is handled in the normal manner. If the settings of the I flag, ILM bits, and the interrupt control register (ICR) are all set so that the interrupt is accepted, then the CPU executes interrupt processing. If the settings do not permit the interrupt to be accepted, then processing resumes from the instruction that follows the last instruction that put the device into stop mode. 6.4.5 Hardware standby mode ● Transition to hardware standby mode By setting the HSTX pin to low level, it is possible to set the standby control circuit to hardware standby mode, regardless of the current status. In hardware standby mode, oscillation stops and all I/O pins go to high impedance as long as the HSTX pin is low, regardless of any other statuses, including resets. Although the contents of internal RAM are maintained in hardware standby mode, the accumulator and other dedicated registers are all initialized. ● Waking up from hardware standby mode Wake-up from hardware standby mode can only be executed through the HSTX pin. When the HSTX pin goes high, the standby control circuit is activated for wake-up from hardware standby mode and the device begins waiting for oscillation stabilization after the internal reset signal is enabled. After the main clock oscillation stabilization waiting period elapses, the standby control circuit releases the internal reset, after which the CPU begins execution, starting from the reset sequence. 6.4.6 CPU intermittent operation function The CPU intermittent operation function regularly stops the clock supplied to the CPU for a given period of time when accessing registers, on-chip memory, on-chip resources, and the external bus, delaying the start of the internal bus cycle. Processing is possible with lower power consumption by reducing the execution speed of the CPU while supplying a high-speed clock to the on-chip resources. The CG1 and CG0 bits select the number of pause cycles in the clock supplied to the CPU. Note that the same clock is used for external bus operations as for resources. 70 Chapter 6: Low Power Control Circuit MB90580 Series 6.4 Operations In addition, the instruction execution time when the CPU intermittent operation function is used can be calculated by adding a compensation factor (the number of register, on-chip memory, on-chip resource, and external bus access multiplied by the number of pause cycles) to the normal execution time. Peripheral clock CPU clock Intermittent operation pause cycle Internal bus activation cycle 6.4.7 Setting the main clock oscillation stabilization waiting period The WS1 and WS0 bits can be used to set the main clock oscillation stabilization waiting period for wakeup from stop mode and hardware standby mode. The oscillation stabilization waiting period should be set in accordance with the type and characteristics of the oscillation circuit and oscillator connected to the X0 and X1 pins. These bits are not initialized in the event of a reset, except for a power-on reset. If a power-on reset is generated, these bits are initialized to "11". Therefore, when power is first applied, the main clock osciloscillalation stabilization waiting period is set to approximately a count of 2 18 pulses of the source tion. 6.4.8 Switching the machine clock ● Main clock/PLL clock switching Switching between the main clock and the PLL clock is accomplished by writing to the MCS bit in the CKSCR register. If the MCS bit is overwritten from a "1" to a "0", the machine clock switches from the main clock to the PLL clock, once the PLL clock oscillation stabilization waiting period passes (211machine clocks). If the MCS bit is overwritten from a "0" to a "1", the machine clock switches from the PLL clock to the main clock, at the point when the edges of the PLL clock and the main clock match (after 1 to 8 PLL clocks). Because the machine clock does not switch immediately after the MCS bit is overwritten, when performing operations on resources that depend on the machine clock, always reference the MCM bit and make sure that the machine clock was switched before performing the operation on the resource. ● Main clock/sub-clock switching Switching between the main clock and the sub-clock is accomplished by writing to the SCS bit in the CKSCR register. If the SCS bit is overwritten from a "1" to a "0", the machine clock switches from the main clock to the subclock when the sub-clock edge is detected. If the SCS bit is overwritten from a "0" to a "1", the machine clock switches from the sub-clock to the main clock after the main clock oscillation stabilization waiting period elapses. Because the machine clock does not switch immediately after the SCS bit is overwritten, when performing operations on resources that depend on the machine clock, always reference the SCM bit and make sure that the machine clock was switched before performing the operation on the resource. MB90580 Series Chapter 6: Low Power Control Circuit 71 6.4 Operations ● Machine clock initialization The MCS bit and the SCS bit are not initialized by a reset caused by an external pin or the RST bit. After other types of resets, these bits are each initialized to "1". Figure 6.4.8a and Figure 6.4.8b show the clock selection state diagram. Power on Main SCS=1, MSC=1 SCM=1,MCM=1 CS1/0=xx Main ⇒ PLLx SCS=1, MSC=0 SCM=1,MCM=1 CS1/0=xx (1) (7) (7) (7) (9) Sub ⇒ PLLx SCS=1, MSC=0 SCM=0,MCM=1 CS1/0=xx PLL1 ⇒ Main SCS=0orMSC=1 SCM=1,MCM=0 CS1/0=00 (3) PLL1 multiplier (6) SCS=1, MSC=0 SCM=1,MCM=0 CS1/0=00 (4) PLL2 ⇒ Main SCS=0orMSC=1 SCM=1,MCM=0 CS1/0=01 (8) (8) (2) (7) PLL3 ⇒ Main SCS=0orMSC=1 (6) SCM=1,MCM=0 CS1/0=10 PLL2 multiplier (6) SCS=1, MSC=0 SCM=1,MCM=0 CS1/0=01 (5) PLL3 multiplier SCS=1, MSC=0 SCM=1,MCM=0 CS1/0=10 (8) Main ⇒ Sub SCS=1, MSC=x MCM=1 SCM=1 PLL4 ⇒ Main SCS=0orMSC=1 (6) (8) SCM=1,MCM=0 CS1/0=11 (1) MCS bit clear and SCS bit set (2) Completion of PLL clock oscillation stabilization wait and CS1/0 = 00 (3) Completion of PLL clock oscillation stabilization wait and CS1/0 = 01 (4) Completion of PLL clock oscillation stabilization wait and CS1/0 = 10 (5) Completion of PLL clock oscillation stabilization wait and CS1/0 = 11 (6) MCS bit set and SCS bit clear (7) PLL clock and main clock synchronization timing and SCS = 1 (8) PLL clock and main clock synchronization timing and SCS = 0 (9) Completion of main clock oscillation stabilization wait MCS = 0 PLL4 multiplier SCS=1, MSC=0 SCM=1,MCM=0 CS1/0=11 Figure 6.4.8a Clock Selection State Transition Diagram (1) 72 Chapter 6: Low Power Control Circuit MB90580 Series 6.4 Operations Power on Main SCS=1, MSC=1 SCM=1 MCM=1 Main ⇒ Sub SCS=0 SCM=1 MCM=1 (1) (4) PLLx ⇒ Sub SCS=0, MSC=x SCM=1,MCM=0 CS1/0=xx (5) Main ⇒ PLLx SCS=1, MSC=0 SCM=1, MCM=1 CS1/0=xx (6) (2) Sub ⇒ Main SCS=1 SCM=0 MCM=1 (3) Sub SCS=0 SCM=0 MCM=1 (1) SCS bit clear (2) Subclock edge detection timing (3) SCS bit set (4) Completion of main clock oscillation stabilization wait and MCS = 1 (5) PLL clock and main clock synchronization timing and SCS = 0 (6) Completion of main clock oscillation stabilization wait and MCS = 0 Figure 6.4.8b Clock Selection State Transition Diagram (2) 6.4.9 State transition Figure 6.4.9a to Figure 6.4.9d show the state transitions in low power consumption mode. In order to keep the state transition diagrams simple, they depict simultaneously occurring events as occurring in stages. In actuality, however, state transitions occur immediately. For example, when MCS is set to "1" and SLP is set to "1" simultaneously in PLL clock mode, the state transition diagrams show the mode changing once to PM transition mode and then to PM transition sleep, but in actuality, the mode changes immediately from PLL clock mode to PM transition sleep. In addition, when a reset occurs in sub sleep mode, the state transition diagrams show the mode changing once to sub mode and then to the main oscillation stabilization period, but in actuality, the mode shifts immediately from sub sleep mode to the main oscillation stabilization period. MB90580 Series Chapter 6: Low Power Control Circuit 73 6.4 Operations MCS: MCS bit (clock selection register) (PLL clock mode is selected when MCS = 0) SCS: SCS bit (clock selection register) (sub-clock mode is selected when SCS = 0) STP: STP bit (low power consumption mode register) (sleep mode is selected when SLP = 0) SLP: SLP bit (low power consumption mode register) (sleep mode is selected when SLP = 0) TMD: TMD bit (low power consumption mode register) (watch mode is selected when TMD = 0) MCM: MCM bit (clock selection register) (PLL clock is in use when MCM = 0) SCM: SCM bit (clock selection register) (sub-clock is in use when SCM = 0) SCD: Sub-clock oscillation stopped (sub-clock oscillation is stopped when SCD = 1) MCD: Main clock oscillation stopped (main clock oscillation is stopped when MCD = 1) PCD: PLL clock oscillation stopped (PLL clock oscillation is stopped when PCD = 1) Table 6.4.9a List of Transition Conditions State before transition Transition conditions 01 Main oscillation stabilization waiting period completed Main mode Main oscillation stabilization 05 Main oscillation stabilization waiting period completed Main mode 06 SCS = 0 written MS transition mode Main mode PLL mode 07 SCS = 1•MCS = 0 written MP transition mode 31 TMD = 1•STP = 0•SLP = 1 written Main sleep 32 TMD = 0 written Main watch transition 33 TMD = 1•STP = 1 written Main stop PM transition mode 21 SCS = 0 written PS transition mode 20 SCS = 1•MCS = 1 written PM transition mode 59 TMD = 1•STP = 0•SLP = 1 written PLL sleep 58 TMD = 0 written PLL watch transition P 57 TMD = 1•STP = 1 written Pseudo-watch transition 10 SCS = 1•MCS = 1 written SM transition mode 12 SCS = 1•MCS = 0 written SP transition mode 11 Reset initiated Main oscillation stabilization 42 TMD = 1•STP = 0•SLP = 1 written Sub-sleep 43 TMD = 0 written Sub-watch 44 TMD = 1•STP = 1 written Sub-stop Sub mode 74 State after transition Power on 13 PLL → main switching timing wait completed Main mode 38 TMD = 1•STP = 0•SLP = 1 written PM transition sleep 39 TMD = 0 written and PLL → main switching timing wait completed Main watch transition 40 TMD = 1 and STP = 1 written and PLL → main switching timing wait completed Main stop Chapter 6: Low Power Control Circuit MB90580 Series 6.4 Operations Table 6.4.9a List of Transition Conditions (Continued) State before transition SM transition mode Transition conditions State after transition 02 Main oscillation stabilization waiting period completed Main mode 03 Reset initiated or interrupt Main oscillation stabilization 04 SCS = 0 written Sub mode 27 TMD = 1•STP = 0•SLP = 1 written SM transition sleep 28 TMD = 0 and main oscillation stabilization waiting period completed Main watch 29 TMD = 1 and STP = 1 written and main oscillation stabilization waiting period completed Main stop 16 PLL oscillation stabilization waiting period completed MP transition mode SP transition mode 14 SCS = 1•MCS = 1 written Main mode 15 SCS = 0 written MS transition mode 68 TMD = 1•STP = 0•SLP = 1 written MP transition sleep 70 TMD = 0 written PLL watch transition M 69 TMD = 1•STP=1 written Pseudo-watch mode 17 Main oscillation stabilization waiting period completed MP transition mode 18 MCS = 1 written SM transition mode 19 Reset initiated Main oscillation stabilization 75 TMD = 1•STP = 0•SLP = 1 written SP transition sleep 76 TMD = 0 written PLL watch 78 TMD = 1 and STP = 1 written and main oscillation stabilization waiting period completed MS transition mode PS transition mode Main sleep SM transition sleep PM transition sleep PLL sleep MP transition sleep SP transition sleep Sub-sleep MB90580 Series PLL mode Pseudo-watch mode 09 Main → sub-clock switching timing wait completed Sub mode 08 Reset initiated Main mode 51 TMD = 1•STP = 0•SLP = 1 written MS transition sleep 52 TMD = 0 written and main → sub switching wait completed Sub watch 53 TMD = 1 and STP = 1 written and main → sub switching wait completed Sub mode 23 PLL → main clock switching timing wait completed MS transition mode 22 SCS = 1 written PM transition mode 56 TMD = 1•STP = 0•SLP = 1 written PS transition sleep 26 Interrupt or reset initiated Main mode 24 Main oscillation stabilization waiting period completed Main sleep 25 Interrupt or reset initiated SM transition mode 34 PLL → main clock switching timing wait completed Main sleep 35 Interrupt or reset initiated PM transition mode 63 Interrupt or reset initiated PLL mode 66 PLL oscillation stabilization waiting period completed PLL sleep 67 Interrupt or reset initiated MP transition mode 73 Main oscillation stabilization waiting period completed MP transition sleep 74 Interrupt or reset initiated SP transition mode 46 Interrupt or reset initiated Sub mode Chapter 6: Low Power Control Circuit 75 6.4 Operations Table 6.4.9a List of Transition Conditions (Continued) State before transition MS transition sleep PS transition sleep Transition conditions 49 Main → sub-clock switching timing wait completed Sub-sleep 50 Interrupt or reset initiated MS transition mode 54 PLL → main clock switching timing wait completed MS transition sleep 55 Interrupt or reset initiated PS transition mode 30 Interrupt or reset initiated SM transition mode 36 Main → sub-clock switching timing wait completed Main watch 37 Interrupt or reset initiated Main mode PLL watch 77 Interrupt or reset initiated SP transition mode PLL watch transition M 72 Main → sub-clock switching timing wait completed PLL watch Main watch Main watch transition PLL watch transition P 71 Interrupt or reset initiated MP transition mode 65 PLL → main clock switching timing wait completed PLL watch transition M 64 Interrupt or reset initiated PLL mode Sub watch 47 Interrupt or reset initiated Sub mode Main stop 41 Interrupt or reset initiated Main oscillation stabilization Pseudo-watch 62 Interrupt or reset initiated MP transition mode Pseudo-watch transition 61 PLL → main clock switching timing wait completed Pseudo-watch mode 60 Interrupt or reset initiated PLL mode 48 Interrupt Sub oscillation stabilization 79 Reset initiated Main oscillation stabilization Sub stop Sub oscillation stabilization 76 State after transition 45 Subclock oscillation stabilization waiting period completed Chapter 6: Low Power Control Circuit 80 Reset initiated Sub mode Main oscillation stabilization MB90580 Series 6.4 Operations State Transition Diagrams Power-on reset SCS=1, MCS=1, STP=0, SLP=0, TMD=1 SCM=1, MCM=1, SCD=0, MCD=0, PCD=1 SM transition mode 02 SCS=1, MCS=1, STP=0, SLP=0, TMD=1 SCM=0, MCM=1, SCD=0, MCD=0, PCD=1 03 Main oscillation stabilization period SCS=1, MCS=1, STP=0, SLP=0, TMD=1 SCM=1, MCM=1, SCD=0, MCD=0, PCD=1 04 05 01 10 Main mode SCS=1, MCS=1, STP=0, SLP=0, TMD=1 SCM=1, MCM=1, SCD=0, MCD=0, PCD=1 11 Sub mode SCS=0, MCS=x, STP=0, SLP=0, TMD=1 SCM=0, MCM=1, SCD=0, MCD=1, PCD=1 MS transition mode 06 08 SCS=1, MCS=x, STP=0, SLP=0, TMD=1 SCM=1, MCM=1, SCD=0, MCD=0, PCD=1 09 07 12 13 18 15 PM transition mode SCS=1, MCS=1, STP=0, SLP=0, TMD=1 SCM=1, MCM=0, SCD=0, MCD=0, PCD=0 14 19 MP transition mode SP transition mode SCS=1, MCS=0, STP=0, SLP=0, TMD=1 SCM=1, MCM=1, SCD=0, MCD=0, PCD=0 SCS=1, MCS=0, STP=0, SLP=0, TMD=1 SCM=0, MCM=1, SCD=0, MCD=0, PCD=1 17 16 23 20 PLL mode SCS=1, MCS=0, STP=0, SLP=0, TMD=1 SCM=1, MCM=0, SCD=0, MCD=0, PCD=0 PS transition mode 22 21 SCS=1, MCS=x, STP=0, SLP=0, TMD=1 SCM=1, MCM=0, SCD=0, MCD=0, PCD=0 Figure 6.4.9a Low Power Consumption Mode Transition Diagram A MB90580 Series Chapter 6: Low Power Control Circuit 77 6.4 Operations Main sleep SCS=1, MCS=1, STP=0, SLP=1, TMD=1 SCM=1, MCM=1, SCD=0, MCD=0, PCD=1 SM transition sleep SCS=1, MCS=1, STP=0, SLP=1, TMD=1 SCM=0, MCM=1, SCD=0, MCD=0, PCD=1 24 26 25 27 SM transition mode 31 28 SCS=1, MCS=1, STP=0, SLP=0, TMD=1 SCM=0, MCM=1, SCD=0, MCD=0, PCD=1 30 Main watch SCS=1, MCS=1, STP=0, SLP=0, TMD=0 SCM=0, MCM=1, SCD=0, MCD=1, PCD=1 32 03 29 Main mode SCS=1, MCS=1, STP=0, SLP=0, TMD=1 SCM=1, MCM=1, SCD=0, MCD=0, PCD=1 33 34 36 37 PM transition sleep Main watch transition SCS=1, MCS=1, STP=0, SLP=1, TMD=1 SCM=1, MCM=0, SCD=0, MCD=0, PCD=0 SCS=1, MCS=1, STP=0, SLP=0, TMD=0 SCM=1, MCM=1, SCD=0, MCD=0, PCD=1 35 05 Main oscillation stabilization time SCS=1, MCS=1, STP=0, SLP=0, TMD=1 SCM=1, MCM=1, SCD=0, MCD=0, PCD=1 16 38 PM transition mode SCS=1, MCS=1, STP=0, SLP=0, TMD=1 SCM=1, MCM=0, SCD=0, MCD=0, PCD=0 39 40 20 Main stop SCS=1, MCS=1, STP=1, SLP=0, TMD=1 SCM=1, MCM=1, SCD=1, MCD=1, PCD=1 41 Figure 6.4.9b Low Power Consumption Mode Transition Diagram B 78 Chapter 6: Low Power Control Circuit MB90580 Series 6.4 Operations Sub mode SCS=0, MCS=x, STP=0, SLP=0, TMD=1 SCM=0, MCM=1, SCD=0, MCD=1, PCD=1 45 44 42 Sub oscillation stabilization time SCS=0, MCS=x, STP=0, SLP=0, TMD=1 SCM=0, MCM=1, SCD=0, MCD=1, PCD=1 80 Main oscillation stabilization time SCS=1, MCS=x, STP=0, SLP=0, TMD=1 SCM=1, MCM=1, SCD=0, MCD=0, PCD=1 43 46 48 Sub sleep SCS=0, MCS=x, STP=0, SLP=1, TMD=1 SCM=0, MCM=1, SCD=0, MCD=1, PCD=1 47 49 Sub watch SCS=0, MCS=x, STP=0, SLP=0, TMD=0 SCM=0, MCM=1, SCD=0, MCD=1, PCD=1 79 Sub stop SCS=0, MCS=x, STP=1, SLP=0, TMD=1 SCM=0, MCM=1, SCD=1, MCD=1, PCD=1 52 MS transition sleep SCS=0, MCS=x, STP=0, SLP=1, TMD=1 SCM=1, MCM=1, SCD=0, MCD=0, PCD=1 51 50 MS transition mode 53 SCS=0, MCS=x, STP=0, SLP=0, TMD=1 SCM=1, MCM=1, SCD=0, MCD=0, PCD=1 23 54 PM transition sleep SCS=0, MCS=x, STP=0, SLP=1, TMD=1 SCM=1, MCM=0, SCD=0, MCD=0, PCD=0 56 55 PM transition mode SCS=0, MCS=x, STP=0, SLP=0, TMD=1 SCM=1, MCM=0, SCD=0, MCD=0, PCD=0 Figure 6.4.9c Low Power Consumption Mode Transition Diagram C MB90580 Series Chapter 6: Low Power Control Circuit 79 6.4 Operations PLL mode SCS=1, MCS=0, STP=0, SLP=0, TMD=1 SCM=1, MCM=0, SCD=0, MCD=0, PCD=0 60 57 58 59 Pseudo-watch transition SCS=1, MCS=0, STP=1, SLP=0, TMD=1 SCM=1, MCM=1, SCD=0, MCD=0, PCD=0 61 Pseudo-watch mode SCS=1, MCS=0, STP=1, SLP=0, TMD=1 62 SCM=1, MCM=1, SCD=0, MCD=0, PCD=1 63 PLL sleep SCS=1, MCS=0, STP=0, SLP=1, TMD=1 SCM=1, MCM=0, SCD=0, MCD=0, PCD=0 PLL watch transition P SCS=1, MCS=0, STP=0, SLP=0, TMD=0 SCM=1, MCM=0, SCD=0, MCD=0, PCD=0 65 16 66 69 MS transition sleep SCS=1, MCS=0, STP=0, SLP=1, TMD=1 SCM=1, MCM=1, SCD=0, MCD=0, PCD=0 68 MP transition mode 67 73 17 SP transition sleep SCS=1, MCS=0, STP=0, SLP=1, TMD=1 SCM=0, MCM=1, SCD=0, MCD=0, PCD=1 75 74 71 SCS=10, MCS=0, STP=0, SLP=0, TMD=1 SCM=1, MCM=1, SCD=0, MCD=0, 70 PCD=0 SCS=1, MCS=0, STP=0, SLP=0, TMD=1 SCM=0, MCM=1, SCD=0, MCD=0, PCD=1 72 78 SP transition mode 77 76 PLL watch transition M SCS=1, MCS=0, STP=0, SLP=0, TMD=0 SCM=1, MCM=1, SCD=0, MCD=0, PCD=1 PLL watch SCS=1, MCS=0, STP=0, SLP=0, TMD=0 SCM=0, MCM=1, SCD=0, MCD=1, PCD=1 Figure 6.4.9d Low Power Consumption Mode Transition Diagram D 80 Chapter 6: Low Power Control Circuit MB90580 Series Chapter 7: Interrupt 7.1 Outline The F2MC-16LX has interrupt functions that terminate the currently executing processing and transfer control to another specified program when a specified event occurs. There are four types of interrupt functions: ● Hardware interrupt: .................................... Interrupt processing due to an internal resource event ● Software interrupt: ..................................... Interrupt processing due to a software event occurrence instruction 2 ● Extended intelligent I/O service (EI OS): ... Transfer processing due to an internal resource event ● Exception: .................................................. Termination due to an operation exception 7.2 Causes of Interrupt 7.2 Causes of Interrupt Table 7.2a Interrupt causes, interrupt vectors, and interrupt control registers Interrupt vector Interrupt control register IIOS clear Number Address Number Address Reset × # 08 FFFFDCH —— —— INT9 instruction × # 09 FFFFD8H —— —— Exception × # 10 FFFFD4H —— —— A/D converter ❍ # 11 FFFFD0H Time base Timer × FFFFCCH ICR00 # 12 0000B0H DTP0 (external 0) / UART3 reception completion ❍ # 13 FFFFC8H DTP1 (external 1) / UART4 reception completion ❍ FFFFC4H ICR01 # 14 0000B1H DTP2 (external 2) / UART3 transmission completion ❍ # 15 FFFFC0H DTP3 (external 3) / UART4 transmission completion ❍ FFFFBCH ICR02 # 16 0000B2H DTP4 - 7 (external 4 - 7) ❍ # 17 FFFFB8H Output compare (channel 1) ❍ FFFFB4H ICR03 # 18 0000B3H UART2 reception completion ❍ # 19 FFFFB0H UART1 reception completion ❍ FFFFACH ICR04 # 20 0000B4H Input capture (channel 3) ❍ # 21 FFFFA8H Input capture (channel 2) ❍ FFFFA4H ICR05 # 22 0000B5H Input capture (channel 1) ❍ # 23 FFFFA0H Input capture (channel 0) ❍ FFFF9CH ICR06 # 24 0000B6H 8/16-bit PPG0 counter borrow × # 25 FFFF98H 16-bit reload timer 2 - 0 ❍ FFFF94H ICR07 # 26 0000B7H Time prescalar × # 27 FFFF90H Output Compare (channel 0) ❍ FFFF8CH ICR08 # 28 0000B8H UART2 transmission completion ❍ # 29 FFFF88H PWC timer ❍ FFFF84H ICR09 # 30 0000B9H UART1 transmission completion ❍ # 31 FFFF80H 16-bit free run timer overflow ❍ FFFF7CH ICR10 # 32 0000BAH UART0 transmission completion ❍ # 33 FFFF78H 8/16-bit PPG1 counter borrow × FFFF74H ICR11 # 34 0000BBH IEBus reception completion # 35 FFFF70H ICR12 0000BCH IEBus transmission completion # 37 FFFF68H ICR13 0000BDH UART0 reception completion # 39 FFFF60H ICR14 0000BEH ICR15 0000BFH Interrupt cause Reserved × # 41 FFFF58H Delayed interrupt × # 42 FFFF54H : The interrupt request flag is cleared by the IIOS interrupt clear signal. : The interrupt request flag is cleared by the IIOS interrupt clear signal. A stop request is available. × : The interrupt request flag is not cleared by the IIOS interrupt clear signal. Note: For a resource with two interrupt causes for a single interrupt number, both interrupt request flags are cleared by the IIOS interrupt clear signal. ❍ 82 Chapter 7: Interrupt MB90580 Series 7.3 Interrupt Vector 7.3 Interrupt Vector Table 7.3a MB90580 interrupt assignment table (1/2) Vector address L Vector address M Vector address H Mode register Interrupt No. INT 0 FFFFFC H FFFFFD H FFFFFE H Unused #0 None INT 7 FFFFE0H FFFFE1H FFFFE2H Unused #7 None INT 8 FFFFDCH FFFFDDH FFFFDEH FFFFDF #8 (RESET vector) Software interrupt instruction Hardware interrupt INT 9 FFFFD8H FFFFD9H FFFFDAH Unused #9 None INT 10 FFFFD4H FFFFD5H FFFFD6H Unused #10 <Exception> INT 11 FFFFD0H FFFFD1H FFFFD2H Unused #11 A/D INT 12 FFFFCCH FFFFCDH FFFFCEH Unused #12 Time base Timer INT 13 FFFFC8H FFFFC9H FFFFCAH Unused #13 DTP0 (External interrupt #0) / UART3 reception completion INT 14 FFFFC4H FFFFC5H FFFFC6H Unused #14 DTP1 (External interrupt #1) / UART4 reception completion INT 15 FFFFC0H FFFFC1H FFFFC2H Unused #15 DTP2 (External interrupt #2) / UART3 transmission completion INT 16 FFFFBCH FFFFBDH FFFFBEH Unused #16 DTP3 (External interrupt #3) / UART4 transmission completion INT 17 FFFFB8H FFFFB9H FFFFBAH Unused #17 DTP4 - 7 (External interrupt #4 - #7) INT 18 FFFFB4H FFFFB5H FFFFB6H Unused #18 Output compare (channel 1) INT 19 FFFFB0H FFFFB1H FFFFB2H Unused #19 UART2 reception completion INT 20 FFFFACH FFFFADH FFFFAEH Unused #20 UART1 reception completion INT 21 FFFFA8H FFFFA9H FFFFAAH Unused #21 Input capture (channel 3) INT 22 FFFFA4H FFFFA5H FFFFA6H Unused #22 Input capture (channel 2) INT 23 FFFFA0H FFFFA1H FFFFA2H Unused #23 Input capture (channel 1) INT 24 FFFF9CH FFFF9DH FFFF9EH Unused #24 Input capture (channel 0) INT 25 FFFF98H FFFF99H FFFF9AH Unused #25 8/16-bit PPG0 counter borrow INT 26 FFFF94H FFFF95H FFFF96H Unused #26 16-bit reload timer 2 - 0 INT 27 FFFF90H FFFF91H FFFF92H Unused #27 Time prescalar INT 28 FFFF8CH FFFF8DH FFFF8EH Unused #28 Output compare (channel 0) INT 29 FFFF88H FFFF89H FFFF8A H Unused #29 UART2 transmission completion INT 30 FFFF84H FFFF85H FFFF86 H Unused #30 PWC timer INT 31 FFFF80H FFFF81H FFFF82 H Unused #31 UART1 transmission completion INT 32 FFFF7CH FFFF7DH FFFF7E H Unused #32 16-bit free run timer overflow INT 33 FFFF78H FFFF79H FFFF7A H Unused #33 UART0 transmission completion INT 34 FFFF74H FFFF75H FFFF76 H Unused #34 8/16 bit PPG 1 counter borrow INT 35 FFFF70H FFFF71H FFFF72 H Unused #35 IEBus reception completion INT 36 FFFF6CH FFFF6DH FFFF6E H Unused #36 None INT 37 FFFF68H FFFF69H FFFF6A H Unused #37 IEBus transmission completion INT 38 FFFF64 H FFFF65H FFFF66 H Unused #38 None INT 39 FFFF60H FFFF61H FFFF62 H Unused #39 UART0 reception completion INT 40 FFFF5CH FFFF5H FFFF5EH Unused #40 None INT 41 FFFF58H FFFF59H FFFF5A H Unused #41 (RESERVED) INT 42 FFFF54H FFFF55H FFFF56H Unused #42 Delayed interrupt MB90580 Series Chapter 7: Interrupt 83 7.4 Hardware Interrupt 7.4 Hardware Interrupt 7.4.1 Overview In response to an interrupt request signal from an internal resource, the CPU pauses current program execution and transfers control to the interrupt processing program defined by the user. This function is called the hardware interrupt function. A hardware interrupt occurs when relevant conditions are satisfied as a result of two operations: comparison between the interrupt request level and the value in the interrupt level mask register of PS of the CPU, and hardware reference to the I flag value in PS. The CPU performs the following processing when a hardware interrupt occurs: Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to the system stack. Sets ILM in the PS register. The currently requested interrupt level is automatically set. Fetches the corresponding interrupt vector value and branches to the processing indicated by that value. 7.4.2 Structure Hardware interrupts are handled by the following three sections: Internal resources ...................Interrupt enable and request bits: Used to control interrupt requests from resources. Interrupt controller...................ICR:Assigns interrupt levels and determines the priority levels of simultaneously requested interrupts. CPU ........................................I and ILM:Used to compare the requested and current interrupt levelsand to identify the interrupt enable status. Microcode:Interrupt processing step The status of these sections are indicated by the resource control registers for internal resources, the ICR for the interrupt controller, and the CCR value for the CPU. To use a hardware interrupt, set the three sections beforehand by using software. The interrupt vector table referenced during interrupt processing is assigned to addresses FFFCH to FFFFFFH in memory. These addresses are shared with software interrupts. 7.4.3 Operation An internal resource that has the hardware interrupt request function has an interrupt request flag and interrupt enable flag. The interrupt request flag indicates whether an interrupt request exists, and the interrupt enable flag indicates whether the relevant internal resource requests an interrupt to the CPU. The interrupt request flag is set when an event occurs that is unique to the internal resource. When the interrupt enable flag indicates "enable," the resource issues an interrupt request to the interrupt controller. When two or more interrupt requests are received at the same time, the interrupt controller compares the interrupt levels (IL) in ICR, selects the request at the highest level (the smallest IL value), then reports that request to the CPU. If multiple requests are at the same level, the interrupt controller selects the request with the lowest interrupt number. The relationship between the interrupt requests and ICRs is determined by the hardware. The CPU compares the received interrupt level and the ILM in the PS register. If the interrupt level is smaller than the ILM value and the I bit of the PS register is set to 1, the CPU activates the interrupt processing microcode after the currently executing instruction is completed. The CPU references the ISE bit of the ICR of the interrupt controller at the beginning of the interrupt processing microcode, checks that the ISE bit is 0 (interrupt), and activates the interrupt processing body. The interrupt processing body saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area indicated by SSB and SSP, fetches three bytes of interrupt vector and loads them onto PC and PCB, 84 Chapter 7: Interrupt MB90580 Series 7.4 Hardware Interrupt updates the ILM of PS to a level value of the received interrupt, sets the S flag, then performs branch processing. As a result, the interrupt processing program defined by the user is executed next. Figure 7.4.3a illustrates the flow from the occurrence of a hardware interrupt until there is no interrupt request in the interrupt processing program. Figure 7.4.3b is a diagram of the hardware interrupt operation flow. PS Register file F2MC-16LX bus Microcode IR ➅ I ILM Check ➄ F2MC-16L•CPU Enable FF AND ➆ PS I ILM IR : : : : ➁ Interrupt level IL Åc Level comparator ➂ Peripheral Cause FF ➀ Comparator ➃ Interrupt controller Processor status Interrupt enable flag Interrupt level mask register Instruction register Figure 7.4.3a Occurrence and release of hardware interrupt ① An interrupt cause occurs in a peripheral. ② The interrupt enable bit in the peripheral is referenced. If interrupts are enabled, the peripheral issues an interrupt request to the interrupt controller. ③ Upon reception of the interrupt request, the interrupt controller determines the priority levels of simultaneously requested interrupts. Then, the interrupt controller transfers the interrupt level of the corresponding interrupt to the CPU. ④ The CPU compares the interrupt level requested by the interrupt controller with the ILM bit of the processor status register. ⑤ If the comparison shows that the requested level is higher than the current interrupt processing level, the I flag value of the same processor status register is checked. ⑥ If the check in step ⑤ shows that the I flag indicates interrupt enable status, the requested level is written to the ILM bit. Interrupt processing is performed as soon as the currently executing instruction is completed, then control is transferred to the interrupt processing routine. ⑦When the interrupt cause of step ① is cleared by software in the user interrupt processing routine, the interrupt request is completed. MB90580 Series Chapter 7: Interrupt 85 7.4 Hardware Interrupt The time required for the CPU to execute the interrupt processing in steps ⑥ and ⑦ is shown below. Interrupt start : 24 + 6 x Table 7.4.3a machine cycles Interrupt return : 15 + 6 x Table 7.4.3a machine cycles (RETI instruction) Table 7.4.3a Compensation values for interrupt processing cycle count Address indicated by the stack pointer Cycle count compensation value External area, 8-bit data bus +4 External area, even-numbered address +1 External area, odd-numbered address +4 Internal area, even-numbered address 0 Internal area, odd-numbered address +2 I ILM IF IE ISE IL S : : : : : : : Flag in CCR CPU level register Internal resource interrupt request Internal resource interrupt enable flag EI2OS enable flag Internal resource interrupt request level Flag in CCR YES I & IF & IE =1 AND ILM > IL NO NO YES ISE = 1 Fetching and decoding next instruction Saving PS, PC, PCB, DTB, ADB, DPR, and A to SSP stack, and setting ILM=IL Extended intelligent I/O service YES INT instruction? NO Executing ordinary instruction NO String instruction repetition completed? Saving PS, PC, PCB, DTB, ADB, DPR, and A to SSP stack, and setting I=0 and ILM=IL S←1 Fetching interrupt vector YES Updating PC Figure 7.4.3b Hardware interrupt operation flow 86 Chapter 7: Interrupt MB90580 Series 7.4 Hardware Interrupt 7.4.4 Hardware Interrupt Ocurrence When Internal Resource Is Being Accessed When internal I/O area is being asscessed, the CPU will not response to hardware interrupt immediately, there will be one instruction delay. Please refer to Chapter 2, section 2.1.3 for details. 7.4.5 Interrupt Inhibit Instruction If F2MC-16LX is executing interrupt inhibit instructions, the CPU will not response to hardware interrupt request immediately, there will be one instruction delay. Please refer to Chapter 2, section 2.1.3 for details. 7.4.6 Multiple Interrupts The F2MC-16LX CPU supports multiple interrupts. If an interrupt of a higher level occurs while another interrupt is being processed, control is transferred to the high-level interrupt after the currently executing instruction is completed. After processing of the high-level interrupt is completed, the original interrupt processing is resumed. An interrupt of the same or lower level may be generated while another interrupt is being processed. If this happens, the new interrupt request is suspended until the current interrupt processing is completed, unless the ILM value or I flag is changed by an instruction. The extended intelligent I/O service cannot be activated from multiple sources; while an extended intelligent I/O service is being processed, all other interrupt requests or extended intelligent I/O service requests are suspended. 7.4.7 Register Saving In Stack Upon Interrupt Register saving upon interrupt Word (16 bits) MSB LSB H SSP (SSP value before interrupt) AH AL DPR ADB DPB PCB PC PS SSP (SSP value after interrupt) L Figure 7.4.7a Registers saved in stack 7.4.8 Precaution in Using Hardware Interrupt When there is an hardware interrupt, the interrupt request flag should be cleared before leaving the corresponding interrupt routine to avoid malfunction. Some of the resources’ interrupt request flag will be cleared automatically when certain register(s) is(are) read. In this case, please read those registers to clear the interrupt request flag before leaving the interrupt routine. MB90580 Series Chapter 7: Interrupt 87 7.5 Software Interrupt 7.5 Software Interrupt 7.5.1 Overview In response to execution of a special instruction, control is transferred from the program currently executed by the CPU to the interrupt processing program defined by the user. This is called the software interrupt function. A software interrupt occurs always when the software interrupt instruction is executed. The CPU performs the following processing when a software interrupt occurs: Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to the system stack. Sets I in the PS register. Interrupts are automatically disabled. Fetches the corresponding interrupt vector value, then branches to the processing indicated by that value. A software interrupt request issued by the INT instruction has no interrupt request or enable flag. A software interrupt request is always issued by executing the INT instruction. The INT instruction does not have an interrupt level. Therefore, the INT instruction does not update ILM. The INT instruction clears the I flag to suspend subsequent interrupt requests. 7.5.2 Structure Software interrupts are handled within the CPU: CPU ........................... Microcode: Interrupt processing step As shown in Table 7.3a, software interrupts share the same interrupt vector area with hardware interrupts. For example, interrupt request number INT 13 is used for external interrupt #0 of a hardware interrupt as well as for INT #13 of a software interrupt. Therefore, external interrupt #0 and INT #13 call the same interrupt processing routine. 88 Chapter 7: Interrupt MB90580 Series 7.5 Software Interrupt 7.5.3 Operation When the CPU fetches and executes the software interrupt instruction, the software interrupt processing microcode is activated. The software interrupt processing microcode saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area indicated by SSB and SSP. The microcode then fetches three bytes of interrupt vector and loads them onto PC and PCB, resets the I flag, and sets the S flag. Then, the microcode performs branch processing. As a result, the interrupt processing program defined by the user application program is executed next. Figure 7.5.3a illustrates the flow from the occurrence of a software interrupt until there is no interrupt request in the interrupt processing program. ➀ PS Register file I F2MC-16 bus ➁ Microcode F2MC-16L •CPU S B unit IR Queue Fetch Save Instruction bus RAM PS : Processor status I : Interrupt enable flag ILM : Interrupt level mask register IR : Instruction register B unit: Bus interface unit Figure 7.5.3a Occurrence and release of software interrupt ① The software interrupt instruction is executed. ② Special CPU registers in the register file are saved according to the microcode corresponding to the software interrupt instruction. ③The interrupt processing is completed with the RETI instruction in the user interrupt processing routine. 7.5.4 Others When the program bank register (PCB) is FFH, the CALLV instruction vector area overlaps the table of the INT #vct8 instruction. When designing software, ensure that the CALLV instruction does not use the same address as that of the #vct8 instruction. MB90580 Series Chapter 7: Interrupt 89 7.6 Extended intelligent I/O service (EI2OS) 7.6 Extended intelligent I/O service (EI2OS) 7.6.1 Overview EI2OS is a type of hardware interrupt operation that automatically transfers data between I/O and memory. Conventionally, data is transferred between I/O and memory by an interrupt processing program. EI2OS, however, enables data to be transferred as if in DMA mode. EI2OS has the following advantages over the conventional interrupt processing method: Writing a transfer program is unnecessary, thus the entire program size can be small. No internal register is used for transfer. Therefore, saving the register values is unnecessary, resulting in a higher transfer speed. I/O can stop transfer at any time. Therefore, unnecessary data is not transferred. The buffer address can be incremented, decremented, or left unupdated. The I/O address can be incremented, decremented, or left unupdated (when the buffer address is updated). At the end of EI2OS processing, the CPU automatically branches to the interrupt processing routine after setting the end condition. Therefore, the user can identify the end condition type. Figure 7.6.1a outlines the EI2OS. Memory space by IOA I/O register ••• ••• ••• ••• ••• I/O register Peripheral CPU Interrupt request ➀ ➂ ISD ➂ by ICS ➁ Interrupt control register Interrupt controller ① I/O requests transfer. ② The interrupt controller selects the by BAP descriptor. ➃ Buffer by DCT ③ The transfer source and destination are read from the descriptor. ④ Data is transferred between I/O and memory. Figure 7.6.1a Outline of extended intelligent I/O service Note: Notes:The area that can be specified by IOA is between 000000H and 00FFFFH. The area that can be specified by BAP is between 000000H and FFFFFFH. The maximum transfer count that can be specified by DCT is 65,536. 90 Chapter 7: Interrupt MB90580 Series 7.6 Extended intelligent I/O service (EI2OS) 7.6.2 Structure EI2OS is handled by the following four sections: Internal resources .................. Interrupt enable and request bits: Used to control interrupt requests from resources. Interrupt controller ICR:Assigns interrupt levels, determines the priority levels of simultaneously requested interrupts, and selects the EI2OS operation. CPU ....................................... I and ILM:Used to compare the requested and current interrupt levels and to identify the interrupt enable status. Microcode:E2OS processing step RAM ....................................... Descriptor:Describes the EI2OS transfer information. Each register is described below. (1) Interrupt control register (ICR) The interrupt control register is in the interrupt controller. This register corresponds to I/Os that have the interrupt function. This register has the following three functions: Sets the interrupt level of the corresponding peripheral. Selects whether to handle the interrupt of the corresponding peripheral as an ordinary interrupt or as an extended intelligent I/O service. Selects the extended intelligent I/O service channel. Do not access this register by a read-modify-write instruction, as doing so causes misoperation. Interrupt control register (ICR) Address : B0H–BFH Read/write Initial value Address : B0H–BFH Read/write Initial value 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1 IL0 (W) (0) (W) (0) (W) (0) (W) (0) (W) 0) (W) (1) (W) (1) (W) (1) 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 — — S1 S0 ISE IL2 IL1 IL0 (–) (X) (–) (X) (R) (0) (R) (0) (R) 0) (R) (1) (R) (1) (R) (1) Bit number when written Bit number when read Note: • ICS3 to ICS0 are valid only when EI2OS is activated. Set ISE to ’1’ to activate EI2OS, and to ’0’ not to activate it. When EI2OS is not to be activated, any value can be written to ICS3 to ICS0. * ’1’ is always read. • ICS1 and ICS0 are valid for write only. S1 and S0 are valid for read only. MB90580 Series Chapter 7: Interrupt 91 7.6 Extended intelligent I/O service (EI2OS) [bits 15 to 12] or [bits 7 to 4] ICS3 to ICS0 These bits are used to select the EI2OS channel. These bits are write-only. The value specified in these bits determines the address of the extended intelligent I/O service descriptor in memory, which is explained later. ICS is initialized upon a reset. Table 7.6.2a shows the correspondence between ICS, channel numbers, and descriptor addresses. Table 7.6.2a ICS bits, channel numbers, and descriptor addresses ICS3 ICS2 ICS1 ICS0 Selected channel Descriptor address 0 0 0 0 0 000100H 0 0 0 1 1 000108H 0 0 1 0 2 000110H 0 0 1 1 3 000118H 0 1 0 0 4 000120H 0 1 0 1 5 000128H 0 1 1 0 6 000130H 0 1 1 1 7 000138H 1 0 0 0 8 000140H 1 0 0 1 9 000148H 1 0 1 0 10 000150H 1 0 1 1 11 000158H 1 1 0 0 12 000160H 1 1 0 1 13 000168H 1 1 1 0 14 000170H 1 1 1 1 15 000178H [bits 13 and 12] or [bits 5 and 4] S0 and S1 These are EI2OS end status bits. These bits are read-only. When the EI2OS is completed, the end condition can be identified by checking the value in these bits. These bits are set to ’00’ upon a reset. Table 7.6.2b shows the relationship between the S bits and end conditions . Table 7.6.2b S bits and end conditions 92 S1 S0 0 0 Reserved 0 1 Count completion 1 0 Reserved 1 1 Resource request Chapter 7: Interrupt End condition MB90580 Series 7.6 Extended intelligent I/O service (EI2OS) [bit 11] or [bit 3] ISE This is the EI2OS enable bit. This bit can be read or written to. Upon issuance of an interrupt request, EI2OS is activated if this bit is set to ’1’ and the interrupt sequence is activated if this bit is set to ’0.’ If the EI2OS end condition is satisfied (the S1 and S0 bits are not ’00’), the ISE bit is cleared to ’0.’ If the corresponding peripheral does not have the EI2OS function, the software must set ISE to ’0.’ This bit is initialized to ’0’ upon a reset. [bits 10 to 8] or [bits 2 to 0] IL0, IL1, and IL2 These are interrupt level setting bits. Specify the interrupt level of the corresponding internal resource. These bits can be read and written to. These bits are initialized to level 7 (no interrupt) upon a reset. Table 7.6.2c describes the relationship between the interrupt level setting bits and interrupt levels. Table 7.6.2c Interrupt level setting bits and interrupt levels MB90580 Series IL2 IL1 IL0 Level 0 0 0 0 (Highest interrupt level) 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 (Lowest interrupt level) 1 1 1 7 (No interrupt) Chapter 7: Interrupt 93 7.6 Extended intelligent I/O service (EI2OS) (2)Extended intelligent I/O service descriptor (ISD) The extended intelligent I/O service descriptor exists between 000100 H and 00017FH in internal RAM, and consists of the following items: Data transfer control data Status data Buffer address pointer Figure 7.6.2a shows the configuration of the extended intelligent I/O service descriptor. H High-order 8 bits of data counter (DCTH) Low-order 8 bits of data counter (DCTL) High-order 8 bits of I/O address pointer (IOAH) Low-order 8 bits of I/O address pointer (IOAL) I2OS status (ISCS) High-order 8 bits of buffer address pointer (BAPH) 000100H + 8 × ICS Medium-order 8 bits of buffer address pointer (BAPM) ISD start address Low-order 8 bits of buffer address pointer (BAPL) L Figure 7.6.2a Extended intelligent I/O service descriptor configuration ■ Data counter (DCT) This is a 16-bit register that works as a counter corresponding to the number of data items transferred. This counter is decremented by one before data transfer. EI2OS is terminated when this counter reaches 0. Upper byte of data counter Initial value Lower byte of data counter Initial value 94 Chapter 7: Interrupt 15 14 13 12 11 10 9 8 Bit number B15 B14 B13 B12 B11 B10 B09 B08 DCTH (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0 Bit number B07 B06 B05 B04 B03 B02 B01 B00 DCTL (X) (X) (X) (X) (X) (X) (X) (X) MB90580 Series 7.6 Extended intelligent I/O service (EI2OS) ■ I/O register address pointer (IOA) This is a 16-bit register that indicates the low-order address (A15 to A0) of the buffer and I/O register used for data transfer to and from the buffer. The high-order address (A23 to A16) are all zeroes, and any I/O between addresses 000000H and 00FFFFH can be specified. Upper address pointer Initial value Lower address pointer Initial value 15 14 13 12 11 10 9 8 Bit number A15 A14 A13 A12 A11 A10 A09 A08 IOAH (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0 A07 A06 A05 A04 A03 A02 A01 A00 (X) (X) (X) (X) (X) (X) (X) (X) Bit number IOAL ■ EI2OS status register (ISCS) This eight-bit register indicates the update direction (increment/decrement), transfer data format (byte/word), and transfer direction of the buffer address pointer and the I/O register address pointer. This register also indicates whether the buffer address pointer or I/O register address pointer is updated or fixed. Read/write Initial value 7 6 5 4 3 2 1 0 — — — IF BW BF DIR SE (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (R/W) (X) (X) Bit number * Always write 0 to bits 7 to 5 of ISCS. Each bit is described below. [bit 4] IF : Specify whether the I/O register address pointer is updated or fixed. 0 The I/O register address pointer is updated after data transfer. 1 The I/O register address pointer is not updated after data transfer. Note: Only increment is allowed. [bit 3] BW: Specify the transfer data length. 0 Byte 1 Word [bit 2] BF: Specify whether the buffer address pointer is updated or fixed. 0 The buffer address pointer is updated after data transfer. 1 The buffer address pointer is not updated after data transfer. Note: Only the low-order 16 bits of the buffer address are updated. Only increment is allowed. MB90580 Series Chapter 7: Interrupt 95 7.6 Extended intelligent I/O service (EI2OS) [bit 1] DIR: Specify the data transfer direction. 0 I/O → Buffer 1 Buffer → I/O [bit 0] SE: Control the termination of the extended intelligent I/O service based on resource requests. 0 The extended intelligent I/O service is not terminated by a resource request. 1 The extended intelligent I/O service is terminated by a resource request. ■ Buffer address pointer (BAP) This 24-bit register holds the address used for the next EI2OS transfer. BAP exists for each EI2OS channel. Therefore, each EI2OS channel can be used for transfer with anywhere in the 16-Mbyte space. Note: If the BF bit of ISCS is set to ’0’ (update enabled), only the low-order 16 bits of BAP changes and BAPH does not change. 96 Chapter 7: Interrupt MB90580 Series 7.6 Extended intelligent I/O service (EI2OS) 7.6.3 Operation . BAP I/OA ISD ISCS DCT ISE S1 and S0 Interrupt request issued from internal resource : : : : : : : Buffer address pointer I/O address pointer EI2OS descriptor EI2OS status Data counter EI2OS enable bit EI2OS end status NO ISE = 1 YES Interrupt sequence Reading ISD/ISCS YES End request from resource NO SE = 1 YES DIR = 1 NO Data indicated by BAP ⇓ (Data transfer) Memory indicated by IOA Data indicated by IOA ⇓ (Data transfer) Memory indicated by BAP YES IF = 0 NO Update value depends on BW. Updating IOA Update value depends on BW. Updating BAP YES BF = 0 NO Decrementing DCT YES DCT = 00 NO Setting S1 and S0 to ’01’ Setting S1 and S0 to ’11’ Setting S1 and S0 to ’00’ Clearing resource interrupt request Clearing ISE to ’0’ CPU operation return Interrupt sequence Figure 7.6.3a EI2OS operation flow MB90580 Series Chapter 7: Interrupt 97 7.6 Extended intelligent I/O service (EI2OS) Processing by CPU Processing by EI2OS I2OS initialization JOB execution Normal termination (Interrupt request) AND (ISE = 1) Data transfer Re-setting of extended intelligent I/O service (Switching channels) Processing data in buffer Figure 7.6.3b EI2OS use flow 98 Chapter 7: Interrupt MB90580 Series 7.6 Extended intelligent I/O service (EI2OS) 7.6.4 EI2OS Execution Time (1) When data transfer continues (when the stop condition is not satisfied) EI2OS Execution Time = (value in Table 7.6.4a + value in Table 7.6.4b) machine cycle Table 7.6.4a Execution time when the extended I2OS continues ISCS SE bit Set to ’0’ I/O address pointer Buffer address pointer Set to ’1’ Fixed Updated Fixed Updated Fixed 32 34 33 35 Updated 34 36 35 37 (2) When a stop request is issued from a resource EI2OS Execution Time = (36 + 6 × value of Table 7.4.3a) machine cycles (3) When the counting is completed EI2OS Execution Time = (value of Table 7.6.4a + value of Table 7.6.4b + (21 + 6 × value of Table 7.4.3a) machine cycles Table 7.6.4b Data transfer compensation values for extended I2OS execution time Internal access I/O address pointer Buffer address pointer MB90580 Series External access B/E O B/E 8/O Internal access B/E 0 +2 +1 +4 O +2 +4 +3 +6 External access B/E +1 +3 +2 +5 8/O +4 +6 +5 +8 B : Byte data transfer 8 : 8-bit external bus word transfer E : Even address word transfer O : Odd address word transfer Chapter 7: Interrupt 99 7.7 Exceptions 7.7 Exceptions The F2MC-16LX performs exception processing when the following event occurs: • Execution of an undefined instruction Exception processing is fundamentally the same as interrupt processing. When an exception is detected between instructions, exception processing is performed separately from ordinary processing. In general, exception processing is performed as a result of an unexpected operation. Fujitsu recommends using exception processing only for debugging or for activating emergency recovery software. 7.7.1 Exception due to execution of an undefined instruction The F2MC-16LX handles all codes that are not defined in the instruction map as undefined instructions. When an undefined instruction is executed, processing equivalent to the INT 10 software interrupt instruction is performed. Specifically, the AL, AH, DPR, DTB, ADB, PCB, PC, and PS values are saved into the system stack, and processing branches to the routine indicated by the interrupt number 10 vector. In addition, the I flag is cleared and the S flag is set. The PC value saved in the stack is the address at which the undefined instruction is stored. Processing can be restored by the RETI instruction, but is of no use, however, because the same exception occurs again. 100 Chapter 7: Interrupt MB90580 Series Chapter 8: Parallel Ports 8.1 Outline In MB90580 series, there are 10 parallel ports which are as follows: • Port 0 (8 CMOS I/O pins) • Port 1 (8 CMOS I/O pins) • Port 2 (8 CMOS I/O pins) • Port 3 (8 CMOS I/O pins) • Port 4 (8 CMOS I/O pins with open-drain control) • Port 5 (8 CMOS I/O pins) • Port 6 (6 CMOS I/O pins) • Port 7 (4 CMOS I/O pins) • Port 8 (8 CMOS I/O pins) • Port 9 (8 CMOS I/O pins) • Port A (3 CMOS I/O pins) Each pin of the ports can be specified as input or output using the direction register if the corresponding peripheral does not use the pin. When a pin is specified as input, the value of the pin level is read from a data register. When a pin is specified as output, the data register latch value is read from the data register. The above also applies to a read operation for a read-modify-write instruction. When a data register is read while the corresponding port is used as a control output, control output value is read from the data register regardless of the direction register value. When an input pin is changed into an output pin, care must be taken to use a read-modify-write instruction (such as a bit set instruction) to set output data in the data register beforehand. In this case, the data input from the pin is read instead of the data register latch value. 8.2 Block Diagram 8.2 Block Diagram Internal data bus Data register read Data register Pin Data register write Direction register Direction register write Direction register read Figure 8.2a Block diagram of I/O port Internal data bus Pull-up resistor (about 50 kΩ) Data register Pin Direction register Resistor register Figure 8.2b Block diagram of input resistor register Internal data bus Data register Pin Direction register Pin register Figure 8.2c Block diagram of Output pin register 102 Chapter 8: Parallel Ports MB90580 Series 8.3 Registers and register details 8.3 Registers and register details Bit Address : 000000H 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 P07 P06 P05 P04 P03 P02 P01 P00 Port 0 data register (PDR0) Address : 000001H P17 P17 P15 P14 P13 P12 P11 P10 Port 1 data register (PDR1) Address : 000002H P27 P26 P25 P24 P23 P22 P21 P20 Port 2 data register (PDR2) Address : 000003H P37 P36 P35 P34 P33 P32 P31 P30 Port 3 data register (PDR3) Address : 000004H P47 P46 P45 P44 P43 P42 P41 P40 Port 4 data register (PDR4) Address : 000005H P57 P56 P55 P54 P53 P52 P51 P50 Port 5 data register (PDR5) P65 P64 P63 P62 P61 P60 Port 6 data register (PDR6) P74 P73 P72 P71 Address : 000006H Address : 000007H Port 7 data register (PDR7) Address : 000008H P87 P86 P85 P84 P83 P82 P81 P80 Port 8 data register (PDR8) Address : 000009H P97 P96 P95 P94 P93 P92 P91 P90 Port 9 data register (PDR9) PA2 PA1 PA0 Port A data register (PDRA) Address : 00000AH Bit Address : 000010H 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 D07 D06 D05 D04 D03 D02 D01 D00 Port 0 data register (DDR0) Address : 000011H D17 D17 D15 D14 D13 D12 D11 D10 Port 1 data register (DDR1) Address : 000012H D27 D26 D25 D24 D23 D22 D21 D20 Port 2 data register (DDR2) Address : 000013H D37 D36 D35 D34 D33 D32 D31 D30 Port 3 data register (DDR3) Address : 000014H D47 D46 D45 D44 D43 D42 D41 D40 Port 4 data register (DDR4) Address : 000015H D57 D56 D55 D54 D53 D52 D51 D50 Port 5 data register (DDR5) D65 D64 D63 D62 D61 D60 Port 6 data register (DDR6) D74 D73 D72 D71 Address : 000016H Address : 000017H Port 7 data register (DDR7) Address : 000018H D87 D86 D85 D84 D83 D82 D81 D80 Port 8 data register (DDR8) Address : 000019H D97 D96 D95 D94 D93 D92 D91 D90 Port 9 data register (DDR9) DA2 DA1 DA0 Port A data register (DDRA) 10 9 8 Address : 00001AH Bit Address : 00001BH Bit Address : 00001CH Bit 15 14 13 12 11 OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40 7 6 5 4 3 2 1 0 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 15/7 14/6 13/5 12/4 11/3 10/2 9/1 Port 4 pin register (ODR4) Port 5 analog input enable register (ADER) 8/0 Address : 00008CH RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 Port 0 resistor register (RDR0) Address : 00008DH RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10 Port 1 resistor register (RDR1) Address : 00008EH RD65 RD64 RD63 RD62 RD61 RD60 Port 6 resistor register (RDR6) Bit Address : 0000A3H 15 Bit Address : 0000A2H 7 LN7 14 13 12 6 5 4 LN6 LN5 LN4 11 10 9 8 LNB LNA LN9 LN8 1 0 LN1 LN0 3 LN3 2 LN2 Low Noise Output Select register (Upper) (LNSRH) Low Noise Output Select register (Lower) (LNSRL) Figure 8.3a Registers of Parallel Ports MB90580 Series Chapter 8: Parallel Ports 103 8.3 Registers and register details 8.3.1 Port data register PDR0 Address: 000000H PDR1 Address: 000001H PDR2 Address: 000002H PDR3 Address: 000003H PDR4 Address: 000004H PDR5 Address: 000005H 7 6 5 4 3 2 1 0 P07 P06 P05 P04 P03 P02 P01 P00 15 14 13 12 11 10 9 8 P17 P16 P15 P14 P13 P12 P11 P10 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 15 14 13 12 11 10 9 8 P37 P36 P35 P34 P33 P32 P31 P30 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 15 14 13 12 11 10 9 8 P57 P56 P55 P54 P53 P52 P51 P50 7 6 5 4 3 2 1 0 P65 P64 P63 P62 P61 P60 13 12 11 10 9 8 P74 P73 P72 P71 PDR6 Address: 000006H 15 14 PDR7 Address: 000007H PDR8 Address: 000008H PDR9 Address: 000009H 7 6 5 4 3 2 1 0 P87 P86 P85 P84 P83 P82 P81 P80 15 14 13 12 11 10 9 8 P97 P96 P95 P94 P93 P92 P91 P90 7 6 5 4 3 2 1 0 PA2 PA1 PA0 PDRA Address: 00000AH Initial value Access xxxxxxxx R/W xxxxxxxx R/W xxxxxxxx R/W xxxxxxxx R/W xxxxxxxx R/W xxxxxxxx R/W --xxxxxx R/W ---xxxx- R/W xxxxxxxx R/W xxxxxxxx R/W -----xxx R/W Note: Note that R/W for I/O ports differ from R/W for memory in the following points: ❍ Input mode Read: The level of the corresponding pin is read. Write: Data is written to an output latch. ❍ Output mode Read: The data register latch value is read. Write: The data is output to the corresponding pin. 104 Chapter 8: Parallel Ports MB90580 Series 8.3 Registers and register details 8.3.2 Port direction registers DDR0 Address: 000010H DDR1 Address: 000011H DDR2 Address: 000012H DDR3 Address: 000013H DDR4 Address: 000014H DDR5 Address: 000015H 7 6 5 4 3 2 1 0 D07 D06 D05 D04 D03 D02 D01 D00 15 14 13 12 11 10 9 8 D17 D16 D15 D14 D13 D12 D11 D10 7 6 5 4 3 2 1 0 D27 D26 D25 D24 D23 D22 D21 D20 15 14 13 12 11 10 9 8 D37 D36 D35 D34 D33 D32 D31 D30 7 6 5 4 3 2 1 0 D47 D46 D45 D44 D43 D42 D41 D40 15 14 13 12 11 10 9 8 D57 D56 D55 D54 D53 D52 D51 D50 7 6 5 4 3 2 1 0 D65 D64 D63 D62 D61 D60 13 12 11 10 9 8 D74 D73 D72 D71 DDR6 Address: 000016H 15 14 DDR7 Address: 000017H DDR8 Address: 000018H DDR9 Address: 000019H 7 6 5 4 3 2 1 0 D87 D86 D85 D84 D83 D82 D81 D80 15 14 13 12 11 10 9 8 D97 D96 D95 D94 D93 D92 D91 D90 7 6 5 4 3 2 1 0 DA2 DA1 DA0 DDRA Address: 00001AH Initial value Access 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W --000000B R/W - - - 0000-B R/W 00000000B R/W 00000000B R/W - - - - -000B R/W When a pin is used as a port, the corresponding pin is controlled as described below: MB90580 Series 0 Input mode 1 Output mode [initial value] Chapter 8: Parallel Ports 105 8.3 Registers and register details 8.3.3 Output pin register Port 4 pin register 15 Address : 00001BH 14 13 12 11 10 9 8 Bit number OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40 R/W 0 Read/write Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 ODR4 This register controls the open drain in output mode. 0 Standard output port in output mode [initial value] 1 Open drain output port in output mode Note: This register is not used in input mode. (Output Hi-z) Note: Input or output mode is determined by the direction register (DDR). Note: No pull-up resistor is used during hardware standby and stop (SPL=1). (High impedance) Note: This function is inhibited when an external bus is used. When using an external bus, do not write data in this register. 8.3.4 Input resistor register Port 0 resistor register 7 Address : 00008CH Read/write Initial value 6 5 4 3 2 1 0 RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 R/W 0 R/W 0 R/W 0 15 16 15 R/W 0 R/W 0 R/W 0 R/W 0 14 13 12 11 Bit number RDR0 R/W 0 Port 1 resistor register Address : 00008DH Read/write Initial value 10 Bit number RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10 RDR1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 R/W 0 R/W 0 Port 6 resistor register Address : 00008EH Read/write Initial value R/W - R/W - 3 2 1 0 RD65 RD64 RD63 RD62 RD61 RD60 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit number RDR6 R/W 0 This register controls whether to use a pull-up resistor in input mode. 0 No pull-up resistor used in input mode. 1 Pull-up resistor used in input mode. [initial value] Note: This register has no use in output mode (no pull-up resistor is used). Note: Input or output mode is determined by the direction register (DDR). Note: No pull-up resistor is used during hardware standby and stop (SPL=1). (High impedance) Note: This function is inhibited when an external bus is used. When using an external bus, do not write data in this register. 106 Chapter 8: Parallel Ports MB90580 Series 8.3 Registers and register details 8.3.5 Analogue Input Enable Register Port 5 analogue enable register 7 Address : 00001CH Read/write Initial value 6 5 4 3 2 1 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit number 0 R/W 1 ADER R/W 1 This register controls the .behaviour of port 5. 0 Port input mode 1 Analogue input mode [initial value] Note: When an intermediate voltage level is applied to the pin during port input mode, a leakage current will be induced. In this case, configure the pin to analogue input mode instead. 8.3.6 Low Noise Output Select Register Low Noise Output Select register (Upper) 15 14 13 12 Address : 0000A3H Read/write Initial value 11 10 9 8 LNB LNA LN9 LN8 R/W 0 R/W 0 R/W 0 R/W 0 2 1 0 Bit number LNSRH Low Noise Output Select register (Lower) 7 Address : 0000A2H 6 5 4 3 LN7 LN6 LN5 LN4 LN3 LN2 LN1 LN0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Read/write Initial value Bit number LNSRL These two register are used to select the low noise output buffer for Port 0 to Port A and the TX output of IE bus. [bit 15 - 12] - unused bits [bit 11] - LNB controls TX pin of IE bus 0 Normal output buffer 1 Low noise output buffer [initial value] [bit 10] - LNA controls Port A MB90580 Series 0 Normal output buffer 1 Low noise output buffer [initial value] Chapter 8: Parallel Ports 107 8.3 Registers and register details [bit 9] - LN9 controls Port 9 0 Normal output buffer 1 Low noise output buffer [initial value] [bit 8] - LN8 controls Port 8 0 Normal output buffer 1 Low noise output buffer [initial value] [bit 7] - LN7 controls Port 7 0 Normal output buffer 1 Low noise output buffer [initial value] [bit 6] - LN6 controls Port 6 0 Normal output buffer 1 Low noise output buffer [initial value] [bit 5] - LN5 controls Port 5 0 Normal output buffer 1 Low noise output buffer [initial value] [bit 4] - LN4 controls Port 4 0 Normal output buffer 1 Low noise output buffer [initial value] [bit 3] - LN3 controls Port 3 0 Normal output buffer 1 Low noise output buffer [initial value] [bit 2] - LN2 controls Port 2 0 Normal output buffer 1 Low noise output buffer [initial value] [bit 1] - LN1 controls Port 1 0 Normal output buffer 1 Low noise output buffer [initial value] [bit 0] - LN0 control Port 0 0 Normal output buffer 1 Low noise output buffer [initial value] Note: These two register are not available for MB90V580. Note: When low noise output buffer is selected, the driving power will be decreased. 108 Chapter 8: Parallel Ports MB90580 Series Chapter 9: DTP/External Interrupt 9.1 Outline The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16LX CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes requests to the F2MC-16LX CPU to activate the extended intelligent I/O service (EI2OS) or interrupt processing. Two request levels ("H" and "L") are provideed for the extended intelligent I/O service (EI2OS). For external interrupt requests, generating interrupts on a rising edge or falling edge as well as "H" and "L" level can be selected, giving a total of four types. 9.2 Block Diagram F2MC-16LX BUS 4 4 4 8 Interrupt/DTP enable register Gate Cause F/F Edge detection circuit 4 Interrupt/DTP cause register Request level setting register Figure 9.2a Block diagram of DTP/External Interrupt Request input 9.3 Registers and Register Details 9.3 Registers and Register Details Interrupt/DTP enable register Address : 000030H Read/write Initial value 7 6 5 4 3 2 1 EN7 EN6 EN5 EN4 EN3 EN2 EN1 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (R/W) (0) (0) 14 13 12 11 10 9 8 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (R/W) (X) (X) (R/W) (X) (R/W) (X) 5 4 LB2 LA2 (R/W) (0) 0 EN0 Bit number ENIR (R/W) (0) Interrupt/DTP cause register 15 Address : 000031H Read/write Initial value Request level setting register (Lower Byte) 7 6 Address : 000032H LB3 LA3 (R/W) (0) Read/write Initial value (R/W) (0) (R/W) (0) 3 LB1 2 1 0 LB0 LA0 (R/W) (0) (R/W) (0) LA1 (R/W) (0) (R/W) (R/W) (0) (0) Bit number EIRR Bit number ELVR (LOW) Request level setting register (Higher Byte) Address : 000033H Read/write Initial value 15 14 13 12 11 10 9 8 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (R/W) (0) (0) Bit number ELVR (HIGH) 9.3.1 Interrupt/DTP enable register (ENIR: Enable interrupt request register) Interrupt/DTP enable register Address : 000030H Read/write Initial value 7 6 5 4 3 2 1 EN7 EN6 EN5 EN4 EN3 EN2 EN1 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (R/W) (0) (0) (R/W) (0) 0 EN0 Bit number ENIR (R/W) (0) ENIR enables the function to issue a request to the interrupt controller using a device pin as an external interrupt/DTP request input. A pin corresponding to a ’1’ bit of this register is used as an external interrupt/DTP request input. A pin corresponding to a ’0’ bit holds the external interrupt/DTP request input cause, but does not issue a request to the interrupt controller. 110 Chapter 9: DTP/External Interrupt MB90580 Series 9.3 Registers and Register Details 9.3.2 Interrupt/DTP cause register (EIRR: External interrupt request register) Interrupt/DTP cause register 15 Address : 000031H Read/write Initial value 14 13 12 11 10 9 8 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (R/W) (X) (X) (R/W) (X) (R/W) (X) Bit number EIRR When read, EIRR indicates the current external interrupt/DTP requests. When written, EIRR clears the flip-flop values indicating those requests. External interrupt/DTP requests exist at the pins corresponding to the ’1’ bits of this register. Writing ’0’ to a bit of this register clears the corresponding request flip-flop value. Writing ’1’ performs no operation. ’1’ is always read from this register by a read-modify-write instruction. 9.3.3 Request level setting register (ELVR: External level register) Request level setting register (Lower Byte) 7 6 Address : 000032H Read/write Initial value LB3 (R/W) (0) LA3 (R/W) (0) 5 4 LB2 LA2 (R/W) (0) 3 LB1 2 LA1 (R/W) (0) (R/W) (R/W) (0) (0) 1 0 LB0 LA0 (R/W) (0) (R/W) (0) Bit number ELVR (LOW) Request level setting register (Higher Byte) Address : 000033H Read/write Initial value 15 14 13 12 11 10 9 8 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (R/W) (0) (0) Bit number ELVR (HIGH) ELVR is used to select a request detection factor. Each pin is assigned two bits as described in the table below. If a request is to be detected based on a level, the register value is maintained while the input is active even when it is cleared. MB90580 Series LBx LAx 0 0 1 1 0 1 0 1 Interrupt request detection factor L level pin input H level pin input Rising edge pin input Falling edge pin input Chapter 9: DTP/External Interrupt 111 9.4 Operations 9.4 Operations 9.4.1 External interrupts Once an external interrupt request is set, this resource issues an interrupt request signal to the interrupt controller when a request specified by the ELVR register is input to the corresponding pin. The interrupt controller identifies the priority levels of the simultaneous interrupts, and issues an interrupt request to the F2MC-16 CPU if the interrupt from this resource has the highest priority level. The F2MC-16 CPU compares the ILM bit of its internal CCR register and the interrupt request. If the interrupt level of the request is higher than that indicated by the ILM bit, the F2MC-16 CPU activates the hardware interrupt processing microprogram as soon as the currently executing instruction is terminated. External interrupt/DTP Other request ELVR Interrupt controller F2MC-16CPU ICRyy IL EIRR CMP ICRxx ENIR CMP ILM NTA Cause Figure 9.4.1a External interrupt In the hardware interrupt processing microprogram, the CPU reads the ISE bit information from the interrupt controller, identifies that the request is for interrupt processing based on that information, and branches to the interrupt processing microprogram. The interrupt processing microprogram reads the interrupt vector area and issues an interrupt acknowledgment signal for the interrupt controller. Then, the microprogram transfers the jump destination address of the macro instruction generated from the vector to the program counter, and executes the user interrupt processing program. 112 Chapter 9: DTP/External Interrupt MB90580 Series 9.4 Operations 9.4.2 DTP operation To activate the intelligent I/O service, the user program initially sets the address of a register, assigned between 000000H and 0000FFH, in the I/O address pointer of the intelligent I/O service descriptor. Then, the user program sets the start address of the memory buffer in the buffer address pointer. The DTP operation sequence is almost the same as for external interrupts. The operation is identical until the CPU activates the hardware interrupt processing microprogram. Then, for the DTP, control is transferred to the intelligent I/O service processing microprogram, since the ISE bit read by the CPU within the hardware interrupt processing microprogram indicates the DTP. Once the intelligent I/O service is activated, a read or write signal is sent to the addresses external peripheral, and data is transferred between the peripheral and the chip. The external peripheral must cancel the interrupt request to this chip within three machine cycles after the transfer is made. When the transfer is completed, the descriptor is updated, and the interrupt controller generates a signal that clears the transfer cause. Upon receiving the signal to clear the transfer cause, this resource clears the flip-flop holding the cause and prepares for the next request from the pin. For details of the intelligent I/O service processing, refer to the MB90700 Programming Manual. Edge request or H level request Internal operation Interrupt cause * When data is transferred from the I/O register to memory in the intelligent I/O service Selecting and reading descriptor Read address Address bus pin Data bus pin Write address Read data Write data ➀ Read signal ➁ Write signal Cancel within three machine cycles. Data, address bus Internal bus Register External peripheral Figure 9.4.2a Timing to cancel the external interrupt at the end of DTP operation ➀ ➁ INT IRQ DTP Cancel within three machine cycles after transfer. CORE MEMORY MB90580 Figure 9.4.2b Sample interface to the external peripheral MB90580 Series Chapter 9: DTP/External Interrupt 113 9.4 Operations 9.4.3 Switching between external interrupt and DTP requests To switch between external interrupt and DTP requests, use the ISE bit in the ICR register corresponding to this resource, which is in the interrupt controller. Each pin is individually assigned ICR. Thus, a pin is used for a DTP request if ’1’ is written to the ISE bit of the corresponding ICR, and is used for an external interrupt request if ’0’ is written to the bit. Interrupt controller 0 ICR xx ICR yy 1 F2MC-16 CPU Pin External Interrupt/DTP DTP External interrupt Figure 9.4.3a Switching between external interrupt and DTP requests 114 Chapter 9: DTP/External Interrupt MB90580 Series 9.5 Notes on use 9.5 Notes on use 9.5.1 Conditions on the externally connected peripheral when DTP is used DTP supports only external peripherals that automatically clear a request once a transfer is completed. The system must be designed so that a transfer request is canceled within three machine cycles (provisional) after transfer operation starts. Otherwise, this resource assumes that a transfer request is issued. 9.5.2 Recovery from standby To use an external interrupt to recover from the standby state in clock stop mode, use an H level request as an input request. A L level request may result in misoperation. If an edge request is used, recovery from the standby state in clock stop mode cannot be performed. 9.5.3 External interrupt/DTP operation procedure To set registers in the external interrupt/DTP, follow the steps below: 1. Disable the bits corresponding to the enable register. 2. Set the bits corresponding to the request level setting register. 3. Clear the bits corresponding to the cause register. 4. Enable the bits corresponding to the enable register. (Steps 3. and 4. can be simultaneously performed by word specification.) To set a register in this resource, ensure that the enable register is disabled. Before enabling the enable register, ensure that the cause register is cleared. Clearing the cause register prevents a false interrupt cause from being determined while registers are set or interrupts are enabled. 9.5.4 External interrupt request level ①To detect an edge for a edge request level, the pulse width must be at least three machine cycles. ②If the request input level is related to level setting, the request to the interrupt controller is kept active. Because of the internal hold circuit, the request is kept active even if it is input from the external device and then canceled. To cancel the request to the interrupt controller, clear the cause hold circuit. Level detection Interrupt cause Cause F/F (cause hold circuit) Enable gate To interrupt controller The cause is kept held unless cleared. Figure 9.5.4a Clearing the cause hold circuit upon level set Interrupt cause Interrupt request to the interrupt controller H level Set inactive when the cause F/F is cleared. Figure 9.5.4b Interrupt cause and interrupt request to the interrupt controller while interrupts are enabled MB90580 Series Chapter 9: DTP/External Interrupt 115 Chapter 10: Delayed Interrupt Generation Module 10.1 Outline The delayed interrupt generation module generates interrupts for switching tasks for development on a real-time operating system (REALOS series). The module can be used to generate softwarewise generates hardware interrupt requests to the CPU and cancel the interrupts. This module does not conform to the extended intelligent I/O service (EI 2OS). F2MC-16LX bus 10.2 Block Diagram Delayed interrupt cause issuance/cancellation decoder Cause latch Figure 10.2a Block diagram of Delayed Interrupt Generation Module 10.3 Registers and Register Details Delayed interrupt cause issuance/cancellation register (DIRR: Delayed interrupt request register) Delayed interrupt cause issuance/cancellation register Address : 00009FH Read/write Initial value 7 6 5 4 3 2 1 0 — — — — — — — R0 (–) (–) (–) (–) (–) (–) (–) (–) (–) (–) (–) (–) (–) (–) (R/W) (0) Bit number DIRR DIRR controls issuance and cancellation of delayed interrupt requests. Writing ’1’ to this register issues a delayed interrupt request, and writing ’0’ cancels the delayed interrupt request. Upon a reset, the request is canceled. Either ’0’ or ’1’ can be written to the reserved bit area. To access this register, use the set bit or clear bit instruction for future expansions. 10.4 Operations 10.4 Operations 10.4.1 Delayed interrupt occurrence When the CPU writes ’1’ to the relevant bit of DIRR by software, the request latch in the delayed interrupt source module is set and an interrupt request is issued to the interrupt controller. If this interrupt has the highest priority or if there is no other interrupt request, the interrupt controller issues an interrupt request to the F2MC-16 CPU. The F2MC-16 CPU compares the ILM bit of its internal CCR register and the interrupt request, and starts the hardware interrupt processing microprogram as soon as the current instruction is completed if the interrupt level of the request is higher than that of the ILM bit. The interrupt processing routine for this interrupt is thus executed. Delayed interrupt source module F2MC-16CPU Interrupt controller WRITE Other requests ICR yy IL CMP CMP ICR xx DDIR ILM NTA Figure 10.4.1a Delayed interrupt issuance The interrupt cause is cleared and tasks are switched by writing ’0’ to the corresponding bit of DDIR in the interrupt processing routine. 10.5 Notes on operation 10.5.1 Delayed interrupt request lock This lock is set by writing ’1’ to the corresponding bit of DIRR, and is cleared by writing ’0’ to the same bit. Therefore, interrupt processing is reactivated immediately after control returns from interrupt processing, unless the software is designed so that the cause of the interrupt is cleared within the interrupt processing routine. 118 Chapter 10: Delayed Interrupt Generation Module MB90580 Series Chapter 11: Communication Prescaler 11.1 Outline The operation clock for the UART is obtained by dividing the machine clock. UART is designed so that a constant baud rate can be obtained for a variety of machine clocks by the user of the communication prescaler. The Clock Division Control Register (CDCR) controls the machine clock division. 11.2 Block Diagram Programmable F2MC-16LX Bus From Main Clock Clock Divider To UART MD Clock DIV3 Division Control DIV2 Register DIV1 (CDCR) DIV0 Figure 11.2a Block diagram of Communication Prescaler 11.3 Register and Register Details 11.3 Register and Register Details 11.3.1 Clock Division Control Registers Clock Division Control Register 0, 1, 2, 3, 4 Address : 00002CH 15 00002EH 000034H MD 000087H 00008FH (R/W) Read/write (0) Initial value 14 13 12 11 10 9 8 — — — DIV3 DIV2 DIV1 DIV0 (–) (–) (–) (–) (–) (–) (R/W) (1) (R/W) (1) (R/W) (1) (R/W) (1) Bit number CDCR0 CDCR1 CDCR2 CDCR3 CDCR4 [bit 15] MD (Machine clock divide mode select): This bit is used to control the operation of the communication prescaler. 0 The communication prescaler is disabled. 1 The communication prescaler is enabled. [initial value] [bits 11, 10, 9, and 8] DIV3 to DIV0 (Divide 3 to 0): These bits are used to determine the machine clock division ratio. DIV3 DIV2 DIV1 DIV0 Division ratio 1 1 1 1 1 1 1 0 2 1 1 0 1 3 1 1 0 0 4 1 0 1 1 5 1 0 1 0 6 1 0 0 1 7 1 0 0 0 8 Reserved [initial value] Note: When the division ratio is changed, allow two cycles for the clock to stabilize before starting communication. Note: In actual application, please use the values other than ‘1111’. 120 Chapter 11: Communication Prescaler MB90580 Series 11.4 Operations 11.4 Operations Depending on the machine clock φ to be used, the communication prescaler register should be set as follows. For details please refer to Chapter 12, UART. . machine clock φ div DIV3 DIV2 DIV1 DIV0 4 MHz 4 1 1 0 0 6 MHz 6 1 0 1 0 8 MHz 8 1 0 0 0 6 MHz 3 1 1 0 1 8 MHz 4 1 1 0 0 10 MHz 5 1 0 1 1 12 MHz 6 1 0 1 0 14 MHz 7 1 0 0 1 16 MHz 8 1 0 0 0 8 MHz 2 1 1 1 0 12 MHz 3 1 1 0 1 16 MHz 4 1 1 0 0 φ/div 1 MHz 2 MHz 4 MHz When using the machine clock and the div at a different setting other than those mentioned above, φ/div should not exceed 4.25 MHz. MB90580 Series Chapter 11: Communication Prescaler 121 Chapter 12: UART 12.1 Outline UART is a serial I/O port for asynchronous communications or CLK synchronous communications. UART has the following features: • Full-duplex double buffers • Asynchronous or CLK synchronous communications • Multi-processor mode • Built-in dedicated baud rate generator Asynchronous: 9615, 31250, 4808, 2404, 1202 bps CLK synchronous: 1 M, 500 K, 250 K, 125 K, 62.5 Kbps • Flexible baud rate setting by external clock • Error detection (parity, framing, and overrun) • NRZ sign transfer signals • Intelligent I/O service (At an internal machine clock of 6, 8, 10, 12, or 16 MHz) 12.2 Block Diagram 12.2 Block Diagram From Communication Prescaler Baud rate generator Upper part of PPG timer (PPG1) Transmission clock Reception clock External clock SIN0/1/2/3/4 Reception status judgment circuit Reception control circuit Transmission control circuit Start bit detect circuit Transmission start circuit Reception bit counter Transmission bit counter Reception parity counter Transmission parity counter Reception shifter End of reception Clock selection circuit Start of transmission Reception interrupt (to CPU) SCK0/1/2/3/4 Transmission interrupt (to CPU) SOT0/1/2/3/4 Transmission shifter SIDR0/1/2 SODR0/1/2 I2OS reception error signal (to CPU) F2MC-16LX BUS SMR0/1/2/3/4 register MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR0/1/2/3/4 register PEN P SBL CL A/D REC RXE TXE SSR0/1/2/3/4 register PE ORE FRE RDRF TDRE RIE TIE Control signal Figure 12.2a Block diagram of UART 124 Chapter 12: UART MB90580 Series 12.3 Register and Register Details 12.3 Register and Register Details Serial mode register Address : 000020H 000024H 000028H 000082H 000088H Read/write Initial value 7 6 5 4 3 2 1 MD1 MD0 CS2 CS1 CS0 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) 15 14 13 12 11 10 9 8 PEN P SBL CL A/D REC RXE TXE SMR0 SMR1 SMR2 (R/W) SMR3 (0) SMR4 Reserved SCKE (R/W) (0) Bit number 0 SOE (R/W) (0) Serial control register Address : 000021H 000025H 000029H 000083H 000089H Read/write Initial value (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (1) Bit number SCR0 SCR1 SCR2 (R/W) SCR3 SCR4 (0) (R/W) (0) Serial input register/Serial output register Address : 000022H 000026H 00002AH 000084H 00008AH Read/write Initial value Bit number 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) 10 9 8 RIE TIE (R/W) (0) (R/W) (0) SIDR0/SODR0 SIDR1/SODR1 SIDR2/SODR2 SIDR3/SODR3 SIDR4/SODR4 Serial status register Address : 000023H 000027H 00002BH 000085H 00008BH Read/write Initial value 15 14 13 12 11 PE ORE FRE RDRF TDRE (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (1) (R/W) (-) Bit number SSR0 SSR1 SSR2 SSR3 SSR4 Figure 12.3a Registers of UART MB90580 Series Chapter 12: UART 125 12.3 Register and Register Details 12.3.1 Serial Mode Register (SMR0/1/2/3/4) Serial mode register Address : 000020H 000024H 000028H 000088H 000082H Read/write Initial value 7 6 5 4 3 MD1 MD0 CS2 CS1 CS0 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) 2 1 Reserved SCKE (R/W) (0) (R/W) (0) 0 Bit number SMR0 SMR1 SMR2 (R/W) SMR3 (0) SMR4 SOE The SMR register specifies the UART operation mode. Set the operation mode while the UART is stopped. Do not write data in this register during UART operation. [bits 7 and 6] MD1 and MD0 (Mode select): These bits are used to select the UART operation mode. Mode MD1 MD0 Operation mode 0 0 0 Asynchronous normal mode 1 0 1 Asynchronous multi-processor mode 2 1 0 CLK synchronous mode - 1 1 Setting inhibited Note: In CLK asynchronous multi-processor mode (mode 1), two or more slave CPUs are connected to a single host CPU. This resource cannot identify the format of the received data. Therefore, this resource only supports a master in multi-processor mode. Since the parity check function cannot be used, write ’0’ to PEN of the SCR register. [bits 5 to 3] CS2, CS1, and CS0 (Clock select):These bits are used to select the baud rate clock source. When a dedicated baud rate generator is selected, the baud rate is determined at the same time. CS2 CS1 CS0 000B to 100B Clock input Dedicated baud rate generator 1 0 1 reserved 1 1 0 Internal timer 1 1 1 External clock Note: If an internal timer is selected, timer 0 is used for UART0 and UART3 in the MB90580 series. Note: If an internal timer is selected, timer 1 is used for UART1 and UART4 in the MB90580 series. Note: If an internal timer is selected, timer 0 is used for UART2 in the MB90580 series. [bit 2] Reserved bit Always write ’0’ to this bit. 126 Chapter 12: UART MB90580 Series 12.3 Register and Register Details [bit 1] SCKE (SCLK enable): This bit is used to specify whether to use the SCK0 pin as a clock input pin or clock output pin in CLK synchronous mode (mode 2) communication. Set ’0’ in this bit in CLK asynchronous mode or external clock mode. 0 The SCK0 pin is used as a clock input pin. 1 The SCK0 pin is used as a clock output pin. [initial value] Note: To use the SCK0 pin as a clock input pin, an external clock source must have been selected. [bit 0] SOE (Serial output enable): This bit is used to specify whether the external pin is used as a serial output pin (SOT0) or I/O port pin. 0 The external pin is used as a general-purpose I/O port pin. 1 The external pin is used as a serial data output (SOT0) pin. MB90580 Series [initial value] Chapter 12: UART 127 12.3 Register and Register Details 12.3.2 Serial Control Register (SCR0/1/2/3/4) Serial control register Address : 000021H 000025H 000029H 000083H 000089H Read/write Initial value Bit number 15 14 13 12 11 10 9 8 PEN P SBL CL A/D REC RXE TXE (R/W) (0) (R/W) (1) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) SCR0 SCR1 SCR2 (R/W) SCR3 SCR4 (0) The SCR register controls the transfer protocol for serial communications. [bit 15] PEN (Parity enable): This bit is used to specify whether to perform serial data communication using a parity bit. 0 With parity 1 Without parity [initial value] Note: A parity bit can be added only in normal asynchronous communication mode (mode 0). No parity bit can be added in multi-processor mode (mode 1) or CLK synchronous communication mode (mode 2). [bit 14] P (Parity): This bit is used to specify an even- or odd-numbered parity for data communications with parity. 0 Even-numbered parity 1 Odd-numbered parity [initial value] [bit 13] SBL (Stop bit length) This bit is used to specify the length of the stop bit, which is used as a frame end mark in asynchronous communications. 0 1 stop bit 1 2 stop bits [initial value] [bit 12] CL (Character length): This bit is used to specify the data length of each frame to be sent or received. 0 7-bit data 1 8-bit data [initial value] Note: 7-bit data can be handled only in normal synchronous communication mode (mode 0). Specify 8-bit data in multi-processor mode (mode 1) or CLK synchronous communication mode (mode 2). 128 Chapter 12: UART MB90580 Series 12.3 Register and Register Details [bit 11> A/D (Address/data): This bit is used to specify the data format of the frame to be sent or received in multi-processor asynchronous communication mode (mode 1). 0 Data frame 1 Address frame [initial value] [bit 10] REC (Receiver error clear): This bit is used to clear the SSR register error flags (PE, ORE, and FRE). Writing ’1’ to this bit is invalid. ’1’ is always read from this bit. [bit 9] RXE (Receiver enable): This bit is used to control UART reception. 0 Disables reception. 1 Enables reception. [initial value] Note: If reception is disabled while data is being received (being input to the reception shift register), reception is terminated when the reception of that frame is completed and the reception data is stored in the reception data buffer (SIDR register). [bit 8] TXE (Transmitter enable): This bit is used to control UART transmission. 0 Disables transmission 1 Enables transmission. [initial value] Note: If transmission is disabled while data is being transmitted (being output from the transmission register), transmission is terminated after all data in the transmission data buffer (SODR register) has been output. MB90580 Series Chapter 12: UART 129 12.3 Register and Register Details 12.3.3 Serial Input Data Register (SIDR0/1/2/3/4)/ Serial Ouput Data Register (SODR0/1/2/3/4) Serial input register/Serial output register Address : 000022H 000026H 00002AH 000084H 00008AH Read/write Initial value 7 6 5 4 3 2 1 0 Bit number D7 D6 D5 D4 D3 D2 D1 D0 (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) SIDR0/SODR0 SIDR1/SODR1 SIDR2/SODR2 SIDR3/SODR3 SIDR4/SODR4 (R/W) (X) These registers are data buffer registers for transmission and reception. When a data item is seven bits long, the high-order one bit (D7) is invalid. To write a data item in the SODR register, ensure that ’1’ is written to TDRE of the SSR register. Note: Writing a data item at this address means to write it to the SODR register. Reading this address means to read the SIDR register. 12.3.4 Serial Status Register (SSR0/1/2/3/4) Serial input register/Serial output register Address : 000022H 000026H 00002AH 000084H 00008AH Read/write Initial value 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) Bit number SIDR0/SODR0 SIDR1/SODR1 SIDR2/SODR2 SIDR3/SODR3 SIDR4/SODR4 The SSR register consists of the flags indicating the UART operation. [bit 15] PE (Parity error) This interrupt request flag is set when a parity error occurs during reception. To clear a set flag, write ’0’ to the REC bit (bit 10) of the SCR register. When this bit is set, the data in SIDR is invalid. 0 1 No parity error has occurred. [initial value] A parity error has occurred. [bit 14] ORE (Overrun error): This interrupt request flag is set when an overrun error occurs during reception. To clear a set flag, write ’0’ to the REC bit (bit 10) of the SCR register. When this bit is set, the data in SIDR is invalid. 0 1 130 No overrun error has occurred. [initial value] An overrun error has occurred. Chapter 12: UART MB90580 Series 12.3 Register and Register Details [bit 13] FRE (Framing error) This interrupt request flag is set when a framing error occurs during reception. To clear a set flag, write ’0’ to the REC bit (bit 10) of the SCR register. When this bit is set, the data in SIDR is invalid. 0 No framing error has occurred. 1 A framing error has occurred. [initial value] [bit 12] RDRF (Receiver data register full): This interrupt request flag indicates that the SIDR register contains received data. This flag is set when received data is loaded into the SIDR register. This flag is automatically cleared when the SIDR register is read. 0 No received data exists. 1 Received data exists. [initial value] [bit 11] TDRE (Transmitter data register empty): This interrupt request flag indicates that transmission data can be written into the SODR register. This flag is cleared when transmission data is written into the SODR register. Then, when the written data is loaded into the transmission shifter and transfer starts, this flag is set again, indicating the next transmission data item can be written. 0 Writing transmission data is disabled. 1 Writing transmission data is enabled. [initial value] 0: Writing transmission data is disabled. 1: Writing transmission data is enabled. [bit 9] RIE (Receiver interrupt enable): This bit is used to control reception interrupts. 0 Interrupts are disabled 1 Interrupts are enabled. [initial value] Note: Reception interrupt causes include normal reception by RDRF in addition to errors due to PE, ORE, and FRE. [bit 8] TIE (Transmitter interrupt enable): This bit is used to control transmission interrupts. 0 Interrupts are disabled 1 Interrupts are enabled. [initial value] Note: Transmission interrupt causes include transmission requests by TDRE. MB90580 Series Chapter 12: UART 131 12.4 Operations 12.4 Operations 12.4.1 Operation modes Table 12.4.1a lists the operation modes of UART. The modes can be switched by setting a value in the SMR or SCR register. Table 12.4.1a UART operation modes Parity Data length Yes/No 7 Yes/No 8 Mode 0 1 No 8+1 2 No 8 Operation mode Stop bit length Asynchronous normal mode 1 bit or 2 bits Asynchronous multi-processor mode CLK synchronous mode No Note: In asynchronous mode, the stop bit length can be specified for transmission only; the stop bit is always one bit long for reception. If a two-bit stop bit length is specified, the UART does not operate. Note: When using clock synchronous mode, start bit and stop bit is not attached to the data byte. 12.4.2 UART clock selection (1) Dedicated baud rate generator When a dedicated baud rate generator is selected, the following baud rates are used: Table 12.4.2a Baud rate (f indicates the machine clock.) CS2 CS1 CS0 Asynchronous Calculation 0 0 0 9615 (∅÷div) / (8×13×2) 0 0 1 4808 (∅÷div) / (8×13×22) 0 1 0 2404 (∅÷div) / (8×13×23) 0 1 1 1202 (∅÷div) / (8×13×24) 1 0 0 31250 (∅÷div) / 26 CS2 CS1 CS0 CLK synchronous Calculation 0 0 0 1 M (∅÷div) / 2 0 0 1 500 K (∅÷div) / 22 0 1 0 250 K (∅÷div) / 23 0 1 1 125 K (∅÷div) / 24 1 0 0 62.5 K (∅÷div) / 25 Note: ∅ : Machine clock div: Division ration Please refer to chaper 11, Communication Prescaler. 132 Chapter 12: UART MB90580 Series 12.4 Operations (2) Internal timer When ’110’ is set in CS2 to CS0 and an internal timer is selected, the 16-bit timer (timer 0) is used in reload mode. The baud rate is calculated as described below in this case: Asynchronous: (∅÷N)/(16 × 2 × (n+1)) CLK synchronous: (∅÷N)/(2 × (n+1)) ∅ : Machine clock N: Timer count clock sourc n: Timer reload value Table 12.4.2b lists the baud rates and reload values (decimal) at a machine clock of 7,3728 MHz . Table 12.4.2b Baud rates and reload values N=21 (Machine clock/2) N=23 (Machine clock/8) 38400 2 19200 5 9600 11 2 4800 23 5 2400 47 11 1200 95 23 600 191 47 300 383 95 When an internal timer (16-bit timer 0) is selected as a baud rate clock source, the 16-bit timer 0 output (TOUT0) is connected inside the controller. Therefore, externally connecting the 16-bit timer 0 external pin (TOT0) to the external clock input pin (SCK0) of the UART is unnecessary. If the timer 0 output pin is not used for other purposes, it can be used as an I/O port pin. (3) External clock When ’111’ is set in CS2 to CS0 and an external clock is selected, the baud rate can be expressed as described below, assuming f to be the external clock frequency: Asynchronous: f/16 CLK synchronous: f Note: f is up to 1 MHz. MB90580 Series Chapter 12: UART 133 12.4 Operations 12.4.3 Asynchronous mode (1) Transfer data format UART handles NRX (non return to zero) format data only. Figure 12.4.3a gives the data format. SIN0, SOT0 0 Start 1 LSB 0 1 1 0 0 1 0 1 1 MSB Stop A/D Stop (Mode 0) (Mode 1) 01001101B is transferred. Figure 12.4.3a Transfer data format (modes 0 and 1) As shown in Figure 12.4.3a, the transfer data always starts from the start bit (’L’ level data), transfer is based on the data bit length specified by the first LSB, and transfer ends at the stop bit (’H’ level data). When external clock is selected, ensure that the clock is input. In normal mode (mode 0), the data length can be 7 or 8 bits. In multi-processor mode (mode 1), the data length must be 8 bits. In multi-processor mode, no parity bit can be added. Instead, the A/D bit is always added. (2) Reception Data is always received while ’1’ is written to the RXE bit (bit 9) of the SCR register. When the start bit appears in the reception line, one frame of data is received according to the data format determined by the SCR register. Once a frame has been received, an error flag is set if an error has occurred, and the RDRF flag (bit 12 of the SSR register) is set. At that time, if ’1’ is written to the RIE bit (bit 9) of the same SSR register, a reception interrupt is issued to the CPU. Check the flags of the SSR register. Read the SIDR register if the reception has been normal. If an error has occurred, take appropriate measures. The RDRF flag is cleared when the SIDR register is read. (3) Transmission Transmission data is written into the SODR register when ’1’ is set in the TXE bit (bit 8) of the SSR register. Then, if ’1’ is written to the TXE bit (bit 8) of the SCR register, transmission is performed. When the data set in the SODR register is loaded into the transmission shift register and transmission starts, the TDRE flag is set again and the next transmission data item can be set. At that time, if ’1’ is written to the TIE bit (bit 8) of the same SSR register, a transmission interrupt is issued to the CPU, requesting to set the transmission data in the SODR register. The TDRE flag is cleared when data is written to the SODR register. 134 Chapter 12: UART MB90580 Series 12.4 Operations 12.4.4 CLK synchronous mode (1) Transfer data format UART handles NRX (non return to zero) format data only. Figure 12.4.4a shows the transmission/reception clock and data. SODR write Mark SCLK RXE, TXE SIN0, SOT0 1 0 1 1 LSB 0 0 1 0 (Mode 2) MSB 01001101B is transferred. Figure 12.4.4a Transfer data format (mode 2) When the internal clock (dedicated baud rate generator or internal timer) is selected, a data reception synchronization clock is automatically generated upon data transmission. When an external clock is selected, it is necessary to supply precisely one byte of clock after it is confirmed that the transmission data buffer (SODR register) of the transmission UART contains data (the TDRE flag is ’0’). Ensure that the signal is at the mark level before and after transmission. Only 8-bit data can be handled, and no parity bit can be added. Since there is no start or stop bits, no errors are detected except for an overrun error. (2) Initialization The control register values for CLK synchronous mode are listed below. ① SMR register MD1 and MD0 : 10 CS2, CS1, and CS0: Clock input ② ③ MB90580 Series SCKE : Dedicated baud rate generator or internal timer: 1External clock: 0 SOE : Transmission and reception: 1 Reception only: 0 PEN : 0 P, SBL, A/D : Invalid CL : 1 REC : 0 (To be initialized) RXE and TXE : 1 written to one or both RIE : Interrupts are enabled: 1 Interrupts are disabled: 0 TIE : 0 SCR register SSR register Chapter 12: UART 135 12.4 Operations (3) Start of communication Communication is started by writing data in the SODR register. Virtual transmission data must be written to the SODR register even when only reception is to be performed. (4) End of communication The end of communication can be checked by ’1’ written to the RDRF flag of the SSR register. Use the ORE bit of the SSR register to check whether communication has been successful. 136 Chapter 12: UART MB90580 Series 12.4 Operations 12.4.5 Interrupt occurrence and flag set timing UART has five flags and two interrupt causes. The five flags are PE, ORE, FRE, RDRF, and TDRE. PE indicates a parity error, ORE indicates an overrun error, and FRE indicates a framing error. These three flags are set when the corresponding error occurs during reception, and are cleared when ’0’ is written to REC of the SCR register. RDRF is set when the received data is loaded into the SIDR register, and is cleared when the SIDR register is read. The parity detection function is not available in mode 1, and the parity and framing error detection functions are not available in mode 2. TDRE is set when the SODR register becomes empty and can be written to. TDRE is cleared when the SODR register is written to. The two interrupt causes are for reception and transmission. During reception, an interrupt is requested by PE, ORE, FRE, and RDRF. During transmission, an interrupt is requested by TDRE. The timing to set interrupt flags in each operation mode is described below. (1) Reception in mode 0 The PE, ORE, FRE, and RDRF flags are set when reception is completed and the last stop bit is detected. Then, an interrupt request is issued to the CPU. If the PE, ORE, and FRE flags are active, the data in SIDR is invalid. Data D6 Stop D7 PE, ORE, FRE RDRF Reception interrupt Figure 12.4.5a Timing to set PE, ORE, FRE, and RDRF (mode 0) (2) Reception in mode 1 The ORE, FRE, and RDRF flags are set when reception is completed and the last stop bit is detected. Then, an interrupt request is issued to the CPU. Since the receivable data length is eight bits, the ninth bit indicating the address and data is invalid. If the ORE and FRE flags are active, the data in SIDR is invalid. Data D7 Address/Data Stop ORE, FRE RDRF Reception interrupt Figure 12.4.5b Timing to set ORE, FRE, and RDRF (mode 1) (3) Reception in mode 2 The ORE and RDRF flags are set when reception is completed and the last data item (D7) is detected. MB90580 Series Chapter 12: UART 137 12.4 Operations Then, an interrupt request is issued to the CPU. If the ORE flag is active, the data in SIDR is invalid. Data D5 D6 D7 ORE RDRF Reception interrupt Figure 12.4.5c Timing to set ORE and RDRF (mode 2) (4) Transmission in modes 0, 1, and 2 TDRE is cleared when a data item is written into the SODR register. When the data item is transferred to the internal shift register and the next data item can be written, TDRE is set and an interrupt request is issued to the CPU. If ’0’ is set in TXE (or additionally RXE in mode 2) of the SCR register during transmission, ’1’ is set in TDRE of the SSR register. Then, the transmission shifter stops and the transmission by UART is disabled. If ’0’ is set in TXE (or additionally RXE in mode 2) of the SCR register during transmission, the data set in the SODR register is transmitted before transmission stops. SODR write TDRE An interrupt request is issued to the CPU. SOT0 interrupt SOT0 output ST D0 ST: Startbit D1 D2 D3 D0 to D7: Databits D4 D5 D6 D7 SP SP ST D0 A/D D1 D2 D3 SP: Stopbit A/D: Address/data multiplexer Figure 12.4.5d Timing to set TDRE (modes 0 and 1) SODR write TDRE An interrupt request is issued to the CPU. SOT0 interrupt SOT0 output D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 to D7: Data bits Figure 12.4.5e Timing to set TDRE (mode 2) 138 Chapter 12: UART MB90580 Series 12.4 Operations 12.4.6 I2OS (Intelligent I/O service) For I2OS, see the section describing I2OS. 12.4.7 Notes on use To set a communication mode, ensure that UART is not in operation. The data sent or received during mode setting is not guaranteed. 12.4.8 Application Mode 1 is used when two or more slave CPUs are connected to a single host CPU (see Figure 12.4.8a). This resource only supports the host side communication interface. SO SI Host CPU SO SI Slave CPU #0 SO SI Slave CPU #1 Figure 12.4.8a Sample system configuration in mode 1 Communication starts when the host CPU transfers address data. Address data means the data used when ’1’ is set in A/D of the SCR register. The address data determines the destination slave CPU and enables communication between the host and slave CPUs. Ordinary data means the data used when ’0’ is set in A/D of the SCR register. Figure 12.4.8b shows the flowchart. In mode 1, the parity check function cannot be used. Therefore, set ’0’ in the PEN bit of the SCR register. MB90580 Series Chapter 12: UART 139 12.4 Operations (Host CPU) START Select transfer mode 1. Set the data for selecting the slave CPUs in D0 to D7 and set ’1’ in A/D to transfer one byte. Set ’0’ in A/D. Reception is enabled. Communication with the slave CPU No End communication? Yes Communicate with other slave CPU? No Yes Reception is disabled. END Figure 12.4.8b Flow chart of communication in mode 1 140 Chapter 12: UART MB90580 Series Chapter 13: IE Bus 13.1 Outline IEBus (Inter Equipment Bus) is a small-scale two-line serial bus interface intended to transfer data between equipment and equipment. It is designed for use in automotive and general industrial applications. The communication protocol of the IEBus has the following features: • Multi-master method All the units connected to the IEBus can transfer data to the other units. • Multiaddress communication function (one unit can communicate to two or more units simultaneously) Group communication: multiaddress communication to group unit Broadcasting communication: multiaddress communication to all units • Three different transfer rates can be selected: Mode IE Bus Internal Frequency at 6 MHz IE Bus Internal Frequency at 6 MHz 0 Approx. 3.9 Kbps Approx. 4.1 Kbps 2 Approx. 17 Kbps Approx. 18 Kbps 3 Approx. 26 Kbps Approx. 27 Kbps • Transmit Data Buffer : 8-Byte FIFO • Receive Data Buffer : 8-Byte FIFO • CPU internal operation frequency: 12 MHz, 12.58 MHz 13.2 Block Diagram 13.2 Block Diagram Uuit Address Register Slave Address Register Multiaddress Control Bit Set Register F2MC-16LX BUS Telegraph Length Set Register TX Write Data Buffer (8-byte FIFO) Master Address Read Register Multiaddress Control Bit Read Register Control Circuitry Telegraph Length Set Register IE Protocol Controller Lock Read Register Read Dta Buffer (8-byte FIFO) RX Command Register Status Register Interrupt Request (Transmit, Receive) 2 Internal Clock (12 MHz / 12.58 MHz) Prescaler (6 MHz / 6.29 MHz) Note: Function of Control Circuitry 1. Control the number of transmit/receive bytes 2. Control max. number of byte transmission 3. Detect arbitration 4. Determine acknowledgement 5. Generate interrupt Figure 13.2a Block Diagram of IE Bus 142 Chapter 13: IE Bus MB90580 Series 13.3 Registers and Register Details 13.3 Registers and Register Details Command register upper byte (CMRH) 15 14 13 12 11 10 9 8 Address: 000077H MD1 MD0 PCOM RIE TIE GOTM GOTS Reserved Read/write Initial value (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (X) 6 5 4 3 2 1 0 RXS TXS TIT1 TIT0 CS1 CS0 RDBC WDBC (R/W) (1) (R/W) (1) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) 11 10 9 8 MA11 MA10 MA09 MA08 (R/W) (X) (R/W) (X) (R/W) (X) Bit Number CMRH Command register lower byte (CMRL) 7 Address: 000076H Read/write Initial value (R/W) (0) Bit Number. CMRL Unit address register (MAWH, MAWL) 15 Address: 000071H Read/write Initial value Read/write Initial value 13 12 Reserved Reserved Reserved Reserved (R/W) (X) 7 Address: 000070H 14 (R/W) (X) 6 (R/W) (X) (R/W) (X) 5 4 MA07 MA06 MA05 (R/W) (X) (R/W) (X) (R/W) (X) MA04 3 2 0 MA01 MA00 MA02 (R/W) (X) (R/W) (X) (R/W) (X) 11 10 9 SA11 SA10 SA09 (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) 4 3 2 (R/W) (X) MAWH (R/W) (X) 1 MA03 Bit Number Bit Number MAWL (R/W) (X) Slave address register (SAWH, SAWL) 15 Address: 000073H Read/write Initial value Address: 000072H Read/write Initial value 14 13 12 Reserved Reserved Reserved Reserved (R/W) (X) (R/W) (X) 7 6 (R/W) (X) 5 SA07 SA06 SA05 (R/W) (X) (R/W) (X) (R/W) (X) SA04 (R/W) (X) SA03 (R/W) (X) SA02 (R/W) (X) 8 SA08 SAWH (R/W) (X) 1 0 SA01 SA00 (R/W) (X) Bit Number Bit Number SAWL (R/W) (X) Figure 13.3a Registers of IE BUS (1/3) MB90580 Series Chapter 13: IE Bus 143 13.3 Registers and Register Details Mutliaddress, control bit set register (DCWR) Address: 000075H Read/write Initial value 15 14 13 12 11 10 9 8 DO3 DO2 DO1 DO0 C3 C2 C1 C0 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) 5 4 3 2 1 0 Bit Number DCWR (R/W) (0) Telegraph length set register (DEWR) 7 Address: 000074H Read/write Initial value 6 Bit Number DE7 DE6 DE5 DE4 DE3 DE2 DE1 DE0 DECR (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) 15 14 13 12 11 10 9 8 COM TE PEF ACK RIF TIF TSL EOD (R) (0) (R/W) (0) (R) (X) (R) (X) (R/W) (0) (R/W) (0) (R) (0) (R) (0) Status register upper byte (STRH) Address: 000079H Read/write Initial value Bit Number STRH Status register lower byte (STRL) Address: 000078H Read/write Initial value 7 6 5 4 3 2 1 0 WDBF RDBF WDBE RDBE ST3 ST2 ST1 ST0 (R) (0) (R) (0) (R) (1) (R) (1) (R) (X) (R) (X) (R) (X) (R) (X) 14 13 12 11 10 9 8 LOC LD11 LD10 LD09 (R) (0) (R) (X) (R) (X) (R) (X) (R) (X) 4 3 2 1 0 LD01 LD00 Bit Number STRL Lock read register (LRRH, LRRL) 15 Address: 00007BH Read/write Initial value Reserved Reserved Reserved (R) (1) 7 Address: 00007AH Read/write Initial value (R) (1) 6 (R/W) (1) 5 LD07 LD06 LD05 LD04 LD03 LD02 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) LD08 Bit Number LRRH Bit Number LRRL (R) (X) Figure 13.3b Registers of IE BUS (2/3) 144 Chapter 13: IE Bus MB90580 Series 13.3 Registers and Register Details Master address read register (MARH, MARL) 15 Address: 00007DH 14 13 12 Reserved Reserved Reserved Reserved Read/write Initial value Address: 00007CH Read/write Initial value (R) (1) (R) (1) 7 6 (R) (1) 11 10 9 8 MA11 MA10 MA09 MA08 (R) (X) (R) (X) 1 0 MA01 MA00 (R) (1) (R) (X) (R) (X) 5 4 3 2 Bit Number MARH Bit Number MARL MA07 MA06 MA05 MA04 MA03 MA02 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) 13 12 11 10 9 8 Bit Number DCRR Multiaddress, control bit read register (DCRR) Address: 00007FH Read/write Initial value 15 14 DO3 DO2 DO1 DO0 C3 C2 C1 C0 (R) (0) (R) (0) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) 2 1 0 Bit Number DE1 DE0 DERR (R) (0) Telegraph length read register (DERR) Address: 00007EH Read/write Initial value 7 6 5 4 3 DE7 DE6 DE5 DE4 DE3 DE2 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) 15 14 13 12 11 10 9 8 Bit Number RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 RDB (R) (R) (R) (R) (X) (X) (X) (X) (R) (X) (R) (X) (R) (X) (R) (X) 7 6 5 4 3 2 1 0 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 (W) (X) (W) (X) (W) (X) (W) (X) (W) (X) (W) (X) (W) (X) Read data buffer (RDB) Address: 000081H Read/write Initial value Write data buffer (WDB) Address: 000080H Read/write Initial value (W) (X) Bit Number WDB Figure 13.3c Registers of IE BUS (3/3) MB90580 Series Chapter 13: IE Bus 145 13.3 Registers and Register Details 13.3.1 Command register upper byte (CMRH) Command register upper byte (CMRH) Bit Number 15 14 13 12 11 10 9 8 Address: 000077H MD1 MD0 PCOM RIE TIE GOTM GOTS Reserved Read/write Initial value (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (X) CMRH [bits 15 and 14] MD1, MD0 (Mode select): These bits are used to select the IEBus operation mode. Table 13.3.1a Transmission mode MD1 MD0 Operation mode 0 0 Mode 0 0 1 Mode 1 1 0 Mode 2 1 1 Setting inhibited [bit 13] PCOM (Communication enable): This bit is used to enable IEBus communication. When PCOM is written ‘1’, the COM flag in status register (STRH) is set and then the communication is enabled. When PCOM is written ‘0’, the communication is ended. Please set this bit to ‘1’ if the COM flag in the status register is ‘0’. [bit 12] RIE (Receive interrupt enable): This bit controls receive interrupt as described below. 0 Receive interrupt disabled 1 Receive interrupt enabled The receive interrupt is occurred under the following condition: • 146 The eight byte Receive data buffer (RDB) is full. • Data reception is finished normally. • The communication has ended without receiving the number of data specified by telegraph length field in one communication frame. • When arbitration lost, the unit cannot be selected as slave unit. Chapter 13: IE Bus MB90580 Series 13.3 Registers and Register Details [bit 11] TIE (Transmit interrupt enable): This bit controls transmit interrupt as described below. 0 Transmit interrupt disabled 1 Transmit interrupt enabled The transmit interrupt is occurred under the following condition: • In master transmit, after master address field has been transmitted, the master unit has won in arbitration. • In slave transmit, the control bits requesting for data transmit are received from master unit. • Writing the number of data bytes (controlled by TIT1, TIT0 bits of command register, CMRL) into write data buffer (WDB) is requested. • Transmission of the number of data specified by telegraph length field has been completed in one communication frame. • The communication has ended without transmitting the number of data specified by telegraph length field in one communication frame. [bit 10] GOTM (Master transmit): This bit indicates the start of transmission. After the communication inhibit state has been released, when GOTM is set to ‘1’, data transmission begins. This bit is written ‘1’ only and alwaays read “0”. Writing ‘0’ to this bit has no meaning. [bit 9] GOTS (Slave transmit): This bit indicates the start of transmission. After the communication inhibit state has been released, when GOTS is set to ‘1’, data transmission begins. This bit is written ‘1’ only and always read”0”. Writing ‘0’ to this bit has no meaning. Table 13.3.1b Setting for GOTM and GOTS GOTM GOTS Abritration Slave Transmit Operation 0 0 none not allowed slave receive 0 1 none allowed slave transmit 1 0 present not allowed after abritration lost, it can change to slave receive 1 1 present allowed after abritration lost, it can change to slave transmit [bit 8] Reserved bits Always write ‘1’ to this bit and the read value is undefined. MB90580 Series Chapter 13: IE Bus 147 13.3 Registers and Register Details 13.3.2 Command register lower byte (CMRL) Command register lower byte (CMRL) 7 Address: 000076H Read/write Initial value 6 RXS TXS (R/W) (1) (R/W) (1) 5 TIT1 (R/W) (0) 4 3 2 1 0 TIT0 CS1 CS0 RDBC WDBC (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) Bit Number. CMRL [bit 7] RXS RX input pin polarity selected for external driver/receiver. Table 13.3.2a Interval for the occurrence of data transmit interrupt RXS RX input status 0 RX pin as postive logic input. Logic ‘1’ is high level and Logic ‘0’ is Low level. 1 RX pin as negative logic input. Logic ‘1’ is low level and Logic ‘0’ is high level. [bit 6] TXS TX output pin polarity selected for external driver/receiver. Table 13.3.2b Interval for the occurrence of data transmit interrupt TXS TX output 0 TX pin as postive logic output. Logic ‘1’ is high level and Logic ‘0’ is Low level. 1 TX pin as negative logic output. Logic ‘1’ is low level and Logic ‘0’ is high level. Note1: For MB90580 series, during reset, TX pin will output ‘L’. If the driver/receiver used is in positive logic (Driver/receiver enable at ‘L’), TX outputs ‘L’ from reset to bit setting that will generate a communication error when there is a communication between other communication units. When it happens, it needs a outside circuit to input ‘H’ to the driver/receiver from reset to bit setting. [bit 5, 4] TIT1, TIT0 (Data transmit interrupt control bits) These bits control the time interval of the occurrence of interrupt for writing transmit data in write data buffer (WDB). Table 13.3.2c Interval for the occurrence of data transmit interrupt 148 TIT1 TIT0 0 0 More than one byte data can be written in WDB 0 1 More than two byte data can be written in WDB 1 0 More than four byte data can be written in WDB 1 1 Eight byte data can be written in WDB Chapter 13: IE Bus Timing for interrupt occurs MB90580 Series 13.3 Registers and Register Details [bit 3, 2] CS1, CS0 (Cycle select): These bits control both the CPU internal clock cycle and IEBUS controller clock cycle and CS1 and CS0 must be set to ‘0’. . Table 13.3.2d Internal clock frequency CPU internal clock φ IEBus internal clock Equation 12MHz (12.58 MHz) 6MHz(6.29MHz) φΙΕ = φ/2 1 Setting inhibited ---- ---- 1 0 Setting inhibited ---- ---- 1 1 Setting inhibited ---- ---- CS1 CS0 0 0 0 Note1: The CPU and IEBus internal clock frequency are calculated by the above equation provided that the CPU operating frequency is inside the guaranteed range. Note2: The accuracy of clock cycle calculation for mode 0 and 1 is ±1.5%, and for mode 2 is ±0.5%. [bit 1] RDBC (Read data buffer clear): This bit is used to clear the 8-byte read data buffer, RDB. When this bit is set to ‘1’, all the eight bytes in RDB are cleared. (RDBE = 1) This bit is always read as ‘0’. [bit 0] WDBC (Write data buffer clear): This bit is used to clear the 8-byte write data buffer, WDB. When this bit is set to ‘1’, all the eight bytes in WDB are cleared and WDB becomes empty (WDBE = 1 ) This bit is alwarys read as ‘0’. For the communication with no. of byte transfer greater than the maximum transfer byte per frame, the data written in the previous frame will no longer valid if ‘1’ is written to this bit. The data written in the current frame will be transmitted first. In converse, if ‘0’ is written to this bit, the unsent data in the previous frame will be prioritized to be sent first. If the transmission is terminated due to timing error, even thought ‘0’ is written to this bit, the transmission will be started from the next data and not the last one which has not been sent completely. MB90580 Series Chapter 13: IE Bus 149 13.3 Registers and Register Details 13.3.3 Unit address register (MAWH, MAWL) Unit address register (MAWH, MAWL) 15 Address: 000071H Read/write Initial value 14 Read/write Initial value 12 Reserved Reserved Reserved Reserved (R/W) (X) (R/W) (X) 7 Address: 000070H 13 6 (R/W) (X) (R/W) (X) 5 4 MA07 MA06 MA05 (R/W) (X) (R/W) (X) (R/W) (X) 11 10 9 8 MA11 MA10 MA09 MA08 (R/W) (X) (R/W) (X) (R/W) (X) 3 MA04 MA03 (R/W) (X) (R/W) (X) 2 MA02 (R/W) (X) Bit Number (R/W) (X) 1 0 MA01 MA00 (R/W) (X) MAWH Bit Number MAWL (R/W) (X) These two registers MAWH, MAWL are used to set its own unit address (12 bits). When the unit is configured as master, the unit address set in MAWH, MAWL is transmitted as master address. When it is configured as slave mode, this unit address is used to compare with the received slave address. Bit 15 to 12 are reserved bits and always write ‘1’ to them. The read values are undefined. Note:Make sure to set the unit address before the communication inhibit state is released. 13.3.4 Slave address register (SAWH, SAWL) Slave address register (SAWH, SAWL) 15 Address: 000073H Read/write Initial value Address: 000072H Read/write Initial value 14 13 12 11 10 9 SA11 SA10 SA09 (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) 4 3 2 Reserved Reserved Reserved Reserved (R/W) (X) (R/W) (X) 7 6 (R/W) (X) 5 SA07 SA06 SA05 (R/W) (X) (R/W) (X) (R/W) (X) SA04 (R/W) (X) SA03 (R/W) (X) SA02 (R/W) (X) SA08 SAWH (R/W) (X) 1 0 SA01 SA00 (R/W) (X) Bit Number 8 Bit Number SAWL (R/W) (X) These two registers SAWH, SAWL are used to set the slave address (12 bits) for master transmit. Bit 15 to 12 are reserved bits and always write ‘1’ to them. The read values are undefined. Note:Make sure to set the slave address before the communication inhibit state is released. 150 Chapter 13: IE Bus MB90580 Series 13.3 Registers and Register Details 13.3.5 Mutliaddress, control bit set register (DCWR) Mutliaddress, control bit set register (DCWR) 15 14 13 12 11 10 9 8 DO3 DO2 DO1 DO0 C3 C2 C1 C0 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) Address: 000075H Read/write Initial value Bit Number DCWR (R/W) (0) [bit 15, 14, 13, 12] DO3, DO2, DO1, DO0 (Multiaddress/normal communication select bits): These bits are used to select multiaddress (more than one slave) or normal communication (one slave). For multiaddress communication, DO3-0 is set to ‘0000’ and then the multiaddress bit in communication frame is sent out as ‘0’. For normal communication, DO3-0 is set to ‘1000’ and then the multiaddress bit in communication frame is sent out as ‘1’. Always write ‘0’ to bit 14, 13, and 12, and when reading, these bits always return ‘0’. [bit 11, 10, 9, 8] C3, C2, C1, C0 (Control bits): These bits are used to control IEBus communication. Table 13.3.5a Control bits setting Control Operation C3Note 1 C2 C1 C0 0H 0 0 0 0 Slave status read 1H 0 0 0 1 Undefined 2H 0 0 1 0 Undefined 3H 0 0 1 1 Data read and lock 4H 0 1 0 0 Lock address read (Lower 8 bits) 5H 0 1 0 1 Lock address read (Upper 4 bits) 6H 0 1 1 0 Slave status read and unlock 7H 0 1 1 1 Data read 8H 1 0 0 0 Undefined 9H 1 0 0 1 Undefined AH 1 0 1 0 Command write and lock BH 1 0 1 1 Data write and lock CH 1 1 0 0 Undefined DH 1 1 0 1 Undefined EH 1 1 1 0 Command write FH 1 1 1 1 Data write Note1: The transfer direction of telegraph length bits in telegraph length field and data bits in data field are controlled by the value of C3 as follows: When C3 is ‘1’: Transfer from master unit to slave unit When C3 is ‘0’: Transfer from slave unit to master unit Note2: 3H, 6H, AH, BH are the lock and unlock function selection bits. Note3: When sending the undefined control bits like 1H, 2H, 8H, 9H, CH, DH, no acknowledge will be returned. MB90580 Series Chapter 13: IE Bus 151 13.3 Registers and Register Details 13.3.6 Telegraph length set register (DEWR) Telegraph length set register (DEWR) 7 Address: 000074H Read/write Initial value 6 5 4 3 2 1 0 Bit Number DE7 DE6 DE5 DE4 DE3 DE2 DE1 DE0 DECR (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) This register is used to set the number of data bytes to be transmitted and is valid only for data transmission. Table 13.3.6a Number of transmit data bytes setting DE7-0 Number of transmit data bytes 01H 1 byte 02H 2 bytes .. .. .. .. FFH 255 bytes 00H 256 bytes During slave transmit, make sure to set the transmit data count byte to ‘1’ when the control frame are 0H (Reading Slave Status), 4H (Reading Lock-address of the lower 8-bit), 5H (Reading Lock-address of the upper 8-bit), 6H (Reading slave -status and diabling lock). If the no. of bytes required to transfer is greater than the maximum no of transfer byte per frame, it will result in multiframe communciation. In that case, DEWR should be set using the following formula. DEWR = DERR - Maximum no. of transfer bytes per frame Upon the completion of one frame, the remaining number of byte required to transfer can be obtained by deducting the maximum no. of transfer byte per frame from DERR. This value is used to set DEWR for the next frame. 152 Chapter 13: IE Bus MB90580 Series 13.3 Registers and Register Details 13.3.7 Status register upper byte (STRH) Status register upper byte (STRH) Address: 000079H Read/write Initial value 15 14 13 12 11 10 9 8 COM TE PEF ACK RIF TIF TSL EOD (R) (0) (R/W) (0) (R) (X) (R) (X) (R/W) (0) (R/W) (0) (R) (0) (R) (0) Bit Number STRH [bit 15] COM (Communication status): This bit indicates the communication status as described below. 0 Communication is prohibited 1 Communication is enabled When this bit is ‘0’ and the PCOM bit in command register (CMRH) is written ‘1’, this bit is set. When communication ends, this bit will be cleared. . [bit 14] TE (Timing error): This bit is set when timing error has occurred during communication. Writing ‘0’ will clear this bit. This bit is written ‘0’ only, there is no meaning for writing ‘1’. [bit 13] PEF (Parity error): This bit is set when parity error has been detected. 0 No parity error 1 Parity error In receive side, if this bit is set, the acknowledge bit will not be returned. This bit will be cleared after the communication inhibit state is released. [bit 12] ACK (Acknowledge bit): This bit indicates 0 The acknowledge bit is ‘0’ 1 The acknowledge bit is ‘1’ During normal communication, acknowlege bit will be returned after each data received correctly. This bit will be cleared after communication inhibit state is released. This bit has no meaning in multiaddress communication and the read value is indefined. MB90580 Series Chapter 13: IE Bus 153 13.3 Registers and Register Details [bit 11] RIF (Receive interrupt flag): This bit is set when receive interrupt is occurred. 0 No receive interrupt request 1 Have receive interrupt request This bit is cleared by writing ‘0’ to this bit or after the extended intelligent I/O service has been served. This bit is written ‘0’ only. [bit 10] TIF (Transmit interrupt flag): This bit is set when transmit interrupt is occurred. 0 No transmit interrupt request 1 Have transmit interrupt request This bit is cleared by writing ‘0’ to this bit or after the extended intelligent I/O service has been served. This bit is written ‘0’ only. [bit 9] TSL (Transmit limit): This bit is set when the maximum number of data bytes that can be transmitted in one communication frame has been reached. And this bit is cleared when next communication frame starts. [bit 8] EOD (End of data): This bit is set when the number of data bytes specified by telegraph length field has been transferred completely. It means communication ends normally. This bit is cleared when next communication frame starts. 154 Chapter 13: IE Bus MB90580 Series 13.3 Registers and Register Details 13.3.8 Status register lower byte (STRL) Status register lower byte (STRL) Address: 000078H Read/write Initial value 7 6 5 4 3 2 1 0 WDBF RDBF WDBE RDBE ST3 ST2 ST1 ST0 (R) (0) (R) (0) (R) (1) (R) (1) (R) (X) (R) (X) (R) (X) (R) (X) Bit Number STRL [bit 7] WDBF (Write data buffer full): This flag indicates the status of the write data buffer (WDB). 0 Write data buffer is not full 1 Write data buffer is full This bit is set when WDB is full and cleared when at least one byte of data can be written into WDB. [bit 6] RDBF (Read data buffer full): This flag indicates the status of the read data buffer (RDB). 0 Read data buffer is not full 1 Read data buffer is full This bit is set when RDB is full and cleared when at least one byte of data can be received and stored in RDB. [bit 5] WDBE (Write data buffer empty): This flag indicates the status of the write data buffer (WDB). 0 Write data buffer is not empty 1 Write data buffer is empty This bit is set when WDB is empty and cleared when data is written into WDB. Writing ‘1’ to WDBC in command register CMRL will set this bit. [bit 4] RDBE (Read data buffer empty): This flag indicates the status of the read data buffer (RDB). 0 Read data buffer is not empty 1 Read data buffer is empty This bit is set when RDB is empty and cleared when data is received and stored in RDB. Writing ‘1’ to RDBC in command register CMRL will set this bit. MB90580 Series Chapter 13: IE Bus 155 13.3 Registers and Register Details [bit 3-0] ST3, ST2, ST1, ST0 (Operation status bits) These bits indicates the communication status of the unit and generates the corresponding interrupt during transmission or reception. By reading these bits, the communication status of the unit can be known. Table 13.3.8a Status flag ST3 ST2 ST1 ST0 Status State 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 Ends without all data being transmitted 0 1 0 0 Master receive starts 0 1 0 1 0 1 1 0 0 1 1 1 Ends without all data being received 1 0 0 0 Slave receive starts 1 0 0 1 1 0 1 0 1 0 1 1 Ends without all data being received 1 1 0 0 Multiaddress receive starts 1 1 0 1 1 1 1 0 1 1 1 1 Transmit starts Master/slave transmit Master receive Slave receive Multiaddress receive During transmission Transmit ends normally Master receive data full Master receive ends normally Slave receive data buffer full Slave receive ends normally Multiaddress receive data buffer full Multiaddress receive ends normally Ends without all data being received For more detail description on setting these four bits, please refer to Table 13.5.2a. 156 Chapter 13: IE Bus MB90580 Series 13.3 Registers and Register Details 13.3.9 Lock read register (LRRH, LRRL) Lock read register (LRRH, LRRL) 15 Address: 00007BH 14 Reserved Reserved Reserved Read/write Initial value (R) (1) (R) (1) 7 Address: 00007AH Read/write Initial value 13 6 (R/W) (1) 5 12 11 10 9 LOC LD11 LD10 LD09 (R) (0) (R) (X) (R) (X) (R) (X) (R) (X) 4 3 2 1 0 LD01 LD00 LD07 LD06 LD05 LD04 LD03 LD02 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) 8 Bit Number LRRH LD08 Bit Number LRRL (R) (X) [bit 15-13] Reserved bits: Always reading ‘1’ from these bits. [bit 12] LOC (Lock check): This bit indicates the status whether the unit is locked or not from other unit. 0 Does not lock 1 Locked Writing ‘0’ to this bit will unlock the unit itself. Writing ‘1’ to this bit has no meaning. [bit 11-0] LD11 - LD00 (Lock address): These bits store the lock address, the address of the master that has executed locking to the unit. When the unit is not locked. there is no meaning for these bits. Note: In IEBus communication, the lock function is used to transmit a message over two or more communication frames. If the master that has executed locking was down before executing the unlocked command, the locked unit cannot receive data anymore. So in order to prevent such condition, the unit in the system that supporting lock function need checking the lock status periodically by reading this lock read register. And the unit can unlock itself by writing ‘0’ to LOC bit.. MB90580 Series Chapter 13: IE Bus 157 13.3 Registers and Register Details 13.3.10 Master address read register (MARH, MARL) Master address read register (MARH, MARL) 15 Address: 00007DH Read/write Initial value Address: 00007CH Read/write Initial value 14 13 12 Reserved Reserved Reserved Reserved (R) (1) (R) (1) 7 6 (R) (1) 11 10 9 8 MA11 MA10 MA09 MA08 (R) (X) (R) (X) 1 0 MA01 MA00 (R) (1) (R) (X) (R) (X) 5 4 3 2 MA07 MA06 MA05 MA04 MA03 MA02 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) Bit Number MARH Bit Number MARL (R) (X) [bit 15 - 12] Reserved bits: Always reading ‘1’ from these bits. [bit 11 - 0] MA11 - MA00 (Master address): In slave mode, these bits store the address of the master that has won the arbitration in master address field. If the unit itself is the master, then the unit address stored in unit address register (MAWH, MAWL) will be read out. 158 Chapter 13: IE Bus MB90580 Series 13.3 Registers and Register Details 13.3.11 Multiaddress, control bit read register (DCRR) Multiaddress, control bit read register (DCRR) Address: 00007FH Read/write Initial value 15 14 DO3 DO2 (R) (0) (R) (0) 13 12 11 10 9 8 Bit Number DO1 DO0 C3 C2 C1 C0 DCRR (R) (0) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) [bit 15-12] DO3, DO2, DO1, DO0 (Multiaddress/normal communication bits): In slave mode, the received multiaddress bit from the master is stored in bit DO0. If the unit itself is the master, the multiaddress/normal communication set bits (DO3-0) in multiaddress, control bit set register (DCWR) is read out. Normal communction: (0001B) Multiaddress communication: (0000B) DO3~0 always read as “0”. [bit 11-8] C3, C2, C1, C0 (Control bits) In slave mode, the received control bits from the master are stored in these bits. If the unit itself is the master, the control bits (C3-0) in multiaddress, control bit set register (DCWR) is read out. These bits are set after the control field has been received and acknowledge bit was detected. For more detail description, please refer to Table 13.3.5a. MB90580 Series Chapter 13: IE Bus 159 13.3 Registers and Register Details 13.3.12 Telegraph length read register (DERR) Telegraph length read register (DERR) Address: 00007EH Read/write Initial value 7 6 5 4 3 2 DE7 DE6 DE5 DE4 DE3 DE2 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) 1 0 Bit Number DE1 DE0 DERR (R) (X) (R) (X) if the unit itself is the receiver, this register stores the number of data specified by telegraph length field. If the unit itself is the transmitter, the telegraph length bits in telegraph length set register (DEWR) are read. This register is set after the following. 1. When used as master unit (a) In transmit mode, the number of transmit data bytes is written into DEWR (b) In receive mode, the telegraph length field is received (c) Communication ends 2. When used as slave unit (a) In transmit mode, the number of transmit data bytes is written into DEWR (b) In receive mode, the telegraph length field is received (c) Communication ends 160 Chapter 13: IE Bus MB90580 Series 13.3 Registers and Register Details 13.3.13 Read data buffer (RDB) Read data buffer (RDB) Address: 000081H Read/write Initial value 12 11 10 9 8 Bit Number RD5 RD4 RD3 RD2 RD1 RD0 RDB (R) (R) (R) (X) (X) (X) (R) (X) (R) (X) (R) (X) (R) (X) 15 14 13 RD7 RD6 (R) (X) This register (internally is a 8-byte FIFO buffer) stores received data in data field of the communication frame. When eight byte data have been received, RDB becomes full and receive interrupt is generated. Then data in RDB should be read out before the next coming byte of data is received as shown in Table 13.3.13a . Otherwise, error will be occurred. When error occurs in multiaddress reception, the communication ends. But when error occurs in normal reception, the acknowledge bit will not returned to the transmitter. Then the transmitter will resend data again until the maximum number of data transmitted is reached. Even though RDB is not full, the receive interrupt will be generated when the number of data specified in the telegraph field have been received, or the maximum number of data received in one communication frame is reached. Once the receive interrupt has occurred, the data in RDB should be read out. Writing ‘1’ to WDBC in CMRL will clear all data in the buffer and return it as empty state. This register can only be read when noit empty Table 13.3.13a Time Required for next data receive after receive buffer full interrupt occurred MB90580 Series Maximum Time (us) No. of Cycles Mode 0 1580 19000 Mode 1 400 4800 Mode 2 290 3400 Chapter 13: IE Bus 161 13.3 Registers and Register Details 13.3.14 Write data buffer (WDB) Write data buffer (WDB) Address: 000080H Read/write Initial value Bit Number 7 6 5 4 3 2 1 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 (W) (X) (W) (X) (W) (X) (W) (X) (W) (X) (W) (X) (W) (X) (W) (X) 0 WDB This register (internally is a 8-byte FIFO buffer) stored data to be transmitted in data field of the communication frame. The data write interrupt timing is set by the two bits TIT1, TIT0 in command register (CMRL). When the write interrupt occurs, next data is requested to write into WDB. When all data has been transmitted (WDB is empty), and the data cannot be writtenin RDB within the time listed in Table 13.3.14a, it will result in an error and the transmission will be terminated. Writing ‘1’ to WDBC bit in command register CMRL will clear the buffer and return it as empty state. This register can only be written when not full. Table 13.3.14a Data write time after WDB empty interrupt 162 Maximum Time No. of cycles Mode 0 1580 19000 Mode 1 400 4800 Mode 2 290 3400 Chapter 13: IE Bus MB90580 Series 13.4 IEBus Communication Protocol 13.4 IEBus Communication Protocol 13.4.1 Overview IEBus (Inter Equipment Bus) is a small-scale two-line serial bus interface intended to transfer data between equipment and equipment. • Communication method Data are transferred by means of half duplex asynchronous communication. • Multi-master method All the units connected to the IEBus can transfer data to the other units. • Multiaddress communication function (one unit can communicate to two or more units simultaneously) Group communication: multiaddress communication to group units Broadcasting communication: multiaddress communication to all units • Three transfer rates can be selected: Table 13.4.1a IEBus transfer rates Mode IEBus internal clock = 6MHz IEBus internal clock = 6.29MHz Maximum number of transfer bytes (bytes / frame) 0 approx. 3.9Kbps approx. 4.1 Kbps 16 1 approx. 17Kbps approx. 18 Kbps 32 2 approx. 26Kbps approx. 27Kbps 128 • Access control: CSMA/CD (Carrier Sense Multiple Access with Collision Detection) • The priority to occupy the IEBus: (1) Multiaddress communication takes precedence over normal communication (communication between one unit and another). (2) The lower master address takes precedence over the higher address. • Communication scale Note Number of units: 50 max. Cable length: 150m max. (when twisted pair cable with resistance less than 0.1 W/m is used) loading Capacitance: 8000pF max. (between BUS- and BUS+) when IEBus internal clock is 6 MHz 7100pF max. (between BUS- and BUS+) when IEBus internal clock is 6.29MHz Terminal resistance: 120 W. Note:The system sacle depends on the IE Bus driver/receiver that is used. MB90580 Series Chapter 13: IE Bus 163 13.4 IEBus Communication Protocol 13.4.2 Determining bus mastership (arbitration) The equipment connected to the IEBus performs an operation to occupy the bus when it controls another equipment. This operation is called arbitration. Arbitration is to grant the bus mastership to one of several units that have simultaneously started transmission. As only one equipment acquires the bus mastership as a result of arbitration, the following priority is used to determine which equipment acquires the bus mastership: • Priority on type of communication Multiaddress communication takes precedence over normal communication. • Priority on master address If the type of communication is the same, the lower master address takes precedence over the higher one. Example: The master address consists of 12 bits, the unit at 000H has the highest priority, and the unit at FFFH has the lowest priority. 13.4.3 Communication mode The IEBus provides three communication modes, in which each has a different transfer rate. The transfer rate in each communication mode and the maximum number of transfer bytes in one communication frame are shown as below: Table 13.4.3a Transfer rate and maximum number of transfer byte in each communication mode Mode Maximum number of transfer bytes (bytes / frame) Effective transfer rate (bps) Note1 IEBus internal clock = 6MHz Note2 IEBus internal clock = 6.29 MHz Note2 0 16 approx. 3.9Kbps approx. 4.1 Kbps 1 32 approx. 17Kbps approx. 18 Kbps 2 128 approx. 26Kbps approx. 27Kbps Note1: Effective transfer rate is measured when the maximum number of data bytes have been transferred. Note2: The relationship between IEBus internal clock and CPU clock is referred to Table 13.3.2d. Caution1: The required communication mode should be selected for each equipment connected to the IEBus before communication is started. Also, the communication is not performed correctly unless the communication mode of the master and the slave unit are the same. Caution2: Be sure that both the communication mode and IEBus internal clock are the same for all units connected to the IEBus. Even though the same communication mode is selected, the communication is still performed incorrectly if the IEBus internal clock frequency is different. 164 Chapter 13: IE Bus MB90580 Series 13.4 IEBus Communication Protocol 13.4.4 Communication address In IEBus, each equipment is assigned to a specific 12-bit communication address. The communication address is consisted of: Higher 4 bits:group number (identify which group the equipment belongs to) Lower 8 bits:unit number (identify each equipment in one group) 13.4.5 Multiaddress communication In normal communication mode, the communication is performed on a one-to-one basis, i.e. only one master and one slave. In contrast, multiaddress communication allows the master transmitting data to more than one slave. As more than one slave exist in the IEBus, none of them returns an acknowledge signal in the communication. The multiaddress bit is used to select either multiaddress communication or normal communication. For detail description, refer to (6) transfer protocol. Multiaddress communication has the following two modes: • Group multiaddress communication Communicating with equipments having the same group number as specifying in higher 4 bits of the communication address. • Broadcasting communication Communicating with all equipments, regardless of the value of the group number The slave address specified in slave address field is used to identify either group multiaddress or broadcasting communication. For detail description, refer to section Section 13.4.6, “Transfer protocol". MB90580 Series Chapter 13: IE Bus 165 13.4 IEBus Communication Protocol 13.4.6 Transfer protocol The signal transmit format of the IEBus is shown as below Field Name No. of bits Header 1 1 Master Slave address address field field 1 12 12 1 1 Control field 4 Slave Multi- Master Control Frame format Start address address P address P A bit bits bit bits bits Transmit time 1 1 P A Telegraph length field 1 1 8 Data field 8 8 1 1 Telegraph Data length P A bits P A bits 1 1 Data bits P A Mode 0 approx. 7330 µs approx. 1590 x N µs Mode 1 approx. 2090 µs approx. 410 x N µs Mode 2 approx. 1590 µs approx. 300 x N µs Note1: P: parity bit A: acknowledge bit where A=0: ACK and A=1: NAK Note2: The acknowledge bit is ignored in multiaddress communication. (1) Header The header field is consisted of start bit and multiaddress bit. • Start bit The start bit is a signal used to inform the other units that data transmission starts. The unit initiating the data transmission outputs a low-level signal (start bit) for a specific time and then outputs the multiaddress bit. When one unit tries to output the start bit, but it found that another unit has already output a start bit, then the unit does not output the start bit. But it waits for the end of the start bit output by the another unit and outputs the multiaddress bit in synchronization with the output end timing of the start bit. The units other than the one that has started transmission detect this start bit and enters the receive status. • Multiaddress bit This bit indicates whether the master selects multiaddress or normal communication. When the multiaddress bit is ‘0’ for multiaddress communication and is ‘1’ for normal communication. Moreover, multiaddress communication is divided into two modes, group multiaddress and broadcasting communication. These two modes are identified by the value of the slave address. In multiaddress communication, since there are two or more slave units, the acknowledge bit for each field following the master field is not returned. If at the same time, two or more units start transmission of a communication frame, multiaddress communication takes precedence over normal communication and is the winner in arbitration. (2) Master address field This field is outputted by the master to identify its address for other units being communicated and is consisted of 12 bit of master address with MSB transmitting first and 1 parity bit. If at the same time, two or more units starts transmitting the multiaddress bit of the same value, judgement of arbitration is based on the master address field value. Everytime when the unit transmits one bit of its unit address, it compares the data output with the data on the IEbus. If they are found to be different, the unit lost the arbitration and then stops transmission and enters receive status. Since the IEBus is configured as wired AND, the unit having the least master address among the units participating in arbitration (arbitration masters) wins arbitration. After 12-bit master address is transmitted out, only one unit remains in transmit status as the master. This master then outputs the parity bit and let other units confirming that the transmit master address data contains no error. After that, the slave address field is output. Note:Even parity is used for parity check. If the total number of ‘1’ in master address bits is odd, the parity bit will be set as ‘1’. 166 Chapter 13: IE Bus MB90580 Series 13.4 IEBus Communication Protocol (3) Slave address field This field outputs the address of the other unit with which the master is to communicate and is consisted of 12 bits of slave address with MSB transmitting first, parity bit and acknowledge bit. After a 12-bit slave address has been transmitted, a parity bit is output to ensure that the slave address is not received by mistake. Then the master unit detects an acknowledge signal from slave unit to confirm its existence on the IEBus. After the detection of acknowledge signal, the master unit starts outputting the control field. However in multiaddress communication mode, the master starts outputting the control field without detecting the acknowledge bit. In the slave side, when it detects that the slave address has coincided with its own unit address, and the parity bit in both master address field and slave address field are even, it outputs an acknowledge signal. However, if parity bit is odd, the slave unit judges that either master address or slave address has been received incorrectly, and then acknowledge signal is not returned. At this moment, the master unit enters the standby (monitor) status, and communication ends. In multiaddress communication mode, the slave address is used to identify whether it is group multiaddress or broadcasting communication as follows: When slave address is FFFH: Broadcasting communication When slave address is not FFFH: Group multiaddress communication Note:The group number for group multiaddress communication is identified by the higher 4 bits of the slave address. (4) Control field This field is used to control the type of following data field and direction of data transfer between master and slave. This field is consisted of 4 bits of control bit with MSB transmitting first, parity bit and acknowledge bit. If even parity is checked and the slave can execute the function requested by the master, the slave returns an acknowledge signal and then proceeds to the telegraph length field. Even though the parity is even, but if the slave unit cannot execute the function requested by the master, or if the parity is odd, the slave unit does not output the acknowledge signal and returns to the standby (monitor) status. After the master confirms the return of acknowledge signal, it proceeds to the telegraph length field. If the master cannot receive the acknowledge signal, it enters the standby status, and communication ends. In multiaddress communication mode, the master unit does not detect the acknowledge signal, but proceeds to the telegraph length field. (5) Telegraph length field This field is used to indicate the number of bytes of transmit data from the transmitter to receiver. This field is consisted of 8 bits of telegraph length with MSB transmitting first, parity bit and acknowledge bit. Table 13.4.6a shows the relationship between the telegraph length field and the number of transmit data bytes. Table 13.4.6a Number of transmit data bytes setting Telegraph length bits (HEX) Number of transmit data bytes 01H 1 byte 02H 2 bytes .. .. .. .. FFH 255 bytes 00H 256 bytes Note:According to the communication mode being set, if the number of transmit data bytes set in telegraph length field is greater than the maximum number of transmit data bytes per frame, then communication with multi-frame is performed. In this MB90580 Series Chapter 13: IE Bus 167 13.4 IEBus Communication Protocol case, the second and following communication frames will transmit the remaining data bytes specified in the telegraph length field. The function of telegraph length field differs when the master is in transmit mode (bit 3 of control bits is ‘1’) or receive mode (bit 3 of control bits is ‘0’) as follow: • Master transmit mode The telegraph length bits and parity bit are output by the master unit. If even parity is detected by the slave, it returns the acknowledge signal. Then the master proceeds to the data field. But in multiaddress communication mode, the slave does not return any acknowledge signal. If odd parity is detected, the slave judges that the telegraph length bits have not been correctly received, and then go into standby (monitor) mode without returning acknowledge signal. At the same time, the master also goes into standby status, and communication ends. • Master receive mode The slave outputs the telegraph length bits and parity bit. If even parity is detected by the master, it returns the acknowledge signal. But if odd parity is detected, the master judges that the telegraph length bits have not been correctly received, and goes into the standby status without returning acknowledge signal. Then the slave also goes into standby status, and communication ends. (6) Data field This field is used by the master to transmit/receive data to/from the slave. This field is consisted of eight data bits with transmitting MSB first, parity bit and acknowledge bit. Multiaddress communication can only be performed when the master unit transmits data and the acknowledge signal is ignored. The operations for master transmits and receives data are described as follow: • Master transmit mode When the master writes data to a slave, it transmits data bits and parity bit to the slave. Then if even parity is detected by the slave and its receive data buffer is not full, the slave returns the acknowledge signal. If odd parity is detected or the receive buffer is full, the slave rejects accepting the corresponding data, and does not return the acknowledge signal. If the acknowledge is not detected by the master, it retransmits the same data until the acknowledge bit is detected or the maximum number of transmit bytes is exceeded. If the parity is even and the acknowledge signal is returned from the slave, the master transmits the next available data if the maximum number of transmit bytes is not exceeded. In multiaddress communication mode, the slave unit does not return the acknowledge signal, and the master transmits data on a 1-byte-by-1-byte basis. • Master receive mode When the master reads data from the slave, the master outputs a synchronous signal corresponding to all the read bits. Then the slave outputs the data and parity bit to the IEBus in response to the synchronous signal output by the master. After that, the master reads these bits and confirm the parity check. If odd parity is detected or the master’s receive buffer is full, it rejects accepting the data and does not return the acknowledge signal. If the maximum number of transmit bytes per frame is not exceeded, the master repeatedly reads the same data. If even parity is detected and the master’s receive buffer is not full, the master accepts the data and returns the acknowledge signal. If the maximum number of transmit bytes per frame is not exceeded, the master reads the next data. (7) Parity bit The parity bit is used to confirm that the transmit data contains no error. It is appended to master address bits, slave address bits, control bits, telegraph length bits and data bits. The parity is an even parity. If the number of ‘1’ bits in the data is odd, then the parity bit is set to ‘1’. If the number of ‘1’ bits in the data is even, then the parity bit is set to ‘0’. (8) Acknowledge bit An acknowledge bit is appended to the following location to confirm whether data has been correctly received in the normal communication mode (communication between one unit and another): 168 • At the end of slave address field • At the end of control field • At the end of telegraph length field Chapter 13: IE Bus MB90580 Series 13.4 IEBus Communication Protocol • At the end of data field The acknowledge bit is defined as: ‘0’: The transmit data is recognized (ACK) ‘1’: The transmit data is not recognized (NAK) The acknowledge bit is ignored in multiaddress communication. 1. Acknowledge bit at the end of slave field The acknowledge bit at the end of the slave field is treated as NAK in any of the following cases, and then transmission is aborted: • If the parity of the master address bits or slave address bits is not correct • If a timing error (error in bit format) occurs • If the specific slave unit does not exist 2. Acknowledge bit at the end of the control field The acknowledge bit at the end of the control field is treated as NAK in any of the following cases, and then transmission is aborted: • • • • If the parity of the control bits is not correct If bit 3 of the control bits is ‘1’ (write operation) but the slave receive bufferNote is full If the control bits indicate data read (3H, 7H) but the slave transmit buffer Note is empty If the slave has been locked, but value of 3H, 6H, 7H, AH, BH, EH or FH in the control bits are requested by another unit other than the one has set locking • If the control bits indicate reading of a lock address (4H) but the slave has not been locked. • If a timing error occurs • If undefined control bit values are set Note:Refer to slave status (SSR) in (7) 3. Acknowledge bit at the end of the telegraph length field The acknowledge bit at the end of the telegraph length field is treated as NAK in any of the following cases, and transmission is aborted: • If the parity of the telegraph length bits is not correct • If a timing error occurs 4. Acknowledge bit at the end of data field The acknowledge bit at the end of the data field is treated as NAK in any of the following cases, and then transmission is aborted: • If the parity of the data bits is not correct Note • If a timing error occurs after the previous acknowledge bit has been transmitted • If the receive buffer has become full and thus no more data can be accepted Note:The same data is retransmitted if the maximum number of transmit data bytes per frame is not exceeded. MB90580 Series Chapter 13: IE Bus 169 13.4 IEBus Communication Protocol 13.4.7 Transmit data The content in data field is controlled by the control bits in control field and is shown below: Table 13.4.7a Control bits setting Bit 3Note Bit 2 Bit 1 Bit 0 0H 0 0 0 0 Slave status (SSR) read 1H 0 0 0 1 Undefined 2H 0 0 1 0 Undefined 3H 0 0 1 1 Data read and lock 4H 0 1 0 0 Lock address read (Lower 8 bits) 5H 0 1 0 1 Lock address read (Upper 4 bits) 6H 0 1 1 0 Slave status (SSR) read and unlock 7H 0 1 1 1 Data read 8H 1 0 0 0 Undefined 9H 1 0 0 1 Undefined AH 1 0 1 0 Command write and lock BH 1 0 1 1 Data write and lock CH 1 1 0 0 Undefined DH 1 1 0 1 Undefined EH 1 1 1 0 Command write FH 1 1 1 1 Data write 1 Function Note 2 Note1: The direction in which telegraph length bits in the telegraph length field and data in the data field are transferred is changed depending on the value of Bit 3 as follows: When Bit 3 is ‘1’: Transfer from master unit to slave unit When Bit 3 is ‘0’: Transfer from slave unit to master unit Note2: Control bits 3H, 6H, AH, BH are used to lock and unlock the unit. When those undefined control bits 1H, 2H, 8H, 9H, CH, DH has been received, the acknowledge bit is not returned. When the slave is locked, it can only execute the following command requesting by other units besides of the master executing the lock command: Table 13.4.7b The control command that can be executed by a locked slave unit 170 Bit 3 Bit 2 Bit 1 Bit 0 0H 0 0 0 0 Slave status (SSR) read 4H 0 1 0 0 Lock address read (Lower 8 bits) 5H 0 1 0 1 Lock address read (Upper 4 bits) Chapter 13: IE Bus Function MB90580 Series 13.4 IEBus Communication Protocol (1) Slave status (SSR) read (control bits: 0H, 6H) By reading the slave status, the master can understand why the slave has not returned the acknowledge bit (ACK). The slave status is determined in respect to the result of the last communication performed by the slave unit. Moreover all slaves can supply the information of slave status as configured below: MSB Slave Status Bit 7 LSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Table 13.4.7c Meaning of Slave Status Bit Bit 0 Note1 Bit 1 Note2 Bit 2 Bit 3 Value Meaning 0 Slave transmit buffer is empty 1 Slave transmit buffer is not empty 0 Slave receive buffer is not full 1 Slave receive buffer is full 0 Unit is not locked 1 Unit is locked 0 Fixed to ‘0’ 0 Slave transmission is stopped Note3 1 Slave transmission is enabled Bit 5 0 Fixed to ‘0’ Bit 4 Bit 6 Bit 7 00 Mode 0 01 Mode 1 10 Mode 2 11 Prohibited Indicates the highest mode that is supported by the unit Note 4 Note1: The slave transmit buffer is the buffer accessed when data is read (control bits: 3H, 7H). This buffer is same as the write data buffer (WDB). Note2: The slave receive buffer is the buffer accessed when data is written (control bits: 8H, AH, BH, EH, FH). This buffer is same as the read data buffer (RDB). Note3: This bit can be selected by the PCOM bit in command register (CMRH). Note4: For MB90580 series, 10 is fixed. (2) Data/command transfer (control bits: read (3H, 7H), write (AH, BH, EH, FH)) If the control bits indicate data read (3H, 7H), the data in the data buffer of the slave is read by the master. If the control bits indicate data write (BH, FH) or command write (AH, EH), the data received by the slave is processed in accordance with the operation regulation of that slave. Note1: The data or command can be selected with the user’s own decision in the corresponding system. Note2: The slave is also locked when control bits are 3H, AH and BH. MB90580 Series Chapter 13: IE Bus 171 13.4 IEBus Communication Protocol (3) Read lock address (control bits: 4H, 5H) When the lock address is read (control bits: 4H, 5H), the address (12-bit) of the master that has issued the lock instruction is configured in 1-byte units as shown below and is read. Control bits: 4H Lower 8 bits Control bits: 5H Undefined MSB Higher 4 bits LSB (4) Locking and unlocking The lock function is used to transmit a message over two or more communication frames. The unit that has been locked cannot receive data from any unit other than the one that has locked it. A unit is locked or unlocked as follows: • Locking When the lock command has been executed (control bits: 3H, AH, BH) and the acknowledge bit ‘0’ in the telegraph length field has been transmitted or received, but the number of data bytes specified by the telegraph length bits cannot be transmitted or received successfully within the communication frame, then the slave is locked by the master, and the bit related to locking (bit 2) in the slave status is set. • Unlocking When the lock command (control bits: 3H, AH, BH) or unlock command (control bits: 6H) has been executed, and the number of data bytes specified by the telegraph length bits can be transmitted or received successful within one communication frame, then the slave is unlocked by the master and the bit related to locking (bit 2) in the slave status is cleared. Furthermore, the slave is not locked or unlocked while multiaddress communication is performed. 172 Chapter 13: IE Bus MB90580 Series 13.4 IEBus Communication Protocol 13.4.8 Bit format The format of the bits constituting an IEBus communication frame is shown below: Logic ‘1’ Logic ‘0’ Preparation Synchronizatio n period period Data period Pause period Synchronizatio n period Data period Logic ‘1’: voltage difference between inter-bus wires (BUS+ and BUS-)is below 20 mV (low level) Logic ‘0’: voltage difference between inter-bus wires (BUS+ and BUS-) is above 120 mV (high level) Preparation period: First low-level period (logic ‘1’) Synchronization period: Next high-level period (logic ‘0’) Data period: Period indicating bit value (logic ‘1’ = low level, logic’0’ = high level) The length of synchronization period and data period are almost the same. The IEBus establishes synchronization for each bit. The specifications of the time of the entire bit and the time of the period assigned to the bit differ depending on the type of the transmit bit, and whether the unit is master or slave. Moreover, the specified interval for every period (preparation, synchronization, data) in the communication are detected by both the master and slave. If data cannot be detected within that specified interval, timing error occurs in both master and slave, and then the communication ends and goes into standby mode. MB90580 Series Chapter 13: IE Bus 173 13.5 Operation 13.5 Operation 13.5.1 IEBus control (1) Master transmit The unit is set as master transmit to transmit data to the slave by sending data/command control bits as AH, BH, EH or FH. The sequences for operating in master transmit are described as below: 1. The master address is written in unit address register (MAWH, MAWL), the slave address is written in slave address register (SAWH, SAWL), multiaddress bit and control bits are written into multiaddress, control bit set register (DCWR). After that, the command register (CMRH) is set to release communication inhibit mode. 2. When the master has won the arbitration (after the master address field is finished), the state code (0H) indicating start of transmission is set in ST3-0 of status register (STRL) and transmit interrupt occurs. At this time, the number of transmitted data byte is required to write into telegraph length set register (DEWR) and transmit data is set in write data buffer (WDB), unless the WDb is not full. 3. When one byte of data is transmitted, the number of data in WDB is deducted by one. According to the setting of TIT1, TIT0 in command register (CMRL) that control the interval for writing data in WDB, the transmit interrupt occurs. At that time, the state code equals ‘1H’ indicating data transmission and WDB is not full. Therefore, data should be written in WDB. 4. If the specified number of data or command has been transmitted correctly, the state code (2H) indicating transmission ends normally is set in ST3-0 of status register (STRL), the EOD bit in STRH is set and transmit interrupt occurs. 5. If error occurs during transmission or in multi-frame communication the number of data byte specified in telegraph bit set register (DEWR) cannot be transmitted completely, the state code (3H) indicating transmission ends without all data are transmitted is set in ST3-0, and transmit interrupt occurs. At this time, the content of communication error can be known by checking the status of TSL, PEF, TE in status register (STRH). When timing error is occurred during the transmission, the data stored in WDB can’t be transmitted. If the TE bit is cleared and re-transnit sequence is executed, those data left in WDB, excluding the data byte that has timing error will be re-transmit. In order to perform new data transmission, the bit WDBC in CMRL must be written ‘1’ to clear the write data buffer. (2) Slave transmit ■ Data transmit This mode is set when the master sends control bits either 3H or 7H to slave and requests it to transmit data back to the master. The sequences for operating in slave data transmit are described as below: 1. After receiving master control code 3H or 7H, the data code (0H) indicating transmit start is set to ST3-0 of status register and the transmit interrupt is occurred. At this time, set the telegraph length set register (DEWR) with the nunmber of byte of data which are required to be transmitted. The transmit data can be written to WDB, provided that WDB is not full. 2. During the start of telegraph field transmission, the status register bits ST3-0 are set to 1H indicating data transmission in progress and transmit interrupt occurs. At that moment, transmit data can be written to the WDB, provided that WDB is not full. 3. When one byte of data is transmitted, the number of data in WDB is deducted by one. According to the setting of TIT1, TIT0 in command register (CMRL) that control the timing for writing data in WDB, the transmit interrupt occurs. Data can be written in WDB if state code is still (1H) and WDB is not full. 4. If the specified number of data or command has been transmitted correctly, the state code (2H) indicating transmission ends normally is set in ST3-0 of status register (STRL), the EOD bit in STRH is set and transmit interrupt occurs. 174 Chapter 13: IE Bus MB90580 Series 13.5 Operation 5. If error occurs during transmission or in multi-frame communication the number of data byte specified in DEWR cannot be transmitted completely, the state code (3H) indicating transmission terminated without all data transmitted is set in STRL:ST3-0. Transmit interrupt will occur. At this time, the content of communication error can be known by checking the status of TSL, PEF, TE in status register (STRH). The interval between setting ST3-0 and the first data is transmitted out from WDB is shown below: Table 13.5.1a Time required to write transmit data to WDB after transmit interrupt has occurred Mode Time (µS) Number of cycles 0 approx. 158 approx. 1900 1 approx. 40 approx. 480 2 approx. 29 approx. 350 Note : 1. Number of transmit bytes and transmit data can be set during the interrupt generated after the receiving of control bits. 2. As the time between the WDB empty interrupt and the next telegraph bit transmit interrupt is very short, thus it is recommended to take the following precautions when the first transmit data is required to write into WDB. • Only write data to WDB after the WDB empty confirmation. • In case of setting the transmit data byte count, it is required to set the value within the time listed in Table 13.5.1a. The default value of the transmit data byte count will transmit 256bytes. • If at least 1 byte of data is not set within the time listed in below after the transmit interrupt, WDB will be detected as empty. Error will be occurred after the transmission of telegraph field and the communication will be terminated. ■ Slave status, lock address transmit When the control bits 0H, 4H, 5H, 6H has been received from the master, the slave status, lock address are automatically transmitted to the master. In this way, there is no need to write data into WDB, but it is required to set 1H to the telegraph bit setting register. (3) Master receive The unit is set as master receive for getting data, slave status and lock address from the slave by first sending control bits 0H, 3H, 4H, 5H, 6H or 7H. The sequences for operating as master receive are described as below: 1. When the slave receives the control bits, it transmits the telegraph length bit. Then after the master receives these telegraph length bits and returns the acknowledge bit, the number of received data byte is written into the telegraph length read register (DERR). At this moment, no interrupt occurs. 2. After the acknowledge bit in telegraph length field is sent by the master, data reception will be started. And for each received data byte, the master stores it in the read data buffer (RDB). 3. After eight bytes of data are received, the state code (5H) is set in ST3-0 of status register (STRL), receive interrupt occurs. 4. When the last byte of data is received and stored in RDB within one communication frame, the state code (5H) is set in ST3-0 and receive interrupt occurs. This interrupt will be generated even thought RDB is not full. 5. If error is occurred during reception, or the maximium number of data byte has been received in one communication frame, the master cannot received the number of data byte specified in telegraph field and communication is terminated. The state code (7H) indicating master receive ends without all data are received is set in ST3-0, and receive interrupt occurs. MB90580 Series Chapter 13: IE Bus 175 13.5 Operation (4) Slave receive This mode is set when the slave unit receive control bits AH, BH, EH or FH from the master. The sequences for operating as slave receive are described as below: 1. After the slave returns the acknowledge bit in telegraph length field, the number of receive data byte is written in the telegraph length read register (DERR). At this moment, no interrupt occurs. 2. Following the telegraph length field is the data field, the master starts transmitting data and each received data byte is stored in the read data buffer (RDB). 3. After eight bytes of data are received, the state code (9H) indicating slave receive buffer full is set in ST3-0 of status register (STRL), and receive interrupt occurs. If the receive interrupt occurs, the RDB can be read after the confirmation of buffer not empty. 4. When the last byte of data in one communication frame is received and stored in RDB, the state code (AH) indicating slave receive ends normally is set in ST3-0 and receive interrupt occurs. This interrupt will occur even thought the buffer is not full. 5. If error is occurred during reception or the maximium number of data byte has been re3ceived in one commmunication frame, the slave cannot receive the number pf data byte specified in telegraph field and communication is terminated.. The state code (BH) indicating slave receive ends without all data are received is set in ST3-0, and receive interrupt occurs. (5) Multiaddress receive 1. After the slave has received the telegraph length field, the number of receive data byte is written in the telegraph length read register (DERR). At this moment, no interrupt occurs. 2. After the telegraph lenght field is received, each correctly received data byte is stored in the read data buffer (RDB). 3. After eight bytes of data are received, the state code (DH) indicating multiaddress receive buffer full is set in ST3-0 of status register (STRL), and receive interrupt occurs. If the receive interrupt occurs, the RDB can be read after the confirmation of buffer not empty. 4. When the last byte of data in one communication frame is received and stored in RDB, the state code (EH) indicating multiaddress receive ends normally is set in ST3-0 and receive interrupt occurs. This interrupt will occur even thought the buffer is not full. 5. If error is occurred during reception or the maximium number of data byte has been received in one communication frame, the slave cannot receive the number of data byte specified in telegraph field and communication is terminated. The state code (FH) indicating multiaddress receive ends without all data are received is set in ST3-0, and receive interrupt occurs. For detail description on ST3-0, please refer to Table 13.5.2a. 176 Chapter 13: IE Bus MB90580 Series 13.5 Operation 13.5.2 Communication status In the status register, there are four bits ST3-0 indicating the status code. After the status code has been set, interrupt request is generated. During the interrupt routine, the communication status can be investigated by reading the status register. But at the beginning of master, slave and multiaddress receive, no interrupt will be generated (1) Master, slave data transmit (transmit interrupt occurs) When the unit won the arbitration in multiaddress or master address field, it becomes master unit. Then data/command is transmitted to or data is received from the slave, and the status code ST3-0 is set and shown as below: Table 13.5.2a Meaning of status code ST3-0 for master, slave transmit Code Name Code ST3-0 Content Transmit starts 0000 Indicates start of master/slave transmission. 1) master transmit Indicates the master address field in communication frame has been transmitted, and the unit has won in arbitration as the master. 2) slave transmit Indicates that the unit has received control bits 0H, 3H, 4H, 5H, 6H, 7H from the master that requests data transmission, and slave data transmission is started. Transmit data 0001 Indicates that data is transmitting by Master unit or Slave unit. This control code will be set after the starting of telegraph length field transmission. Transmit ends normally 0010 Indicates that the number of data transmit specified by telegraph length field has been completed within one communication frame Ends without all data being transmitted 0011 Indicates that the communication has ended without transmitting the number of data specified by telegraph length field in one communication frame. (2) Master receive (receive interrupt occurs) When the unit won the arbitration in multiaddress or master address field, it becomes master unit. Then data, status or log address are received from slave unit, and the status code ST3-0 is set and shown as below: Table 13.5.2b Meaning of status code ST3-0 for master receive Code Name Code ST3-0 Master receive starts 0100 Indicates that the master has received the telegraph field correctly from the slave and master reception is started but receive interrupt does not occur at this moment. Master receive data full 0101 Indicates that the receive data buffer RDB for master reception is full (eight byte of data has been received), and the host controller is requested to read data from the RDB. Master receive ends normally 0110 Indicates the number of data specified by the telegraph field has been received within one communication frame. Ends without all data being received 0111 Indicates that the communication has ended without receiving the number of data specified by telegraph length field in one communication frame. MB90580 Series Content Chapter 13: IE Bus 177 13.5 Operation (3) Slave receive (receive interrupt occurs) When data/command is received from the master unit, the status code ST3-0 is set and shown as below: Table 13.5.2c Meaning of status code ST3-0 for slave receive Code Name Code ST3-0 Content Slave receive starts 1000 Indicates that the slave unit has received the telegraph field correctly from master unit and slave reception is started but receive interrupt does not occur at this moment. Slave receive data full 1001 Indicates that the receive data buffer RDB for slave reception is full (eight byte of data has been received), and the host controller is requested to read data from the RDB. Slave receive ends normally 1010 Indicates the number of data specified by the telegraph field has been received within one communication frame. Ends without all data being received 1011 Indicates that the communication has ended without receiving the number of data specified by telegraph length field in one communication frame. (4) Multiaddress receive (receive interrupt occurs) When the data/command in multiaddress communication are received from the slave unit, the status code ST3-0 is set and shown as below: Table 13.5.2d Meaning of status code ST3-0 for multiaddress receive 178 Code Name Code ST3-0 Content Multiaddress receive starts 1100 Indicates that the slave unit has received the telegraph field correctly from master unit and multiaddress reception is started but receive interrupt does not occur at this moment. Multiaddress receive data full 1101 Indicates that the receive data buffer RDB for slave reception is full (eight byte of data has been received), and the host controller is requested to read data from the RDB. Multiaddress receive ends normally 1110 Indicates the number of data specified by the telegraph field has been received within one communication frame. Ends without all data being received 1111 Indicates that the communication has ended without receiving the number of data specified by telegraph length field in one communication frame. Chapter 13: IE Bus MB90580 Series 13.5 Operation 13.5.3 Program flow example for IEBus controller (1) Main routine Begin IEBus initial setup Enable IEBus controller IEBus controller operates End (2) Interrupt routine This routine is executed when start of transmission or end of reception. In interrupt routine, the status code (ST3-0) in status register STRL is read, then the transmit data can be written or receive data can be read. Begin Read status register Categorize the status code Upper 2 bits of ST300 Y Master Master transmit routine Note1 01 N Slave transmit routine Note2 Master receive routine Note3 10 Slave receive routine 11 Multiaddress receive routine Interrupt enable RETI End Note1: Refer to master transmit routine Note2: Refer to slave transmit routine Note3: Refer to master receive routine MB90580 Series Chapter 13: IE Bus 179 13.5 Operation (3) IEBus initial setup The initial setup sequence includes setting its unit address, the command register and releasing the communication inhibit state. If the unit is not set as master, there is no need to set the slave address in slave address register. In converse, if the unit is set as master, there is no need to set the mutiaddress byte and control byte. When the unit is set as master, the unit address Begin becomes master address. When the unit is set as Set unit address (MAWH, MAWL) slave, the unit address is used to compared with that in slave address field. Set as master N Y Set slave address (SAWH, SAWL) Set multiaddress and control bits (DCWR) Set command register (CMRH, CMRL) For example selecting the communication mode in command register CMRH, CMRL Release communication inhibit state Data transmit The bit PCOM in command register CMRH is set to ‘1’. N During slave receive, .GOTM and GOTS are not Y Enable transmit Set GOTS bit to ‘1’ when GOTM bit is ‘1’/ End Note:It can be executed by write operation of command register. 180 Chapter 13: IE Bus MB90580 Series 13.5 Operation (4) Master transmit routine After the communication inhibit state is released, the unit won the arbitration and acts as master. Then master transmit routine is used to transmit data to the slave. This routine is executed inside interrupt routine with ST3-0 bits (upper 2 bits are 00) in status register indicating the status as master transmit has been set. Begin Status register read Y ST3-0 = 3H? N Note1 Transmission ends without all data being transmitted ST3-0 = 0H? Y N Set multiaddress, control bits sand telegraph length bits Note2 N = 0? N Y Y WDBF = 1? N WDB write Setup master transmit data Note2 N = N-1 ST3-0 = 2H? Done by N Y End Note1: The reason for the abnormal termination of transmission can be known by reading the TE, PEF and ACK bits of status register. The remaining data that can’t be transmitted will be sent out when GOTM bit in command register CMRH is written ‘1’ again. In order to stop the master transmit and clear the WDB, the bit WDBC in CMRL is written ‘1’. Note2: Please do not wrtie WDB when WDBF=1 Note3: N is the number of data byte for master transmit MB90580 Series Chapter 13: IE Bus 181 13.5 Operation (5) Slave transmit routine After the slave receives the control bits and is set as slave transmit, this routine is used to transmit data to the master. This routine is executed inside interrupt routine with ST3-0 bits (upper 2 bits are 00) in status register indicating the status as slave transmit has been set. Begin Status register read Y ST3-0 = 3H? N Note1 Transmission ends without all data being transmitted ST3-0 = 0H? Y N Set telegraph length GOT = 1 Note2 N = 0? Data transmit N Y WDBF = 1? Y N WDB write Setup slave transmit data GOT = 1 Data transmit Note2 N = N-1 ST3-0 = 2H? Done by hardware N Y End Note1: The reason for the abnormal termination of transmission can be known by reading the TE, PEF and ACK bits of status register. The remaining data that can’t be transmitted will be sent out when GOTS bit in command register CMRH is written ‘1’ again. In order clear the WDB, the bit WDBC in CMRL is written ‘1’. Note2: Please do not wrtie WDB when WDBF=1 Note3: N is the number of data byte for slave transmit 182 Chapter 13: IE Bus MB90580 Series 13.5 Operation (6) Master receive routine After the master transmit the control bits, this routine is used for the master to receive data, slave address or log address from the slave. This routine is consisted of four parts depending on the content of ST3-0. 1. Start of master reception (ST3-0 is 4H) When the master receive the telegraph length field from the slave correctly, the status code 4H is set and the master reception starts. However, interrupt will not occur at that time.. Begin Note1 Read multiaddress, control bits and telegraph length bits Read out multiaddress, control bits and master receive byte number number of master receive data byte Done by hardware Note2 N End Note1: The status register need not be read because each registers are set. However, it is required to take care the timing of setting the registers. Before updating the register contents, read the registers first. Note2: N is the number of data byte for master receive. 2. Master received data read request (ST3-0 is 5H) Begin Master receive buffer size Done by hardware I=8 I I-1 Note1 RDBE = 1? Done by hardware Y N End RDB read Note2 N N-1 Done by hardware Note1: Do not read RDB when RDBE=1. Note2: N is the number of data byte for master receive. MB90580 Series Chapter 13: IE Bus 183 13.5 Operation 3. Master receive ends normally (ST3-0 is 6H) Begin Note1 N Read multiaddress, control bits and telegraph length bits Read out multiaddress, control bits and master receive byte number number of master receive data byte Done by hardware RDB read N N-1 Read out master receive data Done by hardware Note2 N RDBE = 1? Done by hardware Y End Note1: It is not required to read the status as these data are stored in different registers. As the data will be updated, read the register before the next communication frame. Note2: Do not read RDB when RDBE = 1. 184 Chapter 13: IE Bus MB90580 Series 13.5 Operation 4. Master reception ends without all data being received (ST3-0 is 7H) Begin Note1 N Read multiaddress, control bits and telegraph length bits Read out multiaddress, control bits and master receive byte number number of master receive data byte Done by hardware STRH/L read Note2 RDBE = 1? Y N Read RDB End Read out master received data Note1: It is not required to read the status as these data are stored in different registers. As the data will be updated, read the register before the next communication frame. Note2: Do not read RDB when RDBE = 1. The routine for slave receive and multiaddress receive is the same as that of master receive but the status code is different. Please refer to section 13.5.2 for the status code of slave receive and multiaddress receive. MB90580 Series Chapter 13: IE Bus 185 13.5 Operation 13.5.4 Timing Diagram of Multiple Frame Transmission 1. When setting ‘1’ on WDBC (Master side of master transmission) Second Frame Frist Frame DataN-3(04H) Start DataN-2(03H) Multi-Add Master- Add Slave-Add Control Telegraph bytes DataN-1(FFH) DataN(FEH) COM Can read the rest of the transmission byte DERR Read DEER N Transmission data left is 0 02H 00H Write DERR value DEWR Write N DEWR Trans. Buffer Transmit the rest of 2 bytes 02H 03H FEH FEH Transmit the data newly set WDB Write 07H, 06H, 05H, 04H, 04H, 03H, 02H, 01H, 00H WDB FFH, FEH, FDH, FCH, FBH, FAH, F9H Write the transmission data 8 bytes WDBC WEDBF=0 due to1 byte transmission WDBE WDBF WDB is empty as WDBC=1 Write until WDB becomes full Note : N = N bytes transmission. The number inside () is the transmission data. Figure 13.5.4a When setting ‘1’ on WDBC (Master side of master transmission) 186 Chapter 13: IE Bus MB90580 Series 13.5 Operation 2. When setting ‘0’ on WDBC (Master side of master transmission) Second Frame Frist Frame DataN-3(04H) Start DataN-2(03H) Multi-Add Master- Add Slave-Add Control Telegraph bytes DataN-1(02H) DataN(01H) COM Can read the rest of the transmission bytes DERR Read N DEER Transmission data left is 0 02H 00H Write DERR value DEWR Write N DEWR Trans. Buffer Transmit the rest of 2 bytes 02H 03H 01H 02H Transmit the previous frame's data WDB Write 07H, 06H, 05H, 04H, 04H, 03H, 02H, 01H, 00H WDB FFH, FEH, FDH, FCH, FBH As data is left from 3 bytes before, write transmission data 5 bytes WDBC WEDBF=0 due to1 byte transmission WDBE WDBF Write until WDB becomes full Note : N = N bytes transmission. The figure inside ()is the transmission data. Figure 13.5.4b When setting ‘0’ on WDBC (Master side of master transmission) MB90580 Series Chapter 13: IE Bus 187 13.5 Operation 13.5.5 Timing diaram of transmission data when an error is generated 1. The following is an example when the master transmission, an error is generated at the second byte data on the slave side. NAK is received by the master. the following data is transmitted at the second frame. Re-transmit until the figure becomes the maximum transmission byte Tele. Length Data1(00H) Header Data2(01H) Data2(01H) .... Data Filed Tele. Length Data2(01H) Data3 (02H) Data2(01H) <Trans. Side> Transmission completed as the figure became maximum COM Trans. Buffer WDBC 00H 01H 01H 02H Transmit the rest of 2 bytes Clear WDB and write data in WDB from the second byte 03H DEER 02H DEWR's value is set 02H 02H 00H Transmits the all data normally Set 3 bytes transmission in DEWR Read DERR and write the value DEWR Write Set DERR's value 03H DEWR 02H Set 3 bytes transmission <Recep. Side> Transmission completed due to an error COM The seoond bytee error and will not be set in RDB RDB XXH DEER 03H Reception by Tele. Lengh byte 00H 02H 02H Necessity to receive the rest of 2 bytes 02H 01H 00H Reception by Tele. Lengh byte Transmits the all data normally Figure 13.5.5a Error happened on the Slave side when master transmission 188 Chapter 13: IE Bus MB90580 Series 13.5 Operation 2. The following is an example when the master transmission, an error is generated at the second byte data on the master side. The following data is transmitted at the second frame. Slave reception movements until the figure becomes the maximum transmission byte Tele. Length Data1(00H) Header DataX(XXH) DataX(XXH) .... DataX(XXH) <Trans. Side> Data Filed Tele. Length Data2(01H) Data3(02H) Transmission completed due to an error COM Trans. Buffer 00H 02H 01H Clear WDB and write data in WDB from the second byte WDBC 02H 03H DEER Set 3 bytes transmission in DEWR DEWR Write DEWR's value is set Transmits the all data normally Read DERR and write the value 03H DEWR 00H 02H 02H Set DERR's value Set 3 bytes transmission <Recep. Side> Reception until the maximum # of transmit data COM The seoond byte error and will not be set at RDB RDB XXH 01H 00H 03H DEER Reception by Tele. Lengh byte 02H Reception of the rest of 2 bytes Reception by Tele. Lengh byte 00H 00H 02H Transmits the all data normally Figure 13.5.5b Error happened on the Master side when master transmission MB90580 Series Chapter 13: IE Bus 189 Chapter 14: 8/16-Bit PPG 14.1 Outline The 8/16-bit PPG timer is an 8-bit reload timer module, and outputs PPG by control pulse output according to timer operation. The hardware includes two eight-bit down counters, four eight-bit reload registers, one 16-bit control register, two external pulse output pins, and two interrupt outputs. The following functions are implemented: • 8-bit PPG output 2-CH independent operation mode This is a mode for operating independent 2-CH 8-bit PPG timer, in which PPG0 and PPG1 pins correspond to outputs from PPG0 and PPG1 respectively. • 16-bit PPG output operation mode In this mode, PPG0 and PPG1 are combined to be operated as a 1-CH 8/16-bit PPG timer operating as a 16-bit timer. Because PRG0 and PRG1 outputs are reversed by an underflow from PRG1 outputting the same output pulses from PRG0 and PRG1 pins. • 8 + 8 bit PPG output operation mode In this mode, PPG0 is operated as an 8-bit pre-scaler, in which an underflow output of PPG0 is used as a clock source for PPG1. A toggle output of PPG0 and PPG output of PPG1 are output from PPG0 and PPG1 respectively. • PPG output operation The 8/16-bit PPG timer can output pulse waveforms with variable period and duty ratio. Also, it can be used as D/A converter in conjunction with an external circuit. 14.2 Block Diagram 14.2 Block Diagram PPG0 output enable PPG0 Peripheral clock 16-division Peripheral clock 8-division Peripheral clock 4-division Peripheral clock 2-division Peripheral clock A/D converter PPG0 Output latch Invert Clear PEN0 Count clock selection Time base counter output 512-division of main clock L/H selection S R Q PCNT (down counter) IRQ Reload ch1-borrow L/H selector PRLL0 PRLBH0 PIE0 PRLH0 PUF0 L data bus H data bus PPGC0 (Operation mode control) Figure 14.2a 8-bit PPG ch0 block diagram 192 Chapter 14: 8/16-Bit PPG MB90580 Series 14.2 Block Diagram PPG0 output enable PPG1 Peripheral clock 16-division Peripheral clock 8-division Peripheral clock 4-division Peripheral clock 2-division Peripheral clock UART PPG1 Output latch Invert Count clock selection ch0 borrow PEN1 S R Q PCNT (down counter) Time base counter output 512-division of main clock L/H selection Clear IRQ Reload L/H selector PRLL1 PRLBH1 PIE PRLH1 PUF L data bus H data bus PPGC1 (Operation mode control) Figure 14.2b 8-bit PPG ch1 block diagram MB90580 Series Chapter 14: 8/16-Bit PPG 193 14.3 Registers and Register Details 14.3 Registers and Register Details PPG0 operation mode control register 7 Address: ch0 000044H 6 PEN0 (R/W) (0) Read/write Initial value 5 4 PE00 PIE0 (-) (X) 3 2 1 Bit No. 0 Reserved PUF0 (R/W) (R/W) (R/W) (0) (0) (0) (-) (X) (-) (X) 10 9 PPGC0 (-) (1) PPG1 operation mode control register 15 14 Address: ch0 000045H PEN1 Read/write Initial value (R/W) (0) (-) (X) 13 12 11 8 Bit No. PE10 PIE1 PUF1 MD1 MD0 Reserved (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (-) (1) PPGC1 PPG0,1 output control register 7 , Address: ch0 1 0046H Read/write Initial value 5 6 4 3 2 1 0 PCS1 PCS0 PCM2 PCM1 PCM0 Reserved Reserved PCS2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (R/W) (0) Bit No. PPGOE (R/W) (0) Reload register H 15 14 13 12 11 10 9 8 Address: ch0 000041H ch1 000043H Read/write Initial value Bit No. PRLH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) Reload register L 7 6 5 4 3 2 1 Address: ch0 000040H ch1 000042H Read/write Initial value 0 Bit No. PRLL (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) Figure 14.3a Registers of 8/16-bit PPG 194 Chapter 14: 8/16-Bit PPG MB90580 Series 14.3 Registers and Register Details 14.3.1 PPG0 operation mode control register (PPGC0) PPG0 operation mode control register 7 Address: ch0 000044H Read/write Initial value 6 5 PEN0 (R/W) (0) 4 PE00 PIE0 (-) (X) 3 2 1 PUF0 (R/W) (R/W) (R/W) (0) (0) (0) 0 Reserved (-) (X) (-) (X) Bit No. PPGC0 (-) (1) PPGC0 is a five-bit control register that selects the operation mode of the block, controls pin outputs, selects count clock, and controls triggers. [bit 7] PEN0 (PPG enable): Operation enable bit This bit selects the PPG operation mode as described below. PEN0 Operation 0 Stop (’L’ level output maintained) 1 PPG operation enabled [initial value] Setting this bit to 1 makes the PPG start counting. This bit is initialized to ’0’ upon a reset. This bit is readable and writable. [bit 5] PE00 (PPG output enable 0): PPG0 pin output enable bit This bit controls the PPG0 pulse output external pin as described below. PE00 Operation 0 General-purpose port pin (pulse output disabled) 1 PPG0 = pulse output pin (pulse output enabled) [initial value] This bit is initialized to ’0’ upon a reset. This bit is readable and writable. [bit 4] PIE0 (PPG interrupt enable): PPG interrupt enable bit This bit controls PPG interrupt as described below. PIE0 Operation 0 Interrupt disabled 1 Interrupt enabled [initial value] While ’1’ is written to this bit, an interrupt request is issued as soon as ’1’ is written to PUF0. No rupt request is issued while this bit is set to ’0.’ inter- This bit is initialized to ’0’ upon a reset. This bit is readable and writable. Note: PIE0 is assigned the same interrupt vector number as that of 16-bit reload timer. When using EI2OS in 16-bit reload timer, write ’0’ to PIE0. [bit 3] PUF0 (PPG underflow flag): PPG counter underflow bit MB90580 Series Chapter 14: 8/16-Bit PPG 195 14.3 Registers and Register Details This bit controls the PPG counter underflow as described below. PUF0 Operation 0 PPG counter underflow is not detected 1 PPG counter underflow is detected [initial value] In 8-bit PPG 2ch mode or 8-bit prescaler + 8-bit PPG mode, ’1’ is written to this bit when an underflow occurs as a result of the ch0 counter value becoming between 00H and FFH. In 16-bit PPG 1ch mode, ’1’ is written to this bit when an underflow occurs as a result of the ch1/ch0 counter value becoming between 0000H and FFFFH. To set this bit to ’0,’ write ’0.’ Writing ’1’ to this bit is invalid. Upon a read operation during a read-modify-write instruction, ’1’ is read. This bit is initialized to ’0’ upon a reset. This bit is readable and writable. [bit 0] This is a reserved bit. When setting PPGC0, always set this bit to 1. 196 Chapter 14: 8/16-Bit PPG MB90580 Series 14.3 Registers and Register Details 14.3.2 PPG1 operation mode control register (PPGC1) PPG1 operation mode control register 15 Address: ch0 000045H PEN1 Read/write Initial value (R/W) (0) 14 13 (-) (X) 12 11 10 9 8 PE10 PIE1 PUF1 MD1 MD0 Reserved (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (-) (1) Bit No. PPGC1 PPGC0 is a seven-bit control register that selects the operation mode of the block, controls pin outputs, selects count clock, and controls triggers. [bit 15] PEN1 (PPG enable): Operation enable bit This bit selects the PPG operation mode as described below. PEN1 Operation 0 Stop (’L’ level output maintained) 1 PPG operation enabled [initial value] Setting this bit to 1 makes the PWM start counting. This bit is initialized to ’0’ upon a reset. This bit is readable and writable. [bit 13] PE10 (PPG output enable 1): PPG1 pin output enable bit PE10 Operation 0 General-purpose port pin (pulse output disabled) 1 PPG1 = pulse output pin (pulse output enabled) [initial value] This bit controls the PPG1 pulse output external pin as described below. This bit is initialized to ’0’ upon a reset. This bit is readable and writable. [bit 12] PIE1 (PPG interrupt enable): PPG interrupt enable bit This bit controls PPG interrupt as described below. PIE1 Operation 0 Interrupt disabled 1 Interrupt enabled [initial value] While ’1’ is set in this bit, an interrupt request is issued as soon as ’1’ is written to PUF1. No interrupt request is issued while this bit is set to ’0.’ This bit is initialized to ’0’ upon a reset. This bit is readable and writable. Note: PIE1 is assigned the same interrupt vector number as that of UART 0 transmission complete. When using EI2OS in UART 0 transmissioin complete, write ’0’ to PIE1. MB90580 Series Chapter 14: 8/16-Bit PPG 197 14.3 Registers and Register Details [bit 11] PUF1 (PPG underflow flag): PPG counter underflow bit This bit controls the PPG counter underflow as described below. PUF1 Operation 0 PPG counter underflow is not detected 1 PPG counter underflow is detected [initial value] In 8-bit PPG 2ch mode or 8-bit prescaler + 8-bit PPG mode, ’1’ is written to this bit when an underflow occurs as a result of the ch1 counter value becoming between 00H and FFH. In 16-bit PPG 1ch mode, ’1’ is written to this bit when an underflow occurs as a result of the ch1/ch0 counter value becoming between 0000H and FFFFH. To set ’0’ in this bit, write ’0.’ Writing ’1’ to this bit is invalid. Upon a read operation during a read-modify-write instruction, ’1’ is read. This bit is initialized to ’0’ upon a reset. This bit is readable and writable. [bit 10, 9] MD2, 1 (PPG count mode): Operation mode selection bit This bit selects the PPG timer operation mode as described below. MD1 MD0 Operation mode 0 0 8-bit PPG 2ch independent mode 0 1 8-bit prescaler + 8-bit PPG 1ch mode 1 0 Reserved (setting inhibited) 1 1 16-bit PPG 1ch mode This bit is initialized to ’00’ upon a reset. This bit is readable and writable. Note: Do not set ’10’ in this bit. Note: To write ’01’ to this bit, ensure that ’01’ is not written to the PEN0 bit of PPGC0 or PEN1 bit of PPGC1. Write ’11’ or ’00’ in both the PEN0 and PEN1 bits simultaneously. Note: To write ’11’ to this bit, update PPGC0 and PPGC1 by word transfer and write ’11’ or ’00’ to both the PEN0 and PEN1 bits simultaneously. [bit 8] This is a reserved bit. When setting PPGC0, always write 1 to this bit. 198 Chapter 14: 8/16-Bit PPG MB90580 Series 14.3 Registers and Register Details 14.3.3 PPG0, 1 output pin control register (PPGOE) PPG0,1 output control register 7 , Address: ch0 1 0046H Read/write Initial value PCS2 6 5 4 3 2 1 0 PCS1 PCS0 PCM2 PCM1 PCM0 Reserved Reserved (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (R/W) (0) Bit No. PPGOE (R/W) (0) This is an 8-bit control register that controls the pin output of this block. [bits 7 to 5) PCS2 to 0 (PPG count select): Count clock selection bit These bits select the channel 1 down counter operation clock as described below. PCS2 PCS1 PCS0 Operation mode 0 0 0 Peripheral clock (62.5-ns machine clock, 16 MHz) 0 0 1 Peripheral clock/2 (125-ns machine clock, 16 MHz) 0 1 0 Peripheral clock/4 (250-ns machine clock, 16 MHz) 0 1 1 Peripheral clock/8 (500-ms machine clock, 16 MHz) 1 0 0 Peripheral clock/16 (1-ms machine clock, 16 MHz) 1 1 1 Clock input from time base counter (128-ms, 4-Mhz source This bit is initialized to ’000’ upon a reset. This bit is readable and writable. Note: In 8-bit prescaler + 8-bit PPG mode or in 16-bit PPG mode, ch1 PPG operates in response to a counter clock from ch0. Therefore, the PCS1 bit is invalid. [bits 4 to 2] PCM2 to 0 (PPG count mode): Count clock selection bit These bits select the channel 0 down counter operation clock as described below. PCM2 PCM1 PCM0 Operation mode 0 0 0 Peripheral clock (62.5-ns machine clock, 16 MHz) 0 0 1 Peripheral clock/2 (125-ns machine clock, 16 MHz) 0 1 0 Peripheral clock/4 (250-ns machine clock, 16 MHz) 0 1 1 Peripheral clock/8 (500-ms machine clock, 16 MHz) 1 0 0 Peripheral clock/16 (1-ms machine clock, 16 MHz) 1 1 1 Clock input from time base counter (128-ms, 4-Mhz source This bit is initialized to ’000’ upon a reset. This bit is readable and writable. MB90580 Series Chapter 14: 8/16-Bit PPG 199 14.3 Registers and Register Details 14.3.4 Reload register (PRLL/PRLH ) Reload register H 15 14 13 12 11 10 9 8 Address: ch0 000041H ch1 000043H Read/write Initial value Bit No. PRLH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) Reload register L 7 6 5 4 3 2 1 Address: ch0 000040H ch1 000042H Read/write Initial value 0 Bit No. PRLL (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) These are 8-bit registers that hold the reload values for the PCNT down counter. Their roles are described below. Function Register name PRLL Holds the L side reload value. PRLH Holds the H side reload value. These registers are readable and writable. Note: In 8-bit prescaler + 8-bit PPG mode, setting different values in PRLL and PRLH of ch1 may cause the PPG waveform of ch1 to vary in each cycle. Write the same value to PRLL and PRLH of ch0. 200 Chapter 14: 8/16-Bit PPG MB90580 Series 14.4 Operations 14.4 Operations This block has two channels of 8-bit PPG units. These two channels can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit PPG mode, and single-channel 16-bit PPG mode. Each of the 8-bit PPG units has two eight-bit reload registers. One reload register is for the L side (PRLL) and the other is for the H side (PRLH). The values stored in these registers are reloaded into the 8-bit down counter (PCNT), from the L side and H side in turn. Thus, the values are decremented for each count clock, and the pin output (PPG) value is inverted upon a reload caused by a counter borrow. This operation results in L-wide or H-wide pulse outputs, corresponding to the reload register value. The operation is started and resumed by writing data in the corresponding register bit. The table below lists the relationship between the reload operation and pulse outputs. Table 14.4a Reload operation and pulse output Reload operation Pin output change PRLH PCNT PPG0x/1x [0 1] Rise PRLL PCNT PPP0x/1x [1 0] Fall When 1 is set in bit 4 (PIE0) of PPGC0 or in bit 12 (PIE1) of PPGC1, an interrupt request is output upon a borrow from 00 to FF (from 0000 to FFFF in 16-bit PPG mode) of each counter. (1) Operation mode This block can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit PPG mode, and single-channel 16-bit PPG mode. In independent two-channel mode, the two channels of 8-bit PPG units operate independently. The PPG0 pin is connected to the ch0 PPG output, while the PPG1 pin is connected to the ch1 PPG output. In 8-bit prescaler + 8-bit PPG mode, ch0 is used as an 8-bit prescaler while the count in ch1 is based on borrow outputs from ch0. Thus, 8-bit PPG waveforms can be output at any cycles. The PPG0 is connected to the ch0 prescaler output, while the PPG1 pin is connected to the ch1 PPG output. In 16-bit PPG 1ch mode, ch0 and ch1 are connected and used as a single 16-bit PPG. The PPG0 and PPG1 pins are connected to the 16-bit PPG output. MB90580 Series Chapter 14: 8/16-Bit PPG 201 14.4 Operations (2) PPG output operation In this block, the ch0 PPG is activated to start counting when ’1’ is written to bit 7 (PEN0) of the PPGC0 (PWM operation mode control) register. Similarly, the ch1 PPG is activated to start counting when ’1’ is written to bit 15 (PEN1) of the PPGC1 register. Once the operation has started, counting is terminated by writing ’0’ to bit 7 (PEN0) of PPGC0 or in bit 15 (PEN1) of PPGC1. Once the counting is terminated, the pulse output is maintained at the L level. In 8-bit prescaler + 8-bit PPG mode, do not set ch1 to be in operation while ch0 operation is stopped. In 16-bit PPG mode, ensure that bit 7 (PEN0) of PPGC0 register and bit 15 (PEN1) of PPGC1 register are started or stopped simultaneously. The figure below is a diagram of PPG output operation. During PPG operation, a pulse wave is continuously output at a frequency and duty ratio (the ratio of the H-level period of the pulse wave to the L-level period). PPG continues operation until stop is specified explicitly. PEN 2.Starts operation based on PEN (from Lside). Output pin PPG T X (L+1) T X (H+1) (Start) L : H : T : PRLL value PRLH value Input from peripheral clock (∅, ∅/4, ∅/16) or timer base counter (depending on the clock selection by PPGC) Figure 14.4a PPG output operation, output waveform (3) Reload value and pulse width The width of the output pulse is determined by adding 1 to the reload register value and multiplying it by the count clock cycle. Note that when the reload register value is 00H during 8-bit PPG operation or 0000H during 16-bit PPG operation, the pulse width is equivalent to one count clock cycle. In addition, note that when the reload register value is FFH during 8-PPG operation, the pulse width is equivalent to 256 count clock cycles. When the reload register value is FFFFH during 16-bit PPG operation, the pulse width is equivalent to 65536 count clock cycles. An example of pulse width calculation is given below. P1=T X (L+1) Ph=T X (H+1) 202 Chapter 14: 8/16-Bit PPG L : H : T : Ph : Pl : PRLL value value Input clock cycle High pulse width Low pulse width MB90580 Series 14.4 Operations (4) Count clock selection The count clock used for the operation of this block is supplied from a peripheral clock or time base counter. The count clock can be selected from six types. Select ch0 clock at bit 4 to 2 (PCM2 to 0) of the PPGOE register, and ch1 clock at bit 7 to S (PCS2 to 0) of the PPGOE register. The clock is selected from a peripheral clock 1/16 to 1 times higher than a machine clock or an input clock from a time base counter. In 8-bit prescaler + 8-bit PPG mode or 16-bit PPG mode, however, the value in bit 14 (PCS1) of the PPGC1 register is invalid. The register is invalid because ch1 PPG receives a count clock from ch0. When the time base counter input is used, the first count cycle after a trigger or a stop may be shifted. The cycle may also be shifted if the time base counter is cleared during operation of this module. In 8-bit prescaler + 8-bit PPG mode, if ch1 is activated while ch0 is in operation and ch1 is stopped, the first count cycle may be shifted. (5) Pulse pin output control The pulses generated by this module can be output from external pins PPG0 and PPG1. To output the pulses from an external pin, write ’1’ to the bit corresponding to each pin. Use bit 5 (PE0) of the PPGC0 register for the PPG0 pin, bit 13 (PE1) of the PPGC1 register for the PPG1 pin. When ’0’ is written to these bits (default), the pulses are not output from the corresponding external pins; the pins work as general-purpose ports. In 16-bit PPG mode, the same waveform is output from PPG0 and PPG1. Thus, the same output can be obtained by enabling any external pin. In 8-bit prescaler + 8-bit PPG mode, the 8-bit prescaler toggle output waveform is output from PPG0, while the 8-bit PPG waveform is output from PPG1. The figure below is a diagram of output waveforms in this mode. Ph0 Pl0 PPG0 PPG1 Ph1 Pl0 = T x (L0+1) Ph0 = T x (L0+1) Pl1 = T x (L0+1) x (Ll+1) Ph1 = T x (L0+1) x (Hl+1) Pl1 L0 L1 H1 T Ph0 Pl0 Ph1 Pl1 : : : : : : : : ch0 PRLL value and ch0 PRLH value ch1 PRLL value ch1 PRLH value Input clock cycle PPG0 high pulse width PPG0 low pulse width PPG1 high pulse width PPG1 low pulse width Note : Set the same value in ch0 PRLL and ch0 PRLH. Figure 14.4b 8+8 PPG output operation waveform MB90580 Series Chapter 14: 8/16-Bit PPG 203 14.4 Operations (6) Interrupts For this module, an interrupt becomes active when the reload value is counted out and a borrow occurs. In 8-bit PPG 2ch mode or 8-bit prescaler + 8-bit PPG mode, an interrupt is requested by a borrow in each counter. In 16-bit PPG mode, PUG0 and PUF1 are simultaneously set by a borrow in the 16-bit counter. Therefore, enable only PIE0 or PIE1 to unify the interrupt causes. In addition, simultaneously clear the interrupt causes for PUF0 and PUF1. (7) Default values of hardware components The hardware components of this block are initialized to the following values when reset: <Registers> <Pulse outputs> <Interrupt requests> • PPGC0 0X000001B • PPGC1 00000001B • PPGOE XXXXXX00B PPG0 ’L’ PPG1 ’L’ PE0 PPG0 output disabled PE1 PPG1 output disabled IRQ0 ’L’ IRQ1 ’L’ Hardware components other than the above are not initialized. 204 Chapter 14: 8/16-Bit PPG MB90580 Series 14.4 Operations (8) Reload register write timing In a mode other than 16-bit PPG mode, it is recommended to use a word transfer instruction to write data in reload registers PRLL and PRLH. If two byte transfer instructions are used to write a data item to these registers, a pulse of unexpected width may be output depending on the timing. PPG0 A B A B C ① B C D C D Figure 14.4c Write timing chart Assume that PRLL is updated from A to C before point ① in the time chart above, and PRLH is updated from B to D after point ①. Since the PRL values at point ① are PRLL=C and PRLH=B, a pulse of L side count value C and H side count value B is output only once. Similarly, to write data in PRL of ch0 and ch1 in 16-bit PPG mode, use a long word transfer instruction, or use word transfer instructions in the order of ch0 and then ch1. In this mode, the data is only temporarily written to ch0 PRL. Then, the data is actually written into ch0 PRL when the ch1 PRL is written to. In a mode other than 16-bit PPG mode, ch0 and ch1 PRL are written independently. ch0 PRL write data ch1 PRL write data Transferred in synchronization with ch1 write in 16-bit Temporary latch PPG mode ch0 write in a mode other than 16-bit PPG mode ch1 write ch0 PRL ch1 PRL Figure 14.4d PRL write operation block diagram MB90580 Series Chapter 14: 8/16-Bit PPG 205 Chapter 15: 16-Bit Reload Timer (with Event Count Function) 15.1 Outline The 16-bit reload timer 1 consists of a 16-bit down-counter, a 16-bit reload register, one input pin (TIN) and one output pin (TOUT), and a control register. It has an internal clock mode for counting down in synchronization to three types of internal clocks and an event count mode for counting down detecting a given edge of the pulse input to the external bus pin, and either of the two functions can be selectively used. For this timer, an “underflow” is defined as the timing of transition from the counter value of “0000H” to “FFFFH”. According to this definition, an underflow occurs after [re-load register setting value + 1] counts. In operating the counter, the re-load mode for repeating counting operation after re-loading a counter value after an underflow or the one-shot mode for stopping the counting operation after an underflow can be selectively used. Because the timer can generate an interrupt upon an underflow, the timer conforms to the extended intelligent I/O service (EI2OS). The output pin (TOUT) outputs a toggle output waveform in reload mode or a square waveform during counting in one-shot mode. The input pin (TIN) functions as the event input in event count mode, or as the trigger input or gate input in internal clock mode. 15.2 Block Diagram 15.2 Block Diagram 16 16-bit reload register 8 Reload RELD 16 F2MC-16LX BUS 16-bit down-counter OUTE UF OUTL 2 INTE OUT CTL. GATE UF IRQ CSL1 Clock selector CNTE CSL0 TRG 2 Clear I2OSCLR Re-trigger IN CTL Port (TIN) EXCK φ φ φ 21 23 25 Output enable 3 Prescaler clear Port (TOUT) MOD2 MOD1 Peripheral clock MOD0 Serial baud rate (ch0) A/DC (ch1) 3 Figure 15.2a Block Diagram of 16-Bit Reload Timer 208 Chapter 15: 16-Bit Reload Timer (with Event Count Function) MB90580 Series 15.3 Registers and Register Details 15.3 Registers and Register Details Timer control status register (upper) 15 Address: ch0 000049H ch1 00004DH ch2 000051H Read/write Initial value 14 13 12 11 10 9 MOD2 8 — — — — CSL1 CSL0 — — — — — — — — (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) 7 6 5 4 3 2 1 MOD0 OUTE OUTL RELD INTE UF (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) Bit number TMCSR0-2 (HIGH) MOD1 Timer control status register (lower) Address: ch0 000048H ch1 00004CH ch2 000050H Read/write Initial value CNTE 0 TMCSR0-2 (LOW) TRG (R/W) (0) Bit number (R/W) (0) 16-bit timer register (upper)/ 16-bit reload register (upper) 15 14 13 12 11 10 9 Bit number 8 00003BH Address: ch0 00004B ch1 00004F 00003FHH ch1 ch2 000053 Read/write Initial value TMR0-2/ TMRLR0-2 (HIGH) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) 16-bit timer register (lower)/ 16-bit reload register (lower) 7 Address: ch0 ch1 ch1 ch2 00003AH 00004A 00003EHH 00004E 000052H 6 5 4 3 2 1 Read/write Initial value 0 Bit number TMR0-2/ TMRLR0-2 (LOW) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) Figure 15.3a Registers of 16-Bit Reload Timer MB90580 Series Chapter 15: 16-Bit Reload Timer (with Event Count Function) 209 15.3 Registers and Register Details 15.3.1 Timer control status register (TMCSR) Timer control status register (upper) 15 Address: ch0 000049H ch1 00004DH ch2 000051H Read/write Initial value 14 13 12 11 10 — — — — CSL1 CSL0 — — — — — — — — (R/W) (0) (R/W) (0) 9 MOD2 (R/W) (0) 8 Bit number TMCSR0-2 (HIGH) MOD1 (R/W) (0) Timer control status register (lower) Address: ch0 000048H ch1 00004CH ch2 000050H Read/write Initial value 7 6 5 4 3 2 MOD0 OUTE OUTL RELD INTE UF (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) CNTE (R/W) (0) 1 TRG 0 Bit number TMCSR0-2 (LOW) (R/W) (0) Figure 15.3.1a Timer Control Status Register Controls the operation mode and interrupts for the 16-bit timer. Only modify bits other than UF, CNTE, and TRG when CNTE = “0”. [Bits 11, 10] CSL1, CSL0 (Clock select 1, 0) The count clock select bits. The following tMable lists the selected clock sources.LL 210 CSL1 CSL0 Clock Source (Machine cycle φ = 16 MHz) 0 0 φ/21 (0.125 µs) 0 1 φ/23 (0.5 µs) 1 0 φ/25 (2.0 µs) 1 1 External event count mode Chapter 15: 16-Bit Reload Timer (with Event Count Function) MB90580 Series 15.3 Registers and Register Details [Bits 9, 8, 7] MOD2, MOD1, MOD0 These bits set the operation mode and I/O pin functions. The MOD2 bit selects the I/O functions. When MOD2 = “0”, the input pin functions as a trigger input. In this case, the reload register contents is loaded to the counter when an active edge is input to the input pin and count operation proceeds. When MOD2 = “1”, the timer operates in gate counter mode and the input pin functions as a gate input. In this mode, the counter only counts while an active level is input to the input pin. The MOD1 and 0 bits set the pin functions for each mode. The following tables list the MOD2, 1, 0 bit settings Internal clock mode (CSL0, 1 = “00”, “01”, or “10”) MOD2 MOD1 MOD0 Input Pin Function Active Edge or Level 0 0 0 Trigger disabled — 0 0 1 Trigger input Rising edge 0 1 0 ⇑ Falling edge 0 1 1 ⇑ Both edges 1 × 0 Gate input “L” level 1 × 1 ⇑ “H” level Event counter mode (CSL0,1 = “11”) MOD2 X MOD1 MOD0 Input Pin Function Active Edge or Level 0 0 — — 0 1 Trigger input Rising edge 1 0 ⇑ Falling edge 1 1 ⇑ Both edges Note: Bits marked as X in the table can be set to any value. [Bit 6] OUTE Output enable bit. The TOUT pin functions as a general-purpose port when this bit is “0” and as the timer output pin when this bit is “1”. In reload mode, the output waveform toggles. In one-shot mode, TOUT outputs a square waveform that indicates that counting is in progress. Note: For reload timer 1 and 2, TOUT is multiplexed with P94/OUT0 and P95/OUT1 respectively. If output capture is enabled, it has higher priority than reload timer output. [Bit 5] OUTL This bit sets the output level for the TOUT pin. When OUTL is “0” or “1”, the output pin level is site MB90580 Series Chapter 15: 16-Bit Reload Timer (with Event Count Function) oppo- 211 15.3 Registers and Register Details [Bit 4] RELD (Reload) This bit enables reload operations. When RELD is “1”, the timer operates in reload mode. In this mode, the timer loads the reload register contents into the counter and continues counting whenever an underflow occurs (when the counter value changes from 0000H to FFFFH). When RELD is “0”, the timer operates in one-shot mode. In this mode, the count operation stops when an underflow occurs due to the counter value changing from 0000H to FFFFH.. OUTE RELD OUTL Output Waveform 0 X X General-purpose port 1 0 0 Output an “H” level square waveform during counting. 1 0 1 Output an “L” level square waveform during counting. 1 1 0 Toggle output. “L” level at count start. 1 1 1 Toggle output. “H” level at count start. [Bit 3] INTE (Interrupt enable) Timer interrupt request enable bit. When INTE is “1”, an interrupt request is generated when the UF bit changes to “1”. When INTE is “0”, no interrupt request is generated, even when the UF bit changes to “1”. [Bit 2] UF (Underflow) Timer interrupt request flag. UF is set to “1” when an underflow occurs (when the counter value changes from 0000H to FFFFH). Cleared by writing “0” or by the intelligent I/O service. Writing “1” to this bit has no meaning. Read as “1” by read-modify-write instructions. [Bit 1] CNTE (Count enable) Timer count enable bit. Writing “1” to CNTE sets the timer to wait for a trigger. Writing “0” stops count operation. [Bit 0] TRG (Trigger) Software trigger bit. Writing “1” to TRG applies a software trigger, causing the timer to load the reload register contents to the counter and start counting. Writing “0” has no meaning. Reading always returns “0”. Applying a trigger using this register is only valid when CNTE = “1”. Writing “1” has no effect if CNTE = “0”. 212 Chapter 15: 16-Bit Reload Timer (with Event Count Function) MB90580 Series 15.3 Registers and Register Details 15.3.2 TMR (16-bit timer register)/TMRLR (16-bit reload register) 16-bit timer register (upper)/ 16-bit reload register (upper) 15 14 13 12 11 10 9 Bit number 8 00003BHH Address: ch0 00004B ch1 00004F 00003FHH ch1 ch2 000053 Read/write Initial value TMR0-2/ TMRLR0-2 (HIGH) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) 16-bit timer register (lower)/ 16-bit reload register (lower) 7 Address: ch0 ch1 ch1 ch2 00003AH 00004A 00003EHH 00004E 000052H 6 5 4 3 2 1 Read/write Initial value 0 Bit number TMR0-2/ TMRLR0-2 (LOW) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) Figure 15.3.2a 16-Bit Timer Register and 16-Bit Reload Register ■ TMR contents (for reading) Reading this register reads the count value of the 16-bit timer. The initial value is undefined. Always read this register using word move instructions. ■ TMRLR contents (for writing) The 16-bit reload register holds the initial count value. The initial value is undefined. Always write to this register using word transfer instructions. MB90580 Series Chapter 15: 16-Bit Reload Timer (with Event Count Function) 213 15.4 Operation 15.4 Operation 15.4.1 Internal clock operation The machine clock divided by 21, 23, or 25 can be selected as the clock sources for operating the timer from an internal divide clock. The external input pin can be selected as either a trigger input or gate input by a register setting. Writing “1” to both the CNTE and TRG bits in the control register enables and starts counting simultaneously. Using the TRG bit as a trigger input is always available when the timer is enabled (CNTE = “1”), regardless of the operation mode. Figure 15.4.1a shows counter activation and counter operation. A time period T (T: machine cycle) is required from the counter start trigger being input until the reload register data is loaded into counter. Count clock Counter Reload data -1 -1 -1 Data load CNTE (bit) TRG (bit) T Figure 15.4.1a Counter Activation and Operation 214 Chapter 15: 16-Bit Reload Timer (with Event Count Function) MB90580 Series 15.4 Operation 15.4.2 Underflow operation An underflow is defined for this timer as the time when the counter value changes from 0000 H to FFFFH. Therefore, an underflow occurs after (reload register setting + 1) counts. If the RELD bit in the control register is “1” when the underflow occurs, the contents of the reload register is loaded into the counter and counting continues. When RELD is “0”, counting stops with the counter at FFFFH. The UF bit in the control register is set when the underflow occurs. If the INTE bit is “1” at this time, an interrupt request is generated. Figure 15.4.2a shows the operation when an underflow occurs. Count clock Counter Reload data 0000H -1 -1 -1 Data load Underflow set [RELD=1] Count clock Counter 0000H FFFFH Underflow set [RELD=0] Figure 15.4.2a Underflow Operation MB90580 Series Chapter 15: 16-Bit Reload Timer (with Event Count Function) 215 15.4 Operation 15.4.3 Input pin functions (for internal clock mode) The TIN pin can be used as either a trigger input or a gate input when an internal clock is selected as the clock source. When used as a trigger input, input of an active edge causes the timer to load the reload register contents to the counter and then start count operation after clearing the internal prescaler. Input a pulse width of at least 2T (T is the machine cycle) to TIN. Figure 15.4.3a shows the operation of trigger input. Count clock Rising edge detected TIN Prescaler clear Counter Reload data -1 -1 -1 -1 Load 2T2.5T Figure 15.4.3a Trigger Input Operation When used as a gate input, the counter only counts while the active level specified by the MOD0 bit of the control register is input to the TIN pin. In this case, the count clock continues to operate unless stopped. The software trigger can be used in gate mode, regardless of the gate level. Input a pulse width of at least 2T (T is the machine cycle) to the TIN pin. Figure 15.4.3b shows the operation of gate input. Count clock TIN When MOD0 = “1” (Count when “H” is input) -1 Counter -1 -1 Figure 15.4.3b Gate Input Operation 15.4.4 External event counter The TIN pin functions as an external event input pin when an external clock is selected. The counter counts on the active edge specified in the register. Input a pulse width of at least 4T (T is the machine cycle) to the TIN pin. 216 Chapter 15: 16-Bit Reload Timer (with Event Count Function) MB90580 Series 15.4 Operation 15.4.5 Output pin functions In reload mode, the TOUT pin performs toggle output (inverts at each underflow). In one-shot mode, the TOUT pin functions as a pulse output that outputs a particular level while the count is in progress. The OUTL bit of the control register sets the output polarity. When OUTL = “0”, the initial value for toggle output is “0” and the one-shot pulse output is “1” while the count is in progress. The output waveforms are opposite when OUTL = “1”. Count start Underflow Level is opposite when OUTL = “1”. TOUT General-purpose port CNTE Trigger [RELD=1, OUTL=0] Figure 15.4.5a Output Pin Functions (1) Underflow TOUT Level is opposite when OUTL = “1”. General-purpose port CNTE Trigger Waiting for a trigger [RELD=0, OUTL=0] Figure 15.4.5b Output Pin Functions (2) 15.4.6 Intelligent I/O service (I2OS) function and interrupts The timer includes a circuit that supports I2OS. The timer can activate I2OS when an underflow occurs. I2OS can be used with both timers on this product. However, as both timers (ch0 and ch1) are connected to the same interrupt control register (ICRx) in the interrupt controller, ch0 and ch1 cannot be assigned to different I2OS services. Also, as the two timers have different interrupt vectors, they can be assigned to two different interrupt services. However, as ch0 and ch1 share an interrupt control register as described above, the same interrupt level applies to both channels. MB90580 Series Chapter 15: 16-Bit Reload Timer (with Event Count Function) 217 15.4.7 Counter operation state The counter state is determined by the CNTE bit in the control register and the internal WAIT signal. Available states are: CNTE = “0” and WAIT = “1” (STOP state), CNTE = “1” and WAIT = “1” (WAIT state for trigger), and CNTE = “1” and WAIT = “0” (RUN state). Figure 15.4.7a shows the transitions between each state. Reset STOP State transitions by hardware CNTE=0, WAIT=1 State transitions by register access Counter: Stores the value when counting stopped. Undefined immediately after a reset. CNTE=‘0’ CNTE=‘0’ CNTE=‘1’ TRG=‘1’ CNTE=‘1’ TRG=‘0’ WAIT RUN CNTE=1, WAIT=1 Counter: Stores the value when counting stopped. Undefined just after a reset until loaded. Counter: Running RELD·UF TRG=‘1’ CNTE=1, WAIT=0 TRG=‘1’ RELD·UF LOAD CNTE=1, WAIT= 0 Load contents of the reload register to the counter. Figure 15.4.7a Counter State Transitions Load complete Chapter 16: A/D Converter 16.1 Outline The A/D converter converts analog input voltages into digital values. The A/D converter has the following features: • Conversion time: 5.2 µs min. per channel (at 16 MHz machine clock) • RC sequential compare conversion format with sample and hold circuit • 10-bit resolution • Analog input selected from eight channels by programming Single conversion mode: One channel is selected for conversion. Scan conversion mode: Voltages in multiple consecutive channels are converted. Up to eight channels can be programmed. Continuous conversion mode: Voltages in the specified channel are converted repeatedly. Stop conversion mode: Voltages in a single channel are converted, then the system pauses and stands by for the next activation. (The conversion start points can be synchronized.) • At the end of A/D conversion, a relevant interrupt request can be issued to the CPU. This interrupt can be used to activate I2OS, which transfers A/D conversion result data to memory. This feature is suitable for continuous processing. • The activation factors can be selected from software, external trigger (falling edge), or timer (rising edge). 16.2 Block Diagram 16.2 Block Diagram AVCC AVR AVSS D/A converter MPX F2MC-16LX BUS AN1 AN2 AN3 AN4 AN5 AN6 Input circuit AN0 Sequential compare register Comparator AN7 Decoder Sample and hold circuit Data register ADCR1, 2 A/D control register 1 A/D control register 2 ADCS1, 2 Activation by trigger ADTG Activation by timer Operation clock PPG01 output Prescaler Figure 16.2a Block Diagram of A/D converter 220 Chapter 16: A/D Converter MB90580 Series 16.3 Registers and Register Details 16.3 Registers and Register Details Control Status Registers (Upper Byte) 15 Address : 000037H BUSY 14 INT (R/W) (R/W) (0) (0) Read/write Initial value 13 12 11 10 9 8 INTE PAUS STS1 STS0 STRT DA (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (W) (0) (R/W) (0) Bit number ADCS2 Control Status Registers (Lower Byte) Address : 000036H Read/write Initial value 7 6 5 4 3 2 1 0 MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 (R/W) (0) (R/W) (R/W) (0) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) 13 12 11 10 9 8 ST0 CT1 D9 D8 Bit number ADCS1 Data Registers (Upper Byte) 15 Address : 000039H 14 Reserved ST1 (W) (0) (W) (0) Read/write Initial value (W) (0) CT0 (W) (0) (W) (1) ( ) ( ) (R) (X) Bit number ADCR2 (R) (X) Data Registers (Lower Byte) Address : 000038H Read/write Initial value 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) Bit number ADCR1 (R) (X) Figure 16.3a Registers of A/D Converter MB90580 Series Chapter 16: A/D Converter 221 16.3 Registers and Register Details 16.3.1 Control status registers (ADCS1 and ADCS2) These registers are used to control the A/D converter and display the status. Control Status Registers (Upper Byte) 15 Address : 000037H Read/write Initial value 14 BUSY INT (R/W) (R/W) (0) (0) 13 12 11 10 9 8 INTE PAUS STS1 STS0 STRT DA (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (W) (0) (R/W) (0) Bit number ADCS2 Control Status Registers (Lower Byte) Address : 000036H Read/write Initial value 7 6 5 4 3 2 1 0 MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 (R/W) (0) (R/W) (0) (R/W) (R/W) (0) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) Bit number ADCS1 Figure 16.3.1a Control Status Registers Note: Do not update ADCS1 during A/D conversion. [bit 15] BUSY (busy flag and stop): Read: This bit indicates the A/D converter operation. This bit is set when the A/D conversion is activated, and cleared when the conversion ends. Write: Writing ’0’ to this bit during A/D conversion forces the conversion to terminate. This features is used for forced stop in continuous or stop mode. ’1’ cannot be written to the operation display bit. With a read-modify-write instruction. ’1’ is read from this bit. In single mode, this bit is cleared at the end of A/D conversion. In continuous or stop mode, this bit is not cleared until conversion is stopped by writing ’0.’ This bit is initialized to ’0’ upon a reset. Do not perform forced termination and activation by software simultaneously. (BUSY=0, STRT=1) [bit 14] INT (Interrupt): A data display bit This bit is set when conversion data is written to ADCR. An interrupt request is issued if this bit is set while bit 5 (INTE) is ’1.’ In addition, I2OS is activated if it is enabled. Writing ’1’ has no effect. This bit is cleared by writing ’0’ or by an I2OS interrupt clear signal. Note: To clear this bit by writing ’0,’ ensure that A/D conversion is not in progress. This bit initialized to ’0’ upon a reset. [bit 13] INTE (Interrupt enable): This bit is used to enable or disable interrupts at the end of conversion.. 0 Interrupts are disabled. 1 Interrupts are enabled. [initial value] Set this bit when using I2OS. I2OS is activated when an interrupt request is issued. Upon a reset, this bit is initialized to ’0.’ 222 Chapter 16: A/D Converter MB90580 Series 16.3 Registers and Register Details [bit 12] PAUS (A/D conversion pause): This bit is set when the A/D conversion is paused. Only one register is available for storing the A/D conversion result. Therefore, unless the conversion results are transferred by I2OS, the result data would be continuously updated and destroyed in continuous conversion. To prevent the above condition, the system is designed so that a data register value must be transferred by I2OS before the next conversion data is saved. A/D conversion pauses during that period. A/D conversion is resumed at the end of transfer by I2OS. This register is valid only when I2OS is used. * For the conversion data protection function, see Section 2.7.4, "Operations." Upon a reset, this bit is initialized to ’0.’ [bits 11 and 10] STS1 and STS0 (Start source select): Upon a reset, these bits are initialized to ’00.’ These bits are used to select the A/D conversion activation factor. STS1 STS0 Function 0 0 Activation by software 0 1 Activation by external pin trigger and software 1 0 Activation by timer and software 1 1 Activation by external pin trigger, timer, and software In a mode allowing two or more activation factors, A/D conversion is activated by the factor that is input first. The activation factor changes as soon as it is updated. Thus, take care when updating it during A/D conversion. * The external pin trigger is detected by the falling edge. If this bit is updated to external trigger activation while the external trigger input level is ’L,’ A/D may be activated at once. * When timer is selected, PPG1 output is selected. [bit 9] STRT (Start): A/D conversion is activated when ’1’ is written to this bit. To reactivate A/D conversion, write ’1’ to this bit again. In stop mode, restart is disabled due to the operation functions. Upon a reset, this bit is initialized to ’0.’ Note: Do not perform forced termination and activation by software simultaneously. (BUSY=0, STRT=1) [bit 8] DA This is a test bit. Always write ’0’ to this bit. MB90580 Series Chapter 16: A/D Converter 223 16.3 Registers and Register Details [bits 7 and 6] MD1 and MD0 (A/D converter mode set): These bits are used to set the A/D converter operation mode. MD1 MD0 0 0 Single mode. Reactivation during operation is allowed. 0 1 Single mode. Reactivation during operation is not allowed. 1 0 Continuous mode. Reactivation during operation is not allowed. 1 1 Stop mode. Reactivation during operation is not allowed. Single mode: Operation mode A/D conversion is continuously performed from the channel specified with ANS2 to ANS0 to the channel specified with ANE2 to ANE0. The conversion stops once it has been done for all these channels. Continuous mode: A/D conversion is repeatedly performed from the channel specified with ANS2 to ANS0 to the channel specified with ANE2 to ANE0. Stop mode: A/D conversion is performed from the channel specified with ANS2 to ANS0 to the channel specified with ANE2 to ANE0, pausing for each channel. The A/D conversion is resumed upon an activation factor. Upon a reset, these bits are initialized to ’00.’ Note: When activated in continuous or stop mode, A/D conversion continues until it is stopped by the BUSY bit. Note: The conversion is stopped by writing ’0’ to the BUSY bit. Note: In single, continuous, or stop mode, reactivation is disabled regardless of the activation factor (timer, external trigger, or software). [bits 5, 4, and 3] ANS2, ANS1, and ANS0 (Analog start channel set): Use these bits to specify the start channel for A/D conversion. When the A/D converter is activated, A/D conversion starts from the channel selected with these bits. ANS2 ANS1 ANS0 Start channel 0 0 0 AN0 0 0 1 AN1 0 1 0 AN2 0 1 1 AN3 1 0 0 AN4 1 0 1 AN5 1 1 0 AN6 1 1 1 AN7 * Read During A/D conversion, the current conversion channel is read from these bits. If the system is stopped in stop mode, the previous conversion channel is read. * Upon a reset, these bits are initialized to ’000.’ 224 Chapter 16: A/D Converter MB90580 Series 16.3 Registers and Register Details [bits 2, 1, and 0] ANE2, ANE1, and ANE0 (Analog end channel set): Use these bits to set the A/D conversion end channel. ANE2 ANE1 ANE0 End channel 0 0 0 AN0 0 0 1 AN1 0 1 0 AN2 0 1 1 AN3 1 0 0 AN4 1 0 1 AN5 1 1 0 AN6 1 1 1 AN7 * When the same channel is written to ANE2 to ANE0 and ANS2 to ANS0, conversion is performed for one channel only (single conversion). * In continuous or stop mode, operation returns to the start channel specified in ANS2 to ANS0 after the conversion is completed for the channel specified in ANE2 to ANE0. * If the ANS value is smaller than the ANE value, conversion starts from the ANS channel. Then, once conversion is complete up to channel 7, operation returns to channel 0 and conversion is performed up to the ANE channel. * Upon a reset, these bits are initialized to ’000.’ Example: ANS=6, ANE=3, single mode Conversion is performed in the following sequence: CH6, CH7, CH0, CH1, CH2, CH3 MB90580 Series Chapter 16: A/D Converter 225 16.3 Registers and Register Details 16.3.2 ADCR1 and ADCR0 (Data registers) Data Registers (Upper Byte) 15 Address : 000039H 14 Reserved ST1 (W) (0) (W) (0) Read/write Initial value 13 12 ST0 CT1 (W) (0) 11 10 CT0 (W) (0) (W) (1) ( ) ( ) 9 8 D9 D8 (R) (X) Bit number ADCR2 (R) (X) Data Registers (Lower Byte) Address : 000038H Read/write Initial value 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) Bit number ADCR1 (R) (X) Figure 16.3.2a Data Registers [bit 15] This is reserved bit. This bit should be written to ‘1’ before AD conversion. Never write ‘0’ to this bit. Note: Reading this bit always returns “1”. [bit 14, 13] : ST1, ST0 (Sampling Time) These bits is used for setting the sampling time in terms of machine cycle. ST1 ST0 Sampling time machine cycle Sampling time 0 0 64 machine cycle 4ms at 16MHz machine clock 0 1 Reserved 1 0 Reserved 1 1 4096 machine cycle 256ms at 16MHz machine clock Note: Reading these bits always return “1”. 226 Chapter 16: A/D Converter MB90580 Series 16.3 Registers and Register Details [bit 12, 11] : CT1, CT0 (Compare Time) These bits is used for setting the comparsion time in terms of machine cycle. CT1 CT0 Comparsion time machine cycle Comparsion time 0 0 176 machine cycle 22ms at 8MHz machine clock 0 1 352 machine cycle 22ms at 16MHz machine clock 1 0 Reserved 1 1 Reserved Note1: When the bits is set to ‘00’, the machine clock should not be higher than 8MHz. Note2: Reading these bits always return “1”. [bit 9 to bit 0] : D9 to D0 (ADCR1:1,0 and ADCR0) ADCR1:1,0 and ADCR0 stores the AD conversion result. These register values are updated each time conversion is completed. Usually, the final conversion value is stored in these bits. Upon a reset, these registers are undefined. The conversion data protection function is available. See Section 2.7.4, "Operations." Note: Ensure that no data is written to these registers during A/D conversion. MB90580 Series Chapter 16: A/D Converter 227 16.4 Operations 16.4 Operations The A/D converter operates in the sequential compare format, and has a 8-bit resolution. Since the A/D converter has only one register (8 bits) for storing the conversion result, the conversion data registers (ADCR0) are updated each time conversion is completed. Thus, the A/D converter must not be used alone for continuous conversion. Use the F2MC-16 intelligent I/O service function to transfer converted data to memory while conversion is in progress. The operation modes are explained below. (1) Single mode In this mode, the converter sequentially converts the analog inputs specified with the ANS and ANE bits. The converter stops operation after the conversion is completed for the end channel specified with the ANE bits. If the start and end channels are the same (ANS=ANE), conversion is performed only for one channel. Example: ANS = 0 0 0 , ANE = 0 1 1 Start → AN0 → AN1 → AN2 → AN3 → End ANS = 0 1 0 , ANE = 0 1 0 Start → AN2 → End (2) Continuous mode In this mode, the converter sequentially converts the analog inputs specified with the ANS and ANE bits. After the conversion is completed for the end channel specified with the ANE bits, conversion is repeated from the analog inputs of the ANS. If the start and end channels are the same (ANS=ANE), conversion for one channel is repeated. Example: ANS = 0 0 0 , ANE = 0 1 1 Start → AN0 → AN1 → AN2 → AN3 → AN0 ...... → Repeat ANS = 0 1 0 , ANE = 0 1 0 Start → AN2 → AN2 → AN2 ...... → Repeat In continuous mode, conversion is repeated until ’0’ is written to the BUSY bit. (Writing ’0’ to the BUSY bit forces the operation to end.) If the operation is terminated forcibly, conversion stops before conversion is completed. (Upon a forced termination, the conversion register stores the previous data that has been converted completely.) 228 Chapter 16: A/D Converter MB90580 Series 16.4 Operations (3) Stop mode In this mode, the converter sequentially converts the analog inputs specified with the ANS and ANE bits, pausing each time conversion for one channel is completed. To release pausing, activate the A/D converter again. After the conversion is completed for the end channel specified with the ANE bits, conversion is repeated from the analog inputs of the ANS. If the start and end channels are the same (ANS=ANE), conversion is performed only for one channel. Example: ANS = 0 0 0 , ANE = 0 1 1 Start → AN0 → End → Restart → AN1 → End → Restartë → AN2 → End → Restart → → AN3 → End → Restart → AN0 ...... → Repeat ANS = 0 1 0 , ANE = 0 1 0 Start → AN2 → End → Restart → AN2 → End → Restartë → AN2 ...... → Repeat Only the activation factors specifies with STS1 and STS0 are used. In this mode, start of conversion can be synchronized. (4) Conversion using I2OS Sample flow from A/D conversion activation to transfer of converted data (continuous mode) Starting A/D conversion Sample and hold Starting I2OS Conversion Transferring data End of conversion Issuing interrupt Interrupt processing Clearing interrupt The portion indicated by the star ( ) is determined according to the I2OS settin Figure 16.4a Flow chart of A/D Conversion MB90580 Series Chapter 16: A/D Converter 229 16.4 Operations Usage ● Starting I2OS in single mode •To terminate conversion after analog inputs AN1 to AN3 are converted •To transfer conversion data sequentially to addresses 200H to 206H •To start conversion by software •To use the highest interrupt level I2OS setting MOV ICR3 MOV BAPL, MOV BAPM, MOV BAPH, MOV ISCS, MOV IOA, MOV DCT, A/D converter setting #08H #00H #02H #00H #18H #38H #03H .............................................. .............................................. .............................................. .............................................. .............................................. .............................................. .............................................. ① ② ③ ④ ⑤ ⑥ ⑦ MOV ADCS1 MOV ADCS2 Interrupt sequence #0BH #A2H .......................................................... .......................................................... ⑧ ⑨ .......................................................... ⑩ RETI ① Specifies the highest interrupt level, I2OS activation upon an interrupt, and the descriptor address. ②③④ Specifies the transfer destination address of converted data. ⑤ Specifies word data transfer. The transfer destination address is incremented after transfer. Data is transferred from I/O to memory. Transfer is terminated in response to a request from a resource. ⑦ I2OS transfer is performed three times. This count is the same as the conversion count. ⑧ Specifies single mode, start channel AN1, and end channel AN3. ⑨ Specifies activation by software and start of A/D conversion. ⑩ Specifies return from an interrupt. ICR3 BAPL BAPM BAPH ISCS I/OA DCT : : : : : : : Interrupt control register Buffer address pointer, low-order Buffer address pointer, medium-order Buffer address pointer, high-order I2OS status register I/O address counter Data counter Activation AN1 → Interrupt → I2OS transfer AN2 → Interrupt → I2OS transfer AN3 → Interrupt → I2OS transfer End Interrupt sequenc Parallel processing 230 Chapter 16: A/D Converter MB90580 Series 16.4 Operations Usage ● Starting I2OS in continuous mode •To convert analog inputs AN3 to AN5 and obtain two conversion data items for each channel •To transfer conversion data sequentially to addresses 600H to 60CH •To start conversion by external edge input • To use the highest interrupt level I2OS setting MOV ICR3 MOV BAPL, MOV BAPM, MOV BAPH, MOV ISCS, MOV I / OA, MOV DCT, A/D converter setting #08H #00H #06H #00H #08H #38H #06H ............................................... ............................................... ............................................... ............................................... ............................................... ............................................... ............................................... ① ② ③ ④ ⑤ ⑥ ⑦ MOV ADCS1 MOV ADCS2 Interrupt sequence #9DH #A4H .......................................................... .......................................................... ⑧ ⑨ MOV RET #00H .......................................................... ⑩ ADCS2 ① Specifies the highest interrupt level, I2OS activation upon an interrupt, and the descriptor address. ②③④ Specifies the transfer destination address of converted data. ⑤ Specifies word data transfer. The transfer destination address is incremented after transfer. Data is transferred from I/O to memory. Transfer is terminated in response to a request from a resource. ⑥ Transfer source address ⑦ I2OS transfer is performed six times. Data is transferred for three channels ×2. ⑧ Specifies continuous mode, start channel AN3, and end channel AN5. ⑨ Specifies activation by external edge and start of A/D conversion. ⑩ Specifies return from an interrupt. ICR3 BAPL BAPM BAPH ISCS I/OA DCT : : : : : : : Interrupt control register Buffer address pointer, low-order Buffer address pointer, medium-order Buffer address pointer, high-order I2OS status register I/O address counter Data counter Activation AN3 → Interrupt → I2OS transfer AN4 → Interrupt → I2OS transfer AN5 → Interrupt → I2OS transfer After six transfers Interrupt sequenc End MB90580 Series Chapter 16: A/D Converter 231 16.4 Operations Usage ● Starting I2OS in stop mode •To convert analog input AN3 12 times at fixed intervals •To transfer conversion data sequentially to addresses 600H to 618H •To start conversion by external edge input • To use the highest interrupt level I2OS setting MOV ICR3 MOV BAPL, MOV BAPM, MOV BAPH, MOV ISCS, MOV I / OA, MOV DCT, A/D converter setting #08H #00H #06H #00H #08H #38H #0CH .............................................. .............................................. .............................................. .............................................. .............................................. .............................................. .............................................. ① ② ③ ④ ⑤ ⑥ ⑦ MOV ADCS1 MOV ADCS2 Interrupt sequence #DBH #A4H .......................................................... .......................................................... ⑧ ⑨ MOV RET #00H .......................................................... ⑩ ADCS2 ① Specifies the highest interrupt level, I2OS activation upon an interrupt, and the descriptor address. ②③④ Specifies the transfer destination address of converted data. ⑤ Specifies word data transfer. The transfer destination address is incremented after transfer. Data is transferred from I/O to memory. Transfer is terminated in response to a request from a resource. ⑥ Transfer source address ⑦ I2OS transfer is performed 12 times. ⑧ Specifies continuous mode, start channel AN3, and end channel AN3 (one-channel conversion). ⑨ Specifies activation by external edge and start of A/D conversion. ⑩ Specifies return from an interrupt. ICR3 BAPL BAPM BAPH ISCS I/OA DCT : Interrupt control register : Buffer address pointer, low-order : Buffer address pointer, medium-order : Buffer address pointer, high-order : I2OS status register :I/O address counter : Data counter Activation AN3 → Interrupt → I2OS transfer After 12 transfers Stop Activation by external edge Interrupt sequenc End 232 Chapter 16: A/D Converter MB90580 Series 16.4 Operations (5) Conversion data protection The A/D converter has a conversion data protection function that enables continuous conversion and preservation of multiple data items using I2OS. Since there is only one conversion data register, its value is updated each time conversion is completed. Thus, continuous data conversion results in the loss of the previous data due to storage of the new data. To prevent this situation, the A/D converter pauses after conversion if the previous data item has not been transferred to memory by I 2OS. The converted data is not saved until the previous data is transferred to memory. The pause is released after data is transferred to memory by I 2OS. If the previous data has been transferred to memory, the A/D converter continues operation without pausing. Note: * This function is related to the INT and INTE bits of ADCS2. The data protection function operates only when interrupts are enabled (INTE=1). If interrupts are disabled (INTE=0), this function is disabled. Continuous A/D conversion results in loss of previous data, since the converted data items are saved to the register one after another. proIf I2OS is not used while interrupts are enabled (INTE=1), the INT bit is not cleared. Thus, the data tection function works and the A/D converter pauses. In this case, clearing the INT bit in the interrupt sequence releases the pause. If the A/D converter is pausing during I2OS operation, disabling interrupts may restart the A/D converter. In this case, the value in the conversion data register may be changed without being transferred. Restarting the A/D converter while it is pausing destroys the standby data. Flow of data protection function (when I2OS is used) Setting I2OS The flow while A/D converter is stopped is omitted. Starting continuous A/D conversion *1: Restarting the converter while paused destroys the standby conversion data. Ending first conversion Saving the result in the data register Starting I2OS Ending second conversion End I2OS? NO Pausing A/D conversion YES YES Saving the result in the data register End I2OS? *1 NO Starting I2OS Ending third conversion Continued Starting I2OS Ending the last conversion Interrupt routine End Stooping A/D conversion Figure 16.4b Flow Chart of Data Protection Function MB90580 Series Chapter 16: A/D Converter 233 16.5 Notes on use 16.5 Notes on use To start the A/D converter upon an external trigger or internal timer, A/D activation factor bits STS1 and STS0 of the ADCS2 register are used. Ensure that the input values of the external trigger or internal timer are inactive. If the values are active, A/D conversion may start immediately. When setting STS1 and STS0, ensure that ’1’ (input) is specified for ADTG and ’0’ (output) is specified for the internal timer (timer 2). 16.5.1 Other considerations Always write ’1’ to the ADER bit corresponding to a pin used as analog input. Analog input enable register Bit Address: 00001CH Read/write Initial value 15 14 13 12 11 10 9 8 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 R/W (1) R/W (1) R/W (1) R/W (1) R/W (1) R/W R/W (1) R/W (1) (1) ADER Port 5 pins are controlled as described below. 0: Port input mode 1: Analog input mode ’1’ is set upon a reset. 234 Chapter 16: A/D Converter MB90580 Series Chapter 17: D/A Converter 17.1 Outline This is an R-2R format D/A converter, having an eight-bit resolution. The D/A converter has two channels. Output control can be performed independently for the two channels using the D/A control register. 17.2 Block Diagram 17.2 Block Diagram F2MC-16LX BUS DA DA DA DA DA DA DA DA 17 16 15 14 13 12 11 10 DA DA DA DA DA DA DA DA 07 06 05 04 03 02 01 00 DVR DVR DA07 DA17 2R DA16 2R DA15 R R 2R DA06 2R DA05 R R DA01 DA11 2R DA10 2R DAE1 Standby control DA output ch1 R 2R DA00 2R 2R R 2R DAE0 Standby control DA output ch0 Figure 17.2a Block Diagram of D/A Cobverter 236 Chapter 17: D/A Converter MB90580 Series 17.3 Registers and Register Details 17.3 Registers and Register Details D/A converter data register 1 Address : 00003BH Read/write Initial value 15 14 13 12 DA17 DA16 DA15 DA14 (R/W) (R/W) (X) (X) (R/W) (X) 11 DA13 (R/W) (X) (R/W) (X) 10 DA12 (R/W) (X) 9 8 DA11 DA10 (R/W) (X) Bit number DAT1 (R/W) (X) D/A converter data register 0 Address : 00003AH Read/write Initial value 7 6 5 4 3 2 DA07 DA06 DA05 DA04 DA03 DA02 (R/W) (R/W) (X) (X) (R/W) (X) (R/W) (X) (R/W) (X) 1 0 DA01 DA00 (R/W) (X) (R/W) (X) (R/W) (X) 8 Bit number DAT0 D/A control register 1 Address : 00003DH Read/write Initial value 15 14 13 12 11 10 9 — — — — — — — DAE1 (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (R/W) (0) 7 6 5 4 3 2 1 0 — — — — — — DAE0 (-) (-) (R/W) (0) Bit number DACR1 D/A control register 0 Address : 00003CH Read/write Initial value — (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) Bit number DACR0 Figure 17.3a Register of D/A Converter MB90580 Series Chapter 17: D/A Converter 237 17.3 Registers and Register Details 17.3.1 DAT0/1 ( D/A data register) D/A converter data register 1 Address : 00003BH Read/write Initial value 15 14 13 12 DA17 DA16 DA15 DA14 (R/W) (R/W) (X) (X) (R/W) (X) 11 DA13 (R/W) (X) (R/W) (X) 10 DA12 (R/W) (X) 9 8 DA11 DA10 (R/W) (X) Bit number DAT1 (R/W) (X) D/A converter data register 0 Address : 00003AH Read/write Initial value 7 6 5 4 3 2 DA07 DA06 DA05 DA04 DA03 DA02 (R/W) (R/W) (X) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) 1 Bit number 0 DA01 DA00 (R/W) (X) (R/W) (X) DAT0 [bits 15 to 8] DA17 to DA10 These bits are used to set the output voltage of D/A converter ch1. These bits are not initialized upon a reset. These bits are readable and writable. [bits 7 to 0] DA07 to DA00 These bits are used to set the output voltage of D/A converter ch0. These bits are not initialized upon a reset. These bits are readable and writable. 17.3.2 DACR0/1 ( D/A control register) D/A control register 1 Address : 00003DH Read/write Initial value 15 14 13 12 11 10 9 8 — — — — — — — DAE1 (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (R/W) (0) 7 6 5 4 3 2 1 — — — — — — DAE0 (-) (-) (R/W) (0) Bit number DACR1 D/A control register 0 Address : 00003CH Read/write Initial value — (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) Bit number 0 DACR0 [bit 0] DAE1 and DAE0 These bits are used to enable or disable the D/A converter output. DAE1 controls channel 1 output, while DAE0 controls channel 0 output. When ’1’ is written to these bits, D/A output is enabled. When ’0’ is set, D/A output is disabled. These bits are initialized to ’0’ upon a reset. These bits are readable and writable. 238 Chapter 17: D/A Converter MB90580 Series 17.4 Operations 17.4 Operations D/A output is started by writing a desired D/A output value to the D/A data register (DADR) and setting ’1’ to the enable bit for the corresponding D/A output channel in the D/A control register (DACR). Disabling D/A output turns off the analog switch that is inserted serially into the output of each D/A converter channel. In addition, the D/A converter is internally cleared to ’0’ and the path of the DC current is shut down. This also applies in stop mode. Table 17.4a shows the theoretical values of D/A converter output voltages The D/A converter output voltages are between 0 V and 255/256 V changed by regulating the DVR voltage externally. × DVR. The output voltage range is The D/A converter output does not have an internal buffer amplifier. Since an analog switch (=100 Ω) is serially inserted into the output, allow sufficient settling time when applying an external output load. Table 17.4a Theoretical values of D/A converter output voltages Values written to DA07 to DA00 and DA17 to DA10 Theoretical values of output voltages 00H 0/256 × DVR (=0 V) 01H 1/256 × DVR 02H 2/256 × DVR FDH 253/256 × DVR FEH 254/256 × DVR FFH 255/256 × DVR MB90580 Series Chapter 17: D/A Converter 239 Chapter 18: Pulse Width Counter (PWC) Timer 18.1 Outline This module is a multi-function 16-bit up-counter with a reload function and a function for counting pulse widths on the input signal. The module hardware consists of a 16-bit up-counter, input pulse divider, divide ratio control register, four count input pins, one pulse output pin, and a 16-bit control register. These perform the following functions. Timer function: • Interrupt requests can be generated at specified time intervals. • A pulse signal can be output synchronized with the timer period. • The counter clock can be selected from three internal clocks. Pulse width count function: • Measures the time between events on an external pulse input. • The counter clock can be selected from three internal clocks. • Count modes H pulse width ( ⇑ to ⇓ )/L pulse width ( ⇓ to ⇑ ) Rising edge period ( ⇑ to ⇑ )/Falling edge period ( ⇓ to ⇓ ) Inter-edge count ( ⇑ or ⇓ to ⇓ or ⇑ ) • Using the 8-bit input divider, the module can divide an input pulse signal by 22n (n = 1, 2, 3, 4) and measure the period. • An interrupt request can be generated on count completion. • Single-shot or continuous counting can be selected. The MB90580 series contains one PWC timer channels. 18.2 Block Diagram 18.2 Block Diagram PWCR read ERR Error detection 16 Internal clock (machine clock/4) PWCR 16 16 Write enable Reload Data transfer 16 Overflow 22 Clock 16-bit up-count timer Clock divider 23 FFMC-16 bus Timer clear Count enable Control bit output Flag set Control circuit Start edge selection Divider clear Divider ON/OFF Count start edge Count end edge Overflow interrupt request PWC Edge detect Count end interrupt request 15 End edge selection CKS1 CKS0 ERR PIS1 PIS0 8-bit divider CKS1 CKS0 Divide ratio selection PWCSR Overflow F.F POT 2 DIVR Figure 18.2a lock Diagram of Pulse Width Counter Timer 242 Chapter 18: Pulse Width Counter (PWC) Timer MB90580 Series 18.3 Regiaters and Register Details 18.3 Regiaters and Register Details PWC Control Status Register (Upper Byte) 15 Address : 000055H Read/write Initial value STRT 14 13 12 11 STOP EDIR EDIE OVIR (R/W) (R/W) (0) (0) (R/W) (0) 10 9 8 OVIE ERR POUT (R/W) (0) (R) (0) (R/W) (0) 1 0 (R) (0) (R/W) (0) 5 4 3 2 PIS0 S/C MOD2 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) 13 12 11 Bit number PWCSR (HIGH) PWC Control Status Register (Lower Byte) 7 Address : 000054H CSK1 Read/write Initial value 6 CSK0 PIS1 (R/W) (R/W) (0) (0) MOD1 MOD0 (R/W) (0) Bit number PWCSR (LOW) (R/W) (0) PWC Data Buffer Register (Upper Byte) 15 14 10 9 8 Address : 000057H (R/W) (R/W) (X) (X) Read/write Initial value (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) 2 1 (R/W) (X) Bit number PWCR (HIGH) PWC Data Buffer Register (Lower Byte) 7 6 5 4 3 0 Address : 000056H (R/W) (R/W) (X) (X) Read/write Initial value (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) 6 5 4 3 2 1 0 Bit number PWCR (LOW) Divide Ratio Control Register 7 Address : 000058H — — — — — — DIV1 DIV0 Read/write Initial value (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (R/W) (0) (R/W) (0) 6 5 4 3 2 1 0 — — — — — SW1 SW0 EN (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (R/W) (0) (R/W) (0) (R/W) (0) Bit number DIVR PWC Noise Cancelling register 7 Address : 000086H Read/write Initial value Bit number RNCR Figure 18.3a Register of Pulse Width Counter Timer MB90580 Series Chapter 18: Pulse Width Counter (PWC) Timer 243 18.3 Regiaters and Register Details 18.3.1 PWC control status register (PWCSR) PWC Control Status Register (Upper Byte) 15 Address : 000055H STRT 14 13 12 11 STOP EDIR EDIE OVIR (R/W) (R/W) (0) (0) Read/write Initial value (R) (0) (R/W) (0) (R/W) (0) 10 9 8 OVIE ERR POUT (R/W) (0) (R) (0) (R/W) (0) 1 0 Bit number PWCSR (HIGH) PWC Control Status Register (Lower Byte) 7 Address : 000054H CSK1 Read/write Initial value 6 5 CSK0 PIS1 (R/W) (R/W) (0) (0) (R/W) (0) 4 3 2 PIS0 S/C MOD2 (R/W) (0) (R/W) (0) (R/W) (0) MOD1 MOD0 (R/W) (0) Bit number PWCSR (LOW) (R/W) (0) The PWCSR is used to control the operation of the PWC timer and to read the PWC timer status. [bit 15] STRT (Start) & [bit 14] STOP (Stop) These bits start, restart, and stop the 16-bit up-count timer. Reading the bits returns the operating state of the timer. The bit functions are as follows. Function of STRT and STOP bits when they are written. (Operation control) STRT STOP 0 0 No function. Has no effect on operation. Operation Control Function 0 1 Starts or restarts the timer (count enable). Note: The clear bit instruction can be used. 1 0 Forcibly halts the operation of the timer (count disable). Note: The clear bit instruction can be used. 1 1 No function. Has no effect on operation. Meaning of the STRT and STOP bits when they are read. (Operating status indication) STRT STOP Operating Status Indication 0 0 Timer is halted (not started or count ended). (Initial value) 1 1 Timer is counting (count in progress). After a reset: Initialized to 00B. Readable and writable. Note that the meanings of the bits differ for reading and writing. Always read as 11B by read-modify-write instructions regardless of the actual values. Although bit manipulation instructions (such as the bit clear instruction) can be used to write to the STRT and STOP bits to start and stop the timer, bit manipulation instructions cannot be used to read the operating status (as these always indicate that the timer is operating). 244 Chapter 18: Pulse Width Counter (PWC) Timer MB90580 Series 18.3 Regiaters and Register Details [bit 13] EDIR (End interrupt request) This flag indicates when counting ends in pulse width count mode. A count end interrupt request is generated if the interrupt is enabled (bit 12: EDIE = "1") when this bit is set. Set timing Clear timing Set when pulse width counting ends (when the count result is placed in PWCR). Cleared by reading PWCR (the count result). Note: This bit has no meaning in timer mode. After a reset: Initialized to "0". Read-only. Writing to the bit does not change the value. [bit 12] EDIE (End interrupt enable) Controls the count end interrupt request in pulse width count mode as follows. 0 Disable output of count end interrupt requests (do not generate an interrupt when EDIR is set). 1 Enable output of count end interrupt requests (generate an interrupt when EDIR is set). (Initial value) Note: Always set to "0" during timer mode. After a reset: Initialized to "0". Readable and writable. [bit 11] OVIR (Overflow interrupt request) This flag indicates when the 16-bit up-count timer overflows from FFFFH to 0000H. Operates in all modes. A timer overflow interrupt request is generated if the interrupt is enabled (bit 10: OVIE = "1") when this bit is set. Set timing Set when a timer overflow occurs (FFFFH to 0000H). Clear timing Cleared by writing "0" or by the extended intelligent I/O service. After a reset: Initialized to "0". Readable and writable. However, only writing "0" is valid. Writing "1" does not change the bit value. Read-modify-write instructions always read the bit as "1" regardless of the actual bit value. [bit 10] OVIE (Overflow interrupt enable) Controls the timer overflow interrupt request as follows. 0 1 Disable output of overflow interrupt requests (do not generate an interrupt when OVIR is set). (Initial value) Enable output of overflow interrupt requests (generate an interrupt when OVIR is set). After a reset: Initialized to "0". Readable and writable. MB90580 Series Chapter 18: Pulse Width Counter (PWC) Timer 245 18.3 Regiaters and Register Details [bit 9] ERR (Error) This flag is used when continuous counting is performed in pulse width count mode. The flag indicates that the next count has completed before the previous count result has been read from PWCR. When this occurs, PWCR is overwritten with the new count result and the previous result is lost. Counting continues regardless of the value of this bit. Set timing Set when a count result that has not been read is overwritten by the next result. Clear timing Cleared by reading PWCR (the count result). After a reset: Initialized to "0". Read-only. Writing to the bit does not change the value. [bit 8] POUT (Pulse output) In timer mode, this bit is inverted each time the 16-bit up-count timer overflows from FFFF H to 0000H. The bit has no meaning in pulse width count mode. Set timing Set when the timer overflows from FFFFH to 0000H when the value of POUT is "0", or by writing "1" when the timer is halted. Clear timing Cleared when the timer overflows from FFFFH to 0000H when the value of POUT is "1", by writing "0" when the timer is halted, or by a reset. After a reset: Initialized to "0". Readable and writable. However, the bit can only be written to when the timer is halted (when bit 15 and bit 14: STRT and STOP are both "0"). The value of the bit does not change if written to during timer operation (when bit 15 and bit 14: STRT and STOP are both "1"). [bits 7, 6] CKS1, CKS0 (Clock select 1, 0) These bits select the internal count clock as follows. CSK1 CSK0 Count Clock Selection 0 0 Machine cycle divided by 4 (0.25µs for a 16MHz machine cycle) (Initial value) 0 1 Machine cycle divided by 16 (1.0µs for a 16MHz machine cycle) 1 0 Machine cycle divided by 32 (2.0µs for a 16MHz machine cycle) 1 1 Note: Prohibited setting After a reset: Initialized to "00B". Readable and writable. However, setting "11B" is prohibited. Note: Changing the setting after activating the timer is prohibited. Only write to these bits before starting or after halting the timer. 246 Chapter 18: Pulse Width Counter (PWC) Timer MB90580 Series 18.3 Regiaters and Register Details [bits 5, 4] PIS1, PIS0 (Pulse input select) These bits select the input pin on which to perform pulse width counting. PIS1 PIS0 0 0 0 1 1 0 1 1 Count Input Pin Selection Always set this value. (Initial value) Setting unavailable (Do not set any of these values.) After a reset: Initialized to "00B". Readable and writable. Note: Changing the setting after activating the timer is prohibited. Only write to these bits before starting or after halting the timer. Note: When developing software for the MB90580 series, always set these bits to "00B". [bit 3] S/C (Single/Continuous) Select the count mode as follows. S/C Count Mode Selection Timer Mode Pulse Width Count Mode 0 Single-shot count mode (Initial value) No reload (single-shot) Halt after one count. 1 Continuous count mode Perform reload (reload timer) Continuous counting: Buffer register enabled After a reset: Initialized to "0". Readable and writable. Note: Changing the setting after activating the timer is prohibited. Only write to these bits before starting or after halting the timer. MB90580 Series Chapter 18: Pulse Width Counter (PWC) Timer 247 18.3 Regiaters and Register Details [bits 2, 1, 0] MOD2, MOD1, MOD0 (MOD2, 1, 0) These bits select the operation mode and the pulse edges for width counting. MOD2 MOD1 MOD0 Operation Mode/Count Edge Selection 0 0 0 Timer mode, no pulse output 0 0 1 Timer mode, pulse output enabled (using the POT pin): Reload mode only (Initial value) 0 1 0 Inter-edge pulse width count mode ( ⇑ or ⇓ to ⇓ or ⇑ ) * 0 1 1 Divided period count mode (using input divider) * 1 0 0 Rising-edge to rising-edge count mode ( ⇑ to ⇑ ). * 1 0 1 "H" pulse width count mode( ⇑ to ⇓ ). * 1 1 0 "L" pulse width count mode( ⇓ to ⇑ ). * 1 1 1 Falling-edge to falling-edge count mode ( ⇓ to ⇓ ). * After a reset: Initialized to "000B". Readable and writable. Note: Changing the setting after activating the timer is prohibited. Only write to these bits before starting or after halting the timer. Note: When continuous count mode is set for the settings marked with an asterisk (*), the divider circuit for the internal count clock is not cleared when the count ends so as to accumulate the number of edges. In all other modes, the divider circuit for the internal count clock is cleared when the count ends. 248 Chapter 18: Pulse Width Counter (PWC) Timer MB90580 Series 18.3 Regiaters and Register Details 18.3.2 PWC data buffer register (PWCR) PWC Data Buffer Register (Upper Byte) 15 14 13 12 11 10 9 8 Address : 000057H Read/write Initial value (R/W) (R/W) (X) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) 2 1 (R/W) (X) Bit number PWCR (HIGH) PWC Data Buffer Register (Lower Byte) 7 6 5 4 3 0 Address : 000056H Read/write Initial value (R/W) (R/W) (X) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) (R/W) (X) Bit number PWCR (LOW) (1) In timer mode In reload timer operation mode (bit 3 S/C of PWCSR = "1"), this register stores the reload value. In this case, the register is readable and writable. In single-shot timer operation mode (bit 3 S/C of PWCSR = "0"), accessing this register directly accesses the up-count timer. Although both reading and writing are allowed in this mode, only write to the register when the timer is halted. The register can be read at any time to read the current timer value. (2) In pulse width count mode ♦ Read-only ♦ In continuous count mode (bit 3 S/C of PWCSR = "1"), this register acts as a buffer register to store the previous count result. In this case, the register is read-only and writing does not change the register value. In single-shot count mode (bit 3 S/C of PWCSR = "0"), accessing this register directly accesses the up-count timer. The register is read-only in this mode also and writing does not change the register value. The register can be read at any time to read the current timer value. After the count ends, the register stores the count result. Note: Always use word transfer instructions to access this register. After a reset: Initialized to "0000 H". MB90580 Series Chapter 18: Pulse Width Counter (PWC) Timer 249 18.3 Regiaters and Register Details 18.3.3 Divide Ratio Control Register (DIVR) Divide Ratio Control Register 7 Address : 000058H Read/write Initial value 6 5 4 3 2 1 0 — — — — — — DIV1 DIV0 (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (R/W) (0) (R/W) (0) Bit number DIVR This register is only used in divided period count mode (bits 2, 1, 0: MOD2, 1, 0 of PWCSR = "011"). In divided period count mode, pulses input from the count pin are divided by the divide ratio set in this register and the period of the divided signal is measured. The divide ratio is selected as follows. DIV1 DIV0 0 0 Divide Ratio Selection 22 = divide by 4 (Initial value) 4 0 1 2 = divide by 16 1 0 26 = divide by 64 1 1 28 = divide by 256 After a reset: Initialized to "00B". Readable and writable. Note: Changing the setting after activating the timer is prohibited. Only write to these bits before starting or after halting the timer. 250 Chapter 18: Pulse Width Counter (PWC) Timer MB90580 Series 18.3 Regiaters and Register Details 18.3.4 PWC noise cancelling register (RNCR) PWC Noise Cancelling register 7 Address : 000086H Read/write Initial value 6 5 4 3 2 1 0 — — — — — SW1 SW0 EN (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (R/W) (0) (R/W) (0) (R/W) (0) Bit number RNCR The PWC noise removal circuit is used for removing noises form the input signal. H level and L level detection will be applied to the input signal after it was ‘cleaned’ by the noise filter. Noise removal circuit is a digital low pass filter, the filter remove the high frequency components of the input signal. The noise-removed signal is called ‘RMCSIG’. This signal has the same polarilty with the orginial input signal, but the there may be slight phase difference. The SW bits of the noise cancelling register specifies the noise pulse width which can be removed by the filter circuit. This noise cancelling register is a 8-bit register, when reset, all bits will be initialized to 0. [bits 2, 1] SW1, SW0 SW1 and SW0 is the clock mode selection bit which specify the noise pulse width to be removed. The timing of the following table assumes the main clock is 16MHz. SW1 SW0 Input Clock Noise Pulse Width 0 0 0.5 MHz 2.0 µs 0 1 31.25 KHz 32.0 µs 1 0 15.62 KHz 64.0 µs 1 1 7.81 KHz 128.0 µs [bits 0] EN EN bit is used for enabling this noise cancelling function. MB90580 Series 0 Noise cancelling function disabled 1 Noise canncelling function enabled (Initial value) Chapter 18: Pulse Width Counter (PWC) Timer 251 18.4 Operations 18.4 Operations (1) Summary of Operation This block is a multi-function timer based on a 16-bit up-count timer and incorporating a count input pin and 8-bit input divider. The block has two main functions: a timer function and a pulse width count function. Two types of count clock can be selected for either function. The following describes the basic functions and operation of each of these functions. (a) Timer Function This function is an up-count timer which can be selected to operate in reload or single-shot mode. Once started, the timer counts on each count clock. An interrupt request can be generated when an overflow from FFFFH to 0000H occurs. When an overflow occurs: • Single-shot mode: ............. The count stops. • Reload mode:.................... The timer is reloaded with the contents of the reload register and the count restarts. Timer count value (The solid line is the timer count value.) Overflow FFFFH Overflow Write to PWCR (Restart is disabled.) ⇓ 0000H Timer start OVIR flag set, timer stop Timer start OVIR flag set, timer stop Time Figure 18.4a Timer Operation (Single-Shot Mode) Timer count value (The solid line is the timer count value.) Overflow FFFFH PWCR write value Reload⇒ Reload Overflow Overflow Reload Reload Overflow Reload Reload 0000H Write to PWCR OVIR flag set POUT bit Timer start ⇓ Timer start ⇓ ⇓ Overflow Reload Timer stop Time ⇓ ⇓ ⇓ Does not toggle when restarted when starting from "L" (unless this occurs at the same time as an overflow) Figure 18.4b Timer Operation (Reload Mode) 252 Chapter 18: Pulse Width Counter (PWC) Timer MB90580 Series 18.4 Operations (2) Pulse Width Count Function This function counts the time period between specified events on an input pulse. After the function is activated, the count does not start until the specified count start edge is input. The counter is cleared to "0000H" and counting starts when the start edge is detected. The count halts when the end edge is detected. The count value at the end of this period is stored in the register as the pulse width. An interrupt request can be generated when the count ends or when an overflow occurs. After counting completes: • Single-shot count mode: ... Operation halts. • Continuous count mode: ... The timer value is transferred to the buffer register and the count halts until the next start edge is input. (The solid line is the timer count value.) Pulse being counted on the PWC0 to 3 inputs Timer count value ⇓ ⇓ ⇓ ⇓ FFFFH 0000H Timer clear Timer start Count start Timer stop Time ⇓ EDIR flag set (count end) Figure 18.4c Pulse Width Count Operation (Single-Shot Count Mode, "H" Width Count Mode) (The solid line is the timer count value.) Pulse being counted on the PWC0 to 3 inputs Timer count value ⇓ FFFFH 0000H ⇓ ⇓ Data transferred ⇓ to PWCR Timer clear ⇓ Data transferred ⇓ to PWCR Timer clear Timer start Timer start Count start Overflow Timer stop ⇓ OVIR flag set Timer stop Time ⇓ EDIR flag set (count end) EDIR flag set Figure 18.4d Pulse Width Count Operation (Continuous Count Mode, "H" Width Count Mode) MB90580 Series Chapter 18: Pulse Width Counter (PWC) Timer 253 18.4 Operations (3) Count Clock Selection The timer count clock can be selected from three internal clock sources. The available clock sources are listed below. Table 18.4a Count Clock Selection PWCSR/bit7, 6:CKS1, 0 00B Selected Internal Count Clock Machine cycle divided by 4 (0.25µs for a 16MHz machine cycle) (Initial value) 01B Machine cycle divided by 16 (1.0µs for a 16MHz machine cycle) 10B Machine cycle divided by 32 (2.0µs for a 16MHz machine cycle) The selection is initialized to "machine cycle divided by 4" after a reset. Note: Always select the count clock before starting the timer. 254 Chapter 18: Pulse Width Counter (PWC) Timer MB90580 Series 18.4 Operations (4) Operation Mode Selection The operation mode and count mode are selected by PWCSR settings. • Operation mode setting PWCSR bits 2, 1, and 0: Bits MOD2, MOD1, and MOD0 (Selects timer or pulse width count mode and specifies which edges control counting.) • Count mode setting PWCSR bit 3: S/C bit (Selects single-shot or continuous counting, or reload or single-shot operation.) The following lists the operation modes selected by the mode setting bits. Figure 18.4e Operation Mode Selection Operation Mode Timer Pulse width count S/C MOD2 MOD1 MOD0 Single-shot timer 0 0 0 0 Reload timer 1 0 0 0 Setting prohibited 1 0 0 1 ⇑ or ⇓ to ⇑ or ⇓ Single-shot count: Buffer not used 0 0 1 0 Counts between all edges Continuous count: Buffer used 1 0 1 0 Divided period count Single-shot count: Buffer not used 0 0 1 1 (divide by 1 to 256) Continuous count: Buffer used 1 0 1 1 ⇑ to ⇑ Single-shot count: Buffer not used 0 1 0 0 Rising-edge to risingedge count Continuous count: Buffer used 1 1 0 0 ⇑ to ⇓ Single-shot count: Buffer not used 0 1 0 1 "H" pulse width count Continuous count: Buffer used 1 1 0 1 ⇓ to ⇑ Single-shot count: Buffer not used 0 1 1 0 "L" pulse width count Continuous count: Buffer used 1 1 1 0 ⇓ to ⇓ Single-shot count: Buffer not used 0 1 1 1 Falling-edge to fallingedge count Continuous count: Buffer used 1 1 1 1 The initial value after a reset selects single-shot timer mode. Note: Always select the operation mode before starting the timer. MB90580 Series Chapter 18: Pulse Width Counter (PWC) Timer 255 18.4 Operations (5) Starting and Stopping the Timer and Pulse Width Count Starting, restarting, and forcibly halting each operation is performed using bits 15 and 14 (STRT and STOP) of PWCSR. Writing "0" to the STRT bit starts or restarts operation and writing "0" to the STOP bit forcibly halts operation. However, neither bit performs its operation if the values written to the two bits are contradictory. When using instructions other than bit manipulation instructions (byte or larger instructions), only write the following bit combinations. Table 18.4b Start and Stop Bit Functions Function STRT STOP Start or restart timer or pulse width count. 0 1 Forcibly halt timer or pulse width count. 1 0 When using a bit manipulation instruction (clear bit instruction), writing of the above combinations is enforced automatically by hardware so no particular care is required. (a) Operation After Starting • Timer mode: ...................... The count operation starts immediately. • Pulse width count mode: ... The count does not start until the count start edge is input. After detecting the count start edge, the 16-bit up-count timer is cleared to 0000H and counting starts. (b) Restarting the Timer Re-applying the start command (writing "0" to the STRT bit) while the timer is still operating after starting in timer mode or pulse width count mode is called restarting. The operation performed for a restart depends on the mode, as follows. • Single-shot timer mode: .... No effect on the operation. • Reload timer mode:........... Performs a reload and continues operation. If the restart occurs at the same time as an overflow, the overflow flag (OVIR) is set and the POUT bit inverted. • Pulse width count mode: ... Has no effect on the operation if the timer is waiting for the count start edge. If applied during a count, the count halts and the timer returns to the "waiting for a count start edge" state. If the restart occurs at the same time as a count end edge is detected, the count end flag (EDIR) is set and, in continuous count mode, the count result is transferred to PWCR. (c) Stopping the Timer In single-shot timer mode or single-shot count mode, the count halts automatically when the timer overflows or the count ends and therefore you do not need to explicitly stop the timer. However, you must forcibly stop the timer in other modes or if you wish to stop the timer before it halts automatically. (d) Checking the Operating State The STRT and STOP bits described previously function as indicator bits for the operating state of the timer when read. The table below lists the bit meanings. Table 18.4c Operating State Indicator Bit Functions STRT STOP Operating State 0 0 The timer is stopped (other than when waiting for a count start edge). Indicates that the timer has not been started or that counting has ended. 1 1 The timer is counting or waiting for a count start edge. The STRT and STOP bits both have the same value when read. However, as the bits always have the value "1B" when read by read-modify-write instructions (such as bit manipulation instructions), do not use these instructions to read the bit values. 256 Chapter 18: Pulse Width Counter (PWC) Timer MB90580 Series 18.4 Operations (6) Clearing the Timer The 16-bit up-count timer is cleared to 0000H in the following cases. • A reset • When counting starts after detection of a count start edge in pulse width count mode(6) (7) Details of Timer Mode Operation (a) Single-Shot Operation Mode When the timer is started in this mode, the timer counts up on each count clock. The timer automatically stops when an overflow from FFFFH to 0000H occurs. If PWCR is set before starting the timer, the count starts from the set value. In this case, the set value is not saved and PWCR contains the current count value. Bit 8 (POUT) of PWCSR is inverted when an overflow occurs but the value is not output from the pin in this mode, even if pulse output mode is specified. (b) Reload Operation Mode When the timer is started in this mode, the reload value in PWCR is set to the timer and the timer counts up on each count clock. When an overflow from FFFFH to 0000H occurs, the reload value in PWCR is set again to the timer (reloading), the POUT bit (bit 8) of PWCSR is inverted, and the count operation repeated. The timer does not stop until forcibly halted by writing to the STOP bit of PWCSR or until a reset occurs. The reload value set to PWCR before starting the timer is stored during counting and is set to the timer when the timer is started or restarted and each time an overflow occurs. If the set value is changed during counting, the new reload value is used when the next overflow or restart occurs. (c) Timer Value and Reload Value In single-shot operation mode, accessing PWCR directly accesses the up-count timer. Writing a value to PWCR writes the value directly to the timer and reading PWCR during count operation reads the current timer value. Setting a value to PWCR before starting the timer causes the count to start from the specified value. In reload operation mode, the up-count timer cannot be accessed and PWCR acts as the reload register (stores the reload value). The value written to PWCR is set to the timer when the timer is started or restarted and each time an overflow occurs. Reading PWCR reads the stored reload value. The value in PWCR and the timer value are indeterminate if the timer is set to single-shot mode after forcibly halting operation in reload mode. Therefore, always set a value before using the timer. The value in PWCR is indeterminate if the timer is set to reload mode after forcibly halting operation in single-shot mode. Therefore, always set a value before using the timer. (d) Generation of Interrupt Requests Interrupt requests can be generated by overflows when operating in timer mode. When an overflow occurs due to the timer counting up, the overflow flag is set and an interrupt request is generated if the overflow interrupt request is enabled. MB90580 Series Chapter 18: Pulse Width Counter (PWC) Timer 257 18.4 Operations (e) Timer Period If the timer is started in single-shot mode after setting 0000H to PWCR, the timer overflows after 65536 counts and the count stops. The following formula calculates the time from the timer starting to the timer stopping. T1 … Time from start to stop (µs) T1 = (65536 -n1) × t n1 … Timer value set in PWCR when the timer starts t … Count clock period (µs) If the timer is started in reload mode after setting 0000H to PWCR, the timer overflows after each 65536 counts. The following formulas calculate the reload period and the period of the POT pin output pulse. TR = (65536 -nR) × t TPOUT = TR × 2 TR … Reload period (overflow period) (µs) TPOUT…Period of the POT pin output pulse (µs) nR … Reload value stored in PWCR t … Count clock period (µs) (f) Count Clock and Maximum Period For timer mode, the maximum period is when 0000H is set to PWCR. The following table lists the count clock period and maximum timer period for a 16MHz machine cycle (indicated by φ below). Table 18.4d Count Clock and Period Count Clock Selection Count clock period Maximum timer period 258 CKS1, 0 = 00 (φ/4) CKS1, 0 = 01 (φ/16) CKS1, 0 = 10 (φ/32) 0.25µs 1µs 2µs 16.38ms 65.5ms 131.1ms Chapter 18: Pulse Width Counter (PWC) Timer MB90580 Series 18.4 Operations (g) Timer Operation Flowchart Settings Count clock selection Operation and count mode selection Clear interrupt flag Enable interrupt Set pulse output initial value Set value to PWCR Start by STRT bit Restart Reload operation mode Single-shot operation mode Reload PWCR value in timer Start count Start count Up-count Up-count Overflow occurs Overflow occurs ⇒ Set OVIR flag ⇒ Set OVIR flag Invert POUT bit value Invert POUT bit value Stop count Stop operation Figure 18.4f Flowchart of Timer Mode Operation MB90580 Series Chapter 18: Pulse Width Counter (PWC) Timer 259 18.4 Operations (8) Details of Pulse Width Count Mode Operation (a) Count Input Pins and Pin Selection The pins used to input the signal for pulse width counting are fixed as pin PWC0 for ch0, PWC1 for ch1, PWC2 for ch2, and PWC3 for ch3. Always set bits 4 and 5 of PWCSR to "00" on the MB90580. Table 18.4e Count Input Pin Selection (n = 3 to 0) PIS1 PIS0 0 0 The PWCn pin for the channel (Initial value) Count Input Pin Selection 0 1 1 0 Setting unavailable (Do not set any of these values.) 1 1 Note: Only select or change the count input pin while the timer is halted. (b) Single-Shot Counting and Continuous Counting Pulse width count mode has a mode to perform a count once only and a mode to perform pulse width counting continuously. The following lists the differences between the two modes. • Single-shot count mode: .. When the first count end edge is input, the timer stops counting, the count end flag (EDIR) in PWCSR is set, and no further count is performed. (However, if a restart is specified at the same time, the timer goes to the "waiting for a count start edge" state.) • Continuous count mode: ... When a count end edge is input, the timer stops counting, the count end flag (EDIR) in PWCSR is set, and the count remains stopped until the next count start edge is input. When the next count start edge is input, the timer is cleared to 0000H and counting restarts. The count result in the timer is transferred to PWCR when the count ends. The S/C bit in PWCSR selects the mode (see (3) Operation Mode Selection). Note: Only select or change the count mode while the timer is halted. Note: For any of the pulse width count modes used with continuous count mode, the divider circuit for the internal count clock is not cleared when the count ends. Therefore, the result in continuous count modes is the accumulated number of edges. (c) Count Result Data The handling of the count result and timer value and the function of PWCR differ for single-shot count mode and continuous count mode. The differences are as follows. • Single-shot count mode: ... Reading PWCR during timer operation reads the current timer value. Reading PWCR after the count has ended reads the count result. • Continuous count mode: ... The count result in the timer is transferred to PWCR when the count ends. Reading PWCR reads the result of the previous count. PWCR continues to store the previous count result while counting is in progress. The timer value during counting cannot be read. In continuous count mode, if the previous count result is not read before the next count completes, the new count result overwrites the old value. If this occurs, the error flag (ERR) in PWCSR is set. The error flag (ERR) is automatically cleared when PWCR is read. 260 Chapter 18: Pulse Width Counter (PWC) Timer MB90580 Series 18.4 Operations (d) Count Mode and Count Operation The count mode can be selected from five different modes. The mode determines which part of the input pulse to measure. To accurately measure the width of high frequency pulses, a mode is available to divide the input pulses by a specified ratio and to measure the resulting period. The following describes each mode. Table 18.4f Count Modes Count Mode H pulse width count MOD2 MOD1 MOD0 1 0 Count Operation (w: Pulse width being measured) 1 W W ⇑Count start ⇓Count stop ⇑Start ⇓Stop Measures the width of the "H" period. • Count (meaOPsurement) detected start: Rising edge • Count (measurement) end: Falling edge detected L pulse width count 1 1 0 W W ⇓Count start ⇑Count stop ⇓Start ⇑Stop Measures the width of the "L" period. • Count (measurement) start: Falling edge detected • Count (measurement) end: Rising edge detected Rising edge to rising edge period count 1 0 0 W W W ⇑Count start ⇑Count stop ⇑Start ⇑Stop ⇑Start ⇑Stop Measures the time between rising edges. • Count (measurement) start: Rising edge detected • Count (measurement) end: Rising edge detected Falling edge to falling edge period count 1 1 1 W W W ⇓Count start ⇓Count stop ⇓Start ⇓Stop ⇓Start ⇓Stop Measures the time between falling edges • Count (measurement) start: Falling edge detected • Count (measurement) end: Falling edge detected MB90580 Series Chapter 18: Pulse Width Counter (PWC) Timer 261 18.4 Operations Table 18.4f Count Modes (Continued) Count Mode Inter-edge pulse width count Count Operation (w: Pulse width being measured) MOD2 MOD1 MOD0 0 1 0 W W W ⇑Count start ⇓Count stop ⇓Start ⇑Stop ⇑Start ⇓Stop Measures the width between consecutive input edges. • Count (measurement) start: Edge detected • Count (measurement) end: Edge detected Divided period count 0 1 1 W ⇓Count start W ⇑Count stop ⇑Start W ⇓Stop (Divide by 4 example shown) The input pulses are divided by the divide ratio set in the divide ratio register (DIVR) and the resulting period measured. • Count (measurement) start: Falling edge detected after operation started • Count (measurement) end: End of one period of the divided signal In all modes, the timer does not count during the time between starting the count and a count start edge being input. After the count start edge is input, the timer is cleared to 0000 H and the timer counts up on each count clock until a count end edge is input. The following operations are performed when a count end edge is input. (1) The count end flag (EDIR) in PWCSR is set. (2) The timer stops counting (unless the timer is restarted at the same time). (3) In continuous count mode:The timer value (count result) is transferred to PWCR and the count remains stopped until the next count start edge is input. (4) In single-shot count mode:The timer stops counting (unless the timer is restarted at the same time). In continuous count mode, the end edge also acts as the next start edge in some modes, including inter-edge pulse width count mode and period count mode. (e) Minimum Input Pulse Width Pulses input to the pulse width count input pins (PWC3 to PWC0) must be longer than the minimum input pulse width shown below. Pulse width:....... 2 machine cycles (≥ 0.125µs for a 16MHz machine clock) However, input pulses shorter than the above specification may be recognized as valid pulses in some cases. The PWC inputs do not have a filter function in the MB90580 series. If required, use a filter or similar circuit externally. 262 Chapter 18: Pulse Width Counter (PWC) Timer MB90580 Series 18.4 Operations (f) Pulse Width/Period Calculation Calculate the width or period of the measured pulse from the count result read from PWCR after the count ends as follows. Tw = n × t ÷ DIV (µs) Tw … Measured pulse width or period (µs) n … Count result stored in PWCR t … Count clock period (µs) DIV… Divide ratio set in the divide ratio register (DIVR) (Use the value 1 for modes other than divided period count mode.) (g) Pulse Width/Period Count Range The range of pulse widths/periods that can be measured depends on the count clock and the divide ratio of the input divider. The table below lists the measurement range for a 16MHz machine cycle (indicated by φ below). Table 18.4g Pulse Width Count Range Divide Ratio DIV1.0 CKS1, 0 = 00 (φ/4) CKS1, 0 = 01 (φ/16) CKS1, 0 = 10 (φ/32) No division – 0.125µs to 16.38ms [0.25µs] 0.125µs to 65.5ms [1.6µs] 0.2µs to 131ms [3.2µs] Divide by 4 00B 0.125µs to 4.10ms [62.5µs] 0.125µs to 16.38ms [0.4µs] 0.2µs to 32.75ms [800ns] Divide by 16 01B 0.125µs to 1024µs [15.6ns] 0.125µs to 4.10ms [0.1µs] 0.2µs to 8.19ms [200ns] Divide by 64 10B 0.125µs to 256µs [3.91ns] 0.125µs to 1024µs [25.0ns] 0.2µs to 2.048ms [50.0ns] Divide by 256 11B 0.125µs to 64µs [0.98ns] 0.125µs to 256µs [6.25ns] 0.2µs to 512ms [12.5ns] Note:The figures in [ ] indicate the resolution per bit. (h) Generation of Interrupt Requests The following two interrupt requests can be generated in pulse width count mode. (1) Timer overflow interrupt request If an overflow occurs during counting, the overflow flag is set and, if the overflow interrupt request is enabled, an interrupt request is generated. (2) Count end interrupt request When the count end edge is detected, the count end flag (EDIR) in PWCSR is set and, if the count end interrupt request is enabled, an interrupt request is generated. The count end flag (EDIR) is automatically cleared by reading PWCR. MB90580 Series Chapter 18: Pulse Width Counter (PWC) Timer 263 18.4 Operations (i) Flowchart of the Pulse Width Count Operation Settings Count clock selection Operation and count mode selection Clear interrupt flag Enable interrupt Set pulse output initial value Restart Start by STRT bit Continuous count mode Single-shot count mode Count start edge detected Count start edge detected Clear timer Clear timer Start count Start count Up-count Up-count Overflow occurs ⇒ Set OVIR flag Overflow occurs ⇒ Set OVIR flag Count end edge detected ⇒ Set EDIR flag Count end edge detected ⇒ Set EDIR flag Stop count Stop count Transfer timer value to PWCR Operation stops Figure 18.4g Flowchart of Operation in Pulse Width Count Mode (9) Initial State • The initial values of each register are: 264 PWCSR ⇒ (00000000 00000000)B PWCR ⇒ (00000000 00000000)B DIVR ⇒ (XXXXXX00)B Chapter 18: Pulse Width Counter (PWC) Timer MB90580 Series 18.5 Precautions 18.5 Precautions (1) Changing Register Values Changing the values of the following PWCSR bits when the timer is operating is prohibited. Only change bit values before starting the timer or after operation stops. [bits 7, 6] CKS1, CKS0: Clock selection bits [bits 5, 4] PIS1, PIS0: Count input pin selection bits [bit 3] S/C: Count mode (single-shot or continuous) selection bit [bits 2, 1, 0] MOD2, MOD1, MOD0: Operating mode and count edge selection bits Note that the value of the pulse output level indication bit (POUT: bit 8) does not change if the bit is written to when the timer is operating. Changing the DIVR value when the timer is operating is prohibited. Only change the DIVR value before starting the timer or after operation stops. (2) Count End Flag in Timer Mode The value of the count end interrupt request flag (EDIR) in PWCSR has no meaning in timer mode. Therefore, always set the enable bit for the count end interrupt request (EDIE) in PWCSR to "0". (3) STRT and STOP bits in PWCSR Note that the meaning of these two bits differs depending on whether they are being read or written (see the register description for details). Also note that read-modify-write instructions always read the bits as "11B" regardless of the actual values. Therefore, bit manipulation instructions cannot be used to read the operation state (as the result will always indicate "operating"). However, bit manipulation instructions (such as the bit clear instruction) can be used to write to the STRT or STOP bit to start or stop the timer. (4) Clearing the Timer In pulse width count mode, the timer is cleared by the count start edge and therefore the previous data in the timer has no meaning. (5) Clock Selection Bits Setting "11B" to the clock selection bits (CKS1, CKS0: bits 7, 6) in PWCSR is prohibited. (6) PWCR and Timer Value When Changing Mode The value in PWCR and the timer value are indeterminate if the timer is set to single-shot mode after forcibly halting operation in reload mode. Therefore, always set a value before using the timer. The value in PWCR is indeterminate if the timer is set to reload mode after forcibly halting operation in single-shot mode. Therefore, always set a value before using the timer. When changing from pulse width count mode to timer mode, always set a value to PWCR before starting the timer. (7) Minimum Input Pulse Width The following restriction applies to pulses input to the pulse width count input pins. • Minimum input pulse width: Machine cycle divided by 2 (≥ 0.125µs for a 16MHz machine cycle) • Maximum input frequency: Machine cycle divided by 4 (≥ 4MHz for a 16MHz machine cycle) The operation of the timer if pulses of shorter width or higher frequency are input is not guaranteed. If it is possible that such noise may be present on the input signal, use an external filter or similar circuit to suppress the noise. MB90580 Series Chapter 18: Pulse Width Counter (PWC) Timer 265 18.5 Precautions (8) Divided Period Count Mode Note that the input pulses are divided when divided period count mode is used in pulse width count mode and therefore the pulse width calculated from the count result is an average value. (9) Restarting the Timer During Operation Depending on the timing, the following may occur when the timer is restarted after starting the count operation. (a) If the restart occurs at the same time as an overflow in reload timer mode: The timer restarts but the overflow flag (OVIR) is set and the POUT bit inverted. (That is, the same operations are performed as for a normal overflow.) (b) If the restart occurs at the same time as the count end edge in single-shot pulse width count mode: The timer restarts and waits for a count start edge but the count end flag (EDIR) is also set. (c) If the restart occurs at the same time as the count end edge in continuous pulse width count mode: The timer restarts and waits for a count start edge but the count end flag (EDIR) is also set and the count result at that time is transferred to PWCR. When restarting the timer while it is still operating, take note of the operation of the flags as described above and perform interrupt and other control accordingly. (10) Pulse Width Count Mode Using Continuous Count Mode Note that, when performing continuous counting in this mode, the divider circuit for the internal count clock is not cleared and therefore the number of edges below the count clock is added to the result. 266 Chapter 18: Pulse Width Counter (PWC) Timer MB90580 Series Chapter 19: Clock Monitor Function 19.1 Outline Clock Monitor Function is used to output the machine clock to a port pin. This clock output is generated by dividing the machineclock by 21 to 28. F2MC-16LX bus 19.2 Block Diagram CKEN machine clock FRQ2 FRQ1 FRQ0 Clock division circuit P65/CKOT Figure 19.2a Block Diagram of Clock Monitor Function 19.3 Registers and Register Details 19.3 Registers and Register Details Clock Output Enable Register Address : 00003EH Read/write Initial value 7 6 5 4 3 — — — — (-) (-) (-) (-) (-) (-) (-) (-) 2 1 0 CKEN FRQ2 FRQ1 FRQ0 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) Bit number CLKR Figure 19.3a Registers of Clock Monitor Function 19.3.1 Clock output enable register (CLKR) Address : 00003EH Read/write Initial value 7 6 5 4 3 — — — — (-) (-) (-) (-) (-) (-) (-) (-) 2 1 0 CKEN FRQ2 FRQ1 FRQ0 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) Bit number CLKR [bit 3] : CKEN CKOT output enable bit. 0 Ordinary port 1 CKOT output [bits 2, 1, and 0] FRQ2, FRQ1, and FRQ0 These bits are used to select the clock output frequency. 268 FRQ2 FRQ1 FRQ0 Output clock ∅=16 MHz ∅=8 MHz ∅=4 MHz 0 0 0 ∅/21 125 ns 250 ns 500 ns 0 0 1 ∅/22 250 ns 500 ns 1 µs 0 1 0 ∅/23 500 ns 1 µs 2 µs 0 1 1 ∅/24 1 µs 2 µs 4 µs 1 0 0 ∅/25 2 µs 4 µs 8 µs 1 0 1 ∅/26 4 µs 8 µs 16 µs 1 1 0 ∅/27 8 µs 16 µs 32 µs 1 1 1 ∅/28 16 µs 32 µs 64 µs Chapter 19: Clock Monitor Function MB90580 Series Chapter 20: 16-Bit I/O Timer 20.1 Outline The 16-bit I/O timer consists of a 16-bit free-run timer, two output compare modules, and four input capture modules. The count values of this timer are used as the base timer for output compare and input capture. Using this function, two independent waveforms can be output based on 16-bit free-run timer to enable measurement of input pulse withs and external clock cycles. • Four types of counter clock are available. • An interrupt can be generated upon a counter value overflow. • The counter value can be initialized upon a match with compare register 0, depending on the mode. ❑ 16-bit free-run timer (×1) The 16-bit free-run timer consists of a 16-bit up counter, control register, and prescaler. The 16-bit up counter is used to counting up in synchronization to the machine clock, in which an interrupt factor can be selected from the overflow interrupt and four types of timer intermediate bit interrupt to be operated as an interval timer. • Four types of counter clock are available. Internal clock: ∅/4, ∅/16, ∅/32, ∅/64 • An interrupt can be generated upon a counter value overflow or a match with compare register 0. (Compare match can be used only in an appropriate mode.) • The counter value can be initialized to '0000H' upon a reset, software clear, or match with compare register 0. The free-run timer can be used to generating reference timing signals for the input capture (ICU) and output compare (OCU). ❑ Output compare (×2) The output compare (OCU) consists of two 16-bit compare registers, compare output latch, and control register. An interrupt request can be generated for each channel upon a match detection by performing time-division comparison between the OCU compare data register setting value and the counter value of the 16-bit free-run timer. When the 16-bit free-run timer value matches the compare register value, the output level is reversed and an interrupt is issued. • The four compare registers can be used independently. Output pins and interrupt flags corresponding to compare registers • Output pins can be controlled based on pairs of the four compare registers. Output pins can be reversed by using the four compare registers. • Initial values for output pins can be set. • Interrupts can be generated upon a compare match. 20.1 Outline ❑ Input capture (×4) The input capture (ICU) generates an interrupt request to the CPU simultaneously with a storing operation of current counter value of the 16-bit free-run timer to the ICU data register (IPCP) upon an input of a trigger edge to the external pin. There are four sets (four channels) of the input capture external pins and ICU data registers (ICDR), enabling measurements of maximum of four events. • The input capture has four sets of external pins (IN0 to IN3) and ICU registers (IPCP0~3), enabling measurements of maximum of four events. • A trigger edge direction can be selected from rising/falling/both edges. • The input capture can be set to generate an interrupt request at the storage timing of the counter value of the 16-bit free-run counter to the ICU data register (IPCP). • The input compare conforms to the extended intelligent I/O service (EI2OS). • The input capture function is suited for measurements of intervals (frequencies) and pulse-widths. A reset clears the timer counter value for the 16-bit free-run timer to all zeroes. 270 Chapter 20: 16-Bit I/O Timer MB90580 Series 20.2 Block Diagram 20.2 Block Diagram 20.2.1 Overall Block Diagram of 16-bit I/O Timer Control logic Interrupt To each block 16-bit free-run timer F2MC-16LX BUS 16-bit timer Clear Output compare 0 Compare register 0 T Q OUT0 Compare register 1 T Q OUT1 Output compare 1 Input capture 0 Capture register 0 Edge selection IN0 Capture register 1 Edge selection IN1 Capture register 2 Edge selection IN2 Edge selection IN3 Input capture 1 Input capture 3 Input capture 4 Capture register 3 Figure 20.2.1a Overall Block diagram of 16-bit I/O Timer MB90580 Series Chapter 20: 16-Bit I/O Timer 271 20.2 Block Diagram 20.2.2 Block Diagram of 16-bit free-run timer F2MC-16LX BUS Interrupt request IVF IVFE STOP MODE CLR CLK1 CLK0 Divider Comparator 0 16-bit up counter Clock Count value output T15 to T00 Figure 20.2.2a Block diagram of 16-bit free-run timer 20.2.3 Block Diagram of Output Comparison 16-bit timer counter value (T15 to T00) T Compare control Q OTE0 OUT0 OTE1 OUT1 F2MC-16LX BUS Compare register 0 CMOD 16-bit timer counter value (T15 to T00) T Compare control Q Compare register 1 ICP1 ICP0 ICE1 ICE0 Controller Compare 1 interrupt Compare 0 interrupt Control blocks Figure 20.2.3a Block diagram of Output Comparison 272 Chapter 20: 16-Bit I/O Timer MB90580 Series 20.2 Block Diagram 20.2.4 Block Diagram of Input Capture F2MC-16LX BUS IN0 (IN2) Edge detection Capture data register 0 EG11 EG10 EG01 EG00 16-bit timer counter value (T15 to T00) Edge detection Capture data register 1 ICP1 ICP0 ICE1 IN1 (IN3) ICE0 Interrupt 1 (3) Interrupt 0 (2) Figure 20.2.4a Block diagram of Input Capture MB90580 Series Chapter 20: 16-Bit I/O Timer 273 20.3 Registers and Register Details 20.3 Registers and Register Details 20.3.1 16-bit free-run timer 16-bit Timer Data Register (Upper) Address: 00006DH Read/write Initial value 15 14 13 12 11 10 9 T15 T14 T13 T12 T11 T10 T09 T08 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit Number 8 TCDTH 16-bit Timer Data Register (Lower) Address: 00006CH Read/write Initial value 7 6 5 4 3 2 1 T07 T06 T05 T04 R/W 0 R/W 0 R/W 0 R/W 0 0 T03 T02 T01 T00 R/W 0 R/W 0 R/W 0 R/W 0 Bit Number TCDTL 16-bit Timer Control Status Register bit 7 Address: 00006EH Reserved Read/write Initial value R/W 0 6 5 4 IVF IVFE STOP R/W 0 R/W 0 R/W 0 3 2 1 0 MODE CLR CLK1 CLK0 R/W 0 R/W 0 R/W 0 R/W 0 Bit Number TCCS Figure 20.3.1a Registers of 16-bit free-run timer 274 Chapter 20: 16-Bit I/O Timer MB90580 Series 20.3 Registers and Register Details 20.3.1.1 16-bit free-run timer data register 16-bit Timer Data Register (Upper) Address: 00006DH Read/write Initial value 15 14 13 12 11 10 9 T15 T14 T13 T12 T11 T10 T09 T08 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit Number 8 TCDTH 16-bit Timer Data Register (Lower) Address: 00006CH Read/write Initial value 7 6 5 4 3 2 1 T07 T06 T05 T04 R/W 0 R/W 0 R/W 0 R/W 0 0 T03 T02 T01 T00 R/W 0 R/W 0 R/W 0 R/W 0 Bit Number TCDTL The data register can read the count value of the 16-bit free-run timer. The counter value is cleared to ’0000’ upon a reset. The timer value can be set by writing a value to this register. However, ensure that the value is written while the operation is stopped (STOP=1). The data register must be accessed in word access mode. The 16-bit free-run timer is initialized upon the following factors: • Reset • Clear bit (CLR) of control status register • A match between compare register 0 and the timer counter value (This can be performed only in an appropriate mode.) MB90580 Series Chapter 20: 16-Bit I/O Timer 275 20.3 Registers and Register Details 20.3.1.2 16-bit free-run timer control status register 16-bit Timer Control Status Register 7 bit Address: 00006EH Reserved Read/write Initial value R/W 0 6 5 4 IVF IVFE STOP R/W 0 R/W 0 R/W 0 3 2 1 0 MODE CLR CLK1 CLK0 R/W 0 R/W 0 R/W 0 R/W 0 Bit Number TCCS [bit 7] Reserved bit Always write ’0’ to this bit. [bit 6] IVF This bit is an interrupt request flag of the 16-bit free-run timer. If the 16-bit free-run timer overflows, or if the counter is cleared by a match with compare register 0 in a certain mode, ’1’ is written to this bit. An interrupt is issued if the interrupt request enable bit (bit 5: IVFE) is set. This bit is cleared by writing ’0.’ Writing ’1’ has no effect. ’1’ is always read by a read-modify-write instruction. 0 No interrupt request (default) 1 Interrupt request [bit 5] IVFE IVFE is an interrupt enable bit of the 16-bit free-run timer. While ’1’ is written to this bit, an interrupt is issued if ’1’ is written to the interrupt flag (bit 5: IVF). 0 Interrupt disabled (default) 1 Interrupt enabled [bit 4] STOP The STOP bit is used to stop the 16-bit free-run timer. Writing ’1’ to this bit stops the timer. Writing ’0’ starts the timer. 0 Counting enabled (operation) (default) 1 Counting disabled (stop) * The output compare operation stops when the 16-bit free-run timer stops. 276 Chapter 20: 16-Bit I/O Timer MB90580 Series 20.3 Registers and Register Details [bit 3] MODE The MODE bit is used to set the initialization condition of the 16-bit free-run timer. When ’0’ is set, the counter value can be initialized by a reset or a clear bit (bit 2: CLR). When ’1’ is set, the counter value can be initialized by a match with compare register 0 in addition to a reset and a clear bit (bit 2: CLR). 0 Initialization by reset or clear bit (default) 1 Initialization by reset, clear bit, or compare register 0 * The counter value is initialized where the count value is changed. [bit 2] CLR The CLR bit initializes the operating 16-bit free-run timer value to ’0000.’ When ’1’ is set, the counter value is initialized to ’0000.’ Writing ’0’ has no effect. ’0’ is always read from this bit. The counter value is initialized where the count value changes. 0 No effect (default) 1 The counter value is initialized to ’0000. * To initialize the counter value while the timer is stopped, write ’0000’ to the data register. [bits 1 and 0] CLK1 and CLK0 CLK1 and CLK0 are used to select the count clock for the 16-bit free-run timer. The clock is updated immediately after a value is written to these bits. Therefore, ensure that the output compare and input capture operations are stopped before a value is written to these bits. CLK1 CLK0 Count clock ∅=16 MHz ∅=8 MHz ∅=4 MHz ∅=1 MHz 0 0 ∅/4 0.25 µs 0.5 µs 1 µs 4 µs 0 1 ∅/16 1 µs 2 µs 4 µs 16 µs 1 0 ∅/64 4 µs 8 µs 16 µs 64 µs 1 1 ∅/256 16 µs 32 µs 64 µs 256 µs * ∅ = Machine clock MB90580 Series Chapter 20: 16-Bit I/O Timer 277 20.3 Registers and Register Details 20.3.2 Output comparison The output compare module consists of 16-bit compare registers, compare output pins, and control register. If the value written to the compare register of this module matches the 16-bit free-run timer value, the output level of the pin can be reversed and an interrupt can be issued. • Two compare registers exist that can be used independently. Depending on the setting, the two compare registers can be used to control pin outputs. • The initial value for the pin output can be specified. • An interrupt can be issued upon a match as a result of comparison. Output Compare Register 0, 1 Address: 00005BH 00005DH Read/write Initial value 14 13 12 11 10 C15 C14 C13 C12 C11 C10 C09 C08 R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X 7 6 5 4 3 2 1 C07 C06 C05 C04 C03 C02 C01 C00 R/W X R/W X R/W X R/W X R/W X R/W X R/W X Address: 00005AH 00005CH Read/write Initial value R/W X 9 Bit Number OCCP0 (Upper) OCCP1 (Upper) 15 8 Bit Number 0 OCCP0 (Lower) OCCP1 (Lower) Output Compare Control Status Register 0, 1 15 14 13 Address: 00005FH Read/write Initial value Address: 00005EH Read/write Initial value 12 11 10 9 8 CMOD OTE1 OTE0 OTD1 OTD0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 2 1 4 3 Bit Number OCS1 7 6 5 0 ICP1 ICP0 ICE1 ICE0 CST1 CST0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit Number OCS0 Figure 20.3.2a Registers of output comparsion 278 Chapter 20: 16-Bit I/O Timer MB90580 Series 20.3 Registers and Register Details 20.3.2.1 Compare register Output Compare Register 0, 1 Address: 00005BH 00005DH Read/write Initial value 14 13 12 11 10 C15 C14 C13 C12 C11 C10 C09 C08 R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X 7 6 5 4 3 2 1 C07 C06 C05 C04 C03 C02 C01 C00 R/W X R/W X R/W X R/W X R/W X R/W X R/W X Address: 00005AH 00005CH Read/write Initial value R/W X 9 8 Bit Number OCCP0 (Upper) OCCP1 (Upper) 15 0 Bit Number OCCP0 (Lower) OCCP1 (Lower) This 16-bit compare register is compared with the 16-bit free-run timer. Since the initial register value is undefined, set a value before enabling the register. This register must be accessed in word mode. When the value of this register matches that of the 16-bit free-run timer, a compare signal is generated and the output compare interrupt flag is set. If output is enabled, the output level corresponding to the compare register is reversed. MB90580 Series Chapter 20: 16-Bit I/O Timer 279 20.3 Registers and Register Details 20.3.2.2 Control status register Output Compare Control Status Register 0, 1 15 14 13 Address: 00005FH Read/write Initial value 11 10 9 8 CMOD OTE1 OTE0 OTD1 OTD0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 2 1 4 3 Bit Number OCS1 7 6 5 ICP1 ICP0 ICE1 ICE0 CST1 CST0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Address: 00005EH Read/write Initial value 12 0 Bit Number OCS0 [bits 15, 14, and 13] Unused bits [bit 12] CMOD CMOD is used to switch the pin output level reverse mode upon a match while pin output is enabled (OTE1=1 or OTE0=1). • When CMOD=0 (default), the output level of the pin corresponding to the compare register is reversed. • OUT0: The level is reversed upon a match with compare register 0. OUT1: The level is reversed upon a match with compare register 1. When CMOD=1, the output level is reversed for compare register 0 in the same manner as for CMOD=0. The output level of the pin corresponding to compare register 1 (OUT1), however, is reversed upon a match with compare register 0 or 1. If compare registers 0 and 1 have the same value, the same operation as with a single compare register is performed. OUT0: The level is reversed upon a match with compare register 0. OUT1: The level is reversed upon a match with compare register 0 or 1. [bits 11 and 10] OTE1 and OTE0 These bits are used to enable output compare pin output. The initial value for these bits is '0.' 0 General-purpose port (default) 1 Output compare pin output * OTE1: Corresponds to output compare 1/3 OTE0: Corresponds to output compare 0/2 * OUT0/1 are multiplexed with P94/TOUT1 and P95/TOUT2 respectively. Whne both output capture and reload timer output are enabled. OUT0/OUT1 get the higher priority. [bits 9 and 8] OTD1 and OTD0 These bits are used to change the pin output level when the output compare pin output is enabled. The initial value of the compare pin output is '0.' Ensure that the compare operation is stopped before a value is written. When read, these bits indicate the output compare pin output value. 0 Sets '0' for the compare pin output. (default) 1 Sets '1' for the compare pin output. * OTD1: Corresponds to output compare 1/3 OTD0: Corresponds to output compare 0/2 280 Chapter 20: 16-Bit I/O Timer MB90580 Series 20.3 Registers and Register Details [bits 7 and 6] ICP1 and ICP0 These bits are used as output compare interrupt flags. ’1’ is written to these bits when the compare register value matches the 16-bit free-run timer value. While the interrupt request bits (ICE1 and ICE0) are enabled, an output compare interrupt occurs when the ICP1 and ICP0 bits are set. These bits are cleared by writing ’0.’ Writing ’1’ has no effect. ’1’ is always read by a read-modify-write instruction. 0 No compare match (default) 1 Compare match * ICP1: Corresponds to output compare 1/3 ICP0: Corresponds to output compare 0/2 [bits 5 and 4] ICE1 and ICE0 These bits are used as output compare interrupt enable flags. While the ’1’ is written to these bits, an output compare interrupt occurs when an interrupt flag (ICP1 or ICP0) is set. 0 Output compare interrupt disabled (default) 1 Output compare interrupt enabled * ICE1: Corresponds to output compare 1/3 ICE0: Corresponds to output compare 0/2 [bits 3 and 2] Unused bits [bits 1 and 0] CST1 and CST0 The*se bits are used to enable the comparison with 16-bit free-run timer. 0 Compare operation disabled (default) 1 Compare operation enabled Ensure that a value is written to the compare register before the compare operation is enabled. * CST1: Corresponds to output compare 1/3 CST0: Corresponds to output compare 0/2 Note: Since output compare is synchronized with the 16-bit free-run timer clock, stopping the 16-bit free-run timer stops compare operation. MB90580 Series Chapter 20: 16-Bit I/O Timer 281 20.3 Registers and Register Details 20.3.3 Input capture This module detects a rising or falling edge or both edges of an externally input signal and stores the 16-bit free-run timer value in a register. In addition, this module can generate an interrupt upon detection of an edge. The input capture module consists of an input capture data register and a control register. Each input capture has a corresponding external input pin. • The detection edge of an external input can be selected from three types. • Rising edge, falling edge, or both edges • An interrupt can be generated upon detection of a valid edge of an external input. Input Capture Data Register 0, 1, 2, 3 Address: 000061H 15 000063H 000065H 000067H CP15 Read/write Initial value R X Address: 000060H 000062H 000064H 000066H Read/write Initial value 14 13 12 11 10 9 8 Bit Number CP14 CP13 CP12 CP12 CP11 CP09 CP08 R X R X R X R X R X R X R X 5 4 3 7 6 2 1 IPCP0 (Upper) IPCP1 (Upper) IPCP2 (Upper) IPCP3 (Upper) 0 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 R X R X R X R X R X R X R X R X 1 0 Bit Number IPCP0 (Lower) IPCP1 (Lower) IPCP2 (Lower) IPCP3 (Lowerr) Input Capture Control Status Register ch0,1 & Ch2,3 7 Address: 000068H 00006AH Read/write Initial value 6 5 4 3 2 ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit Number ICS01 ICS23 Figure 20.3.3a Register of input capture 282 Chapter 20: 16-Bit I/O Timer MB90580 Series 20.3 Registers and Register Details 20.3.3.1 Input capture data register Input Capture Data Register 0, 1, 2, 3 Address: 000061H 15 000063H 000065H 000067H CP15 Read/write Initial value R X Address: 000060H 000062H 000064H 000066H Read/write Initial value 14 13 12 11 10 9 8 Bit Number CP14 CP13 CP12 CP12 CP11 CP09 CP08 R X R X R X R X R X R X R X 5 4 3 7 6 2 1 IPCP0 (Upper) IPCP1 (Upper) IPCP2 (Upper) IPCP3 (Upper) 0 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 R X R X R X R X R X R X R X R X Bit Number IPCP0 (Lower) IPCP1 (Lower) IPCP2 (Lower) IPCP3 (Lowerr) This register stores the 16-bit timer value when a valid edge of the corresponding external pin input waveform is detected. (This register must be accessed in word mode. No value can be written to this register.) MB90580 Series Chapter 20: 16-Bit I/O Timer 283 20.3 Registers and Register Details 20.3.3.2 Control status register Input Capture Control Status Register ch0,1 & Ch2,3 7 Address: 000068H 00006AH Read/write Initial value 6 5 4 3 ICP1 ICP0 ICE1 ICE0 EG11 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 2 Bit Number 1 0 EG10 EG01 EG00 R/W 0 R/W 0 R/W 0 ICS01 ICS23 [bits 7 and 6] ICP1 and ICP0 These bits are used as input capture interrupt flags. ’1’ is written to this bit upon detection of a valid edge of an external input pin. While the interrupt enable bits (ICE0 and ICE1) are set, an interrupt can be generated upon detection of a valid edge. These bits are cleared by writing ’0.’ Writing ’0’ has no effect. ’1’ is always read by a read-modify-write instruction. 0 No valid edge detection (default) 1 Valid edge detection * ICP0: Corresponds to input capture 0. ICP1: Corresponds to input capture 1. [bits 5 and 4] ICE1 and ICE0 These bits are used to enable input capture interrupts. While ’1’ is written to these bits, an input capture interrupt is generated when the interrupt flag (ICP0 or ICP1) is set. 0 Interrupt disabled (default) 1 Interrupt enabled * ICE0: Corresponds to input capture 0. ICE1: Corresponds to input capture 1. [bits 3, 2, 1, and 0] EG11, EG10, EG01, and EG00 These bits are used to specify the valid edge polarity of an external input. These bits are also used to enable input capture operation. EG11 EG01 EG10 EG00 0 0 No edge detection (stop) 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both edge detection Edge detection polarity (default) *EG01 and EG00: Correspond to input capture 0. EG11 and EG10: Correspond to input capture 1. 284 Chapter 20: 16-Bit I/O Timer MB90580 Series 20.4 Operations 20.4 Operations 20.4.1 16-bit free-run timer The 16-bit free-run timer starts counting from counter value ’0000’ after the reset is released. The counter value is used as the reference time for the 16-bit output compare and 16-bit input capture operations. The counter value is cleared in the following conditions: • When an overflow occurs. • When a match with output compare register 0 occurs. (This depends on the mode.) • When '1' is written to the CLR bit of the TCCS register during operation. • When '0000' is written to the TCDC register during stop. • Reset An interrupt can be generated when an overflow occurs or when the counter is cleared due to a match with compare register 0. (Compare match interrupts can be used only in an appropriate mode.) ■ Clearing the counter by an overflow Counter value Overflow FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset Interrupt ■ Clearing the counter upon a match with output compare register 0 Counter value FFFFH BFFFH Match Match 7FFFH 3FFFH Time 0000H Reset Compare register value BFFFH Interrupt MB90580 Series Chapter 20: 16-Bit I/O Timer 285 20.4 Operations 20.4.2 16-bit output compare In 16-bit output compare operation, an interrupt request flag can be set and the output level can be reversed when the specified compare register value matches the 16-bit free-run timer value. ■ Sample output waveform when compare registers 0 and 1 are used (The initial output value is 0.) Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset Compare register 0 value Compare register 1 value BFFFH 7FFFH OUT0 OUT1 Compare 0 interrupt Compare 1 interrupt The output level can be changed using two compare registers (when CMOD=1). ■ Sample output waveform with two compare registers (The initial output value is ’0.’) Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset Compare register 0 value Compare register 1 value BFFFH 7FFFH OUT0 OUT1 Corresponds to compare 0 and 1 Compare 0 interrupt Compare 1 interrupt 286 Chapter 20: 16-Bit I/O Timer MB90580 Series 20.4 Operations 20.4.3 16-bit input capture In 16-bit input capture operation, an interrupt can be generated upon detection of a specified valid edge, fetching the 16-bit free-run timer value and writing it to the capture register. ■ Sample input capture fetch timing Capture 0: Rising edge Capture 1: Falling edge Capture example: Both edges Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset IN0 IN1 IN example Capture 0 Undefined Capture 1 Undefined Capture example Undefined 3FFFH 7FFFH BFFFH 7FFFH Capture 0 interrupt Capture 1 interrupt Capture interrupt MB90580 Series Chapter 20: 16-Bit I/O Timer 287 20.5 Timing 20.5 Timing 20.5.1 16-bit free-run timer count timing The 16-bit free-run timer is incremented based on the input clock (internal or external clock). When external clock is selected, the 16-bit free-run timer is incremented at the rising edge. ■ Free-run timer count timing External clock input Count clock N Counter value N+1 The counter can be cleared upon a reset, software clear, or a match with compare register 0. By a reset or software clear, the counter is immediately cleared. By a match with compare register 0, the counter is cleared in synchronization with the count timing. ■ Free-run timer clear timing (match with compare register 0) Compare register value N Compare match Counter value 288 Chapter 20: 16-Bit I/O Timer N 0000H MB90580 Series 20.5 Timing 20.5.2 Output compare timing In output compare operation, a compare match signal is generated when the free-run timer value matches the specified compare register value. The output value can be reversed and an interrupt can be issued. The output reverse timing upon a compare match is synchronized with the counter count timing. ■ Compare operation upon update of compare register When the compare register is updated, comparison with the counter value is not performed. Counter value N N+1 N+2 N+3 No match signal is generated. Compare register 0 value M N+1 Compare register 0 write Compare register 1 value N+3 M Compare register 1 write Compare 0 stop Compare 1 stop ■ Interrupt timing Counter value N N+1 Compare register value N Compare match Interrupt ■ Output pin change timing Counter value Compare register value N N+1 N N+1 N Compare match signal Pin output MB90580 Series Chapter 20: 16-Bit I/O Timer 289 20.5 Timing 20.5.3 Input capture input timing ■ Capture timing for input signals Counter value Input capture input N N+1 Valid edge Capture signal Capture register N+1 Interrupt 290 Chapter 20: 16-Bit I/O Timer MB90580 Series Chapter 21: ROM Correction Module 21.1 Outline When the setting of the address is the same as the ROM Correction Address register, the INT9 instruction will be executed. By processing the INT9 interrupt service routine, the ROM correction function can be achieved. There are two address registers, in each containing compare enable bit. When the address register and the program counter are in agreement, and when the compare enable bit is at ‘ 1’, then the CPU will be forced to execute INT9 instruction. 21.2 Block Diagram address latch F2MC-16LX BUS comparitor INT9 command ROM Correction Address Register F2 MC-16 LX enable bit CPU core Figure 21.2a Block Diagram of ROM Correction Module 21.3 Registers and Register Details 21.3 Registers and Register Details Program Address Detect Register 0/1 byte byte byte access initial value PADR0 1FF2H/1FF1H/1FF0H R/W undefined PADR1 1FF5H/1FF4H/1FF3H R/W undefined Program Address Detect Control Status Register 7 6 5 4 3 2 1 0 Address : 009EH — — — — AD1E — AD0E — Read/write Initial value (–) (–) (–) (–) (–) (0) (–) (0) (R/W) (0) (–) (0) (R/W) (0) (–) (0) Bit number PACSR Figure 21.3a Registers of ROM Correction Module 21.3.1 Program Address Detect Register 0/1 (PADR0/PADR1) These registers hold the addresses for the comparison with program counter. If there is an agreement and when the corresponding ADCSR interrupt enable bit is at ‘ 1’, this module demands the CPU to execute the INT9 instruction. If the corresponding interrupt enalble bit is ‘ 0’, nothing will occur even there is a match. Program Address Detect Register 0/1 byte byte byte access initial value PADR0 1FF2H/1FF1H/1FF0H R/W undefined PADR1 1FF5H/1FF4H/1FF3H R/W undefined The correspondance to the PACSR will be as follows. ROM correction register PADR0 PADR1 292 Chapter 21: ROM Correction Module Compare enable bit AD0E AD1E MB90580 Series 21.3 Registers and Register Details 21.3.2 Program Address detect Control Status Register (PACSR) Program Address Detect Control Status Register 7 6 5 4 3 2 1 0 Address : 009EH — — — — AD1E — AD0E — Read/write Initial value (–) (–) (–) (–) (–) (0) (–) (0) (R/W) (0) (–) (0) (R/W) (0) (–) (0) Bit number PACSR This register provides control bits and status bit for the ROM correction function. [bit 5~4] These are the reserved bits, be sure to write ‘ 0’. [bit 3]: AD1E (Compare Enable 1) This is the ADR1 enable bit. When this bit is at ‘ 1’, this module compares the PADR1 register and the program counter. If there is an agreement, the INT9 instruction is sent to the CPU. [bit 2]: This is a reserved bit. [bit 1]: AD0E (Compare Enable 0) This is the ADR0 enable bit. When this bit is at ‘ 1’, this module compares the PADR0 register and the program counter. If there is an agreement, the INT9 instruction is sent to the CPU. [bit 0]: This is a reserved bit. MB90580 Series Chapter 21: ROM Correction Module 293 21.4 Operations 21.4 Operations When the program counter indicates the same address as the ROM Correction Address register, the INT9 instruction will be executed. By processing the INT9 interrupt service routine, the ROM correction function can be achieved. There are two address registers, in each containing a compare enable bit. When the address register and the program counter are in agreement, and when the compare enable bit is at ‘ 1’ , then the CPU will be forced to execute INT9 instructions. Note: When the address detection register and the program counter are in agreement, the internal data bus content will be forced to be ‘ 01H’, so interrupt INT9 will be executed. Before changing the content of the address detect register, make sure the compare enable bit is at ‘ 0’. If it is changed while the compare enable bit is at ‘ 1’, there will occur an error. 294 Chapter 21: ROM Correction Module MB90580 Series 21.5 Application Example 21.5 Application Example (1) System Structure EPROM MCU F2MC16-LX pull up resistor connector (UART) SIN Figure 21.5a System Structure Example (2) EPROM memory map address:content 0000H:number of bytes of the corrected program No. 0 (0 implies no ROM correction) 0001H:bit 7-0 program address No. 0 0002H:bit 15-8 program address No. 0 0003H:bit 24-16 program address No. 0 0004H:number of bytes of the corrected program No. 0 (0 implies no ROM correction) 0005H:bit 7-0 program address No. 1 0006H:bit 15-8 program address No. 1 0007H:bit 24-16 program address No. 1 0010H~: corrected program No. 0/1 body (3) Initial Condition EPROM all at ‘ 0’. (4) When ROM Correction is Needed Send the body of the corrected program and the program address to the MCU through the connector (UART). MCU will write that information into the EEPROM. (5) Reset Sequence After resetting, the MCU reads the content of the EEPROM. If the byte number of the corrected program is not ‘ 0’, the body of the corrected program will be read from the EEPROM and written in the RAM. Then the MCU sets the correction address either on PADR0 or on PADR1 and sets the compare enable bit. First address of the corrected program can be written in the user-defined location of the RAM if a relocatable correction program is desired. In this case INT9 service routine looks for this user-defined location to jump to the corrected program. MB90580 Series Chapter 21: ROM Correction Module 295 21.5 Application Example (6) INT9 interrupt In the interrupt routine, the address that produces the interrupt can be known by checking the stack program couter value. The information stacked during interrupt will be discarded. MB90580 FFFFFFh (3) Erroneous Program (1) PC= Trigger Address ROM External E2PROM O Number of program byte Register setting for ROM Correction O Interrupt Trigger Address O Corrected Program Data sent via UART RAM Corrected Program (2) 000000h Figure 21.5b ROM Correction Processing Example 296 Chapter 21: ROM Correction Module MB90580 Series 21.5 Application Example Reset YES Read the 00h of E2PROM INT9 0000h (E2PROM)=0 NO Read the Address 0001h~0003h (E2PROM) MOV PADR0 (MCU) To Corrected Program JMP 000400h Read the Corrected Program 0010h~0090h (E2PROM) MOV 000400h~000480h (MCU) Corrected Program Execution 000400h~000480h End of Corrected Program JMP FF0050h Enable compare MOV PACSR, #02h Normal Program Execution PC=PADR0 NO FFFFFFH YES FF0050H INT9 E2 PROM ROM Erroneous Program FF0000H FFFFH FE0000H 0090H Corrected Program 0010H 001100H Stack Area Lower Program Address: 00 RAM Area 0003H Middle Program Address: 00 0002H Upper Program Address: FF 0001H 0000H Size of Corrected Program in Byte: 80 RAM 000480H Corrected Program 000400H RAM/Register Area 000100H I/O Area 000000H Figure 21.5c ROM Correction Processing Flow Diagram MB90580 Series Chapter 21: ROM Correction Module 297 Chapter 22: ROM Mirroring Module 22.1 Outline In ROM Mirroring Module the FF bank of the ROM can be seen through the 00 bank when chosen during register setting. 22.2 Block Diagram F2MC-16LX BUS ROM Mirrroring Register Address Area FF bank 00 bank ROM Figure 22.2a Block Diagram of ROM Mirroring Module 22.3 Registers and Register Details 22.3 Registers and Register Details ROM Mirror Function Select Register Address : 0006FH Read/write Initial value 15 14 13 12 11 10 9 8 Bit number — — — — — — — MI ROMM (–) (–) (–) (–) (–) (–) (–) (–) (–) (–) (–) (–) (–) (W) (1) (–) Figure 22.3a Register of ROM Mirroring Module 22.3.1 ROM Mirror Function Select Register ROM Mirror Function Select Register Address : 0006FH Read/write Initial value 15 14 13 12 11 10 9 8 Bit number — — — — — — — MI ROMM (–) (–) (–) (–) (–) (–) (–) (–) (–) (–) (–) (–) (–) (W) (1) (–) Note: Do not access this register when the addresses 004000H~00FFFFH is being accessed. [bit 8] : MI The ROM data in the FF bank can also be found in the 00 bank when ‘ 1’ is written to this bit. However, such as memory mapping will not be done when this bit is written to ‘ 0’. This bit is write only. The memory during single chip mode and during internal ROM external bus mode will be as shown below. Note: Only FF4000~FFFFFF is mirrorred to 004000~00FFFF when ROM mirroring functing is activated. Therefore, addresses FFF000~FF3FFF will not be mirrorred to 00 bank. 300 MB90583 MB90F583 MB90V580 Address 1 FE0000H FE0000H FE0000H Address 2 001900H 001900H 001900H Chapter 22: ROM Mirroring Module MB90580 Series 22.3 Registers and Register Details ADDRESS FFFFFFH Address 1 ROM Area ROM Area 010000H ROM Area 004000H 002000H Address 2 RAM Area RAM Area IO Area IO Area 000100H 0000C0H 000000H When MI= ‘ 1’ Internal Area When MI= ‘ 0’ Figure 22.3b Memory in Single Chip Mode ADDRESS FFFFFFH ROM Area ROM Area Address 1 010000H ROM Area 004000H 002000H Address 2 RAM Area RAM Area IO Area IO Area 000100H 0000C0H 000000H When MI= ‘ 1’ Internal Area External Bus Area When MI= ‘ 0’ Figure 22.3c Memory in Internal ROM External Bus Mode MB90580 Series Chapter 22: ROM Mirroring Module 301 Appendix A: I/O Map A.1 I/O Map Table A.1a lists the addresses assigned to the registers of each microcontroller resource Table A.1a I/O map Address Abbreviation Access Resource Initial value 00 H 01 H Port 0 data register PDR0 R/W Port 0 XXXXXXXX Port 1 data register PDR1 R/W Port 1 XXXXXXXX 02 H 03 H Port 2 data register PDR2 R/W Port 2 XXXXXXXX Port 3 data register PDR3 R/W Port 3 XXXXXXXX 04 H 05 H Port 4 data register PDR4 R/W Port 4 XXXXXXXX Port 5 data register PDR5 R/W Port 5 XXXXXXXX 06 H 07 H Port 6 data register PDR6 R/W Port 6 --XXXXXX Port 7 data register PDR7 R/W Port 7 ---XXXX- 08 H 09 H Port 8 data register PDR8 R/W Port 8 XXXXXXXX Port 9 data register PDR9 R/W Port 9 XXXXXXXX 0A H Port A data register PDRA R/W Port A -----XXX 0B to 0F H 10 H Register Reserved area Port 0 direction register DDR0 R/W Port 0 00000000 11 H 12 H Port 1 direction register DDR1 R/W Port 1 00000000 Port 2 direction register DDR2 R/W Port 2 00000000 13 H 14 H Port 3 direction register DDR3 R/W Port 3 00000000 Port 4 direction register DDR4 R/W Port 4 00000000 15 H 16 H Port 5 direction register DDR5 R/W Port 5 00000000 Port 6 direction register DDR6 R/W Port 6 --000000 17 H 18 H Port 7 direction register DDR7 R/W Port 7 ---0000- Port 8 direction register DDR8 R/W Port 8 00000000 00000000 19 H Port 9 direction register DDR9 R/W Port 9 1A H 1B H Port A direction register DDRA R/W Port A -----000 Port 4 pin register ODR4 R/W Port 4 00000000 1C H Analog input enable register ADER R/W Port 5, A/D 11111111 1D to 1F H 20 H Serial mode register 0 SMR0 R/W 00000000 21 H Serial control register 0 SCR0 R/W 00000100 22 H Serial input register/serial output register 0 SIDR/ SODR0 R/W 23 H 24 H Serial status register 0 SSR0 R/W 00001-00 Serial mode register 1 SMR1 R/W 00000000 25 H Serial control register 1 SCR1 R/W 26 H Serial input register/serial output register 1 27 H 28 H Reserved area UART0 XXXXXXXX 00000100 UART1 SIDR/ SODR1 R/W Serial status register 1 SSR1 R/W 00001-00 Serial mode register 2 SMR2 R/W 00000000 29 H Serial control register 2 SCR2 R/W 2A H Serial input register/serial output register 2 2B H Serial status register 2 SIDR/ SODR2 R/W SSR2 R/W XXXXXXXX 00000100 UART2 XXXXXXXX 00001-00 A.1 I/O Map Table A.1a I/O map (Continued) Address Abbreviation Access Resource Initial value CDCR0 R/W Communication prescaler 0 0---1111 Communication prescaler 1 0---1111 Clock division control register 0 2E H 2F H Clock division control register 1 30 H 31 H Interrupt /DTP enable register ENIR R/W 00000000 Interrupt/DTP cause register EIRR R/W XXXXXXXX Request level setting register ELVR R/W CDCR2 R/W 32 H 33 H 34 H 35 H 36 H 37 H 38 H 39 H Reserved area CDCR1 R/W Reserved area Clock division control register 2 DTP/external interrupt 00000000 00000000 Communication prescaler 2 0---1111 Reserved area Control status register Data register ADCS1 ADCS2 ADCR1 ADCR2 00000000 R/W A/D converter R 00000000 XXXXXXXX 00001--XX 3A H 3B H D/A converter data register 0 DAT0 R/W D/A converter data register 1 DAT1 R/W 3C H 3D H D/A control register 0 DACR0 R/W D/A control register 1 DACR1 R/W 3E H 3F H Clock output enable register CLKR R/W 40 H 41 H Reload register L (ch.0) PRLL0 R/W XXXXXXXX Reload register H (ch.0) PRLH0 R/W XXXXXXXX 42 H 43 H Reload register L (ch.1) PRLL1 R/W Reload register H (ch.1) PRLH1 R/W 44 H 45 H PPG0 operation mode control register PPGC0 R/W 0X000XX1 PPG1 operation mode control register PPGC1 R/W 0X000001 46 H 47 H PPG0 and PPG1 output control register PPGOE R/W 00000000 D/A converter XXXXXXXX -------0 -------0 Clock monitor function - - - - 0000 XXXXXXXX 8-/16-bit PPG XXXXXXXX Reserved area Control status register 0 TMCSR0 4A H 4B H 16-bit timer register 0 / 16-bt reload register 0 TMR0 / TMRLR0 R/W 4C H 4D H Control status register 1 TMCSR1 R/W 4E H 4F H 16-bit timer register 1 / 16-bt reload register 1 TMR1 / TMRLR1 R/W 50 H 51 H Control status register 2 TMCSR2 R/W 52 H 53 H 16-bit timer register 2 / 16-bt reload register 2 TMR2 / TMRLR2 R/W 54 H 55 H PWC control status register PWCSR R/W 58 H 59 H XXXXXXXX Reserved area 48 H 49 H 56 H 57 H 304 Register 2C H 2D H PWC data buffer register Divide ratio control register Appendix A: I/O Map 00000000 R/W 16-bit reload timer 0 00000000 DIVR R/W ---- 0000 XXXXXXXX XXXXXXXX 00000000 16-bit reload timer 2 R/W XXXXXXXX XXXXXXXX 16-bit reload timer 1 PWCR ---- 0000 ---- 0000 XXXXXXXX XXXXXXXX 00000000 00000000 16-bit PWC timer XXXXXXXX XXXXXXXX ------00 Reserved area MB90580 Series A.1 I/O Map Table A.1a I/O map (Continued) Address Register Abbreviation Access Output Compare Register 0 OCCP0 R/W Output Compare Register 1 OCCP1 R/W 5E H Output Compare Control Status Register 0 OCS0 R/W 0000--00 5F H Output Compare Control Status Register 1 OCS1 R/W ---00000 Input Capture Register 0 IPCP0 Input Capture Register 1 IPCP1 5A H 5B H 5C H 5D H 60 H 61 H 62 H 63 H 64 H Input Capture Register 2 65 H 66 H IPCP2 Resource Initial value XXXXXXXX XXXXXXXX Output Compare (Channel 0 To 1) XXXXXXXX XXXXXXXX R XXXXXXXX R XXXXXXXX R XXXXXXXX R XXXXXXXX R R XXXXXXXX Input Capture (Channel 0 To 3) XXXXXXXX R XXXXXXXX R XXXXXXXX Input Capture Register 3 IPCP3 Input Capture Control Status Register Ch0,1 ICS01 R/W 00000000 Input Capture Control Status Register Ch2,3 ICS23 R/W 00000000 6C H 16-bit Timer Data Register (Low) TCDTL R/W 6D H 16-bit Timer Data Register (High) TCDTH R/W 67 H 68 H 69 H 6A H Reserved area 6B H Reserved area 00000000 Free Run Timer 00000000 6E H 16-bit Timer Control Status Register TCCS R/W 6F H 70 H Rom Mirror Function Select Register ROMM W Unit Address Register (Low) MAWL R/W XXXXXXXX 71 H Unit Address Register (High) MAWH R/W XXXXXXXX 72 H 73 H Slave Address Register (Low) SAWL R/W XXXXXXXX Slave Address Register (High) SAWH R/W XXXXXXXX 00000000 ROM mirroring Module ---- ---1 74 H Telegraph Length Set Register DEWR R/W 00000000 75 H 76 H Multiaddress, Control Bit Set Register DCWR R/W 00000000 Command Register (Low) CMRL R/W XX00000 77 H 78 H Command Register (High) CMRH R/W 000000XX Status Register (Low) STRL R 79 H 7A H Status Register (High) STRH R/W Lock Read Register (Low) LRRL R XXXXXXXX Lock Read Register (High) LRRH R XXX0XXXX 7B H 7C H IEBus Interface 0011XXXX 00000000 Master Address Read Register (Low) MARL R XXXXXXXX 7D H 7E H Master Address Read Register (High) MARH R XXXXXXXX Telegraph Length Read Register DERR R XXXXXXXX 7F H 80 H Multiaddress, Control Bit Read Register DCRR R 000XXXXX Write Data Buffer WDB R/W XXXXXXXX 81 H 82 H Read Data Buffer RDB R XXXXXXXX Serial mode register 3 SMR3 R/W 00000000 83 H Serial control register 3 SCR3 R/W 00000100 84 H Serial input register/serial output register 3 SIDR/ SODR3 R/W 85 H Serial status register 3 SSR3 R/W UART3 XXXXXXXX 00001-00 86H PWC Noise cancelling register RNCR R/W PWC noise filter ---- -000 87H Clock division control register 3 CDCR3 R/W Communication prescaler 3 0---1111 MB90580 Series Appendix A: I/O Map 305 A.1 I/O Map Table A.1a I/O map (Continued) Address Register Abbreviation 88H Serial mode register 4 Access Resource SMR4 R/W 00000000 89H Serial control register 4 SCR4 R/W 00000100 8AH Serial input register/serial output register 4 SIDR/ SODR4 R/W UART4 Initial value XXXXXXXX 8BH Serial status register 4 SSR4 R/W 8CH Port 0 resistor register RDR0 R/W Port 0 00000000 8DH Port 1 resistor register RDR1 R/W Port 1 00000000 8EH Port 6 resistor register RDR6 R/W Port 6 --000000 8FH Clock division control register 4 CDCR4 R/W Communication prescaler 4 0---1111 90H to 9DH 00001-00 Reserved area 9E H Program address detect control status register PACSR R/W ROM correction module --000000 9F H Delayed interrupt cause occurrence/ release register DIRR R/W Delayed interrupt occurrence module - - - - - - -0 A0 H Low-power mode register LPMCR R/W A1 H A2 H Clock selection register CKSCR R/W Low noise output select register (Lower) LNSRL R/W I/O port 00000000 A3 H A4 H Low noise output select register (Upper) LNSRH R/W I/O port ----0000 A5 H A6 H Automatic read function selection register ARSR W External address output control register HACR W A7 H A8 H Bus control signal selection register ECSR W Watchdog control register WDTC R/W Watchdog timer A9 H AAH Time base timer control register TBTC R/W Time base timer 1- -00100 Watch timer control register WTC R/W Watch Timer 1X000000 Flash interface 000X0XX0 00011000 11111100 Reserved area ABH to ADH AEH Low power 0011- -00 External bus interface 0000000 0000000XXXXX111 Reserved area Flash control register FMCS AFH R/W Reserved area B0 H B1 H Interrupt control register 00 ICR00 R/W 00000111 Interrupt control register 01 ICR01 R/W 00000111 B2 H B3 H Interrupt control register 02 ICR02 R/W 00000111 Interrupt control register 03 ICR03 R/W 00000111 B4 H B5 H Interrupt control register 04 ICR04 R/W 00000111 Interrupt control register 05 ICR05 R/W 00000111 B6 H B7 H Interrupt control register 06 ICR06 R/W 00000111 Interrupt control register 07 ICR07 R/W B8 H B9 H Interrupt control register 08 ICR08 R/W Interrupt control register 09 ICR09 R/W 00000111 BA H BB H Interrupt control register 10 ICR10 R/W 00000111 Interrupt control register 11 ICR11 R/W 00000111 BC H BD H Interrupt control register 12 ICR12 R/W 00000111 Interrupt control register 13 ICR13 R/W 00000111 BE H BF H Interrupt control register 14 ICR14 R/W 00000111 Interrupt control register 15 ICR15 R/W 00000111 CO to FF Interrupt controller 00000111 00000111 External area — — — — 100H to #H RAM area — — — — #H to 1FEFH Reserved area — — — — H 306 Appendix A: I/O Map MB90580 Series A.1 I/O Map Table A.1a I/O map (Continued) Address Register 1FF0 H 1FF1 H Program address detection register 0 1FF02 H Program address detection register 2 1FF3 H 1FF4 H Program address detection register 3 1FF5 H 1FF6H to 1FFFH Program address detection register 5 Program address detection register 1 Program address detection register 4 MB90580 Series Reserved area Abbreviation PADR0 Access XXXXXXXX R/W XXXXXXXX R/W — Initial value R/W R/W PADR1 Resource Program patch manipulation XXXXXXXX XXXXXXXX R/W XXXXXXXX R/W XXXXXXXX — — — Appendix A: I/O Map 307 APPENDIX B: Instructions B.1 Addressing In the F2MC-16LX, the address format is determined by either the instruction’s effective address specification, or by the instruction code itself (implied addressing). B.1.1 Effective address field The address formats specified in the effective address field are shown in Table B.1.1a. Table B.1.1a Effective Address Field Code 00 01 02 03 04 05 06 07 Notation R0 R1 R2 R3 R4 R5 R6 R7 RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 Address format RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) 08 09 0A 0B @RW0 @RW1 @RW2 @RW3 0C 0D 0E 0F @RW0+ @RW1+ @RW2+ @RW3+ 10 11 12 13 @RW0+disp8 @RW1+disp8 @RW2+disp8 @RW3+disp8 14 15 16 17 @RW4+disp8 @RW5+disp8 @RW6+disp8 @RW7+disp8 18 19 1A 1B @RW0+disp16 @RW1+disp16 @RW2+disp16 @RW3+disp16 1C 1D 1E 1F @RW0+RW7 @RW1+RW7 @PC+disp16 addr16 Default bank Register direct Starting from the left, “ea” corresponds to the byte, word and long-word types. None Register indirect DTB DTB ADB SPB Register indirect with post-incrementing DTB DTB ADB SPB Register indirect with 8-bit displacement DTB DTB ADB SPB Register indirect with 8-bit displacement DTB DTB ADB SPB Register indirect with 16-bit displacement DTB DTB ADB SPB Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address DTB DTB PCB DTB B.1 Addressing B.1.2 Addressing Details (1) Immediate value (#imm) This format specifies the operand value directly. • #imm4 • #imm8 • #imm16 • #imm32 (2) Compressed direct address (dir) In this format, the operand specifies the low-order 8 bits of the memory address. Bits 8 to 15 of the address are specified by the DPR. Bits 16 to 23 of the address are indicated by the DTB. (3) Direct address (addr16) In this format, the operand specifies the low-order 16 bits of the memory address. Bits 16 to 23 of the address are indicated by the DTB. (4) Register direct This format specifies a direct register as the operand. General-purpose registers Byte: R0, R1, R2, R3, R4, R5, R6, R7 Word: RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 Long word: RL0, RL1, RL2, RL3 Dedicated registers Accumulator: A, AL Pointer: SP Bank: PCB, DTB, USB, SSB, ADB Page: DPR Control: PS, CCR, RP, ILM Note: Regarding the SP, either the USP or the SSP is selected and used, depending on the value of the S bit in the CCR. In addition, in a branching instruction, the PC is implicitly specified, and is not described in the instruction operand. 310 APPENDIX B: Instructions MB90580 Series B.1 Addressing (5) Register indirect (@RWj j = 0 to 3) This format accesses the memory address indicated by the contents of the general-purpose register RWj. When RW0/RW1 is used, bits 16 to 23 of the address are indicated by DTB; if RW3 is used, bits 16 to 23 of the address are indicated by SPB, and if RW2 is used, bits 16 to 23 of the address are indicated by ADB. (6) Register indirect with post-incrementing (@RWj+ j = 0 to 3) This format accesses the memory address indicated by the contents of the general-purpose register RWj. After the operand operation, RWj is incremented by the data length of the operand (by 1 for a byte, 2 for a word, and 4 for a long-word). When RW0/RW1 is used, bits 16 to 23 of the address are indicated by DTB; if RW3 is used, bits 16 to 23 of the address are indicated by SPB, and if RW2 is used, bits 16 to 23 of the address are indicated by ADB. Note that if the post-incremented result is the address of the register for which the increment specification was made, the value that is referenced subsequently is the incremented value. In addition, in such a case, if the instruction was a write instruction, the data written by the instruction is given priority, so the register that was to have been incremented contains the write data in the end. (7) Register indirect with displacement (@RWi + disp8 i= 0 to 7/@RWj + disp16 j = 0 to 3) This format accesses the memory address indicated by the sum of the contents of the general-purpose register RWj and the displacement value. The displacement value can be one of two types, either a byte or a word, and is added as a signed value. When RW0, RW1, RW4, or RW5 is used, bits 16 to 23 of the address are indicated by DTB; if RW3 or RW7 is used, bits 16 to 23 of the address are indicated by SPB, and if RW2 or RW6 is used, bits 16 to 23 of the address are indicated by ADB. (8) Register indirect with base index (@RW0 + RW7, @RW1 + RW7) This format accesses the memory address indicated by the sum of the contents of the general-purpose register and either RW0 or RW1. Bits 16 to 23 of the address are indicated by DTB. (9) Program counter indirect with displacement (@PC + disp16) This format accesses the memory address indicated by the sum of the “instruction address + 4 + disp16”. The displacement value is a word length value. Bits 16 to 23 of the address are indicated by PCB. The operand address is generally regarded as “the next instruction address + disp16”, but note that this does not hold true for the instructions indicated below: • DBNZ eam, rel • DWBNZ eam, rel • MOV eam, #imm8 • MOVW eam, #imm16 • CBNE eam, #imm8, rel • CWBNE eam, #imm16, rel MB90580 Series APPENDIX B: Instructions 311 B.1 Addressing (10) Accumulator indirect (@A) This format has two types: one in which the contents of AL specify bits 00 to 15 of the address and DTB indicates bits 16 to 23; and one in which the low-order 24 bits of A specify bits 00 to 23 of the address. (11) I/O direct (io) In this format, the memory address of the operand is specified directly by the 8-bit displacement value. Regardless of the value of DTB and DPR, the I/O space from 000000 H to 0000FFH is accessed. The access space specification prefix has no effect on this addressing format. (12) Long register indirect with displacement (@RLi + disp8 i = 0 to 3) This format accesses the memory address indicated by the low-order 24 bits of the sum of the contents of the general-purpose register RLi plus the displacement value. The displacement value is 8 bits, and is added as a signed numeral. (13) Compressed direct bit address (dir:bp) This format specifies the low-order 8 bits of the memory address with the operand. In addition, bits 8 to 15 of the address are indicated by DPR. Finally, bits 16 to 23 of the address are indicated by DTB. The bit position is indicated by “:bp”, with larger numbers being closer to the MSB and smaller numbers being closer to the LSB. (14) I/O direct bit address (io:bp) This format directly specifies a bit within a physical address from 000000H to 0000FFH. The bit position is indicated by “:bp”, with larger numbers being closer to the MSB and smaller numbers being closer to the LSB. (15) Direct bit address (addr16:bp) This format directly specifies any bit within a 64-kilobyte region. Bits 16 to 23 of the address are indicated by DTB. The bit position is indicated by “:bp”, with larger numbers being closer to the MSB and smaller numbers being closer to the LSB. (16) Register list (rlst) This format specifies the register that is the target of a stack push/pop instruction. MSB LSB RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0 A register is selected when the corresponding bit is “1”, and is not selected when the corresponding bit is “0”. Fig. B.1.2a Register List Configuration 312 APPENDIX B: Instructions MB90580 Series B.1 Addressing (17) Program counter relative branching address (rel) With this format, the address of the destination of a branching instruction is the sum of the value of the PC and the 8-bit displacement value. If the result exceeds 16 bits, the amount of the overflow is ignored and the bank register is not incremented or decremented; therefore, the address is kept within a 64-kilobyte bank. This format is used in unconditional and conditional branching instructions. Bits 16 to 23 of the address are indicated by PCB. (18) Direct branching address (addr16) With this format, the address of the destination of a branching instruction is specified directly by the displacement value. The displacement value is 16 bits, and indicates the branching destination within a logical memory space. This format is used in unconditional branching instructions and subroutine call instructions. Bits 16 to 23 of the address are indicated by PCB. (19) Physical direct branching address (addr24) With this format, the address of the destination of a branching instruction is specified directly by the displacement value. The displacement value is 24 bits, and specifies the physical address of the branching destination. This format is used in unconditional branching instructions, subroutine call instructions, and software interrupt instructions. (20) Accumulator indirect branching address (@A) In this format, the 16 bits of the accumulator AL specify the branching destination address. This address indicates a branching destination within a bank space; in this case, bits 16 to 23 of the address are indicated by the PCB. In the case of JCTX, however, bits 16 to 23 of the address are indicated by DTB. This format is used in unconditional branching instructions. (21) Vector address (#vct) The contents of the specified vector become the branching destination address. There are two data lengths for vector numbers: 4 bits and 8 bits. This format is used in subroutine call instructions and software interrupt instructions. (22) Indirect specification branching address (@ear) The word data in the address indicated by “ear” is the branching destination address. (23) Indirect specification branching address (@eam) The word data in the address indicated by “eam” is the branching destination address. MB90580 Series APPENDIX B: Instructions 313 B.2 Instruction Set B.2 Instruction Set Table B.2a Explanation of Items in Table of Instructions Item Mnemonic Explanation Upper-case letters and symbols: ....... Described as they appear in assembler. Lower-case letters: ............................. Replaced when described in assembler. Numbers after lower-case letters: ...... Indicate the bit width within the instruction. # Indicates the number of bytes. ~ Indicates the number of cycles. See Table 4.2.4 for details about meanings of letters in items. RG B Operation Indicates the register access count during execution of instruction. Used to calculate compensation values for CPU intermittent operation. Indicates the compensation value for calculating the number of actual cycles during execution of instruction. The number of actual cycles during execution of instruction is the compensation value summed with the value in the “~” column. Indicates operation of instruction. LH Indicates special operations involving bits 15 through 08 of the accumulator. Z:........ Transfers “0”. X:........ Sign-extended transfer through sign extension. -:......... Transfers nothing. AH Indicates special operations involving the high-order 16 bits in the accumulator. *:......... Transfers from AL to AH. -:......... No transfer. Z:........ Transfers 00 to AH. X:........ Transfers 00H or FFH to AH using sign extension AL. I S T N Z V Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). *:......... Changes due to execution of instruction. -:......... No change. S:........ Set by execution of instruction. R: ....... Reset by execution of instruction. C RMW 314 Indicates whether the instruction is a read-modify-write instruction (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.). *:......... Instruction is a read-modify-write instruction. -:......... Instruction is not a read-modify-write instruction. Note: A read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written. APPENDIX B: Instructions MB90580 Series B.2 Instruction Set • Number of execution cycles The number of cycles required for the execution of an instruction is obtained by summing the value shown in the table for the “number of cycles” for the instruction in question, the compensation value (which depends on certain conditions), and the “number of cycles” needed for the program fetch. When fetching a program in memory connected to the 16-bit bus, such as on-chip ROM, a program fetch is performed for each two-byte (word) boundary crossed by the instruction being executed; therefore, if there is any interference with data access, etc., the number of execution cycles increases. When fetching a program in memory connected to the 8-bit external data bus, a program fetch is performed for each byte of the instruction being executed; therefore, if there is any interference with data access, etc., the number of execution cycles increases. In CPU intermittent operation, each access to general-purpose registers, internal ROM, internal RAM, internal I/O functions or external bus causes the CPU clock to pause for a fixed number of cycles determined by the CG1/CG0 bits in the low power consumption mode control register. For this reason, the number of machine clock cycles required to execute an instruction under CPU intermittent operation is the normal number of cycles plus an offset number of cycles that is derived by multiplying the number of access operations by the length (in cycles) of the fixed pause. MB90580 Series APPENDIX B: Instructions 315 B.2 Instruction Set Table B.2b Explanation of Symbols in Table of Instructions Symbol 316 Explanation A 32-bit accumulator The bit length varies according to the instruction. Byte:............ Low-order 8 bits of AL Word: .......... 16 bits of AL Long: ........... 32 bits of AL:AH AH AL High-order 16 bits of A Low-order 16 bits of A SP Stack pointer (USP or SSP) PC Program counter PCB Program bank register DTB Data bank register ADB Additional data bank register SSB System stack bank register USB User stack bank register SPB Current stack bank register (SSB or USB) DPR Direct page register brg1 DTB, ADB, SSB, USB, DPR, PCB, SPB brg2 DTB, ADB, SSB, USB, DPR, SPB Ri R0, R1, R2, R3, R4, R5, R6, R7 RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RWj RW0, RW1, RW2, RW3 RLi RL0, RL1, RL2, RL3 dir addr16 addr24 ad24 0 to 15 ad24 16 to 23 Compact direct addressing Direct addressing Physical direct addressing Bits 0 to 15 of addr24 Bits 16 to 23 of addr24 io I/O area (000000H to 0000FFH) #imm4 #imm8 #imm16 #imm32 ext(imm8) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data disp8 disp16 8-bit displacement 16-bit displacement bp Bit offset value vct4 vct8 Vector number (0 to 15) Vector number (0 to 255) ( )b Bit address rel ear eam Branch specification relative to PC Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F) rlst Register list APPENDIX B: Instructions MB90580 Series B.2 Instruction Set Table B.2c Effective Address Fields Code 00 01 02 03 04 05 06 07 Notation R0 R1 R2 R3 R4 R5 R6 R7 RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Address format Number of bytes in address extension [Note] Register direct “ea” corresponds to byte, word, and longword types, starting from the left – 08 09 0A 0B @RW0 @RW1 @RW2 @RW3 Register indirect 0 0C 0D 0E 0F @RW0+ @RW1+ @RW2+ @RW3+ Register indirect with post-incrementing 0 10 11 12 13 14 15 16 17 @RW0+disp8 @RW1+disp8 @RW2+disp8 @RW3+disp8 @RW4+disp8 @RW5+disp8 @RW6+disp8 @RW7+disp8 Register indirect with 8-bit displacement 1 18 19 1A 1B @RW0+disp16 @RW1+disp16 @RW2+disp16 @RW3+disp16 Register indirect with 16-bit displacement 2 1C 1D 1E 1F @RW0+RW7 @RW1+RW7 @PC+disp16 addr16 Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address 0 0 2 2 Note: The number of bytes for address extension is indicated by the “+” symbol in the “#” (number of bytes) column in the Table of Instructions and by the number of bytes in the detailed instruction rules. MB90580 Series APPENDIX B: Instructions 317 B.2 Instruction Set Table B.2d Number of Execution Cycles for Each Form of Addressing (a) Number of execution Number of accesses for cycles for each form of each form of addressing addressing Code Operand 00 to 07 Ri RWi RLi Listed in Table of Instructions Listed in Table of Instructions 08 to 0B @RWj 2 1 0C to 0F @RWj+ 4 2 10 to 17 @RWi+disp8 2 1 18 to 1B @RWj+disp16 2 1 1C 1D 1E 1F @RW0+RW7 @RW1+RW7 @PC+disp16 addr16 4 4 2 1 2 2 0 0 Note: “(a)” is used in the “~” (number of cycles) column, column B (compensation value) and in the detailed instruction rules in the Table of Instructions. Table B.2e Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles (b) byte Operand (c) word Cycles Access cycles Internal register +0 Internal RAM even address Internal RAM odd address (d) long Cycles Access cycles Cycles Access cycles 1 +0 1 +0 2 +0 +0 1 1 +0 +2 1 2 +0 +4 2 4 Even address on external data bus (16 bits) Odd address on external data bus (16 bits) +1 +1 1 1 +1 +4 1 2 +2 +8 2 4 External data bus (8 bits) +1 1 +4 2 +8 4 Note: “(b)”, “(c)”, and “(d)” are used in the “~” (number of cycles) column, column B (compensation value) and in the detailed instruction rules in the Table of Instructions. When the external data bus is used, it is necessary to add in the number of weighted cycles used for ready input and automatic ready. 318 APPENDIX B: Instructions MB90580 Series B.2 Instruction Set Table B.2f Compensation Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles Instruction Byte boundary Word boundary Internal memory – +2 External data bus (16 bits) – +3 External data bus (8 bits) +3 – Note: When the external data bus is used, it is necessary to add in the number of weighted cycles used for ready input and automatic ready. Because instruction execution is not slowed down by all program fetches in actuality, these compensation values should be used for “worst case” calculations. MB90580 Series APPENDIX B: Instructions 319 B.2 Instruction Set B.2.1 F2MC-16LX Instruction Set (351 Instructions) Table B.2.1a Transfer Instructions (Byte) (41 Instructions) Mnemonic # RG B Operation LH AH I S T N Z V C RMW MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN A,dir A,addr16 A,Ri A,ear A,eam A,io A,#imm8 A,@A A,@RLi+disp8 A,#imm4 2 3 3 4 1 2 2 2 2+ 3+(a) 2 3 2 2 2 3 3 10 1 1 0 0 1 1 0 0 0 0 2 0 (b) (b) 0 0 (b) (b) 0 (b) (b) 0 byte (A) ← (dir) byte (A) ← (addr16) byte (A) ← (Ri) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← (io) byte (A) ← (imm8) byte (A) ← ((A)) byte (A) ← ((RLi)+disp8) byte (A) ← imm4 Z Z Z Z Z Z Z Z Z Z ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ R ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ - - - MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX A,dir A,addr16 A,Ri A,ear A,eam A,io A,#imm8 A,@A A,@RWi+disp8 A,@RLi+disp8 2 3 3 4 2 2 2 2 2+ 3+(a) 2 3 2 2 2 3 2 5 3 10 0 0 1 1 0 0 0 0 1 2 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) byte (A) ← (dir) byte (A) ← (addr16) byte (A) ← (Ri) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← (io) byte (A) ← (imm8) byte (A) ← ((A)) byte (A) ← ((RWi)+disp8) byte (A) ← ((RLi)+disp8) X X X X X X X X X X ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ - - - MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV dir,A addr16,A Ri,A ear,A eam,A io,A @RLi+disp8,A Ri,ear Ri,eam ear,Ri eam,Ri Ri,#imm8 io,#imm8 dir,#imm8 ear,#imm8 eam,#imm8 @AL,AH / MOV @A,T 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 3 4 2 2 3+(a) 3 10 3 4+(a) 4 5+(a) 2 5 5 2 4+(a) 3 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) byte (dir) ← (A) byte (addr16) ← (A) byte (Ri) ← (A) byte (ear) ← (A) byte (eam) ← (A) byte (io) ← (A) byte ((RLi)+disp8) ← (A) byte (Ri) ← (ear) byte (Ri) ← (eam) byte (ear) ← (Ri) byte (eam) ← (Ri) byte (Ri) ← imm8 byte (io) ← imm8 byte (dir) ← imm8 byte (ear) ← imm8 byte (eam) ← imm8 byte ((A)) ← (AH) - - - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ - - - XCH XCH XCH XCH A,ear A,eam Ri,ear Ri,eam 2 4 2+ 5+(a) 2 7 2+ 9+(a) 2 0 4 2 0 2×(b) 0 2×(b) byte (A) ←→ (ear) byte (A) ←→ (eam) byte (Ri) ←→ (ear) byte (Ri) ←→ (eam) Z Z - - - - - - - - - - ~ Note: For an explanation of “(a)” to “(d)” in the colunm “B”, see Table B.2d and Table B.2e. 320 APPENDIX B: Instructions MB90580 Series B.2 Instruction Set Table B.2.1b Transfer Instructions (Word/Long-Word) (38 Instructions) Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW A,dir A,addr16 A,SP A,RWi A,ear A,eam A,io A,@A A,#imm16 A,@RWi+disp8 A,@RLi+disp8 2 3 3 4 1 1 1 2 2 2 2+ 3+(a) 2 3 2 3 3 2 2 5 3 10 0 0 0 1 1 0 0 0 0 1 2 (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) word (A) ← (dir) word (A) ← (addr16) word (A) ← (SP) word (A) ← (RWi) word (A) ← (ear) word (A) ← (eam) word (A) ← (io) word (A) ← ((A)) word (A) ← imm16 word (A) ← ((RWi)+disp8) word (A) ← ((RLi)+disp8) - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ - - - MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW dir,A addr16,A SP,A RWi,A ear,A eam,A io,A @RWi+disp8,A @RLi+disp8,A RWi,ear RWi,eam ear,RWi eam,RWi RWi,#imm16 io,#imm16 ear,#imm16 eam,#imm16 @AL,AH / MOVW @A,T 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 3 4 1 2 2 3+(a) 3 5 10 3 4+(a) 4 5+(a) 2 5 2 4+(a) 3 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 (c) (c) 0 0 0 (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) word (dir) ← (A) word (addr16) ← (A) word (SP) ← (A) word (RWi) ← (A) word (ear) ← (A) word (eam) ← (A) word (io) ← (A) word ((RWi)+disp8) ← (A) word ((RLi)+disp8) ← (A) word (RWi) ← (ear) word (RWi) ← (eam) word (ear) ← (RWi) word (eam) ← (RWi) word (RWi) ← imm16 word (io) ← imm16 word (ear) ← imm16 word (eam) ← imm16 word ((A)) ← (AH) - - - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ - - - XCHW XCHW XCHW XCHW A,ear A,eam RWi,ear RWi,eam 2 4 2+ 5+(a) 2 7 2+ 9+(a) 2 0 4 2 0 2×(c) 0 2×(c) word (A) ←→ (ear) word (A) ←→ (eam) word (RWi) ←→ (ear) word (RWi) ←→ (eam) - - - - - - - - - - MOVL MOVL MOVL A,ear A,eam A,#imm32 4 2 2+ 5+(a) 3 5 2 0 0 0 (d) 0 long (A) ← (ear) long (A) ← (eam) long (A) ← imm32 - - - - - ∗ ∗ ∗ ∗ ∗ ∗ - - - MOVL MOVL ear,A eam,A 4 2 2+ 5+(a) 2 0 0 (d) long (ear1) ← (A) long (eam1) ← (A) - - - - - ∗ ∗ ∗ ∗ - - - Note: For an explanation of “(a)” to “(d)” in the colunm “B”, see Table B.2d and Table B.2e. MB90580 Series APPENDIX B: Instructions 321 B.2 Instruction Set Table B.2.1c Addition and Subtraction Instructions (Byte/Word/Long-Word) (42 Instructions) Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW byte (A) ← (A) + imm8 byte (A) ← (A) + (dir) byte (A) ← (A) + (ear) byte (A) ← (A) + (eam) byte (ear) ← (ear) + (A) byte (eam) ← (eam) + (A) byte (A) ← (AH) + (AL) + (C) byte (A) ← (A) + (ear) + (C) byte (A) ← (A) + (eam) + (C) byte (A) ← (AH) + (AL) + (C) (hexadecimal) byte (A) ← (A) - imm8 byte (A) ← (A) - (dir) byte (A) ← (A) - (ear) byte (A) ← (A) - (eam) byte (ear) ← (ear) - (A) byte (eam) ← (eam) - (A) byte (A) ← (AH) - (AL) - (C) byte (A) ← (A) - (ear) - (C) byte (A) ← (A) - (eam) - (C) byte (A) ← (AH) - (AL) - (C) (hexadecimal) Z Z Z Z Z Z Z Z Z - - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ - Z Z Z Z Z Z Z Z - - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ - word (A) ← (AH) + (AL) word (A) ← (A) + (ear) word (A) ← (A) + (eam) word (A) ← (A) + imm16 word (ear) ← (ear) + (A) word (eam) ← (eam) + (A) word (A) ← (A) + (ear) + (C) word (A) ← (A) + (eam) + (C) word (A) ← (AH) - (AL) word (A) ← (A) - (ear) word (A) ← (A) - (eam) word (A) ← (A) - imm16 word (ear) ← (ear) - (A) word (eam) ← (eam) - (A) word (A) ← (A) - (ear) - (C) word (A) ← (A) - (eam) - (C) - - - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ - long (A) ← (A) + (ear) long (A) ← (A) + (eam) long (A) ← (A) + imm32 long (A) ← (A) - (ear) long (A) ← (A) - (eam) long (A) ← (A) - imm32 - - - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ - ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC A,#imm8 A,dir A,ear A,eam ear,A eam,A A A,ear A,eam A 2 2 2 5 2 3 2+ 4+(a) 2 3 2+ 5+(a) 1 2 2 3 2+ 4+(a) 1 3 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2×(b) 0 0 (b) 0 SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A,dir A,ear A,eam ear,A eam,A A A,ear A,eam A 2 2 2 5 2 3 2+ 4+(a) 2 3 2+ 5+(a) 1 2 2 3 2+ 4+(a) 1 3 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2×(b) 0 0 (b) 0 ADDW ADDW ADDW ADDW ADDW ADDW ADDCW ADDCW SUBW SUBW SUBW SUBW SUBW SUBW SUBCW SUBCW A A,ear A,eam A,#imm16 ear,A eam,A A,ear A,eam A A,ear A,eam A,#imm16 ear,A eam,A A,ear A,eam 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 3 4+(a) 2 3 5+(a) 3 4+(a) 2 3 4+(a) 2 3 5+(a) 3 4+(a) 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 0 0 (c) 0 0 2×(c) 0 (c) 0 0 (c) 0 0 2×(c) 0 (c) ADDL ADDL ADDL SUBL SUBL SUBL A,ear A,eam A,#imm32 A,ear A,eam A,#imm32 2 6 2+ 7+(a) 5 4 2 6 2+ 7+(a) 5 4 2 0 0 2 0 0 0 (d) 0 0 (d) 0 Note: For an explanation of “(a)” to “(d)” in the colunm “B”, see Table B.2d and Table B.2e. 322 APPENDIX B: Instructions MB90580 Series B.2 Instruction Set Table B.2.1d Increment and Decrement Instructions (Byte/Word/Long-Word) (12 Instructions) Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW INC INC ear eam 2 3 2+ 5+(a) 2 0 0 2×(b) byte (ear) ← (ear) + 1 byte (eam) ← (eam) + 1 - - - - - ∗ ∗ ∗ ∗ ∗ ∗ - * DEC DEC ear eam 2 3 2+ 5+(a) 2 0 0 2×(b) byte (ear) ← (ear) - 1 byte (eam) ← (eam) - 1 - - - - - ∗ ∗ ∗ ∗ ∗ ∗ - ∗ INCW INCW ear eam 2 3 2+ 5+(a) 2 0 0 2×(c) word (ear) ← (ear) + 1 word (eam) ← (eam) + 1 - - - - - ∗ ∗ ∗ ∗ ∗ ∗ - ∗ DECW DECW ear eam 2 3 2+ 5+(a) 2 0 0 2×(c) word (ear) ← (ear) - 1 word (eam) ← (eam) - 1 - - - - - ∗ ∗ ∗ ∗ ∗ ∗ - ∗ INCL INCL ear eam 2 7 2+ 9+(a) 4 0 0 2×(d) long (ear) ← (ear) + 1 long (eam) ← (eam) + 1 - - - - - ∗ ∗ ∗ ∗ ∗ ∗ - ∗ DECL DECL ear eam 2 7 2+ 9+(a) 4 0 0 2×(d) long (ear) ← (ear) - 1 long (eam) ← (eam) - 1 - - - - - ∗ ∗ ∗ ∗ ∗ ∗ - ∗ Table B.2.1e Compare Instructions (Byte/Word/Long-Word) (11 Instructions) RG B LH AH I S T N Z V C RMW CMP CMP CMP CMP Mnemonic A A,ear A,eam A,#imm8 1 1 2 2 2+ 3+(a) 2 2 # 0 1 0 0 0 0 (b) 0 byte (AH) - (AL) byte (A) - (ear) byte (A) - (eam) byte (A) - imm8 - - - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ - CMPW CMPW CMPW CMPW A A,ear A,eam A,#imm16 1 1 2 2 2+ 3+(a) 3 2 0 1 0 0 0 0 (c) 0 word (AH) - (AL) word (A) - (ear) word (A) - (eam) word (A) - imm16 - - - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ - CMPL CMPL CMPL A,ear A,eam A,#imm32 2 6 2+ 7+(a) 5 3 2 0 0 0 (d) 0 long (A) - (ear) long (A) - (eam) long (A) - imm32 - - - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ - ~ Operation Note: For an explanation of “(a)” to “(d)” in the colunm “B”, see Table B.2d and Table B.2e. MB90580 Series APPENDIX B: Instructions 323 B.2 Instruction Set Table B.2.1f Unsigned Multiplication and Division Instructions (Word/Long-Word) (11 Instructions) Mnemonic # ~ RG B DIVU A 1 *1 0 0 DIVU A,ear 2 *2 1 0 DIVU A,eam 2+ *3 0 *6 DIVUW A,ear 2 *4 1 0 DIVUW A,eam 2+ *5 0 *7 MULU MULU MULU MULUW MULUW MULUW A A,ear A,eam A A,ear A,eam 1 2 2+ 1 2 2+ *8 *9 *10 *11 *12 *13 0 1 0 0 1 0 0 0 (b) 0 0 (c) Operation LH AH I S T N Z V C RMW word (AH) / byte (AL) Quotient → byte (AL) Remainder → byte (AH) word (A) / byte (ear) Quotient → byte (A) Remainder → byte (ear) word (A) / byte (eam) Quotient → byte (A) Remainder → byte (ear) long (A) / word (ear) Quotient → word (A) Remainder → word (ear) long (A) / word (eam) Quotient → word (A) Remainder → word (eam) - - - - - - - ∗ ∗ - - - - - - - - ∗ ∗ - - - - - - - - ∗ ∗ - - - - - - - - ∗ ∗ - - - - - - - - ∗ ∗ - byte (AH) * byte (AL) → word (A) byte (A) * byte (ear) → word (A) byte (A) * byte (eam) → word (A) word (AH) * word (AL) → Long (A) word (A) * word (ear) → Long (A) word (A) * word (eam) → Long (A) - - - - - - - - - - *1: 3 when dividing into zero, 7 when an overflow occurs, and 15 normally. *2: 4 when dividing into zero, 8 when an overflow occurs, and 16 normally. *3: 6 + (a) when dividing into zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. *4: 4 when dividing into zero, 7 when an overflow occurs, and 22 normally. *5: 6 + (a) when dividing into zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. *6: (b) when dividing into zero or when an overflow occurs, and 2 × (b) normally. *7: (c) when dividing into zero or when an overflow occurs, and 2 × (c) normally. *8: 3 when byte (AH) is zero, and 7 when byte (AH) is not 0. *9: 4 when byte (ear) is zero, and 8 when byte (ear) is not 0. *10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. *11: 3 when word (AH) is zero, and 11 when word (AH) is not 0. *12: 4 when word (ear) is zero, and 12 when word (ear) is not 0. *13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not 0. Note: For an explanation of “(a)” to “(d)” in the colunm “B”, see Table B.2d and Table B.2e. 324 APPENDIX B: Instructions MB90580 Series B.2 Instruction Set Table B.2.1g Signed Multiplication and Division Instructions (Word/Long-Word) (11 Instructions) Mnemonic # ~ RG B DIV A 1 *1 0 0 DIV A,ear 2 *2 1 0 DIV A,eam 2+ *3 0 *6 DIVW A,ear 2 *4 1 0 DIVW A,eam 2+ *5 0 *7 MUL MUL MUL MULW MULW MULW A A,ear A,eam A A,ear A,eam 2 2 2+ 2 2 2+ *8 *9 *10 *11 *12 *13 0 1 0 0 1 0 0 0 (b) 0 0 (c) Operation LH AH I S T N Z V C RMW word (AH) / byte (AL) Quotient → byte (AL) Remainder → byte (AH) word (A) / byte (ear) Quotient → byte (A) Remainder → byte (ear) word (A) / byte (eam) Quotient → byte (A) Remainder → byte (ear) long (A) / word (ear) Quotient → word (A) Remainder → word (ear) long (A) / word (eam) Quotient → word (A) Remainder → word (eam) Z - - - - - - ∗ ∗ - Z - - - - - - ∗ ∗ - Z - - - - - - ∗ ∗ - - - - - - - - ∗ ∗ - - - - - - - - ∗ ∗ - byte (AH) * byte (AL) → word (A) byte (A) * byte (ear) → word (A) byte (A) * byte (eam) → word (A) word (AH) * word (AL) → Long (A) word (A) * word (ear) → Long (A) word (A) * word (eam) → Long (A) - - - - - - - - - - *1: 3 when dividing into zero, 8 or 18 when an overflow occurs, and 18 normally. *2: 3 when dividing into zero, 10 or 21 when an overflow occurs, and 22 normally. *3: 4 + (a) when dividing into zero, 11 + (a) or 22 + (a) when an overflow occurs, and 23 + (a) normally. *4: When dividend is positive: 4 when dividing into zero, 10 or 29 when an overflow occurs, and 30 normally. When dividend is negative: 4 when dividing into zero, 11 or 30 when an overflow occurs, and 31 normally. *5: When dividend is positive: 4+ (a) when dividing into zero, 11+ (a) or 30+ (a) when an overflow occurs, and 31+ (a) normally. When dividend is negative: 4+ (a) when dividing into zero, 12+ (a) or 31+ (a) when an overflow occurs, and 32+ (a) normally. *6: (b) when dividing into zero or when an overflow occurs, and 2 × (b) normally. *7: (c) when dividing into zero or when an overflow occurs, and 2 × (c) normally. *8: 3 when byte (AH) is zero, 12 when the result is possible, and 13 when the result is negative. *9: 3 when byte (ear) is zero, 12 when the result is possible, and 13 when the result is negative. *10: 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11: 3 when word (AH) is zero, 12 when the result is possible, and 13 when the result is negative. *12: 3 when word (ear) is zero, 16 when the result is possible, and 19 when the result is negative. *13: 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. Note: Two cycle counts are given for overflows occurring from DIV or DIVW instructions, because the overflow may be detected before or after execution. The contents of AL are destroyed when an overflow occurs from a DIV or DIVW instruction. For an explanation of “(a)” to “(d)” in the colunm “B”, see Table B.2d and Table B.2e. MB90580 Series APPENDIX B: Instructions 325 B.2 Instruction Set Table B.2.1h Logical 1 Instructions (Byte/Word) (39 Instructions) Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW AND AND AND AND AND A,#imm8 A,ear A,eam ear,A eam,A 2 2 2 3 2+ 4+(a) 2 3 2+ 5+(a) 0 1 0 2 0 0 0 (b) 0 2×(b) byte (A) ← (A) and imm8 byte (A) ← (A) and (ear) byte (A) ← (A) and (eam) byte (ear) ← (ear) and (A) byte (eam) ← (eam) and (A) - - - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ R R R R R - ∗ OR OR OR OR OR A,#imm8 A,ear A,eam ear,A eam,A 2 2 2 3 2+ 4+(a) 2 3 2+ 5+(a) 0 1 0 2 0 0 0 (b) 0 2×(b) byte (A) ← (A) or imm8 byte (A) ← (A) or (ear) byte (A) ← (A) or (eam) byte (ear) ← (ear) or (A) byte (eam) ← (eam) or (A) - - - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ R R R R R - ∗ XOR XOR XOR XOR XOR NOT NOT NOT A,#imm8 A,ear A,eam ear,A eam,A A ear eam 2 2 2 3 2+ 4+(a) 2 3 2+ 5+(a) 1 2 2 3 2+ 5+(a) 0 1 0 2 0 0 2 0 0 0 (b) 0 2×(b) 0 0 2×(b) byte (A) ← (A) xor imm8 byte (A) ← (A) xor (ear) byte (A) ← (A) xor (eam) byte (ear) ← (ear) xor (A) byte (eam) ← (eam) xor (A) byte (A) ← not (A) byte (ear) ← not (ear) byte (eam) ← not (eam) - - - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ R R R R R R R R - * ∗ ANDW ANDW ANDW ANDW ANDW ANDW A A,#imm16 A,ear A,eam ear,A eam,A 1 2 3 2 2 3 2+ 4+(a) 2 3 2+ 5+(a) 0 0 1 0 2 0 0 0 0 (c) 0 2×(c) word (A) ← (AH) and (A) word (A) ← (A) and imm16 word (A) ← (A) and (ear) word (A) ← (A) and (eam) word (ear) ← (ear) and (A) word (eam) ← (eam) and (A) - - - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ R R R R R R - ∗ ORW ORW ORW ORW ORW ORW A A,#imm16 A,ear A,eam ear,A eam,A 1 2 3 2 2 3 2+ 4+(a) 2 3 2+ 5+(a) 0 0 1 0 2 0 0 0 0 (c) 0 2×(c) word (A) ← (AH) or (A) word (A) ← (A) or imm16 word (A) ← (A) or (ear) word (A) ← (A) or (eam) word (ear) ← (ear) or (A) word (eam) ← (eam) or (A) - - - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ R R R R R R - ∗ XORW XORW XORW XORW XORW XORW NOTW NOTW NOTW A A,#imm16 A,ear A,eam ear,A eam,A A ear eam 1 2 3 2 2 3 2+ 4+(a) 2 3 2+ 5+(a) 1 2 2 3 2+ 5+(a) 0 0 1 0 2 0 0 2 0 0 0 0 (c) 0 2×(c) 0 0 2×(c) word (A) ← (AH) xor (A) word (A) ← (A) xor imm16 word (A) ← (A) xor (ear) word (A) ← (A) xor (eam) word (ear) ← (ear) xor (A) word (eam) ← (eam) xor (A) word (A) ← not (A) word (ear) ← not (ear) word (eam) ← not (eam) - - - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ R R R R R R R R R - ∗ ∗ Note: For an explanation of “(a)” to “(d)” in the colunm “B”, see Table B.2d and Table B.2e. 326 APPENDIX B: Instructions MB90580 Series B.2 Instruction Set Table B.2.1i Logical 2 Instructions (Long-Word) (6 Instructions) Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW ANDL ANDL A,ear A,eam 2 6 2+ 7+(a) 2 0 0 (d) long (A) ← (A) and (ear) long (A) ← (A) and (eam) - - - - - ∗ ∗ ∗ ∗ R R - - ORL ORL A,ear A,eam 2 6 2+ 7+(a) 2 0 0 (d) long (A) ← (A) or (ear) long (A) ← (A) or (eam) - - - - - ∗ ∗ ∗ ∗ R R - - XORL XORL A,ear A,eam 2 6 2+ 7+(a) 2 0 0 (d) long (A) ← (A) xor (ear) long (A) ← (A) xor (eam) - - - - - ∗ ∗ ∗ ∗ R R - - Table B.2.1j Sign Inversion Instructions (Byte/Word) (6 Instructions) Mnemonic # ~ RG B NEG A 1 2 0 0 NEG NEG ear eam 2 0 0 2+(b) NEGW A 0 0 NEGW NEGW ear eam 2 0 0 2+(c) 2 3 2+ 5+(a) 1 2 2 2 2+ 5+(a) Operation LH AH I S T N Z V C RMW byte (A) ← 0 - (A) X - - - - ∗ ∗ ∗ ∗ - byte (ear) ← 0 - (ear) byte (eam) ← 0 - (eam) - - - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ word (A) ← 0 - (A) - - - - - ∗ ∗ ∗ ∗ - word (ear) ← 0 - (ear) word (eam) ← 0 - (eam) - - - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ Table B.2.1k Normalize Instruction (Long-Word) (1 Instruction) Mnemonic NRML A,R0 *1: # ~ RG B Operation LH AH I S T N Z V C RMW 2 *1 1 0 long (A) ← Shift to the position where 1 was formerly placed byte (R0) ← Number of shifts at that time - - - - - - ∗ - - - 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases. Note: For an explanation of “(a)” to “(d)” in the colunm “B”, see Table B.2d and Table B.2e. MB90580 Series APPENDIX B: Instructions 327 B.2 Instruction Set Table B.2.1l Shift Instructions (Byte/Word/Long-Word) (18 Instructions) Mnemonic # ~ RG B 2 2 0 0 0 0 Operation LH AH I S T N Z V C RMW byte (A) ← Right rotate with carry byte (A) ← Left rotate with carry - - - - - ∗ ∗ ∗ ∗ - ∗ ∗ - byte (ear) ← Right rotate with carry byte (eam) ← Right rotate with carry byte (ear) ← Left rotate with carry byte (eam) ← Left rotate with carry - - - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ - ∗ ∗ ∗ ∗ ∗ ∗ 0 0 0 byte (A) ← Arithmetic right barrel shift (A,R0) byte (A) ← Logical right barrel shift (A,R0) byte (A) ← Logical left barrel shift (A,R0) - - - - ∗ ∗ - ∗ ∗ ∗ ∗ ∗ ∗ - ∗ ∗ ∗ - 0 0 0 0 0 0 word (A) ← Arithmetic right shift (A,1 bit) word (A) ← Logical right shift (A,1 bit) word (A) ← Logical left shift (A,1 bit) - - - - ∗ ∗ - ∗ R ∗ ∗ ∗ ∗ - ∗ ∗ ∗ - *1 *1 *1 1 1 1 0 0 0 word (A) ← Arithmetic right barrel shift (A,R0) word (A) ← Logical right barrel shift (A,R0) word (A) ← Logical left barrel shift (A,R0) - - - - ∗ ∗ - ∗ ∗ ∗ ∗ ∗ ∗ - ∗ ∗ ∗ - *2 *2 *2 1 1 1 0 0 0 long (A) ← Arithmetic right barrel shift (A,R0) long (A) ← Logical right barrel shift (A,R0) long (A) ← Logical left barrel shift (A,R0) - - - - ∗ ∗ - ∗ ∗ ∗ ∗ ∗ ∗ - ∗ ∗ ∗ - RORC ROLC A A 2 2 RORC RORC ROLC ROLC ear eam ear eam 2 3 2+ 5+(a) 2 3 2+ 5+(a) 2 0 2 0 0 2×(b) 0 2×(b) ASR LSR LSL A,RO A,RO A,RO 2 2 2 *1 *1 *1 1 1 1 ASRW LSRW LSLW A 1 A /SHRW A 1 A /SHLW A 1 2 2 2 ASRW LSRW LSLW A,R0 A,R0 A,R0 2 2 2 ASRL LSRL LSLL A,R0 A,R0 A,R0 2 2 2 *1: 6 when R0 is 0, 5 + (R0) in all other cases. *2: 6 when R0 is 0, 6 + (R0) in all other cases. Note: For an explanation of “(a)” to “(d)” in the colunm “B”, see Table B.2d and Table B.2e. 328 APPENDIX B: Instructions MB90580 Series B.2 Instruction Set Table B.2.1m Branch 1 Instructions (31 Instructions) Mnemonic # ~ RG B 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BZ / BEQ BNZ / BNE BC / BLO BNC / BHS BN BP BV BNV BT BNT BLT BGE BLE BGT BLS BHI BRA rel rel rel rel rel rel rel rel rel rel rel rel rel rel rel rel rel JMP JMP JMP JMP JMPP JMPP JMPP @A 1 2 addr16 3 3 @ear 2 3 @eam 2+ 4+(a) @ear *1 2 5 @eam *1 2+ 6+(a) addr24 4 4 0 0 1 0 2 0 0 CALL CALL CALL CALLV CALLP CALLP @ear *2 2 6 @eam *2 2+ 7+(a) addr16 *3 3 6 #vct4 *3 1 7 @ear *4 2 10 @eam *4 2+ 11+(a) CALLP addr24 *5 4 10 Operation LH AH I S T N Z V C RMW Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0 Branch when ((V) xor (N)) or (Z) = 1 Branch when ((V) xor (N)) or (Z) = 0 Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Unconditional branching - - - - - - - - - - 0 0 0 (c) 0 (d) 0 word (PC) ← (A) word (PC) ← addr16 word (PC) ← (ear) word (PC) ← (eam) word (PC) ← (ear), (PCB) ← (ear+2) word (PC) ← (eam), (PCB) ← (eam+2) word (PC) ← ad24 0-15, (PCB) ← ad24 16-23 - - - - - - - - - - 1 0 0 0 2 0 (c) 2×(c) (c) 2×(c) 2×(c) *2 - - - - - - - - - - 0 2×(c) word (PC) ← (ear) word (PC) ← (eam) word (PC) ← addr16 Vector call instruction word (PC) ← (ear) 0-15, (PCB) ← (ear)16-23 word (PC) ← (eam) 0-15, (PCB) ← (eam)16-23 word (PC) ← addr0-15, (PCB) ← addr16-23 - - - - - - - - - - *1: 4 when branching, 3 when not branching. *2: 3 × (c) + (b) Note 1: Read (word) branch address. Note 2: W: Save (word) into stack; R: read (word) branch address. Note 3: Save (word) into stack. Note 4: W: Save (long-word) into W stack; R: read (long-word) R branch address. Note 5: Save (long-word) into stack. Note: For an explanation of “(a)” to “(d)” in the colunm “B”, see Table B.2d and Table B.2e. MB90580 Series APPENDIX B: Instructions 329 B.2 Instruction Set Table B.2.1n Branch 2 Instructions (19 Instructions) Mnemonic CBNE A,#imm8,rel CWBNE A,#imm16,rel # ~ RG B 3 4 *1 *1 0 0 0 0 Operation LH AH I S T N Z V C RMW Branch when byte (A) ≠ imm8 Branch when word (A)≠ imm16 - - - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ - Branch when byte (ear)≠ imm8 Branch when byte (eam)≠ imm8 Branch when word (ear)≠ imm16 Branch when word (eam)≠ imm16 - - - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ - CBNE CBNE CWBNE CWBNE ear,#imm8,rel 4 eam,#imm8,rel 4+ ear,#imm16,rel 5 eam,#imm16,rel 5+ *2 *3 *4 *3 1 0 1 0 0 (b) 0 (c) DBNZ DBNZ ear,rel eam,rel 3 3+ *5 *6 2 2 0 2×(b) Branch when byte (ear)=(ear)-1, (ear)≠ 0 Branch when byte (eam)=(eam)-1, (eam)≠ 0 - - - - - ∗ ∗ ∗ ∗ ∗ ∗ - ∗ DWBNZ DWBNZ ear,rel eam,rel 3 3+ *5 *6 2 2 0 2×(c) Branch when word (ear)=(ear)-1, (ear)≠ 0 Branch when word (eam)=(eam)-1, (eam)≠ 0 - - - - - ∗ ∗ ∗ ∗ ∗ ∗ - ∗ INT INT INTP INT9 RETI #vct8 addr16 addr24 2 3 4 1 1 20 16 17 20 11 0 0 0 0 0 8×(c) 6×(c) 6×(c) 8×(c) *7 Software interrupt Software interrupt Software interrupt Software interrupt Recovery from interrupt - - R R R R ∗ S S S S ∗ ∗ ∗ ∗ ∗ ∗ - LINK #imm8 2 6 0 (c) - - - - - - - - - - 1 5 0 (c) At the entrance of function, save old frame pointers into a stack, set up new frame pointers, reserve area for local pointers. At the exit of function, recover the old frame pointers from the stack. - - - - - - - - - - 1 1 4 6 0 0 (c) (d) Recover from the subroutine. Recover from the subroutine. - - - - - - - - - - UNLINK RET RETP *1 *2 *1: 5 when branching, 4 when not branching *2: 13 when branching, 12 when not branching *3: 7 + (a) when branching, 6 + (a) when not branching *4: 8 when branching, 7 when not branching *5: 7 when branching, 6 when not branching *6: 8 + (a) when branching, 7 + (a) when not branching *7: 3 × (b) + 2 × (c) when an interrupt request is generated, 6 × (c) at recovery. Note 1: Return from stack (word) Note 2: Return from stack (long) Note 3: RWj+ addressing mode should not be used with the CBNE/CWBNE instructions. Note: For an explanation of “(a)” to “(d)” in the colunm “B”, see Table B.2d and Table B.2e. 330 APPENDIX B: Instructions MB90580 Series B.2 Instruction Set Table B.2.1o Other Control Instructions (Byte/Word/Long-Word) (36 Instructions) Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW PUSHW PUSHW PUSHW PUSHW A AH PS rlst 1 1 1 2 4 4 4 *3 0 0 0 +& (c) (c) (c) *4 word (SP) ← (SP) -2, ((SP)) ← (A) word (SP) ← (SP) -2, ((SP)) ← (AH) word (SP) ← (SP) -2, ((SP)) ← (PS) (SP) ← (SP) - 2n, ((SP)) ← (rlst) - - - - - - - - - - POPW POPW POPW POPW A AH PS rlst 1 1 1 2 3 3 4 *2 0 0 0 +& (c) (c) (c) *4 word (A) ← ((SP)), (SP) ← (SP) + 2 word (AH) ← ((SP)), (SP) ← (SP) + 2 word (PS) ← ((SP)), (SP) ← (SP) + 2 (rlst) ← ((SP)), (SP) ← (SP) - ∗ - ∗ - ∗ - ∗ - ∗ - ∗ - ∗ - ∗ - - JCTX @A 1 14 0 6×(c) Context switching instruction - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ - AND OR CCR,#imm8 CCR,#imm8 2 2 3 3 0 0 0 0 byte (CCR) ← (CCR) and imm8 byte (CCR) ← (CCR) or imm8 - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ - MOV MOV RP,#imm8 ILM,#imm8 2 2 2 2 0 0 0 0 byte (RP) ← imm8 byte (ILM) ← imm8 - - - - - - - - - - MOVEA MOVEA MOVEA MOVEA RWi,ear RWi,eam A,ear A,eam 2 2+ 2 2+ 3 2+(a) 1 1+(a) 1 1 0 0 0 0 0 0 word (RWi) ← ear word (RWi) ← eam word (A) ← ear word (A) ← eam - ∗ ∗ - - - - - - - - ADDSP ADDSP #imm8 #imm16 2 3 3 3 0 0 0 0 word (SP) ← ext(imm8) word (SP) ← imm16 - - - - - - - - - - MOV MOV A,brgl brg2,A 2 2 *1 1 0 0 0 0 byte (A) ← (brg1) byte (brg2) ← (A) Z - ∗ - - - - ∗ ∗ ∗ ∗ - - - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 No operation Prefix code for AD space access Prefix code for DT space access Prefix code for PC space access Prefix code for SP space access Prefix code for flag unchange setting Prefix for common register banks - - - - - - - - - - NOP ADB DTB PCB SPB NCC CMR *1: PCB, ADB, SSB, USB, and SPB: ...1 cycle DTB, DPR: ......................................2 cycles *2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when RLST = 0 *3: 29 + 3 × (pop count) - 3 × (last register number to be popped), 8 when RLST = 0 *4: Pop count x (c), or push count x (c) Note: For an explanation of “(a)” to “(d)” in the colunm “B”, see Table B.2d and Table B.2e. MB90580 Series APPENDIX B: Instructions 331 B.2 Instruction Set Table B.2.1p Bit Manipulation Instructions (22 Instructions) Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW byte (A) ← ( dir:bp )b byte (A) ← ( addr16:bp )b byte (A) ← ( io:bp )b Z Z Z ∗ ∗ ∗ - - - ∗ ∗ ∗ ∗ ∗ ∗ - - - 2×(b) 2×(b) 2×(b) bit ( dir:bp )b ← (A) bit ( addr16:bp )b ← (A) bit ( io:bp )b ← (A) - - - - - ∗ ∗ ∗ ∗ ∗ ∗ - - ∗ ∗ ∗ 0 0 0 2×(b) 2×(b) 2×(b) bit ( dir:bp )b ← 1 bit ( addr16:bp )b ← 1 bit ( io:bp )b ← 1 - - - - - - - - - ∗ ∗ ∗ 7 7 7 0 0 0 2×(b) 2×(b) 2×(b) bit ( dir:bp )b ← 0 bit ( addr16:bp )b ← 0 bit ( io:bp )b ← 0 - - - - - - - - - ∗ ∗ ∗ 4 5 4 *1 *1 *2 0 0 0 (b) (b) (b) Branch when ( dir:bp )b = 0 Branch when ( addr16:bp )b = 0 Branch when ( io:bp)b = 0 - - - - - - ∗ ∗ ∗ - - - dir:bp,rel addr16:bp,rel io:bp,rel 4 5 4 *1 *1 *2 0 0 0 (b) (b) (b) Branch when ( dir:bp )b = 1 Branch when ( addr16:bp )b = 1 Branch when ( io:bp)b = 1 - - - - - - ∗ ∗ ∗ - - - SBBS addr16:bp,rel 5 *3 0 2×(b) Branch when (addr16:bp) b = 1, bit = 1 - - - - - - ∗ - - ∗ WBTS io:bp 3 *4 0 *5 Wait until (io:bp) b = 1 - - - - - - - - - - WBTC io:bp 3 *4 0 *5 Wait until (io:bp) b = 0 - - - - - - - - - - MOVB MOVB MOVB A,dir:bp A,addr16:bp A,io:bp 3 4 3 5 5 4 0 0 0 (b) (b) (b) MOVB MOVB MOVB dir:bp,A addr16:bp,A io:bp,A 3 4 3 7 7 6 0 0 0 SETB SETB SETB dir:bp addr16:bp io:bp 3 4 3 7 7 7 CLRB CLRB CLRB dir:bp addr16:bp io:bp 3 4 3 BBC BBC BBC dir:bp,rel addr16:bp,rel io:bp,rel BBS BBS BBS *1: 8 when branching, 7 when not branching *2: 7 when branching, 6 when not branching *3: 10 when condition is satisfied, 9 when not satisfied *4: Undefined count *5: Until condition is satisfied Note: For an explanation of “(a)” to “(d)” in the colunm “B”, see Table B.2d and Table B.2e. 332 APPENDIX B: Instructions MB90580 Series B.2 Instruction Set Table B.2.1q Accumulator Manipulation Instructions (Byte/Word) (6 Instructions) Mnemonic SWAP SWAPW / XCHW A,T EXT EXTW ZEXT ZEXTW # ~ RG B 1 1 1 1 1 1 3 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Operation byte (A)0-7 ←→ (A)8-15 word (AH) ←→ (AL) byte signed extension word signed extension byte zero extension word zero extension LH AH X Z - ∗ X Z I S T N Z V C RMW - - - ∗ ∗ R R ∗ ∗ ∗ ∗ - - - Table B.2.1r String Instructions (10 Instructions) Mnemonic # ~ RG B Operation N Z V C RMW MOVS / MOVSI MOVSD 2 2 *2 *2 +& +& *3 *3 byte transfer @AH+ ← @AL+, counter = RW0 byte transfer @AH- ← @AL-, counter = RW0 LH AH I S T - - - - - - - - - - SCEQ / SCEQI SCEQD 2 2 *1 *1 +& +& *4 *4 byte search @AH+ ← AL, counter = RW0 byte search @AH- ← AL, counter = RW0 - - - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ - FILS / FILSI 2 6m+6 +& *3 byte fill @AH+ ← AL, counter = RW0 - - - - - ∗ ∗ - - - MOVSW / MOVSWI MOVSWD 2 2 *2 *2 +) +) *6 *6 word transfer @AH+ ← @AL+, counter = RW0 word transfer @AH- ← @AL-, counter = RW0 - - - - - - - - - - SCWEQ / SCWEQI SCWEQD 2 2 *1 *1 +) +) *7 *7 word search @AH+ ← AL, counter = RW0 word search @AH- ← AL, counter = RW0 - - - - - ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ - FILSW / FILSWI 2 6m+6 +) *6 word fill @AH+ ← AL, counter = RW0 - - - - - ∗ ∗ - - - *1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7n + 5 when match occurs. *2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case. *3: (b) × (RW0) + (b) × (RW0): when accessing a source and a destination in different areas, the value of item (b) should be computed separately for each. *4: (b) × n *5: 2 × (RW0) *6: (c) × (RW0) + (c) × (RW0): when accessing a source and a destination in different areas, the value of item (c) should be computed separately for each. *7: (c) × n *8: 2 × (RW0) m: RW0 value (counter value) n : Loop count Note: For an explanation of “(a)” to “(d)” in the colunm “B”, see Table B.2d and Table B.2e. MB90580 Series APPENDIX B: Instructions 333 B.3 Instruction Map B.3 Instruction Map Because the F2MC-16LX operation codes each consist of one or two bytes, the instruction map consists of numerous pages. The structure of the instruction map is shown below. Basic Page Map Bit manipulation Instructions Character string manipulation instructions First byte 2-byte instructions “ea” instructions × 9 Second byte Fig. B.3a Structure of F2MC-16LX Instruction Map Instructions that consist of only one byte (such as NOP) are concluded on the basic page. Regarding instructions that require two bytes (such as MOVS), the existence of the map for the second byte is indicated when the first byte is referenced, so it is clear that it is necessary to use the following byte to reference the map for the second byte. 334 APPENDIX B: Instructions MB90580 Series B.3 Instruction Map The correspondence between the actual instruction code and the instruction map is shown below. May not exist for some instructions Length differs according to the instruction First byte Second byte operand operand ••• Instruction code [Basic page map] XY +Z [Extension page map] Note UV +W Note: Extended page maps are provided for bit manipulation instructions, character string manipulation instructions, two-byte instructions, and “ea” instructions; multiple-extended-page maps exist for each type of instruction. Fig. B.3b Correspondence between Actual Instructions and the Instruction Maps MB90580 Series APPENDIX B: Instructions 335 336 APPENDIX B: Instructions SWAP DTB ADB SPB +4 +5 +6 +7 LSRW +F A A ASRW ADDSP #16 SWAPW ADDSP #8 LINK ADDL imm#8 A, #32 UNLINK SUBL A, #32 MOV MOV RP, #8 ILM, #8 NEGW CMPL A A, #32 LSLW EXTW A ZEXTW +E +D +C +B +A +9 +8 ZEXT PCB +3 A JCTX @A EXT NEG +2 A SUBDC ADDDC +1 A NCC INT9 +0 10 CMR NOP 00 A A, dir A, dir SUBC SUB A A, #8 A, #8 30 ADD MOV MOV dir, A A, dir 40 MOV A, #8 CMP MOVX CMP A, #8 A A, #8 AND AND MOV A, #8 dir, #8 CCR, #8 MOVX OR OR A, #8 A, dir CCR, #8 XOR DIVU MOVW A, #8 A A, SP MOVW NOT MULU A SP, A A MOVW ADDW ADDW A, #16 A, dir A SUBW SUBW MOVW A, #16 dir, A A MOVW CWBNE CBNE A, A, #16, rel A, #16 #8, rel CMPW CMPW MOVL A, #32 A, #16 A PUSHW ANDW ANDW A, #16 A A PUSHW ORW ORW A, #16 AH A PUSHW XORW XORW PS A, #16 A PUSHW NOTW MULUW A rlst A ADDC SUB ADD 20 B.3.1 Basic Page Map A, io io, A MOV A, addr16 MOV addr 16, A MOV io, #8 MOVX A, io MOVW io, #16 MOVX A, addr16 MOVW A, io MOVW io, A MOVW A, addr16 MOVW addr16, A POPW A POPW AH POPW PS POPW rlst MOV MOV 50 @A rel #vct8 70 instructions (9) ea instructions (8) ea instructions (7) ea instructions (6) ea instructions (5) ea instructions (4) ea instructions (3) ea instructions (2) ea instructions (1) ea INT addr16 MOVEA RWi, ea MOV INTP Ri, ea addr24 MOVW RETI RWi, ea Bit MOV operation ea, Ri instructions MOVW ea, RWi String XCH operation Ri, ea instructions XCRW Two-byte RWi, ea instructions INT RET addr16 JMPP addr24 CALL addr16 CALLP addr24 RETP JMP JMP BRA 60 A, Ri MOVW A, RWi MOV 80 Table B.3.1a Basic Page Map 90 Ri, A MOVW RWi, A MOV B0 MOVX C0 MOVW @RWi+dB, A MOVX A, Ri A,@RWi+d8 MOVW MOVW RWi, #16 @RWi+dB Ri, #8 A0 MOV D0 MOVN A, #4 E0 CALLV F0 BZ /BEQ #4 rel BNZ/BNE rel BC /BLO rel BNC/BHS rel BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel B.3 Instruction Map MB90580 Series MB90580 Series Table B.3.1b Bit Manipulation Instruction Map (First byte = 6 CH) 00 +0 10 MOVB A, io:bp 20 30 MOVB io:bp, A 40 50 CLRB 60 70 SETB io:bp io:bp 80 90 A0 BBC io:bp, rel BBS io:bp, rel BBC BBC dir:bp,rel ad16:bp, rel BBS dir:bp, rel B0 C0 WBTS io:bp D0 E0 F0 WBTC io:bp +1 +2 +3 +4 +5 +6 +7 +8 MOVB A, dir:bp MOVB A, addr16:bp MOVB dir: bp,A MOVB addr16: bp, A CLRB dir:bp CLRB addr16:bp SETB dir:bp SETB addr16:bp BBS ad 16:bp, rel SBBS addr16:bp +9 +A +B +C +D +E +F 337 B.3 Instruction Map APPENDIX B: Instructions APPENDIX B: Instructions 00 10 MOVSD 20 MOVSWI 30 MOVSWD 40 50 60 70 80 90 A0 B0 C0 D0 E0 SCEQI PCB SCEQD PCB SCWEQI PCB SCWEQD PCB FILSI PCB FILSWI PCB +0 MOVSI PCB, PCB +1 PCB, DTB DTB DTB DTB DTB DTB DTB +2 PCB, ADB ADB ADB ADB ADB ADB ADB +3 PCB, SPB SPB SPB SPB SPB SPB SPB +4 DTB, PCB +5 DTB, DTB +6 DTB, ADB +7 DTB, SPB +8 ADB, PCB +9 ADB, DTB +A ADB, ADB +B ADB, SPB +C SPB, PCB +D SPB, DTB +E SPB, ADB +F SPB, SPB F0 B.3 Instruction Map 338 Table B.3.1c Character String Manipulation Instruction Map (First byte = 6EH) MB90580 Series MB90580 Series +F +E +D +C +B +A +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 00 10 LSLL A, R0 MOVW @AL, AH ASRL A, R0 LSRL A, R0 A, R0 MOVW A, @A ASRW A, R0 LSRW A, R0 MOV DTB, A MOV ADB, A MOV SSB, A MOV USB, A MOV DPR, A MOV @AL, AH MOVX A, @A RORC A LSLW MOV A, DTB MOV A, ADB MOV A, SSB MOV A, USB MOV A. DPR MOV A. @A MOV A, PCB ROLC A 20 30 40 MOV A, @RL2+d8 MOV A, @RL1+d8 MOV A, @RL0+d8 MOVW A, R0 @RL2+d8, A NRML A, R0 ASR MOVW A, R0 @RL3+d8, A LSR A, R0 LSL MOVW @RL1+d8, A MOVW A, @RL3+d8 MOVW A, @RL2+d8 MOVW A, @RL1+d8 MOVW MOVW @RL0+d8, A A, @RL0+d8 MOVX MOV MOV A, @RL3+d8 @RL3+d8, A A, @RL3+d8 MOVX MOV A, @RL2+d8 @RL2+d8, A MOVX MOV A, @RL1+d8 @RL1+d8, A MOVX MOV A, @RL0 +d8 @RL0+d8, A 50 60 DIVU MULW MUL 70 A A A 80 90 A0 Table B.3.1d Two-byte Instruction Map (First byte = 6F H) B0 C0 D0 E0 F0 B.3 Instruction Map APPENDIX B: Instructions 339 340 APPENDIX B: Instructions +F +E +D +C +B +A +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 00 10 20 SUBL @RW7+d8 A, RL3 SUBL ADDL A, @RW6+d8 A,RL3 SUBL ADDL A, @RW5+d8 A, RL2 SUBL ADDL A, @RW4+d8 A, RL2 SUBL ADDL A, @RW3+d8 A, RL1 SUBL ADDL A, @RW2+d8 A, RL1 SUBL ADDL A, @RW1+d8 A, RL0 SUBL ADDL A, @RW0+d8 A, RL0 SUBL ADDL A, ADDL A, 30 SUBL A, @RW7+d8 @RW6+d8 SUBL A, @RW5+d8 SUBL A, @RW4+d8 SUBL A, @RW3+d8 SUBL A, @RW2+d8 SUBL A, @RW1+d8 SUBL A, @RW0+d8 SUBL A, SUBL A, A, @RW3+ addr16 A, @RW3+ addr16 A, @RW2+ @PC+d16 A, @RW2+ @PC+d16 SUBL SUBL A, ADDL ADDL A, A, @RW1+ @RW1+RW7 A, @RW1+ @RW1+RW7 SUBL SUBL A, ADDL ADDL A, A, @RW0+ @RW0+RW7 A, @RW0+ @RW0+RW7 SUBL SUBL A, ADDL A, ADDL A, @RW3 @RW3+d16 A, @RW3 @RW3+d16 SUBL SUBL A, ADDL A, ADDL A, @RW2 @RW2+d16 A, @RW2 @RW2+d16 SUBL SUBL A, ADDL ADDL A, A, @RW1 @RW1+d16 A, @RW1 @RW1+d16 SUBL SUBL A, ADDL A, ADDL A, @RW0 @RW0+d16 A, @RW0 @RW0+d16 SUBL SUBL A, ADDL A, ADDL A, RL3 ADDL A, RL3 ADDL A, RL2 ADDL A, RL2 ADDL A, RL1 ADDL A, RL1 ADDL A, RL0 ADDL A, RL0 ADDL ADDL Prohibit Prohibit Prohibit Prohibit CWBNE RW0, #16, rel CWBNE RW1, #16, rel CWBNE RW2, #16, rel CWBNE RW3, #16, rel CWBNE RW4, #16, rel CWBNE RW5, #16, rel CWBNE RW6, #16, rel CWBNE RW7, #16, rel CWBNE @ RW0, #16, rel CWBNE @ RW1, #16, rel CWBNE @ RW2, #16, rel CWBNE @ RW3, #16, rel 40 CWBNE @RW0+d8, #16, rel CWBNE @RW1+d8, #16, rel CWBNE @RW2+d8, #16, rel CWBNE @RW3+d8, #16, rel CWBNE @RW4+d8, #16, rel CWBNE @RW5+d8, #16, rel CWBNE @RW6+d8, #16, rel CWBNE @RW7+d8, #16, rel CWBNE @RW0+d16, #16, rel CWBNE @RW1, d16, #16, rel CWBNE @RW2+d16, #16, rel CWBNE @RW3+d16, #16, rel CWBNE @RW0+RW7 ,#16, rel CWBNE @RW1+RW7 ,#16, rel CWBNE @PC+d16, #16, rel CWBNE addr16, #16, rel 50 70 80 ANDL A, RL3 @RW7+d8 ANDL CMPL A, A, RL3 @RW6+d8 ANDL CMPL A, A, RL2 @RW5+d8 ANDL CMPL A, A, RL2 @RW4+d8 ANDL CMPL A, A, RL1 @RW3+d8 ANDL CMPL A, A, RL1 @RW2+d8 ANDL CMPL A, A, RL0 @RW1+d8 ANDL CMPL A, A, RL0 @RW0+d8 ANDL CMPL A, CMPL A, 90 A0 ORL A, RL3 @RW7+d8 ORL ANDL A, A, RL3 @RW6+d8 ORL ANDL A, A, RL2 @RW5+d8 ORL ANDL A, A, RL2 @RW4+d8 ORL ANDL A, A, RL1 @RW3+d8 ORL ANDL A, A, RL1 @RW2+d8 ORL ANDL A, A, RL0 @RW1+d8 ORL ANDL A, A, RL0 @RW0+d8 ORL ANDL A, ANDL A, B0 C0 XORL A, RL3 @RW7+d8 XORL ORL A, A, RL3 @RW6+d8 XORL ORL A, A, RL2 @RW5+d8 XORL ORL A, A, RL2 @RW4+d8 XORL ORL A, A, RL1 @RW3+d8 XORL ORL A, A, RL1 @RW2+d8 XORL ORL A, A, RL0 @RW1+d8 XORL ORL A, A, RL0 @RW0+d8 XORL ORL A, ORL A, D0 @RW7+d8 XORL A, @RW6+d8 XORL A, @RW5+d8 XORL A, @RW4+d8 XORL A, @RW3+d8 XORL A, @RW2+d8 XORL A, @RW1+d8 XORL A, @RW0+d8 XORL A, XORL A, A, @RW3+ addr16 A, @RW3+ addr16 A, @RW3+ addr16 A, @RW3+ addr16 @PC+d16 @PC+d16 A, @RW2+ @PC+d16 A, @RW2+ A, @RW2+ @PC+d16 A, @RW2+ XORL ORL ORL A, XORL A, ANDL ANDL A, CMPL CMPL A, A, @RW1+ @RW1+RW7 A, @RW1+ @RW1+RW7 A, @RW1+ @RW1+RW7 A, @RW1+ @RW1+RW7 ORL XORL XORL A, ORL A, ANDL ANDL A, CMPL CMPL A, A, @RW0+ @RW0+RW7 A, @RW0+ @RW0+RW7 A, @RW0+ @RW0+RW7 A, @RW0+ @RW0+RW7 ORL XORL XORL A, ANDL ANDL A, ORL A, CMPL CMPL A, A, @RW3 @RW3+d16 A, @RW3 @RW3+d16 A, @RW3 @RW3+d16 A, @RW3 @RW3+d16 XORL ORL XORL A, ORL A, ANDL ANDL A, CMPL CMPL A, A, @RW2 @RW2+d16 A, @RW2 @RW2+d16 A, @RW2 @RW2+d16 A, @RW2 @RW2+d16 ORL XORL XORL A, ORL A, ANDL ANDL A, CMPL CMPL A, A, @RW1 @RW1+d16 A, @RW1 @RW1+d16 A, @RW1 @RW1+d16 A, @RW1 @RW1+d16 XORL ORL XORL A, ANDL ANDL A, ORL A, CMPL CMPL A, A, @RW0 @RW0+d16 A, @RW0 @RW0+d16 A, @RW0 @RW0+d16 A, @RW0 @RW0+d16 XORL ORL XORL A, ORL A, ANDL ANDL A, CMPL CMPL A, A, RL3 CMPL A, RL3 CMPL A, RL2 CMPL A, RL2 CMPL A, RL1 CMPL A, RL1 CMPL A, RL0 CMPL A, RL0 CMPL CMPL 60 Table B.3.1e “ea” Instructions 1 (First byte = 70H) E0 Prohibit Prohibit Prohibit Prohibit CBNE R0, #8, rel CBNE R1, #8, rel CBNE R2, #8, rel CBNE R3, #8, rel CBNE R4, #8, rel CBNE R5, #8, rel CBNE R6, #8, rel CBNE R7, #8, rel CBNE @RW0, #8, rel CBNE @RW1, #8, rel CBNE @RW2, #8, rel CBNE @RW3, #8, rel F0 CBNE @RW0+d8, #8, rel CBNE @RW1+d8, #8, rel CBNE @RW2+d8, #8, rel CBNE @RW3+d8, #8, rel CBNE @RW4+d8, #8, rel CBNE @RW5+d8, #8, rel CBNE @RW6+d8, #8, rel CBNE @RW7+d8, #8, rel CBNE @RW0+d16, #8, rel CBNE @RW1+d16, #8, rel CBNE➲ @RW2+d16, #8, rel CBNE @RW3+d16, #8, rel CBNE @RW0+RW7 , #8, rel CBNE @RW1+RW7 #8, rel CBNE @PC+d16, #8, rel CBNE addr16, #8, rel B.3 Instruction Map MB90580 Series JMPP @@RW1+d8 JMPP @@RW2+d8 JMPP @@RW3+d8 JMPP @@RW4+d8 JMPP @@RW5+d8 JMPP @@RW6+d8 JMPP @@RW7+d8 JMPP @ @RW0+d16 JMPP @ @RW1+d16 JMPP @ @RW2+d16 JMPP @ @RW3+d16 JMPP @ CALLP CALLP @ @RW0+RW7 @@RW0+ @RW0+RW7 JMPP @ CALLP CALLP @ @RW1+RW7 @@RW1+ @RW1+RW7 JMPP @@PC+d16 JMPP @addr16 JMPP @RL0 JMPP @RL1 JMPP @RL1 JMPP @RL2 JMPP @RL2 JMPP @RL3 JMPP @RL3 JMPP @@RW0 JMPP @@RW1 JMPP @@RW2 JMPP @@RW3 JMPP @@RW0+ JMPP @@RW1+ JMPP @@RW2+ JMPP @@RW3+ +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F 30 MB90580 Series CALLP @@RW7+d8 CALLP @@RW6+d8 CALLP @@RW5+d8 CALLP @@RW4+d8 CALLP @@RW3+d8 CALLP @@RW2+d8 CALLP @@RW1+d8 CALLP @ @RW3+d16 CALLP @ @RW2+d16 CALLP @ @RW1+d16 CALLP CALLP @@RW3+ @addr16 CALLP CALLP @@RW2+ @@PC+d16 CALLP @@RW3 CALLP @@RW2 CALLP @@RW1 CALLP CALLP @ @@RW0 @RW0+d16 CALLP @RL3 CALLP @RL3 CALLP @RL2 CALLP @RL2 CALLP @RL1 CALLP @RL1 CALLP @RL0 CALLP @@RW0+d8 +0 20 CALLP @RL0 10 JMPP @@RW0+d8 00 JMPP @RL0 INCL @RW3+ INCL @RW2+ INCL @RW1+ INCL @RW0+ INCL @RW3 INCL @RW2 INCL @RW1 INCL @RW0 INCL RL3 INCL RL3 INCL RL2 INCL RL2 INCL RL1 INCL RL1 INCL RL0 INCL RL0 40 INCL addr16 INCL @PC+d16 INCL @RW1+RW7 INCL @RW0+RW7 INCL @RW3+d16 INCL @RW2+d16 INCL @RW1+d16 INCL @RW0+d16 INCL @RW7+d8 INCL @RW6+d8 INCL @RW5+d8 INCL @RW4+d8 INCL @RW3+d8 INCL @RW2+d8 INCL @RW1+d8 INCL @RW0+d8 50 DECL @RW3+ DECL @RW2+ DECL @RW1+ DECL @RW0+ DECL @RW3 DECL @RW2 DECL @RW1 DECL @RW0 DECL RL3 DECL RL3 DECL RL2 DECL RL2 DECL RL1 DECL RL1 DECL RL0 DECL RL0 60 DECL addr16 DECL @PC+d16 DECL @RW1+RW7 DECL @RW0+RW7 DECL @RW3+d16 DECL @RW2+d16 DECL @RW1+d16 DECL @RW0+d16 DECL @RW7+d8 DECL @RW6+d8 DECL @RW5+d8 DECL @RW4+d8 DECL @RW3+d8 DECL @RW2+d8 DECL @RW1+d8 DECL @RW0+d8 70 90 MOVL A, @RW7+d8 MOVL A, @RW6+d8 MOVL A, @RW5+d8 MOVL A, @RW4+d8 MOVL A, @RW3+d8 MOVL A, @RW2+d8 MOVL A, @RW1+d8 MOVL A, @RW0+d8 A0 MOVL RL3, A MOVL RL3, A MOVL RL2, A MOVL RL2, A MOVL RL1, A MOVL RL1, A MOVL RL0, A MOVL RL0, A B0 MOVL @R W7+d8, A MOVL @R W6+d8, A MOVL @R W5+d8, A MOVL @R W4+d8, A MOVL @R W3+d8, A MOVL @R W2+d8, A MOVL @R W1+d8, A MOVL @R W0+d8, A MOVL @RW3, A MOVL @RW2, A MOVL @RW1, A MOVL @R W3+d16, A MOVL @R W2+d16, A MOVL @R W1+d16, A C0 D0 MOV @R W7+d8, #8 MOV @R W6+d8, #8 MOV @R W5+d8, #8 MOV @R W4+d8, #8 MOV @R W3+d8, #8 MOV @R W2+d8, #8 MOV @R W1+d8, #8 MOV @R W0+d8, #8 MOV MOV @R @RW3, #8 W3+d16, #8 MOV MOV @R @RW2, #8 W2+d16, #8 MOV MOV @R @RW1, #8 W1+d16, #8 MOV MOV @R @RW0, #8 W0+d16, #8 MOV R7, #8 MOV R6, #8 MOV R5, #8 MOV R4, #8 MOV R3, #8 MOV R2, #8 MOV R1, #8 MOV R0, #8 E0 F0 MOVEA A, @RW7+d8 MOVEA A, @RW6+d8 MOVEA A, @RW5+d8 MOVEA A, @RW4+d8 MOVEA A, @RW3+d8 MOVEA A, @RW2+d8 MOVEA A, @RW1+d8 MOVEA A, @RW0+d8 MOVEA A, @RW3 MOVEA A, @RW2 MOVEA A, @RW1 MOVEA A, @RW3+d16 MOVEA A, @RW2+d16 MOVEA A, @RW1+d16 MOVEA MOVEA A, A, @RW0 @RW0+d16 MOVEA A, RW7 MOVEA A, RW6 MOVEA A, RW5 MOVEA A, RW4 MOVEA A, RW3 MOVEA A, RW2 MOVEA A, RW1 MOVEA A, RW0 MOVL MOVL A, A, @RW3+ addr16 MOVL MOVL A, A, @RW2+ @PC+d16 MOVL MOVL @RW3+, A addr16, A MOV MOV @RW3+, #8 addr16, #8 MOVL MOV MOVL @P MOV @P @RW2+, A C+d16, A @RW2+, #8 C+d16, #8 MOVEA MOVEA A, A, @RW3+ addr16 MOVEA MOVEA A, A, @RW2+ @PC+d16 MOVL MOVL MOV MOVEA MOVL A, MOVL @R MOV @R MOVEA A, A, @RW1+ @RW1+RW7 @RW1+, A W1+RW7, A @RW1+, #8 W1+RW7, #8 A, @RW1+ @RW1+RW7 MOVL MOVL MOV MOVEA MOVL A, MOVL @R MOV @R MOVEA A, A, @RW0+ @RW0+RW7 @RW0+, A W0+RW7, A @RW0+, #8 W0+RW7, #8 A, @RW0+ @RW0+RW7 MOVL MOVL A, A,@ RW3 @RW3+d16 MOVL MOVL A, A, @RW2 @RW2+d16 MOVL MOVL A, A, @RW1 @RW1+d16 MOVL MOVL MOVL A, MOVL @R A, @RW0 @RW0+d16 @RW0, A W0+d16, A MOVL A, RL3 MOVL A, RL3 MOVL A, RL2 MOVL A, RL2 MOVL A, RL1 MOVL A, RL1 MOVL A, RL0 MOVL A, RL0 80 Table B.3.1f “ea” Instructions 22 (First byte = 71H) B.3 Instruction Map APPENDIX B: Instructions 341 342 ROLC @RW2+d8 ROLC @RW3+d8 ROLC @RW4+d8 ROLC @RW5+d8 ROLC @RW6+d8 ROLC @RW7+d8 ROLC @RW0+d16 ROLC @RW1+d16 ROLC @RW2+d16 ROLC @RW3+d16 ROLC RORC @RW0+RW7 @RW0+ ROLC RORC @RW1+RW7 @RW1+ ROLC @PC+d16 ROLC addr16 ROLC R2 ROLC R3 ROLC R4 ROLC R5 ROLC R6 ROLC R7 ROLC @RW0 ROLC @RW1 ROLC @RW2 ROLC @RW3 ROLC @RW0+ ROLC @RW1+ ROLC @RW2+ ROLC @RW3+ +2 +3 +4 +5 APPENDIX B: Instructions +6 +7 +8 +9 +A +B +C +D +E +F RORC @RW3+ RORC @RW2+ RORC @RW3 RORC @RW2 RORC @RW1 RORC @RW0 RORC R7 RORC R6 RORC R5 RORC R4 RORC R3 RORC R2 RORC R1 ROLC @RW1+d8 ROLC R1 +1 20 RORC R0 +0 10 ROLC @RW0+d8 00 ROLC R0 30 RORC addr16 RORC @PC+d16 RORC @RW1+RW7 RORC @RW0+RW7 RORC @RW3+d16 RORC @RW2+d16 RORC @RW1+d16 RORC @RW0+d16 RORC @RW7+d8 RORC @RW6+d8 RORC @RW5+d8 RORC @RW4+d8 RORC @RW3+d8 RORC @RW2+d8 RORC @RW1+d8 RORC @RW0+d8 INC @RW3+ INC @RW2+ INC @RW1+ INC @RW0+ INC @RW3 INC @RW2 INC @RW1 INC @RW0 INC R7 INC R6 INC R5 INC R4 INC R3 INC R2 INC R1 INC R0 40 INC addr16 INC @PC+d16 INC @RW1+RW7 INC @RW0+RW7 INC @RW3+d16 INC @RW2+d16 INC @RW1+d16 INC @RW0+d16 INC @RW7+d8 INC @RW6+d8 INC @RW5+d8 INC @RW4+d8 INC @RW3+d8 INC @RW2+d8 INC @RW1+d8 INC @RW0+d8 50 DEC @RW3+ DEC @RW2+ DEC @RW1+ DEC @RW0+ DEC @RW3 DEC @RW2 DEC @RW1 DEC @RW0 DEC R7 DEC R6 DEC R5 DEC R4 DEC R3 DEC R2 DEC R1 DEC R0 60 DEC addr16 DEC @PC+d16 DEC @RW1+RW7 DEC @RW0+RW7 DEC @RW3+d16 DEC @RW2+d16 DEC @RW1+d16 DEC @RW0+d16 DEC @RW7+d8 DEC @RW6+d8 DEC @RW5+d8 DEC @RW4+d8 DEC @RW3+d8 DEC @RW2+d8 DEC @RW1+d8 DEC @RW0+d8 70 90 MOV A, @RW7+d8 MOV A, @RW6+d8 MOV A, @RW5+d8 MOV A, @RW4+d8 MOV A, @RW3+d8 MOV A, @RW2+d8 MOV A, @RW1+d8 MOV A, @RW0+d8 A0 MOV R7, A MOV R6, A MOV R5, A MOV R4, A MOV R3, A MOV R2, A MOV R1, A MOV R0, A B0 MOV @R W7+d8, A MOV @R W6+d8, A MOV @R W5+d8, A MOV @R W4+d8, A MOV @R W3+d8, A MOV @R W2+d8, A MOV @R W1+d8, A MOV @R W0+d8, A MOV @RW3, A MOV @RW2, A MOV @RW1, A MOV @R W3+d16, A MOV @R W2+d16, A MOV @R W1+d16, A C0 MOVX A, @RW3 MOVX A, @RW2 MOVX A, @RW1 MOVX A, @RW0 MOVX A, R7 MOVX A, R6 MOVX A, R5 MOVX A, R4 MOVX A, R3 MOVX A, R2 MOVX A, R1 MOVX A, R0 D0 E0 F0 XCH A, @RW7+d8 XCH A, @RW6+d8 XCH A, @RW5+d8 XCH A, @RW4+d8 XCH A, @RW3+d8 XCH A, @RW2+d8 XCH A, @RW1+d8 XCH A, @RW0+d8 XCH MOVX A, A, @RW3 @RW3+d16 XCH MOVX A, A, @RW2 @RW2+d16 XCH MOVX A, A, @RW1 @RW1+d16 XCH A, @RW3+d16 XCH A, @RW2+d16 XCH A, @RW1+d16 XCH MOVX A, XCH A, A, @RW0 @RW0+d16 @RW0+d16 XCH MOVX A, A, R7 @RW7+d8 XCH MOVX A, A, R6 @RW6+d8 XCH MOVX A, A, R5 @RW5+d8 XCH MOVX A, A, R4 @RW4+d8 XCH MOVX A, A, R3 @RW3+d8 XCH MOVX A, A, R2 @RW2+d8 XCH MOVX A, A, R1 @RW1+d8 XCH MOVX A, A, R0 @RW0+d8 MOV MOV A, A, @RW3+ addr16 MOV MOV A, A, @RW2+ @PC+d16 MOV MOV @RW3+, A addr16, A MOV MOV @P @RW2+, A C+d16, A MOVX A, @RW3+ MOVX A, @RW2+ MOVX A, addr16 MOVX A, @PC+d16 XCH XCH A, A, @RW3+ addr16 XCH XCH A, A, @RW2+ @PC+d16 MOV MOV MOVX XCH MOV A, MOV @R MOVX A, XCH A, A, @RW1+ @RW1+RW7 @RW1+, A W1+RW7, A A, @RW1+ @RW1+RW7 A, @RW1+ @RW1+RW7 MOV MOV MOVX XCH MOV A, MOV @R MOVX A, XCH A, A, @RW0+ @RW0+RW7 @RW0+, A W0+RW7, A A, @RW0+ @RW0+RW7 A, @RW0+ @RW0+RW7 MOV MOV A, A, @RW3 @RW3+d16 MOV MOV A, A, @RW2 @RW2+d16 MOV MOV A, A, @RW1 @RW1+d16 MOV MOV MOV A, MOV @R A, @RW0 @RW0+d16 @RW0, A W0+d16, A MOV A, R7 MOV A, R6 MOV A, R5 MOV A, R4 MOV A, R3 MOV A, R2 MOV A, R1 MOV A, R0 80 Table B.3.1g “ea” Instructions 3 (First byte = 72H) B.3 Instruction Map MB90580 Series INCW INCW @RW3 @RW3+d16 INCW INCW @RW0+ @RW0+RW7 INCW INCW @RW1+ @RW1+RW7 INCW INCW @RW2+ @PC+d16 CALL CALL @@RW0 @@RW0+d16 CALL @@RW3+d16 CALL @@RW1 CALL @@RW2 CALL @@RW3 JMP @@RW3+d8 JMP @@RW4+d8 JMP @@RW5+d8 JMP @@RW6+d8 JMP @@RW7+d8 JMP @RW3 JMP @RW4 JMP @RW5 JMP @RW6 JMP @RW7 JMP JMP @@RW0 @@RW0+d16 JMP JMP @@RW1 @@RW1+d16 JMP JMP @@RW2 @@RW2+d16 JMP JMP @@RW3 @@RW3+d16 JMP JMP CALL CALL @ @@RW1+ @@RW1+RW7 @@RW1+ @RW1+RW7 CALL CALL @@RW3+ @addr16 JMP @@RW2+d8 JMP @RW2 JMP JMP CALL CALL @ @@RW0+ @@RW0+RW7 @@RW0+ @RW0+RW7 CALL CALL @@RW2+ @@PC+d16 JMP @@RW1+d8 MB90580 Series JMP JMP @@RW2+ @@PC+d16 JMP JMP @@RW3+ @addr16 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F CALL @RW7 CALL @RW6 CALL @RW5 CALL @RW4 CALL @RW3 CALL @RW2 CALL @RW1 CALL @@RW2+d16 CALL @@RW1+d16 CALL @@RW7+d8 CALL @@RW6+d8 CALL @@RW5+d8 CALL @@RW4+d8 CALL @@RW3+d8 CALL @@RW2+d8 CALL @@RW1+d8 INCW @RW7+d8 INCW @RW6+d8 INCW @RW5+d8 INCW @RW4+d8 INCW @RW3+d8 INCW @RW2+d8 INCW @RW1+d8 INCW INCW @RW3+ addr16 INCW INCW @RW2 @RW2+d16 INCW INCW @RW1 @RW1+d16 INCW INCW @RW0 @RW0+d16 INCW RW7 INCW RW6 INCW RW5 INCW RW4 INCW RW3 INCW RW2 INCW RW1 50 INCW @RW0+d8 JMP @RW1 40 INCW RW0 +1 30 CALL @@RW0+d8 +0 20 CALL @RW0 10 JMP @@RW0+d8 00 JMP @RW0 DECW @RW3+ DECW @RW2+ DECW @RW1+ DECW @RW0+ DECW @RW3 DECW @RW2 DECW @RW1 DECW @RW0 DECW RW7 DECW RW6 DECW RW5 DECW RW4 DECW RW3 DECW RW2 DECW RW1 DECW RW0 60 DECW addr16 DECW @PC+d16 DECW @RW1+RW7 DECW @RW0+RW7 DECW @RW3+d16 DECW @RW2+d16 DECW @RW1+d16 DECW @RW0+d16 DECW @RW7+d8 DECW @RW6+d8 DECW @RW5+d8 DECW @RW4+d8 DECW @RW3+d8 DECW @RW2+d8 DECW @RW1+d8 DECW @RW0+d8 70 90 A0 MOVW RW7, A MOVW RW6, A MOVW RW5, A MOVW RW4, A MOVW RW3, A MOVW RW2, A MOVW RW1, A MOVW RW0, A B0 C0 D0 MOVW @R MOVW MOVW @RW RW7, #16 7+d8, #16 W7+d8, A MOVW @R MOVW MOVW @RW RW6, #16 6+d8, #16 W6+d8, A MOVW @R MOVW MOVW @RW RW5, #16 5+d8, #16 W5+d8, A MOVW @R MOVW MOVW @RW RW4, #16 4+d8, #16 W4+d8, A MOVW @R MOVW MOVW @RW RW3, #16 3+d8, #16 W3+d8, A MOVW @R MOVW MOVW @RW RW2, #16 2+d8, #16 W2+d8, A MOVW @R MOVW MOVW @RW RW1, #16 1+d8, #16 W1+d8, A MOVW @R MOVW MOVW @RW RW0, #16 0+d8, #16 W0+d8, A E0 XCHW A, RW7 XCHW A, RW6 XCHW A, RW5 XCHW A, RW4 XCHW A, RW3 XCHW A, RW2 XCHW A, RW1 XCHW A, RW0 F0 XCHW A, @RW7+d8 XCHW A, @RW6+d8 XCHW A, @RW5+d8 XCHW A, @RW4+d8 XCHW A, @RW3+d8 XCHW A, @RW2+d8 XCHW A, @RW1+d8 XCHW A, @RW0+d8 MOVW @RW3, A MOVW @RW2, A MOVW @RW1. A MOVW @R MOVW MOVW @RW3 XCHW @RW3, #16 +d16, #16 A, @RW3 W3+d16, A MOVW @R MOVW MOVW@ RW2 XCHW @RW2, #16 +d16, #16 A, @RW2 W2+d16, A MOVW @R MOVW MOVW@RW1 XCHW @RW1, #16 +d16, #16 A, @RW1 W1+d16, A XCHW A, @RW3+d16 XCHW A, @RW2+d16 XCHW A, @RW1+d16 MOVW MOVW A, A, @RW3+ addr16 MOVW MOVW A, A, @RW2+ @PC+d16 MOVW MOVW @RW3+, A addr16, A MOVW @ MOVW ad RW3+, #16 dr16, #16 XCHW XCHW A, A, @RW3+ addr16 MOVW MOVW @P MOVW @ MOVW @PC XCHW XCHW A, @RW2+, A C+d16, A RW2+, #16 +d16, #16 A, @RW2+ @PC+d16 MOVW MOVW MOVW A, MOVW @R MOVW @ MOVW @RW1 XCHW XCHW A, A, @RW1+ @RW1+RW7 @RW1+, A W1+RW7, A RW1+, #16 +RW7, #16 A, @RW1+ @RW1+RW7 MOVW MOVW MOVW A, MOVW @R MOVW @ MOVW@RW0 XCHW XCHW A, A, @RW0+ @RW0+RW7 @RW0+, A W0+RW7, A RW0+, #16 +RW7, #16 A, @RW0+ @RW0+RW7 MOVW MOVW A, A, @RW3 @RW3+d16 MOVW MOVW A, A, @RW2 @RW2+d16 MOVW MOVW A, A, @RW1 @RW1+d16 MOVW MOVW MOVW A, MOVW @R MOVW MOVW@RW0 XCHW XCHW A, A, @RW0 @RW0+d16 @RW0, A W0+d16, A @RW0, #16 +d16, #16 A, @RW0 @RW0+d16 MOVW MOVW A, A, RW7 @RW7+d8 MOVW MOVW A, A, RW6 @RW6+d8 MOVW MOVW A, A, RW5 @RW5+d8 MOVW MOVW A, A, RW4 @RW4+d8 MOVW MOVW A, A, RW3 @RW3+d8 MOVW MOVW A, A, RW2 @RW2+d8 MOVW MOVW A, A, RW1 @RW1+d8 MOVW MOVW A, A, RW0 @RW0+d8 80 Table B.3.1h “ea” Instructions 4 (First byte = 73H) B.3 Instruction Map APPENDIX B: Instructions 343 344 SUB SUB A, A, @RW0 @RW0+d16 SUB SUB A, A, @RW1 @RW1+d16 SUB SUB A, A, @RW3 @RW3+d16 SUB SUB A, A, @RW0+ @RW0+RW7 SUB SUB A, A, @RW1+ @RW1+RW7 SUB SUB A, A, @RW2+ @PC+d16 SUB SUB A, A, @RW3+ addr16 ADD A, @RW1+d8 ADD A, @RW2+d8 ADD A, @RW3+d8 ADD A, @RW4+d8 ADD A, @RW5+d8 ADD A, @RW6+d8 ADD A, @RW7+d8 ADD A, @RW2+d16 ADD A, @RW3+d16 ADD A, R2 ADD A, R3 ADD A, R4 ADD A, R5 ADD A, R6 ADD A, R7 ADD ADD A, A, @RW0 @RW0+d16 ADD A, @RW1+d16 ADD A, R1 ADD A, @RW1 ADD A, @RW2 ADD A, @RW3 ADD ADD A, A, @RW0+ @RW0+RW7 ADD ADD A, A, @RW1+ @RW1+RW7 ADD ADD A, A, @RW2+ @PC+d16 ADD ADD A, A, @RW3+ addr16 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F 30 APPENDIX B: Instructions SUB A, @RW7+d8 SUB A, @RW6+d8 SUB A, @RW5+d8 SUB A, @RW4+d8 SUB A, @RW3+d8 SUB A, @RW2+d8 SUB A, @RW1+d8 SUB SUB A, A, @RW2 @RW2+d16 SUB A, R7 SUB A, R6 SUB A, R5 SUB A, R4 SUB A, R3 SUB A, R2 SUB A, R1 SUB A, @RW0+d8 +0 20 SUB A, R0 10 ADD A, @RW0+d8 00 ADD A, R0 50 ADDC A, @RW3+d16 ADDC A, @RW2+d16 ADDC A, @RW1+d16 ADDC A, @RW0+d16 ADDC A, @RW7+d8 ADDC A, @RW6+d8 ADDC A, @RW5+d8 ADDC A, @RW4+d8 ADDC A, @RW3+d8 ADDC A, @RW2+d8 ADDC A, @RW1+d8 ADDC A, @RW0+d8 ADDC ADDC A, @RW3+ addr16 A, ADDC ADDC A, A, @RW2+ @PC+d16 ADDC ADDC A, A, @RW1+ @RW1+RW7 ADDC ADDC A, A, @RW0+ @RW0+RW7 ADDC A, @RW3 ADDC A, @RW2 ADDC A, @RW1 ADDC A, @RW0 ADDC A. R7 ADDC A, R6 ADDC A, R5 ADDC A, R4 ADDC A, R3 ADDC A, R2 ADDC A, R1 ADDC A, R0 40 70 CMP A, @RW7+d8 CMP A, @RW6+d8 CMP A, @RW5+d8 CMP A, @RW4+d8 CMP A, @RW3+d8 CMP A, @RW2+d8 CMP A, @RW1+d8 CMP A, @RW0+d8 CMP CMP A, A, @RW3+ addr16 CMP CMP A, A, @RW2+ @PC+d16 CMP CMP A, A, @RW1+ @RW1+RW7 CMP CMP A, A, @RW0+ @RW0+RW7 CMP CMP A, A, @RW3 @RW3+d16 CMP CMP A, A, @RW2 @RW2+d16 CMP CMP A, A, @RW1 @RW1+d16 CMP CMP A, A, @RW0 @RW0+d16 CMP A, R7 CMP A, R6 CMP A, R5 CMP A, R4 CMP A, R3 CMP A, R2 CMP A, R1 CMP A, R0 60 90 AND A, @RW7+d8 AND A, @RW6+d8 AND A, @RW5+d8 AND A, @RW4+d8 AND A, @RW3+d8 AND A, @RW2+d8 AND A, @RW1+d8 AND A, @RW0+d8 OR OR OR OR OR OR OR A, R7 A, R6 A, R5 A, R4 A, R3 A, R2 A, R1 A, R0 A0 OR B0 C0 OR A, XOR A, R7 @RW7+d8 OR A, XOR A, R6 @RW6+d8 OR A, XOR A, R5 @RW5+d8 OR A, XOR A, R4 @RW4+d8 OR A, XOR A, R3 @RW3+d8 OR A, XOR A, R2 @RW2+d8 OR A, XOR A, R1 @RW1+d8 OR A, XOR A, R0 @RW0+d8 OR A, @RW3 OR A, @RW2 OR A, @RW1 OR A, XOR A, @RW3 @RW3+d16 OR A, XOR A, @RW2 @RW2+d16 OR A, XOR A, @RW1 @RW1+d16 AND AND A, A, @RW3+ addr16 AND AND A, A, @RW2+ @PC+d16 OR OR A, A, @RW3+ addr16 OR OR A, A, @RW2+ @ PC+d16 XOR A, @RW3+ XOR A, @RW2+ AND AND A, OR OR A, XOR A, @RW1+ @RW1+RW7 A, @RW1+ @RW1+RW7 A, @RW1+ AND AND A, OR OR A, XOR A, @RW0+ @RW0+RW7 A, @RW0+ @RW0+RW7 A, @RW0+ AND AND A, A, @RW3 @RW3+d16 AND AND A, A, @RW2 @RW2+d16 AND AND A, A, @RW1 @RW1+d16 AND AND A, OR OR A, XOR A, @RW0 @RW0+d16 A, @RW0 @RW0+d16 A, @RW0 AND A, R7 AND A, R6 AND A, R5 AND A, R4 AND A, R3 AND A, R2 AND A, R1 AND A, R0 80 Table B.3.1i “ea” Instructions 5 (First byte = 74H) D0 E0 F0 DBNZ RW3+d16, r DBNZ RW2+d16, r DBNZ RW1+d16, r DBNZ RW0+d16, r XOR addr16 A, XOR A, @PC+d16 DBNZ DBNZ @RW3+, r @ addr16, r DBNZ DBNZ @RW2+, r @ PC+d16, r XOR A, DBNZ DBNZ @RW1+RW7 @RW1+, r RW1+RW7, r XOR A, DBNZ DBNZ @RW0+RW7 @RW0+, r RW0+RW7, r XOR A, DBNZ @RW3, r @RW3+d16 XOR A, DBNZ @RW2, r @RW2+d16 XOR A, DBNZ @RW1, r @RW1+d16 XOR A, DBNZ @RW0, r @RW0+d16 XOR A, DBNZ DBNZ @ R7, r RW7+d8, r @RW7+d8 XOR A, DBNZ DBNZ @ R6, r RW6+d8, r @RW6+d8 XOR A, DBNZ DBNZ @ R5, r RW5+d8, r @RW5+d8 XOR A, DBNZ DBNZ @ R4, r RW4+d8, r @RW4+d8 XOR A, DBNZ DBNZ @ R3, r RW3+d8, r @RW3+d8 XOR A, DBNZ DBNZ @ R2, r RW2+d8, r @RW2+d8 XOR A, DBNZ DBNZ @ R1, r RW1+d8, r @RW1+d8 XOR A, DBNZ DBNZ @ R0, r RW0+d8, r @RW0+d8 B.3 Instruction Map MB90580 Series MB90580 Series SUBC SUBC A, A, @RW0 @RW0+d16 SUBC SUBC A, A, @RW1 @RW1+d16 SUBC SUBC A, A, @RW2 @RW2+d16 SUBC SUBC A, A, @RW3 @RW3+d16 SUBC SUBC A, A, @RW0+ @RW0+RW7 SUBC SUBC A, A, @RW1+ @RW1+RW7 SUBC SUBC A, A, @RW2+ @PC+d16 SUBC SUBC A, @RW3+ addr16 SUB @R W2+d8, A SUB @R W3+d8, A SUB @R W4+d8, A SUB @R W5+d8, A SUB @R W6+d8, A SUB @R W7+d8, A ADD @R SUB W2+d8, A R2, A ADD @R SUB W3+d8, A R3, A ADD @R SUB W4+d8, A R4, A ADD @R SUB W5+d8, A R5, A ADD @R SUB W6+d8, A R6, A ADD @R SUB W7+d8, A R7, A ADD @R SUB SUB @R RW2+d16, A @RW2, A W2+d16, A ADD @R SUB SUB @R RW3+d16, A @RW3, A W3+d16, A ADD R3, A ADD R4, A ADD R5, A ADD R6, A ADD R7, A ADD @R SUB ADD SUB @R @RW0, A W0+d16, A @RW0, A W0+d16, A ADD @R SUB SUB @R W1+d16, A @RW1, A W1+d16, A ADD R2, A ADD @RW1, A ADD @RW2, A ADD @RW3, A ADD ADD @R SUB SUB @R @RW0+, A W0+RW7, A @RW0+, A W0+RW7, A ADD ADD @R SUB SUB @R @RW1+, A W1+RW7, A @RW1+, A W1+RW7, A ADD @P SUB ADD SUB @P @RW2+, A C+d16, A @RW2+, A C+d16, A ADD ADD SUB SUB @RW3+, A addr16, A @RW3+, A addr16, A +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F SUBC A, R7 SUBC A, R6 SUBC A, R5 SUBC A, R4 SUBC A, R3 SUBC A, R2 A, SUBC A, @RW7+d8 SUBC A, @RW6+d8 SUBC A, @RW5+d8 SUBC A, @RW4+d8 SUBC A, @RW3+d8 SUBC A, @RW2+d8 SUBC A, @RW1+d8 +2 SUBC A, R1 SUB @R W1+d8, A ADD @R SUB W1+d8, A R1, A SUBC A, @RW0+d8 50 ADD R1, A SUBC A, R0 40 +1 SUB @R W0+d8, A 30 ADD @R SUB W0+d8, A R0, A 20 ADD R0, A 10 +0 00 NEG @RW3+ NEG @RW2+ NEG @RW1+ NEG @RW0+ NEG @RW3 NEG @RW2 NEG @RW1 NEG @RW0 NEG R7 NEG R6 NEG R5 NEG R4 NEG R3 NEG R2 NEG R1 NEG R0 60 NEG addr16 NEG @PC+d16 NEG @RW1+RW7 NEG @RW0+RW7 NEG @RW3+d16 NEG @RW2+d16 NEG @RW1+d16 NEG @RW0+d16 NEG @RW7+d8 NEG @RW6+d8 NEG @RW5+d8 NEG @RW4+d8 NEG @RW3+d8 NEG @RW2+d8 NEG @RW1+d8 NEG @RW0+d8 70 A0 AND @R OR R7, A W7+d8, A AND @R OR R6, A W6+d8, A AND @R OR R5, A W5+d8, A AND @R OR R4, A W4+d8, A AND @R OR R3, A W3+d8, A AND @R OR R2, A W2+d8, A AND @R OR R1, A W1+d8, A AND @R OR R0, A W0+d8, A 90 OR @RW7+d8, A OR @RW6+d8, A OR @RW5+d8, A OR @RW4+d8, A OR @RW3+d8, A OR @RW2+d8, A OR @RW1+d8, A OR @RW0+d8, A B0 XOR XOR XOR XOR XOR XOR XOR XOR R7, A R6, A R5, A R4, A R3, A R2, A R1, A R0, A C0 AND AND @RW3+, A addr16, A OR OR @RW3+, A addr16, A AND AND @P OR OR @RW2+, A @RW2+, A @PC+d16, A C+d16, A AND AND @R OR OR @R @RW1+, A W1+RW7, A @RW1+, A W1+RW7, A XOR @RW3+, A XOR @RW2+, A XOR @RW1+, A XOR @RW0+, A XOR AND @R OR OR @RW3, A @RW3+d16, A @RW3, A W3+d16, A XOR AND @R OR OR @RW2, A @RW2+d16, A @RW2, A W2+d16, A XOR AND @R OR OR @RW1, A @RW1+d16, A @RW1, A W1+d16, A AND AND @R OR OR @R @RW0+, A W0+RW7, A @RW0+, A W0+RW7, A AND @RW3, A AND @RW2, A AND @RW1, A AND XOR AND @R OR OR @RW0, A W0+d16, A @RW0, A @RW0+d16, A @RW0, A AND R7, A AND R6, A AND R5, A AND R4, A AND R3, A AND R2, A AND R1, A AND R0, A 80 Table B.3.1j “ea” Instructions 6 (First byte = 75H) NOT @RW3+ NOT addr16 NOT @PC+d16 XOR @P NOT @RW2+ C+d16, A XOR addr16, A NOT @RW1+RW7 NOT @RW0+RW7 NOT @RW3+d16 NOT @RW2+d16 NOT @RW1+d16 NOT @RW0+d16 NOT @RW7+d8 NOT @RW6+d8 NOT @RW5+d8 NOT @RW4+d8 NOT @RW3+d8 NOT @RW2+d8 XOR @R NOT W1+RW7, A @RW1+ XOR @R NOT W0+RW7, A @RW0+ XOR @R NOT @RW3 W3+d16, A XOR @R NOT @RW2 W2+d16, A XOR @R NOT @RW1 W1+d16, A XOR @R NOT @RW0 W0+d16, A XOR @R NOT R7 W7+d8, A XOR @R NOT R6 W6+d8, A XOR @R NOT R5 W5+d8, A XOR @R NOT R4 W4+d8, A XOR @R NOT R3 W3+d8, A XOR @R NOT R2 W2+d8, A NOT @RW1+d8 XOR @R NOT R1 W1+d8, A F0 NOT @RW0+d8 E0 XOR @R NOT R0 W0+d8, A D0 B.3 Instruction Map APPENDIX B: Instructions 345 346 ADDCW ADDCW A, A, RW7 @RW7+d8 ADDCW ADDCW A, A, @RW0 @RW0+d16 ADDCW ADDCW A, A, @RW1 @RW1+d16 SUBW SUBW A, A, RW7 @RW7+d8 SUBW SUBW A, A, @RW0+ @RW0+RW7 SUBW SUBW A, A, @RW1+ @RW1+RW7 SUBW SUBW A, A, @RW2+ @PC+d16 SUBW SUBW A, A, @RW3+ addr16 ADDW A, @RW2+d8 ADDW A, @RW3+d8 ADDW A, @RW4+d8 ADDW A, @RW5+d8 ADDW A, @RW6+d8 ADDW A, @RW7+d8 ADDW A, @RW1+d16 ADDW A, @RW2+d16 ADDW A, @RW3+d16 ADDW A, RW2 ADDW A, RW3 ADDW A, RW4 ADDW A, RW5 ADDW A, RW6 ADDW A, RW7 ADDW ADDW A, SUBW SUBW A, A, @RW0 @RW0+d16 A, @RW0 @RW0+d16 SUBW SUBW A, A, @RW3 @RW3+d16 ADDW A, @RW1+d8 ADDW A, RW1 ADDW A, @RW1 ADDW A, @RW2 ADDW A, @RW3 ADDW ADDW A, A, @RW0+ @RW0+RW7 ADDW ADDW A, A, @RW1+ @RW1+RW7 ADDW ADDW A, A, @RW2+ @PC+d16 ADDW ADDW A, A, @RW3+ addr16 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F 50 +1 40 APPENDIX B: Instructions SUBW SUBW A, A, @RW2 @RW2+d16 SUBW SUBW A, A, @RW1 @RW1+d16 SUBW SUBW A, A, RW6 @RW6+d8 SUBW SUBW A, A, RW5 @RW5+d8 SUBW SUBW A, A, RW4 @RW4+d8 SUBW SUBW A, A, RW3 @RW3+d8 SUBW SUBW A, A, RW2 @RW2+d8 SUBW SUBW A, A, RW1 @RW1+d8 ADDCW ADDCW A, @RW3+ addr16 A, ADDCW ADDCW A, A, @RW2+ @PC+d16 ADDCW ADDCW A, A, @RW1+ @RW1+RW7 ADDCW ADDCW A, A, @RW0+ @RW0+RW7 ADDCW ADDCW A, A, @RW3 @RW3+d16 ADDCW ADDCW A, A, @RW2 @RW2+d16 ADDCW ADDCW A, A, RW6 @RW6+d8 ADDCW ADDCW A, A, RW5 @RW5+d8 ADDCW ADDCW A, A, RW4 @RW4+d8 ADDCW ADDCW A, A, RW3 @RW3+d8 ADDCW ADDCW A, A, RW2 @RW2+d8 ADDCW ADDCW A, A, RW1 @RW1+d8 ADDCW ADDCW A, A, RW0 @RW0+d8 +0 30 SUBW SUBW A, A, RW0 @RW0+d8 10 ADDW A, @RW0+d8 00 ADDW A, RW0 20 70 CMPW CMPW A, @RW3+ addr16 A, CMPW CMPW A, A, @RW2+ @PC+d16 CMPW CMPW A, A, @RW1+ @RW1+RW7 CMPW CMPW A, A, @RW0+ @RW0+RW7 CMPW CMPW A, A, @RW3 @RW3+d16 CMPW CMPW A, A, @RW2 @RW2+d16 CMPW CMPW A, A, @RW1 @RW1+d16 CMPW CMPW A, A, @RW0 @RW0+d16 CMPW CMPW A, A, RW7 @RW7+d8 CMPW CMPW A, A, RW6 @RW6+d8 CMPW CMPW A, A, RW5 @RW5+d8 CMPW CMPW A, A, RW4 @RW4+d8 CMPW CMPW A, A, RW3 @RW3+d8 CMPW CMPW A, A, RW2 @RW2+d8 CMPW CMPW A, A, RW1 @RW1+d8 CMPW CMPW A, A, RW0 @RW0+d8 60 90 A0 B0 C0 ORW A, XORW @RW7+d8 A, RW7 ORW A, XORW @RW6+d8 A, RW6 ORW A, XORW @RW5+d8 A, RW5 ORW A, XORW @RW4+d8 A, RW4 ORW A, XORW @RW3+d8 A, RW3 ORW A, XORW @RW2+d8 A, RW2 ORW A, XORW @RW1+d8 A, RW1 ORW A, XORW @RW0+d8 A, RW0 ANDW ANDW A, ORW ORW A, @RW3+ addr16 A, @RW3+ addr16 A, XORW A, @RW3+ ANDW ANDW A, ORW ORW A, XORW A, @RW2+ @PC+d16 A, @RW2+ @ PC+d16 A, @RW2+ ANDW ANDW A, ORW ORW A, XORW A, @RW1+ @RW1+RW7 A, @RW1+ @RW1+RW7 A, @RW1+ ANDW ANDW A, ORW ORW A, XORW A, @RW0+ @RW0+RW7 A, @RW0+ @RW0+RW7 A, @RW0+ ANDW ANDW A, ORW ORW A, XORW A, @RW3 @RW3+d16 A, @RW3 @RW3+d16 A, @RW3 ANDW ANDW A, ORW ORW A, XORW A, @RW2 @RW2+d16 A, @RW2 @RW2+d16 A, @RW2 ANDW ANDW A, ORW ORW A, XORW A, @RW1 @RW1+d16 A, @RW1 @RW1+d16 A, @RW1 ANDW ANDW A, ORW ORW A, XORW A, @RW0 @RW0+d16 A, @RW0 @RW0+d16 A, @RW0 ANDW ANDW A, ORW A, RW7 @RW7+d8 A, RW7 ANDW ANDW A, ORW A, RW6 @RW6+d8 A, RW6 ANDW ANDW A, ORW A, RW5 @RW5+d8 A, RW5 ANDW ANDW A, ORW A, RW4 @RW4+d8 A, RW4 ANDW ANDW A, ORW A, RW3 @RW3+d8 A, RW3 ANDW ANDW A, ORW A, RW2 @RW2+d8 A, RW2 ANDW ANDW A, ORW A, RW1 @RW1+d8 A, RW1 ANDW ANDW A, ORW A, RW0 @RW0+d8 A, RW0 80 Table B.3.1k “ea” Instructions 7 (First byte = 76H) D0 E0 F0 DWBNZ @R W3+d16, r DWBNZ @R W2+d16, r DWBNZ @R W1+d16, r DWBNZ @R W0+d16, r XORW addr16 A, DWBNZ DWBNZ @RW3+, r addr16, r XORW A, DWBNZ DWBNZ @ @PC+d16 @RW2+, r PC+d16, r XORW A, DWBNZ DWBNZ @R @RW1+RW7 @RW1+, r W1+RW7, r XORW A, DWBNZ DWBNZ @R @RW0+RW7 @RW0+, r W0+RW7, r XORW A, DWBNZ @RW3+d16 @RW3, r XORW A, DWBNZ @RW2+d16 @RW2, r XORW A, DWBNZ @RW1+d16 @RW1, r XORW A, DWBNZ @RW0+d16 @RW0, r XORW A, DWBNZ DWBNZ @ @RW7+d8 RW7, r RW7+d8, r XORW A, DWBNZ DWBNZ @ @RW6+d8 RW6, r RW6+d8, r XORW A, DWBNZ DWBNZ @ @RW5+d8 RW5, r RW5+d8, r XORW A, DWBNZ DWBNZ @ @RW4+d8 RW4, r RW4+d8, r XORW A, DWBNZ DWBNZ @ @RW3+d8 RW3, r RW3+d8, r XORW A, DWBNZ DWBNZ @ @RW2+d8 RW2, r RW2+d8, r XORW A, DWBNZ DWBNZ @ @RW1+d8 RW1, r RW1+d8, r XORW A, DWBNZ DWBNZ @ @RW0+d8 RW0, r RW0+d8, r B.3 Instruction Map MB90580 Series MB90580 Series NEGW NEGW @RW3+ addr16 A, SUBCW SUBCW A, @RW3+ addr16 SUBW SUBW addr16, A @RW3+, A ADDW addr16, A ADDW @RW3+, A +F ANDW ANDW addr16, A @RW3+, A ORW ORW @RW3+, A addr16, A ANDW @P ORW ANDW @RW2+, A @RW2+, A C+d16, A XORW @RW3+, A XORW addr16, A NOTW @RW3+ NOTW addr16 NOTW @PC+d16 XORW @P NOTW C+d16, A @RW2+ ORW @P XORW C+d16, A @RW2+, A NEGW NEGW @RW2+ @PC+d16 SUBCW A, SUBCW A, @RW2+ @PC+d16 SUBW SUBW @RW2+, A @PC+d16, A ADDW @P C+d16, A ADDW @RW2+, A +E NOTW @RW1+RW7 XORW @R NOTW W1+RW7, A @RW1+ ORW @R XORW ANDW @R ORW ANDW W1+RW7, A @RW1+, A @RW1+, A W1+RW7, A @RW1+, A NEGW NEGW @RW1+ @RW1+RW7 SUBCW A, SUBCW A, @RW1+ @RW1+RW7 SUBW @R SUBW @RW1+, A W1+RW7, A ADDW @R W1+RW7 ADDW @RW1+, A +D NOTW @RW0+RW7 XORW @R NOTW W0+RW7, A @RW0+ ORW @R XORW W0+RW7, A @RW0+, A ANDW @R ORW ANDW @RW0+, A W0+RW7, A @RW0+, A NEGW NEGW @RW0+ @RW0+RW7 SUBCW A, SUBCW A, @RW0+ @RW0+RW7 SUBW @R SUBW @RW0+, A W0+RW7, A ADDW @R W0+RW7 ADDW @RW0+, A +C NOTW @RW3+d16 XORW @R NOTW W3+d16, A @RW3 ORW @RW3, A ORW @R XORW W3+d16, A @RW3, A ANDW @R ANDW @RW3, A W3+d16, A NEGW NEGW @RW3 @RW3+d16 SUBCW A, SUBCW A, @RW3 @RW3+d16 SUBW @R SUBW @RW3, A W3+d16, A ADDW @R W3+d16, A ADDW @RW3, A +B NOTW @RW2+d16 XORW @R NOTW W2+d16, A @RW2 ORW @R XORW W2+d16, A @RW2, A ORW @RW2, A ANDW @R ANDW @RW2, A W2+d16, A NEGW NEGW @RW2 @RW2+d16 SUBCW A, SUBCW A, @RW2 @RW2+d16 SUBW @R W2+d16, A SUBW @RW2, A ADDW @R W2+d16, A ADDW @RW2, A +A NOTW @RW1+d16 XORW @R NOTW W1+d16, A @RW1 ORW @R XORW W1+d16, A @RW1, A ORW @RW1, A ANDW @R ANDW @RW1, A W1+d16, A NEGW NEGW @RW1 @RW1+d16 SUBCW A, SUBCW A, @RW1 @RW1+d16 SUBW @R W1+d16, A SUBW @RW1, A ADDW @R W1+d16, A ADDW @RW1, A +9 NOTW @RW0+d16 XORW @R NOTW W0+d16, A @RW0 ORW @R XORW ORW W0+d16, A @RW0, A @RW0, A ANDW @R ANDW @RW0, A W0+d16, A NEGW NEGW @RW0 @RW0+d16 SUBCW A, SUBCW A, @RW0 @RW0+d16 SUBW @R W0+d16, A SUBW @RW0, A ADDW @R W0+d16, A ADDW @RW0, A +8 NOTW @RW7+d8 XORW @R NOTW W7+d8, A RW7 ORW @R XORW W7+d8, A RW7, A ORW RW7, A ANDW @R ANDW W7+d8, A RW7, A NEGW NEGW @RW7+d8 RW7 SUBCW A, @RW7+d8 SUBCW A,RW7 SUBW @R SUBW W7+d8, A RW7, A ADDW @R W7+d8, A ADDW RW7, A +7 NOTW @RW6+d8 XORW @R NOTW W6+d8, A RW6 ORW @R XORW W6+d8, A RW6, A ORW RW6, A ANDW @R ANDW W6+d8, A RW6, A NEGW NEGW @RW6+d8 RW6 SUBCW A, SUBCW @RW6+d8 A, RW6 SUBW @R SUBW W6+d8, A RW6, A ADDW @R W6+d8, A ADDW RW6, A +6 NOTW @RW5+d8 XORW @R NOTW W5+d8, A RW5 ORW @R XORW W5+d8, A RW5, A ORW RW5, A ANDW @R ANDW RW5, A W5+d8, A NEGW NEGW @RW5+d8 RW5 SUBCW A, SUBCW @RW5+d8 A, RW5 SUBW @R SUBW W5+d8, A RW5, A ADDW @R W5+d8, A ADDW RW5, A +5 NOTW @RW4+d8 XORW @R NOTW W4+d8, A RW4 ORW @R XORW W4+d8, A RW4, A ORW RW4, A ANDW @R ANDW W4+d8, A RW4, A NEGW NEGW @RW4+d8 RW4 SUBCW A, SUBCW @RW4+d8 A, RW4 SUBW @R SUBW W4+d8, A RW4, A ADDW @R W4+d8, A ADDW RW4, A +4 NOTW @RW3+d8 XORW @R NOTW W3+d8, A RW3 ORW @R XORW W3+d8, A RW3, A ORW RW3, A ANDW @R ANDW W3+d8, A RW3, A NEGW NEGW @RW3+d8 RW3 SUBCW A, SUBCW @RW3+d8 A, RW3 SUBW @R SUBW W3+d8, A RW3, A ADDW @R W3+d8, A ADDW RW3, A +3 NOTW @RW2+d8 XORW @R NOTW W2+d8, A RW2 ORW @R XORW W2+d8, A RW2, A OWR RW2, A ANDW @R ANDW W2+d8, A RW2, A NEGW NEGW @RW2+d8 RW2 SUBCW A, SUBCW @RW2+d8 A, RW2 SUBW @R SUBW W2+d8, A RW2, A ADDW @R W2+d8, A ADDW RW2, A +2 NOTW @RW1+d8 F0 XORW @R NOTW W1+d8, A RW1 E0 ORW @R XORW W1+d8, A RW1, A ORW RW1, A ANDW @R ANDW RW1, A W1+d8, A NEGW NEGW @RW1+d8 RW1 SUBCW A, SUBCW @RW1+d8 A, RW1 D0 NOTW @RW0+d8 SUBW @R SUBW W1+d8, A RW1, A C0 ADDW @R W1+d8, A B0 ADDW RW1, A A0 XORW @R NOTW W0+d8, A RW0 90 ORW @R XORW W0+d8, A RW0, A 80 +1 70 +0 60 ORW RW0, A 50 ANDW @R ANDW RW0, A W0+d8, A 40 NEGW NEGW @RW0+d8 RW0 30 SUBCW A, SUBCW @RW0+d8 A, RW0 20 SUBW @R SUBW W0+d8, A RW0, A 10 ADDW @R W0+d8, A 00 ADDW RW0, A Table B.3.1l “ea” Instructions 8 (First byte = 77H) B.3 Instruction Map APPENDIX B: Instructions 347 348 MULUW MULUW A, MUL MUL A, A, @RW0 @RW0+d16 A, @RW0 @RW0+d16 MULUW MULUW A, MUL A, @RW1 @RW1+d16 A, @RW1 MULUW MULUW A, MUL MUL A, A, @RW0+ @RW0+RW7 A, @RW0+ @RW0+RW7 MULUW MULUW A, MUL MUL A, A, @RW1+ @RW1+RW7 A, @RW1+ @RW1+RW7 MULUW MULUW A, MUL MUL A, A, @RW2+ @PC+d16 A, @RW2+ @PC+d16 MULUW MULUW A, MUL MUL A, A, @RW3+ addr16 A, @RW3+ addr16 MULU A, @RW1+d8 MULU A, @RW2+d8 MULU A, @RW3+d8 MULU A, @RW4+d8 MULU A, @RW5+d8 MULU A, @RW6+d8 MULU A, @RW7+d8 MULU A, @RW2+d16 MULU A, @RW3+d16 MULU A, R2 MULU A, R3 MULU A, R4 MULU A, R5 MULU A, R6 MULU A, R7 MULU MULU A, A, @RW0 @RW0+d16 MULU A, @RW1+d16 MULU A, R1 MULU A, @RW1 MULU A, @RW2 MULU A, @RW3 MULU MULU A, A, @RW0+ @RW0+RW7 MULU MULU A, A, @RW1+ @RW1+RW7 MULU MULU A, A, @RW2+ @PC+d16 MULU MULU A, A, @RW3+ addr16 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F 50 APPENDIX B: Instructions MULUW MULUW A, MUL A, @RW3 @RW3+d16 A, @RW3 MULUW MULUW A, MUL A, @RW2 @RW2+d16 A, @RW2 MULUW MULUW A, MUL A, RW7 @RW7+d8 A, R7 MULUW MULUW A, MUL A, RW6 @RW6+d8 A, R6 MULUW MULUW A, MUL A, RW5 @RW5+d8 A, R5 MULUW MULUW A, MUL A, RW4 @RW4+d8 A, R4 MULUW MULUW A, MUL A, RW3 @RW3+d8 A, R3 MULUW MULUW A, MUL A, RW2 @RW2+d8 A, R2 MULUW MULUW A, MUL A, RW1 @RW1+d8 A, R1 MUL A, @RW3+d16 MUL A, @RW2+d16 MUL A, @RW1+d16 MUL A, @RW7+d8 MUL A, @RW6+d8 MUL A, @RW5+d8 MUL A, @RW4+d8 MUL A, @RW3+d8 MUL A, @RW2+d8 MUL A, @RW1+d8 MUL A, @RW0+d8 +1 40 +0 30 MULUW MULUW A, MUL A, RW0 @RW0+d8 A, R0 10 MULU A, @RW0+d8 00 MULU A, R0 20 70 MULW MULW A, A, @RW3+ addr16 MULW MULW A, A, @RW2+ @PC+d16 MULW MULW A, A, @RW1+ @RW1+RW7 MULW MULW A, A, @RW0+ @RW0+RW7 MULW MULW A, A, @RW3 @RW3+d16 MULW MULW A, A, @RW2 @RW2+d16 MULW MULW A, A, @RW1 @RW1+d16 MULW MULW A, A, @RW0 @RW0+d16 MULW MULW A, A, RW7 @RW7+d8 MULW MULW A, A, RW6 @RW6+d8 MULW MULW A, A, RW5 @RW5+d8 MULW MULW A, A, RW4 @RW4+d8 MULW MULW A, A, RW3 @RW3+d8 MULW MULW A, A, RW2 @RW2+d8 MULW MULW A, A, RW1 @RW1+d8 MULW MULW A, A, RW0 @RW0+d8 60 90 DIVU A, @RW7+d8 DIVU A, @RW6+d8 DIVU A, @RW5+d8 DIVU A, @RW4+d8 DIVU A, @RW3+d8 DIVU A, @RW2+d8 DIVU A, @RW1+d8 DIVU A, @RW0+d8 A0 DIVUW A, RW7 DIVUW A, RW6 DIVUW A, RW5 DIVUW A, RW4 DIVUW A, RW3 DIVUW A, RW2 DIVUW A, RW1 DIVUW A, RW0 B0 C0 DIVUW A, DIV @RW7+d8 A, R7 DIVUW A, DIV @RW6+d8 A, R6 DIVUW A, DIV @RW5+d8 A, R5 DIVUW A, DIV @RW4+d8 A, R4 DIVUW A, DIV @RW3+d8 A, R3 DIVUW A, DIV @RW2+d8 A, R2 DIVUW A, DIV @RW1+d8 A, R1 DIVUW A, DIV @RW0+d8 A, R0 D0 E0 DIV A, DIVW @RW7+d8 A, RW7 DIV A, DIVW @RW6+d8 A, RW6 DIV A, DIVW @RW5+d8 A, RW5 DIV A, DIVW @RW4+d8 A, RW4 DIV A, DIVW @RW3+d8 A, RW3 DIV A, DIVW @RW2+d8 A, RW2 DIV A, DIVW @RW1+d8 A, RW1 DIV A, DIVW @RW0+d8 A, RW0 F0 DIVW A, @RW7+d8 DIVW A, @RW6+d8 DIVW A, @RW5+d8 DIVW A, @RW4+d8 DIVW A, @RW3+d8 DIVW A, @RW2+d8 DIVW A, @RW1+d8 DIVW A, @RW0+d8 DIVUW A, @RW3 DIVUW A, @RW2 DIVUW A, @RW1 DIVUW A, DIV DIV A, DIVW @RW3+d16 A, @RW3 @RW3+d16 A, @RW3 DIVUW A, DIV DIV A, DIVW @RW2+d16 A, @RW2 @RW2+d16 A, @RW2 DIVUW A, DIV DIV A, DIVW @RW1+d16 A, @RW1 @RW1+d16 A, @RW1 DIVW A, @RW3+d16 DIVW A, @RW2+d16 DIVW A, @RW1+d16 DIVU DIVU A, A, @RW3+ addr16 DIVU DIVU A, A, @RW2+ @PC+d16 DIVUW DIVUW A, @RW3+ addr16 A, DIV DIV A, A, @RW3+ addr16 DIVW DIVW A, A, @RW3+ addr16 DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, @RW2+ @ PC+d16 A, @RW2+ @PC+d16 A, @RW2+ @ PC+d16 DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, @RW1+ @RW1+RW7 A, @RW1+ @RW1+RW7 A, @RW1+ @RW1+RW7 A, @RW1+ @RW1+RW7 DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, @RW0+ @RW0+RW7 A, @RW0+ @RW0+RW7 A, @RW0+ @RW0+RW7 A, @RW0+ @RW0+RW7 DIVU DIVU A, A, @RW3 @RW3+d16 DIVU DIVU A, A, @RW2 @RW2+d16 DIVU DIVU A, A, @RW1 @RW1+d16 DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, @RW0 @RW0+d16 A, @RW0 @RW0+d16 A, @RW0 @RW0+d16 A, @RW0 @RW0+d16 DIVU A, R7 DIVU A, R6 DIVU A, R5 DIVU A, R4 DIVU A, R3 DIVU A, R2 DIVU A, R1 DIVU A, R0 80 Table B.3.1m “ea” Instructions 9 (First byte = 78H) B.3 Instruction Map MB90580 Series MB90580 Series MOVEA RW3, MOVEA @RW5+d8 RW4, RW5 MOVEA RW3, MOVEA @RW6+d8 RW4, RW6 MOVEA RW3, MOVEA @RW7+d8 RW4, RW7 MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA MOVEA RW0, RW6 @RW6+d8 RW1, RW6 @RW6+d8 RW2, RW6 @RW6+d8 RW3, RW6 MOVEA MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA RW0, RW7 @RW7+d8 RW1, RW7 @RW7+d8 RW2, RW7 @RW7+d8 RW3, RW7 MOVEA MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA MOVEA RW3, MOVEA MOVEA RW4, MOVEA MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, RW0, @RW0 @RW0+d16 RW1, @RW0 @RW0+d16 RW2, @RW0 @RW0+d16 RW3, @RW0 @RW0+d16 RW4, @RW0 @RW0+d16 RW5, @RW0 @RW0+d16 RW6, @RW0 ,@RW0+d16 RW7, @RW0 @RW0+d16 MOVEA MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA MOVEA RW3, MOVEA MOVEA RW4, MOVEA MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, RW0, @RW1 @RW1+d16 RW1, @RW1 @RW1+d16 RW2, @RW1 @RW1+d16 RW3, @RW1 @RW1+d16 RW4, @RW1 @RW1+d16 RW5, @RW1 @RW1+d16 RW6, @RW1 ,@RW1+d16 RW7, @RW1 @RW1+d16 MOVEA MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA MOVEA RW3, MOVEA MOVEA RW4, MOVEA MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, RW0, @RW2 @RW2+d16 RW1, @RW2 @RW2+d16 RW2, @RW2 @RW2+d16 RW3, @RW2 @RW2+d16 RW4, @RW2 @RW2+d16 RW5, @RW2 @RW2+d16 RW6, @RW2 ,@RW2+d16 RW7, @RW2 @RW2+d16 MOVEA MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA MOVEA RW3, MOVEA MOVEA RW4, MOVEA MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, RW0, @RW3 @RW3+d16 RW1, @RW3 @RW3+d16 RW2, @RW3 @RW3+d16 RW3, @RW3 @RW3+d16 RW4, @RW3 @RW3+d16 RW5, @RW3 @RW3+d16 RW6, @RW3 ,@RW3+d16 RW7, @RW3 @RW3+d16 MOVEA R MOVEA RW0, MOVEA R MOVEA RW1, MOVEA R MOVEA RW2, MOVEA R MOVEA RW3, MOVEA R MOVEA RW4, MOVEA R MOVEA RW5, MOVEA R MOVEA RW6 MOVEA R MOVEA RW7, W0, @RW0+ @RW0+RW7 W1, @RW0+ @RW0+RW7 W2, @RW0+ @RW0+RW7 W3, @RW0+ @RW0+RW7 W4, @RW0+ @RW0+RW7 W5, @RW0+ @RW0+RW7 W6, @RW0+ ,@RW0+RW7 W7, @RW0+ @RW0+RW7 MOVEA R MOVEA RW0, MOVEA R MOVEA RW1, MOVEA R MOVEA RW2, MOVEA R MOVEA RW3, MOVEA R MOVEA RW4, MOVEA R MOVEA RW5, MOVEA R MOVEA RW6 MOVEA R MOVEA RW7, W0, @RW1+ @RW1+RW7 W1, @RW1+ @RW1+RW7 W2, @RW1+ @RW1+RW7 W3, @RW1+ @RW1+RW7 W4, @RW1+ @RW1+RW7 W5, @RW1+ @RW1+RW7 W6, @RW1+ ,@RW1+RW7 W7, @RW1+ @RW1+RW7 MOVEA R MOVEA RW0, MOVEA R MOVEA RW1, MOVEA R MOVEA RW2, MOVEA R MOVEA RW3, MOVEA R MOVEA RW4, MOVEA R MOVEA RW5, MOVEA R MOVEA RW6 MOVEA R MOVEA RW7, W0, @RW2+ @PC+d16 W1, @RW2+ @PC+d16 W2, @RW2+ @PC+d16 W3, @RW2+ @PC+d16 W4, @RW2+ @PC+d16 W5, @RW2+ @PC+d16 W6, @RW2+ ,@PC+d16 W7, @RW2+ @PC+d16 MOVEA R MOVEA RW0, MOVEA R MOVEA RW1, MOVEA R MOVEA RW2, MOVEA R MOVEA RW3, MOVEA R MOVEA RW4, MOVEA R MOVEA RW5, MOVEA MOVEA RW6 MOVEA R MOVEA RW7, W0, @RW3+ addr16 W1, @RW3+ addr16 W2, @RW3+ addr16 W3, @RW3+ addr16 W4, @RW3+ addr16 W5, @RW3+ addr16 W6, @RW3+ ,addr16 W7, @RW3+ addr16 +6 +7 +8 +9 +A +B +C +D +E +F MOVEA RW4, MOVEA @RW7+d8 RW5, RW7 MOVEA RW4, MOVEA @RW6+d8 RW5, RW6 MOVEA RW4, MOVEA @RW5+d8 RW5, RW5 MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, @RW7+d8 RW6, RW7 ,@RW7+d8 RW7, RW7 @RW7+d8 MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, @RW6+d8 RW6, RW6 ,@RW6+d8 RW7, RW6 @RW6+d8 MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, @RW5+d8 RW6, RW5 ,@RW5+d8 RW7, RW5 @RW5+d8 MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, @RW4+d8 RW6, RW4 ,@RW4+d8 RW7, RW4 @RW4+d8 MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, @RW3+d8 RW6, RW3 ,@RW3+d8 RW7, RW3 @RW3+d8 MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, @RW2+d8 RW6, RW2 ,@RW2+d8 RW7, RW2 @RW2+d8 MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, @RW1+d8 RW6, RW1 ,@RW1+d8 RW7, RW1 @RW1+d8 MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA MOVEA RW0, RW5 @RW5+d8 RW1, RW5 @RW5+d8 RW2, RW5 @RW5+d8 RW3, RW5 MOVEA RW4, MOVEA @RW4+d8 RW5, RW4 MOVEA RW4, MOVEA @RW3+d8 RW5, RW3 MOVEA RW4, MOVEA @RW2+d8 RW5, RW2 MOVEA RW4, MOVEA @RW1+d8 RW5, RW1 +5 F0 MOVEA RW3, MOVEA @RW4+d8 RW4, RW4 E0 MOVEA MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA @RW4+d8 RW1, RW4 @RW4+d8 RW2, RW4 @RW4+d8 RW3, RW4 RW0, RW4 D0 +4 C0 MOVEA RW3, MOVEA @RW3+d8 RW4, RW3 B0 MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, @RW0+d8 RW6, RW0 ,@RW0+d8 RW7, RW0 @RW0+d8 MOVEA MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA @RW3+d8 RW1, RW3 @RW3+d8 RW2, RW3 @RW3+d8 RW3, RW3 RW0, RW3 A0 +3 90 MOVEA RW4, MOVEA @RW0+d8 RW5, RW0 MOVEA RW3, MOVEA @RW2+d8 RW4, RW2 80 MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA MOVEA @RW2+d8 RW1, RW2 @RW2+d8 RW2, RW2 @RW2+d8 RW3, RW2 RW0, RW2 70 +2 60 MOVEA RW3, MOVEA @RW1+d8 RW4, RW1 50 MOVEA MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA RW0, RW1 @RW1+d8 RW1, RW1 @RW1+d8 RW2, RW1 @RW1+d8 RW3, RW1 40 +1 30 +0 20 MOVEA RW3, MOVEA @RW0+d8 RW4, RW0 10 MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA MOVEA @RW0+d8 RW1, RW0 @RW0+d8 RW2, RW0 @RW0+d8 RW3, RW0 RW0, RW0 00 Table B.3.1n MOVEA RWi, ea (First byte = 79H) B.3 Instruction Map APPENDIX B: Instructions 349 350 MOV R7, @RW0+ MOV R7, @RW1+ MOV R7, @RW2+ MOV R2, MOV @RW0+d16 R3, @RW0 MOV R2, MOV @RW1+d16 R3, @RW1 MOV MOV R2, MOV R2, @RW2 @RW2+d16 R3, @RW2 MOV MOV R2, MOV R2, @RW3 @RW3+d16 R3, @RW3 MOV R0, MOV @RW5+d8 R1, R5 MOV R0, MOV @RW6+d8 R1, R6 MOV R0, MOV @RW7+d8 R1, R7 MOV R0, R7 MOV MOV R0, MOV MOV R1, R0, @RW2 @RW2+d16 R1, @RW2 @RW2+d16 MOV MOV R0, MOV MOV R1, R0, @RW3 @RW3+d16 R1, @RW3 @RW3+d16 MOV MOV R0, MOV R1, MOV MOV R6, MOV R6, R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, R0, @RW0+ @RW0+RW7 R1, @RW0+ @RW0+RW7 R2, @RW0+ @RW0+RW7 R3, @RW0+ @RW0+RW7 R4, @RW0+ @RW0+RW7 R5, @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 MOV MOV R0, MOV R1, MOV MOV R6, MOV R6, R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, R0, @RW1+ @RW1+RW7 R1, @RW1+ @RW1+RW7 R2, @RW1+ @RW1+RW7 R3, @RW1+ @RW1+RW7 R4, @RW1+ @RW1+RW7 R5, @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 MOV R1, MOV R1, R1, @RW3+ addr16 MOV R0, R6 MOV MOV R0, MOV MOV R1, R0, @RW1 @RW1+d16 R1, @RW1 @RW1+d16 MOV R1, MOV R1, R1, @RW2+ @PC+d16 MOV R0, R5 MOV MOV R0, MOV MOV R1, MOV R0, @RW0 @RW0+d16 R1, @RW0 @RW0+d16 R2, @RW0 MOV R2, @RW1 MOV R0, MOV @RW4+d8 R1, R4 MOV MOV R0, R0, @RW2+ @PC+d16 MOV MOV R0, R0, @RW3+ @addr16 +5 +6 +7 +8 +9 +A +B +C +D +E +F E0 MOV R0, R4 D0 APPENDIX B: Instructions MOV R1, @RW7+d8 MOV R1, @RW6+d8 MOV R1, @RW5+d8 MOV R1, @RW4+d8 MOV R1, @RW3+d8 MOV R1, @RW2+d8 MOV R1, @RW1+d8 MOV MOV R2, R2, @RW3+ addr16 MOV MOV R3, R3, @RW3+ addr16 MOV R4, MOV @RW3+d16 R5, @RW3 MOV R4, MOV @RW2+d16 R5, @RW2 MOV R4, MOV @RW1+d16 R5, @RW1 MOV R4, MOV @RW0+d16 R5, @RW0 MOV R4, MOV R5, R7 @RW7+d8 MOV R4, MOV R5, R6 @RW6+d8 MOV R4, MOV R5, R5 @RW5+d8 MOV R4, MOV R5, R4 @RW4+d8 MOV R4, MOV R5, R3 @RW3+d8 MOV R4, MOV R5, R2 @RW2+d8 MOV R4, MOV R5, R1 @RW1+d8 MOV R5, @RW3+d16 MOV R5, @RW2+d16 MOV R5, @RW1+d16 MOV R5, @RW0+d16 MOV R5, @RW7+d8 MOV R5, @RW6+d8 MOV R5, @RW5+d8 MOV R5, @RW4+d8 MOV R5, @RW3+d8 MOV R5, @RW2+d8 MOV R5, @RW1+d8 MOV MOV R4, R4, @RW3+ addr16 MOV MOV R5, R5, @RW3+ addr16 MOV MOV R4, MOV MOV R5, R4, @RW2+ @PC+d16 R5, @RW2+ @PC+d16 MOV R3, MOV @RW3+d16 R4, @RW3 MOV R3, MOV @RW2+d16 R4, @RW2 MOV R3, MOV @RW1+d16 R4, @RW1 MOV R3, MOV @RW0+d16 R4, @RW0 MOV R3, MOV R4, R7 @RW7+d8 MOV R3, MOV R4, R6 @RW6+d8 MOV R3, MOV R4, R5 @RW5+d8 MOV R3, MOV R4, R4 @RW4+d8 MOV R3, MOV R4, R3 @RW3+d8 MOV R3, MOV R4, R2 @RW2+d8 MOV R3, MOV R4, R1 @RW1+d8 MOV MOV R3, R3, @RW2+ @PC+d16 MOV R2, MOV R3, R7 @RW7+d8 MOV R2, MOV R3, R6 @RW6+d8 MOV R2, MOV R3, R5 @RW5+d8 MOV R2, MOV R3, R4 @RW4+d8 MOV R2, MOV R3, R3 @RW3+d8 MOV R2, MOV R3, R2 @RW2+d8 MOV R2, MOV R3, R1 @RW1+d8 MOV MOV R2, R2, @RW2+ @PC+d16 MOV R2, R7 MOV R2, R6 MOV R2, R5 MOV R2, R4 MOV R2, R3 MOV R2, R2 MOV R2, R1 MOV R6, @RW3+ MOV R6, @RW2+ MOV R6, @RW3 MOV R6, @RW2 MOV R6, @RW1 MOV R6, @RW0 MOV R6, R7 MOV R6, R6 MOV R6, R5 MOV R6, R4 MOV R6, R3 MOV R6, R2 MOV R6, R1 F0 MOV R7, @RW7+d8 MOV R7, @RW6+d8 MOV R7, @RW5+d8 MOV R7, @RW4+d8 MOV R7, @RW3+d8 MOV R7, @RW2+d8 MOV R7, @RW1+d8 MOV R7, @RW0+d8 MOV R6, addr16 MOV R6, @PC+d16 MOV R7, @RW3+ MOV MOV R6, @RW3+d16 R7, @RW3 MOV MOV R6, @RW2+d16 R7, @RW2 MOV MOV R6, @RW1+d16 R7, @RW1 MOV R7, addr16 MOV R7, @PC+d16 MOV R7, @RW1+RW7 MOV R7, @RW0+RW7 MOV R7, @RW3+d16 MOV R7, @RW2+d16 MOV R7, @RW1+d16 MOV MOV R6, MOV R7, @RW0+d16 R7, @RW0 @RW0+d16 MOV MOV R6, R7, R7 @RW7+d8 MOV MOV R6, R7, R6 @RW6+d8 MOV MOV R6, R7, R5 @RW5+d8 MOV MOV R6, R7, R4 @RW4+d8 MOV MOV R6, R7, R3 @RW3+d8 MOV MOV R6, R7, R2 @RW2+d8 MOV MOV R6, R7, R1 @RW1+d8 MOV MOV R6, R7, R0 @RW0+d8 +4 C0 MOV R6, R0 MOV R0, MOV @RW3+d8 R1, R3 B0 MOV R5, @RW0+d8 MOV R0, R3 A0 +3 90 MOV R4, MOV R5, R0 @RW0+d8 MOV R0, MOV @RW2+d8 R1, R2 80 MOV R0, R2 70 MOV R3, MOV R4, R0 @RW0+d8 +2 60 MOV R0, MOV @RW1+d8 R1, R1 50 MOV R2, MOV R3, R0 @RW0+d8 MOV R0, R1 40 MOV R2, R0 +1 30 MOV R1, @RW0+d8 +0 MOV R1, R0 10 MOV R0, @RW0+d8 00 MOV R0, R0 20 Table B.3.1o MOV Ri, ea (First byte = 7AH) B.3 Instruction Map MB90580 Series MB90580 Series MOVW RW3, MOVW @RW6+d8 RW4, RW6 MOVW RW3, MOVW @RW7+d8 RW4, RW7 MOVW MOVW RW0, MOVW MOVW RW1, MOVW MOVW RW2, MOVW RW0, RW6 @RW6+d8 RW1, RW6 @RW6+d8 RW2, RW6 @RW6+d8 RW3, RW6 MOVW MOVW RW0, MOVW MOVW RW1, MOVW MOVW RW2, MOVW RW0, RW7 @RW7+d8 RW1, RW7 @RW7+d8 RW2, RW7 @RW7+d8 RW3, RW7 MOVW MOVW RW0, MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, MOVW MOVW RW5, MOVW MOVW RW6, MOVW MOVW RW7, RW0, @RW0 @RW0+d16 RW1, @RW0 @RW0+d16 RW2, @RW0 @RW0+d16 RW3, @RW0 @RW0+d16 RW4, @RW0 @RW0+d16 RW5, @RW0 @RW0+d16 RW6, @RW0 @RW0+d16 RW7, @RW0 @RW0+d16 MOVW MOVW RW0, MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, MOVW MOVW RW5, MOVW MOVW RW6, MOVW MOVW RW7, RW0, @RW1 @RW1+d16 RW1, @RW1 @RW1+d16 RW2, @RW1 @RW1+d16 RW3, @RW1 @RW1+d16 RW4, @RW1 @RW1+d16 RW5, @RW1 @RW1+d16 RW6, @RW1 @RW1+d16 RW7, @RW1 @RW1+d16 MOVW MOVW RW0, MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, MOVW MOVW RW5, MOVW MOVW RW6, MOVW MOVW RW7, RW0, @RW2 @RW2+d16 RW1, @RW2 @RW2+d16 RW2, @RW2 @RW2+d16 RW3, @RW2 @RW2+d16 RW4, @RW2 @RW2+d16 RW5, @RW2 @RW2+d16 RW6, @RW2 @RW2+d16 RW7, @RW2 @RW2+d16 MOVW MOVW RW0, MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, MOVW MOVW RW5, MOVW MOVW RW6, MOVW MOVW RW7, RW0, @RW3 @RW3+d16 RW1, @RW3 @RW3+d16 RW2, @RW3 @RW3+d16 RW3, @RW3 @RW3+d16 RW4, @RW3 @RW3+d16 RW5, @RW3 @RW3+d16 RW6, @RW3 @RW3+d16 RW7, @RW3 @RW3+d16 MOVW R MOVW RW0, MOVW R MOVW RW1, MOVW R MOVW RW2, MOVW R MOVW RW3, MOVW R MOVW RW4, MOVW R MOVW RW5, MOVW R MOVW RW6, MOVW R MOVW RW7, W0, @RW0+ @RW0+RW7 W1, @RW0+ @RW0+RW7 W2, @RW0+ @RW0+RW7 W3, @RW0+ @RW0+RW7 W4, @RW0+ @RW0+RW7 W5, @RW0+ @RW0+RW7 W6, @RW0+ @RW0+RW7 W7, @RW0+ @RW0+RW7 MOVW R MOVW RW0, MOVW R MOVW RW1, MOVW R MOVW RW2, MOVW R MOVW RW3, MOVW R MOVW RW4, MOVW R MOVW RW5, MOVW R MOVW RW6, MOVW R MOVW RW7, W0, @RW1+ @RW1+RW7 W1, @RW1+ @RW1+RW7 W2, @RW1+ @RW1+RW7 W3, @RW1+ @RW1+RW7 W4, @RW1+ @RW1+RW7 W5, @RW1+ @RW1+RW7 W6, @RW1+ @RW1+RW7 W7, @RW1+ @RW1+RW7 MOVW R MOVW RW0, MOVW R MOVW RW1, MOVW R MOVW RW2, MOVW R MOVW RW3, MOVW R MOVW RW4, MOVW R MOVW RW5, MOVW R MOVW RW6, MOVW R MOVW RW7, W0, @RW2+ @PC+d16 W1, @RW2+ @PC+d16 W2, @RW2+ @PC+d16 W3, @RW2+ @PC+d16 W4, @RW2+ W7, @RW2+ @PC+d16 @PC+d16 W5, @RW2+ @PC+d16 W6, @RW2+ @PC+d16 MOVW R MOVW RW0, MOVW R MOVW RW1, MOVW R MOVW RW2, MOVW R MOVW RW3, MOVW R MOVW RW4, MOVW R MOVW RW5, MOVW R MOVW RW6, MOVW R MOVW RW7, W0, @RW3+ addr16 W1, @RW3+ W2, @RW3+ addr16 W3, @RW3+ addr16 W4, @RW3+ W5, @RW3+ addr16 W6, @RW3+ addr16 W7, @RW3+ addr16 addr16 addr16 +6 +7 +8 +9 +A +B +C +D +E +F MOVW RW4, MOVW RW5, RW7 @RW7+d8 MOVW RW4, MOVW RW5, RW6 @RW6+d8 MOVW RW4, MOVW RW5, RW5 @RW5+d8 MOVW RW7, @RW6+d8 MOVW RW7, @RW5+d8 MOVW RW5, MOVW MOVW RW6, MOVW MOVW RW7, RW6, RW7 RW7, RW7 @RW7+d8 @RW7+d8 @RW7+d8 MOVW RW5, MOVW MOVW RW6, MOVW RW6, RW6 RW7, RW6 @RW6+d8 @RW6+d8 MOVW RW5, MOVW MOVW RW6, MOVW RW6, RW5 RW7, RW5 @RW5+d8 @RW5+d8 MOVW RW7, @RW4+d8 MOVW RW7, @RW3+d8 MOVW RW7, @RW2+d8 MOVW RW7, @RW1+d8 MOVW RW3, MOVW @RW5+d8 RW4, RW5 MOVW RW5, MOVW MOVW RW6, MOVW RW6, RW4 RW7, RW4 @RW4+d8 @RW4+d8 MOVW RW5, MOVW MOVW RW6, MOVW RW6, RW3 RW7, RW3 @RW3+d8 @RW3+d8 MOVW RW5, MOVW MOVW RW6, MOVW RW6, RW2 RW7, RW2 @RW2+d8 @RW2+d8 MOVW RW5, MOVW MOVW RW6, MOVW RW6, RW1 RW7, RW1 @RW1+d8 @RW1+d8 MOVW MOVW RW0, MOVW MOVW RW1, MOVW MOVW RW2, MOVW RW0, RW5 @RW5+d8 RW1, RW5 @RW5+d8 RW2, RW5 @RW5+d8 RW3, RW5 MOVW RW4, MOVW RW5, RW4 @RW4+d8 MOVW RW4, MOVW RW5, RW3 @RW3+d8 MOVW RW4, MOVW RW5, RW2 @RW2+d8 MOVW RW4, MOVW RW5, RW1 @RW1+d8 +5 F0 MOVW RW7, @RW0+d8 MOVW RW3, MOVW @RW4+d8 RW4, RW4 E0 MOVW MOVW RW0, MOVW MOVW RW1, MOVW MOVW RW2, MOVW RW0, RW4 @RW4+d8 RW1, RW4 @RW4+d8 RW2, RW4 @RW4+d8 RW3, RW4 D0 +4 C0 MOVW RW3, MOVW @RW3+d8 RW4, RW3 B0 MOVW RW5, MOVW MOVW RW6, MOVW RW6, RW0 @RW0+d8 RW7, RW0 @RW0+d8 MOVW MOVW RW0, MOVW MOVW RW1, MOVW MOVW RW2, MOVW RW0, RW3 @RW3+d8 RW1, RW3 @RW3+d8 RW2, RW3 @RW3+d8 RW3, RW3 A0 +3 90 MOVW RW4, MOVW RW5, RW0 @RW0+d8 MOVW RW3, MOVW @RW2+d8 RW4, RW2 80 MOVW MOVW RW0, MOVW MOVW RW1, MOVW MOVW RW2, MOVW RW0, RW2 @RW2+d8 RW1, RW2 @RW2+d8 RW2, RW2 @RW2+d8 RW3, RW2 70 +2 60 MOVW RW3, MOVW @RW1+d8 RW4, RW1 50 MOVW MOVW RW0, MOVW MOVW RW1, MOVW MOVW RW2, MOVW RW0, RW1 @RW1+d8 RW1, RW1 @RW1+d8 RW2, RW1 @RW1+d8 RW3, RW1 40 +1 30 +0 20 MOVW RW3, MOVW @RW0+d8 RW4, RW0 10 MOVW MOVW RW0, MOVW MOVW RW1, MOVW MOVW RW2, MOVW RW0, RW0 @RW0+d8 RW1, RW0 @RW0+d8 RW2, RW0 @RW0+d8 RW3, RW0 00 Table B.3.1p MOVW RWi, ea (First byte = 7BH) B.3 Instruction Map APPENDIX B: Instructions 351 352 APPENDIX B: Instructions MOV @RW MOV 2+d16, R1 @RW2, R2 MOV @RW MOV 3+d16, R1 @RW3, R2 MOV MOV @RW2+, R2 PC+d16, R2 MOV MOV @RW MOV @RW2, R0 W2+d16, R0 @RW2, R1 MOV MOV @RW MOV @RW3, R0 W3+d16, R0 @RW3, R1 MOV MOV @RW MOV MOV @RW MOV MOV @RW MOV MOV @RW MOV MOV @RW MOV MOV @RW MOV MOV @RW MOV MOV @RW @RW1+, R0 W1+RW7, R0 @RW1+, R1 @RW1+, R3 1+RW7, R3 @RW1+, R4 1+RW7, R4 @RW1+, R5 1+RW7, R5 @RW1+, R6 1+RW7,R6 @RW1+, R7 1+RW7, R7 1+RW7, R1 @RW1+, R2 1+RW7, R2 MOV MOV @RW3+, R3 addr16, R3 MOV @RW MOV 1+d16, R1 @RW1, R2 MOV MOV @RW MOV @RW1, R0 W1+d16, R0 @RW1, R1 MOV MOV @RW MOV MOV @RW MOV MOV @RW MOV MOV @RW MOV MOV @RW MOV MOV @RW MOV MOV @RW MOV MOV @RW @RW0+, R0 W0+RW7, R0 @RW0+, R1 @RW0+, R3 0+RW7, R3 @RW0+, R4 0+RW7, R4 @RW0+, R5 0+RW7, R5 @RW0+, R6 0+RW7, R6 @RW0+, R7 0+RW7, R7 0+RW7, R1 @RW0+, R2 0+RW7, R2 MOV MOV @RW2+, R3 PC+d16, R3 MOV @RW MOV 0+d16, R1 @RW0, R2 MOV MOV @RW2+, R0 PC+d16, R0 MOV MOV MOV MOV MOV MOV @RW3+, R0 addr16, R0 @RW3+, R1 addr16, R1 @RW3+, R2 addr16, R2 +9 +A +B +C +D +E +F MOV MOV @RW2+, R1 PC+d16, R1 MOV @R MOV R7, R4 W7+d8, R3 MOV R7, R5 MOV @R W7+d8, R5 MOV @R W6+d8, R5 MOV R7, R6 MOV R6, R6 MOV MOV MOV MOV @RW3+, R4 addr16, R4 @RW3+, R5 addr16, R5 MOV @R W7+d8, R7 MOV @R W6+d8, R7 MOV @R W5+d8, R7 MOV @R W4+d8, R7 MOV MOV @RW3+, R6 addr16, R6 MOV @RW 3+d16, R7 MOV @RW 2+d16, R7 MOV @RW 1+d16, R7 MOV MOV @RW3+, R7 addr16, R7 MOV MOV @RW2+, R7 PC+d16, R7 MOV @RW MOV @RW3, R7 3+d16, R6 MOV @RW MOV @RW2, R7 2+d16, R6 MOV @RW MOV @RW1, R7 1+d16, R6 MOV @RW MOV MOV @RW @RW0, R7 0+d16, R6 0+d16, R7 MOV @R MOV R7, R7 W7+d8, R6 MOV @R MOV R6, R7 W6+d8, R6 MOV MOV @RW2+, R6 PC+d16, R6 MOV @RW MOV @RW3, R6 3+d16, R5 MOV @RW MOV @RW2, R6 2+d16, R5 MOV @RW MOV @RW1, R6 1+d16, R5 MOV MOV @RW2+, R5 PC+d16, R5 MOV @RW MOV @RW3, R5 3+d16, R4 MOV @RW MOV @RW2, R5 2+d16, R4 MOV @RW MOV @RW1, R5 1+d16, R4 MOV @RW MOV MOV @RW MOV @RW0, R5 0+d16, R5 @RW0, R6 0+d16, R4 MOV @R W7+d8, R4 MOV MOV @RW2+, R4 PC+d16, R4 MOV @RW MOV MOV @RW MOV @RW3, R3 3+d16, R3 @RW3, R4 3+d16, R2 MOV @RW MOV MOV @RW MOV @RW2, R3 2+d16, R3 @RW2, R4 2+d16, R2 MOV @RW MOV MOV @RW MOV @RW1, R3 1+d16, R3 @RW1, R4 1+d16, R2 MOV @RW MOV MOV @RW MOV @RW0, R3 @RW0, R4 0+d16, R2 0+d16, R3 MOV @R MOV R7, R3 W7+d8, R2 MOV R6, R5 MOV @R MOV R5, R7 W5+d8, R6 MOV @R MOV R4, R7 W4+d8, R6 MOV @R W3+d8, R7 MOV @R W2+d8, R7 MOV @R W1+d8, R7 MOV MOV @RW MOV @RW0, R0 W0+d16, R0 @RW0, R1 MOV @R MOV W7+d8, R1 R7, R2 MOV @R W6+d8, R4 MOV R5, R6 MOV R4, R6 MOV @R MOV R3, R7 W3+d8, R6 MOV @R MOV R2, R7 W2+d8, R6 MOV @R MOV R1, R7 W1+d8, R6 +8 MOV R7, R1 MOV @R MOV R6, R4 W6+d8, R3 MOV @R W5+d8, R5 MOV @R W4+d8, R5 MOV R3, R6 MOV R2, R6 MOV R1, R6 MOV @R W7+d8, R0 MOV @R MOV R6, R3 W6+d8, R2 MOV R5, R5 MOV R4, R5 MOV @R W3+d8, R5 MOV @R W2+d8, R5 MOV @R W1+d8, R5 MOV R7, R0 MOV @R MOV W6+d8, R1 R6, R2 MOV @R W5+d8, R4 MOV @R W4+d8, R4 MOV R3, R5 MOV R2, R5 MOV R1, R5 +7 MOV R6, R1 MOV @R MOV R5, R4 W5+d8, R3 MOV @R MOV R4, R4 W4+d8, R3 MOV @R, W3+d8, R4 MOV @R, W2+d8, R4 MOV @R W1+d8, R4 MOV @R W6+d8, R0 MOV @R MOV R5, R3 W5+d8, R2 MOV R2, R4 MOV @R MOV R3, R4 W3+d8, R3 MOV @R W2+d8, R3 MOV @R MOV R1, R4 W1+d8, R3 MOV R6, R0 MOV @R MOV W5+d8, R1 R5, R2 MOV @R MOV R4, R3 W4+d8, R2 MOV @R MOV R3, R3 W3+d8, R2 MOV @R MOV R2, R3 W2+d8, R2 MOV @R MOV R1, R3 W1+d8, R2 +6 MOV R5, R1 MOV @R MOV R4, R2 W4+d8, R1 MOV @R MOV R3, R2 W3+d8, R1 MOV @R MOV R2, R2 W2+d8, R1 MOV @R MOV W1+d8, R1 R1, R2 MOV @R W5+d8, R0 MOV R4, R1 MOV R3, R1 MOV R2, R1 MOV R1, R1 MOV R5, R0 F0 MOV @R W0+d8, R7 +5 E0 MOV @R W4+d8, R0 D0 MOV @R MOV R0, R7 W0+d8, R6 MOV R4, R0 C0 MOV R0, R6 +4 B0 MOV @R W0+d8, R5 MOV @R W3+d8, R0 A0 MOV R0, R5 MOV R3, R0 90 MOV @R W0+d8, R4 +3 80 MOV @R W2+d8, R0 70 MOV @R MOV R0, R4 W0+d8, R3 MOV R2, R0 60 +2 50 MOV @R, MOV R0, R3 W0+d8, R2 MOV @R W1+d8, R0 40 MOV R1, R0 30 MOV @R MOV W0+d8, R1 R0, R2 +1 20 MOV R0, R1 +0 10 MOV @R W0+d8, R0 MOV R0, R0 00 Table B.3.1q MOV ea, Ri (First byte = 7CH) B.3 Instruction Map MB90580 Series MB90580 Series MOVW @RW 1+d8, RW7 MOVW @RW 2+d8, RW7 MOVW @RW 3+d8, RW7 MOVW @RW 4+d8, RW7 MOVW @RW 5+d8, RW7 MOVW @RW 6+d8, RW7 MOVW @RW 7+d8, RW7 MOVW @RW MOVW RW1, RW7 1+d8, RW6 MOVW @RW MOVW RW2, RW7 2+d8, RW6 MOVW @RW MOVW RW3, RW7 3+d8, RW6 MOVW @RW MOVW RW4, RW7 4+d8, RW6 MOVW @RW MOVW RW5, RW7 5+d8, RW6 MOVW @RW MOVW RW6, RW7 6+d8, RW6 MOVW @RW MOVW RW7, RW7 7+d8, RW6 MOVW @RW MOVW RW1, RW6 1+d8, RW5 MOVW @RW MOVW RW2, RW6 2+d8, RW5 MOVW @RW MOVW RW3, RW6 3+d8, RW5 MOVW @RW MOVW RW4, RW6 4+d8, RW5 MOVW @RW MOVW RW5, RW6 5+d8, RW5 MOVW @RW MOVW RW6, RW6 6+d8, RW5 MOVW @RW MOVW RW7, RW6 7+d8, RW5 MOVW @RW MOVW RW1, RW5 1+d8, RW4 MOVW @RW MOVW RW2, RW5 2+d8, RW4 MOVW @RW MOVW RW3, RW5 3+d8, RW4 MOVW @RW MOVW RW4, RW5 4+d8, RW4 MOVW @RW MOVW RW5, RW5 5+d8, RW4 MOVW @RW MOVW RW6, RW5 6+d8, RW4 MOVW @RW MOVW RW7, RW5 7+d8, RW4 MOVW @RW MOVW RW1, RW4 1+d8, RW3 MOVW @RW MOVW RW2, RW4 2+d8, RW3 MOVW @RW MOVW RW3, RW4 3+d8, RW3 MOVW @RW MOVW RW4, RW4 4+d8, RW3 MOVW @RW MOVW RW5, RW4 5+d8, RW3 MOVW @RW MOVW RW6, RW4 6+d8, RW3 MOVW @RW MOVW RW7, RW4 7+d8, RW3 MOVW @RW MOVW RW2, RW3 2+d8, RW2 MOVW @RW MOVW RW3, RW3 3+d8, RW2 MOVW @RW MOVW RW4, RW3 4+d8, RW2 MOVW @RW MOVW RW5, RW3 5+d8, RW2 MOVW @RW MOVW RW6, RW3 6+d8, RW2 MOVW @RW MOVW RW7, RW3 7+d8, RW2 MOVW @RW MOVW RW2, RW2 2+d8, RW1 MOVW @RW MOVW RW3, RW2 3+d8, RW1 MOVW @RW MOVW RW4, RW2 4+d8, RW1 MOVW @RW MOVW RW5, RW2 5+d8, RW1 MOVW @RW MOVW RW6, RW2 6+d8, RW1 MOVW @RW MOVW RW7, RW2 7+d8, RW1 MOVW @RW MOVW RW2, RW1 2+d8, RW0 MOVW @RW MOVW RW3, RW1 3+d8, RW0 MOVW @RW MOVW RW4, RW1 4+d8, RW0 MOVW @RW MOVW RW5, RW1 5+d8, RW0 MOVW @RW MOVW RW6, RW1 6+d8, RW0 MOVW @RW MOVW RW7, RW1 7+d8, RW0 MOVW RW2, RW0 MOVW RW3, RW0 MOVW RW4, RW0 MOVW RW5, RW0 MOVW RW6, RW0 MOVW RW7, RW0 MOVW@RW0 MOVW@RW0 MOVW MOVW@RW0 MOVW MOVW@RW0 MOVW MOVW@RW0 MOVW MOVW@RW0 MOVW MOVW@RW0 MOVW MOVW@RW0 MOVW MOVW @RW0, RW7 +d16, RW7 @RW0, RW6 +d16, RW6 @RW0, RW5 +d16, RW5 @RW0, RW4 +d16, RW4 @RW0, RW3 +d16, RW3 @RW0, RW2 +d16, RW2 @RW0, RW1 +d16, RW1 @RW0, RW0 +d16, RW0 MOVW@RW1 MOVW@RW1 MOVW MOVW@RW1 MOVW MOVW@RW1 MOVW MOVW@RW1 MOVW MOVW@RW1 MOVW MOVW@RW1 MOVW MOVW@RW1 MOVW MOVW @RW1, RW7 +d16, RW7 @RW1, RW6 +d16, RW6 @RW1, RW5 +d16, RW5 @RW1, RW4 +d16, RW4 @RW1, RW3 +d16, RW3 @RW1, RW2 +d16, RW2 @RW1, RW1 +d16, RW1 @RW1, RW0 +d16, RW0 MOVW@RW2 MOVW@RW2 MOVW MOVW@RW2 MOVW MOVW@RW2 MOVW MOVW@RW2 MOVW MOVW@RW2 MOVW MOVW@RW2 MOVW MOVW@RW2 MOVW MOVW @RW2, RW7 +d16, RW7 @RW2, RW6 +d16, RW6 @RW2, RW5 +d16, RW5 @RW2, RW4 +d16, RW4 @RW2, RW3 +d16, RW3 @RW2, RW2 +d16, RW2 @RW2, RW1 +d16, RW1 @RW2, RW0 +d16, RW0 MOVW@RW3 MOVW@RW3 MOVW MOVW@RW3 MOVW MOVW@RW3 MOVW MOVW@RW3 MOVW MOVW@RW3 MOVW MOVW@RW3 MOVW MOVW@RW3 MOVW MOVW @RW3, RW7 +d16, RW7 @RW3, RW6 +d16, RW6 @RW3, RW5 +d16, RW5 @RW3, RW4 +d16, RW4 @RW3, RW3 +d16, RW3 @RW3, RW2 +d16, RW2 @RW3, RW1 +d16, RW1 @RW3, RW0 +d16, RW0 @ MOVW@RW0 @ MOVW@RW0 MOVW @ MOVW@RW0 MOVW @ MOVW@RW0 MOVW @ MOVW@RW0 MOVW @ MOVW@RW0 MOVW @ MOVW@RW0 MOVW MOVW@RW0 MOVW MOVW +RW7, RW7 RW0+, RW7 +RW7, RW6 RW0+, RW6 +RW7, RW5 RW0+, RW5 +RW7, RW4 RW0+, RW4 +RW7, RW3 RW0+, RW3 +RW7, RW2 RW0+, RW2 +RW7, RW0 RW0+, RW1 +RW7, RW1 @RW0+, RW0 @ MOVW@RW1 @ MOVW@RW1 MOVW @ MOVW@RW1 MOVW @ MOVW@RW1 MOVW @ MOVW@RW1 MOVW @ MOVW@RW1 MOVW @ MOVW@RW1 MOVW MOVW@RW1 MOVW MOVW +RW7, RW7 RW1+, RW7 +RW7, RW6 RW1+, RW6 +RW7, RW5 RW1+, RW5 +RW7, RW4 RW1+, RW4 +RW7, RW3 RW1+, RW3 +RW7, RW2 RW1+, RW2 RW1+, RW1 +RW7, RW1 @RW1+, RW0 +RW7, RW0 @ MOVW @PC+ @ MOVW @PC+ MOVW @ MOVW @PC+ MOVW @ MOVW @PC+ MOVW @ MOVW @PC+ MOVW @ MOVW @PC+ MOVW @ MOVW @PC+ MOVW MOVW @PC+ MOVW MOVW d16, RW7 d16, RW6 RW2+, RW7 d16, RW5 RW2+, RW6 d16, RW4 RW2+, RW5 d16, RW3 RW2+, RW4 d16, RW2 RW2+, RW3 d16, RW1 RW2+, RW2 RW2+, RW1 d16, RW0 @RW2+, RW0 MOVW @ MOVW addr MOVW @ MOVW addr MOVW @ MOVW addr MOVW @ MOVW addr MOVW @ MOVW addr MOVW @ MOVW addr MOVW @ MOVW addr MOVW addr MOVW 16, RW7 16, RW6 RW3+, RW7 16, RW5 RW3+, RW6 16, RW4 RW3+, RW5 16, RW3 RW3+, RW4 16, RW2 RW3+, RW3 16, RW1 RW3+, RW2 16, RW0 RW3+, RW1 @RW3+, RW0 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F MOVW @R 1+d8, RW2 MOVW RW1, RW3 F0 MOVW RW1, RW2 E0 MOVW @R 1+d8, RW1 D0 MOVW @RW MOVW RW1, RW1 1+d8, RW0 C0 MOVW RW1, RW0 B0 +1 A0 MOVW @RW 0+d8, RW7 90 MOVW @RW MOVW RW0, RW7 0+d8, RW6 80 MOVW @RW MOVW RW0, RW6 0+d8, RW5 70 MOVW @RW MOVW RW0, RW5 0+d8, RW4 60 MOVW @RW MOVW RW0, RW4 0+d8, RW3 50 MOVW @RW MOVW RW0, RW3 0+d8, RW2 40 MOVW @RW MOVW RW0, RW2 0+d8, RW1 30 MOVW @RW MOVW RW0, RW1 0+d8, RW0 20 MOVW RW0, RW0 10 +0 00 Table B.3.1r MOVW ea, RWi (First byte = 7DH) B.3 Instruction Map APPENDIX B: Instructions 353 354 APPENDIX B: Instructions 30 80 90 A0 B0 C0 D0 E0 F0 XCH R0, XCH XCH R1, @RW2+d16 R1, @RW2 @RW2+d16 XCH R0, XCH XCH R1, @RW3+d16 R1, @RW3 @RW3+d16 XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, @RW1+ @RW1+RW7 R1, @RW1+ @RW1+RW7 R2, @RW1+ @RW1+RW7 R3, @RW1+ @RW1+RW7 R4, @RW1+ @RW1+RW7 R5, @RW1+ @RW1+RW7 R6, @RW1+ @RW1+RW7 R7, @RW1+ @RW1+RW7 XCH XCH R1, R1, @RW3+ addr16 XCH R0, @RW3 XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, @RW0+ @RW0+RW7 R1, @RW0+ @RW0+RW7 R2, @RW0+ @RW0+RW7 R3, @RW0+ @RW0+RW7 R4, @RW0+ @RW0+RW7 R5, @RW0+ @RW0+RW7 R6, @RW0+ @RW0+RW7 R7, @RW0+ @RW0+RW7 XCH XCH R1, R1, @RW2+ @PC+d16 XCH R0, @RW2 XCH XCH R0, R0, @RW2+ @PC+d16 XCH XCH R0, R0, @RW3+ addr16 +A +B +C +D +E +F XCH XCH R2, R2, @RW3+ addr16 XCH XCH R2, R2, @RW2+ @PC+d16 XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R3, @RW3+ addr16 R4, @RW3+ R5, @RW3+ addr16 R6, @RW3+ addr16 R7, @RW3+ addr16 addr16 XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R3, @RW2+ @PC+d16 R4, @RW2+ R6, @RW2+ @PC+d16 R7, @RW2+ @PC+d16 @PC+d16 R5, @RW2+ @PC+d16 XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R2, @RW3 @RW3+d16 R3, @RW3 @RW3+d16 R4, @RW3 @RW3+d16 R5, @RW3 @RW3+d16 R6, @RW3 @RW3+d16 R7, @RW3 @RW3+d16 XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R2, @RW2 @RW2+d16 R3, @RW2 @RW2+d16 R4, @RW2 @RW2+d16 R5, @RW2 @RW2+d16 R6, @RW2 @RW2+d16 R7, @RW2 @RW2+d16 XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R2, @RW1 @RW1+d16 R3, @RW1 @RW1+d16 R4, @RW1 @RW1+d16 R5, @RW1 @RW1+d16 R6, @RW1 @RW1+d16 R7, @RW1 @RW1+d16 XCH R5, XCH XCH R6, XCH XCH R7, R6, @RW0 @RW0+d16 R7, @RW0 @RW0+d16 @RW0+d16 XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R3, R7 R4, R7 R5, R7 @RW7+d8 R6, R7 @RW7+d8 R7, R7 @RW7+d8 @RW7+d8 @RW7+d8 @RW7+d8 XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R3, R6 R4, R6 R5, R6 @RW6+d8 R6, R6 @RW6+d8 R7, R6 @RW6+d8 @RW6+d8 @RW6+d8 @RW6+d8 XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R3, R5 R4, R5 R5, R5 @RW5+d8 R6, R5 @RW5+d8 R7, R5 @RW5+d8 @RW5+d8 @RW5+d8 @RW5+d8 XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH NOTW R7, R3, R4 R4, R4 R5, R4 @RW4+d8 R6, R4 @RW4+d8 R7, R4 @RW4+d8 @RW4+d8 @RW4+d8 @RW4+d8 XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH NOTW R7, R3, R3 R4, R3 R5, R3 @RW3+d8 R6, R3 @RW3+d8 R7, R3 @RW3+d8 @RW3+d8 @RW3+d8 @RW3+d8 XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R3, R2 R4, R2 R5, R2 @RW2+d8 R6, R2 @RW2+d8 R7, R2 @RW2+d8 @RW2+d8 @RW2+d8 @RW2+d8 XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH NOTW R7, R3, R1 R4, R1 R5, R1 @RW1+d8 R6, R1 @RW1+d8 R7, R1 @RW1+d8 @RW1+d8 @RW1+d8 @RW1+d8 XCH R0, XCH XCH R1, @RW1+d16 R1, @RW1 @RW1+d16 R2, R7 R2, R6 R2, R5 R2, R4 R2, R3 R2, R2 R2, R1 XCH R0, @RW1 XCH XCH XCH XCH XCH 70 +9 XCH R0, XCH XCH R1, @RW7+d8 R1, R7 @RW7+d8 XCH R0, XCH XCH R1, @RW6+d8 R1, R6 @RW6+d8 XCH R0, XCH XCH R1, @RW5+d8 R1, R5 @RW5+d8 XCH R0, XCH XCH R1, @RW4+d8 R1, R4 @RW4+d8 XCH R0, XCH XCH R1, @RW3+d8 R1, R3 @RW3+d8 60 XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH @RW0+d16 R1, @RW0 @RW0+d16 R2, @RW0 @RW0+d16 R3, @RW0 @RW0+d16 R4, @RW0 @RW0+d16 R5, @RW0 R0, R7 R0, R6 R0, R5 R0, R4 R0, R3 XCH XCH 50 XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R2, R0 R3, R0 R4, R0 R5, R0 @RW0+d8 R6, R0 @RW0+d8 R7, R0 @RW0+d8 @RW0+d8 @RW0+d8 @RW0+d8 40 XCH XCH R0, @RW0 XCH XCH XCH XCH XCH XCH R0, XCH XCH R1, @RW2+d8 R1, R2 @RW2+d8 R0, R2 XCH XCH R1, @RW0+d8 XCH R0, XCH XCH R1, R0, R1 @RW1+d8 R1, R1 @RW1+d8 R1, R0 20 XCH XCH R0, R0 10 XCH R0, @RW0+d8 +8 +7 +6 +5 +4 +3 +2 +1 +0 00 XCH Table B.3.1s CH Ri, ea (First byte = 7EH) B.3 Instruction Map MB90580 Series MB90580 Series XCHW RW2, XCHW @RW6+d8 RW3, RW6 XCHW RW2, XCHW @RW7+d8 RW3, RW7 XCHW XCHW RW0, XCHW XCHW RW1, XCHW RW0, RW6 @RW6+d8 RW1, RW6 @RW6+d8 RW2, RW6 XCHW XCHW RW0, XCHW XCHW RW1, XCHW RW0, RW7 @RW7+d8 RW1, RW7 @RW7+d8 RW2, RW7 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, @RW0 @RW0+d16 RW1, @RW0 @RW0+d16 RW2, @RW0 @RW0+d16 RW3, @RW0 @RW0+d16 RW4, @RW0 @RW0+d16 RW5, @RW0 @RW0+d16 RW6, @RW0 @RW0+d16 RW7, @RW0 @RW0+d16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, @RW1 @RW1+d16 RW1, @RW1 @RW1+d16 RW2, @RW1 @RW1+d16 RW3, @RW1 @RW1+d16 RW4, @RW1 @RW1+d16 RW5, @RW1 @RW1+d16 RW6, @RW1 @RW1+d16 RW7, @RW1 @RW1+d16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, @RW2 @RW2+d16 RW1, @RW2 @RW2+d16 RW2, @RW2 @RW2+d16 RW3, @RW2 @RW2+d16 RW4, @RW2 @RW2+d16 RW5, @RW2 @RW2+d16 RW6, @RW2 @RW2+d16 RW7, @RW2 @RW2+d16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, @RW3 @RW3+d16 RW1, @RW3 @RW3+d16 RW2, @RW3 @RW3+d16 RW3, @RW3 @RW3+d16 RW4, @RW3 @RW3+d16 RW5, @RW3 @RW3+d16 RW6, @RW3 @RW3+d16 RW7, @RW3 @RW3+d16 XCHW R XCHW RW0, XCHW R XCHW RW1, XCHW R XCHW RW2, XCHW R XCHW RW3, XCHW R XCHW RW4, XCHW R XCHW RW5, XCHW R XCHW RW6, XCHW R XCHW RW7, W0, @RW0+ @RW0+RW7 W1, @RW0+ @RW0+RW7 W2, @RW0+ @RW0+RW7 W3, @RW0+ @RW0+RW7 W4, @RW0+ @RW0+RW7 W5, @RW0+ @RW0+RW7 W6, @RW0+ @RW0+RW7 W7, @RW0+ @RW0+RW7 XCHW R XCHW RW0, XCHW R XCHW RW1, XCHW R XCHW RW2, XCHW R XCHW RW3, XCHW R XCHW RW4, XCHW R XCHW RW5, XCHW R XCHW RW6, XCHW R XCHW RW7, W0, @RW1+ @RW1+RW7 W1, @RW1+ @RW1+RW7 W2, @RW1+ @RW1+RW7 W3, @RW1+ @RW1+RW7 W4, @RW1+ @RW1+RW7 W5, @RW1+ @RW1+RW7 W6, @RW1+ @RW1+RW7 W7, @RW1+ @RW1+RW7 XCHW R XCHW RW0, XCHW R XCHW RW1, XCHW R XCHW RW2, XCHW R XCHW RW3, XCHW R XCHW RW4, XCHW R XCHW RW5, XCHW R XCHW RW6, XCHW R XCHW RW7, W0, @RW2+ @PC +d16 W1, @RW2+ @PC+d16 W2, @RW2+ @PC+d16 W3, @RW2+ @PC+d16 W4, @RW2+ @PC+d16 W5, @RW2+ @PC+d16 W6, @RW2+ @PC+d16 W7, @RW2+ @PC+d16 XCHW R XCHW RW0, XCHW R XCHW RW1, XCHW R XCHW RW2, XCHW R XCHW RW3, XCHW R XCHW RW4, XCHW R XCHW RW5, XCHW R XCHW RW6, XCHW R XCHW RW7, W0, @RW3+ addr16 W1, @RW3+ addr16 W2, @RW3+ addr16 W3, @RW3+ addr16 W4, @RW3+ addr16 W5, @RW3+ addr16 W6, @RW3+ addr16 W7, @RW3+ addr16 +6 +7 +8 +9 +A +B +C +D +E +F XCHW RW3, XCHW @RW7+d8 RW4, RW7 XCHW RW3, XCHW @RW6+d8 RW4, RW6 XCHW RW3, XCHW @RW5+d8 RW4, RW5 XCHW RW4, XCHW @RW7+d8 RW5, RW7 XCHW RW4, XCHW @RW6+d8 RW5, RW6 XCHW RW4, XCHW @RW5+d8 RW5, RW5 XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, @RW7+d8 RW6, RW7 @RW7+d8 RW7, RW7 @RW7+d8 XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, @RW6+d8 RW6, RW6 @RW6+d8 RW7, RW6 @RW6+d8 XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, @RW5+d8 RW6, RW5 @RW5+d8 RW7, RW5 @RW5+d8 XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, @RW4+d8 RW6, RW4 @RW4+d8 RW7, RW4 @RW4+d8 XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, @RW3+d8 RW6, RW3 @RW3+d8 RW7, RW3 @RW3+d8 XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, @RW2+d8 RW6, RW2 @RW2+d8 RW7, RW2 @RW2+d8 XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, @RW1+d8 RW6, RW1 @RW1+d8 RW7, RW1 @RW1+d8 XCHW RW2, XCHW @RW5+d8 RW3, RW5 XCHW RW4, XCHW @RW4+d8 RW5, RW4 XCHW RW4, XCHW @RW3+d8 RW5, RW3 XCHW RW4, XCHW @RW2+d8 RW5, RW2 XCHW RW4, XCHW @RW1+d8 RW5, RW1 XCHW XCHW RW0, XCHW XCHW RW1, XCHW RW0, RW5 @RW5+d8 RW1, RW5 @RW5+d8 RW2, RW5 XCHW RW3, XCHW @RW4+d8 RW4, RW4 XCHW RW3, XCHW @RW3+d8 RW4, RW3 XCHW RW3, XCHW @RW2+d8 RW4, RW2 XCHW RW3, XCHW @RW1+d8 RW4, RW1 +5 F0 XCHW RW2, XCHW @RW4+d8 RW3, RW4 E0 XCHW XCHW RW0, XCHW XCHW RW1, XCHW RW0, RW4 @RW4+d8 RW1, RW4 @RW4+d8 RW2, RW4 D0 +4 C0 XCHW RW2, XCHW @RW3+d8 RW3, RW3 B0 XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, @RW0+d8 RW6, RW0 @RW0+d8 RW7, RW0 @RW0+d8 XCHW XCHW RW0, XCHW XCHW RW1, XCHW RW0, RW3 @RW3+d8 RW1, RW3 @RW3+d8 RW2, RW3 A0 +3 90 XCHW RW4, XCHW @RW0+d8 RW5, RW0 XCHW RW2, XCHW @RW2+d8 RW3, RW2 80 XCHW XCHW RW0, XCHW XCHW RW1, XCHW RW0, RW2 @RW2+d8 RW1, RW2 @RW2+d8 RW2, RW2 70 XCHW RW3, XCHW @RW0+d8 RW4, RW0 +2 60 XCHW RW2, XCHW @RW1+d8 RW3, RW1 50 XCHW XCHW RW0, XCHW XCHW RW1, XCHW RW0, RW1 @RW1+d8 RW1, RW1 @RW1+d8 RW2, RW1 40 +1 30 +0 20 XCHW RW2, XCHW @RW0+d8 RW3, RW0 10 XCHW XCHW RW0, XCHW XCHW RW1, XCHW RW0, RW0 @RW0+d8 RW1, RW0 @RW0+d8 RW2, RW0 00 Table B.3.1t XCHW RWi, ea (First byte = 7FH) B.3 Instruction Map APPENDIX B: Instructions 355 Appendix C: The Flash Memory in the MB90F583 C.1 Outline There is a 1M-bit Flash memory (128K word x 8/64K word x 16) located at the FE~FF bank of the CPU memory map in MB90F583. With the flash memory interface circuit, it is possible for read access from and program access to the CPU. Programming or erasing the flash memory are done by the CPU operation instruction through the flash memory interface circuit. Therefore, with proper CPU control software, it is possible re-programming the flash memory of on-board MB90F583. That means changing of the data in the flash memory of on-board MB90F583 can be done. • Features 128K word x 8/64K word x 16 bit (16K+8K+8K+32K+64K sector architecture) Compatible with JEDEC standard command Automatic Algorithm (Embedded TM Algorithm: same as MBM29F400TA) - Automatic Program Algorithm - Automatic Erase Algorithm Sector Erase Suspend/Sector Erase Resume function available Program/Erase cycle completion can be detected by data polling, toggle bit and CPU interrupt Sector erase function (any combination of sector) Number of programming/erasing: 10,000 times (minimum) Note: EmbeddedTM Algorithm is trademarks of Advanced Mirco device, Inc. • Program/Erase operation The flash memory of MB90F583 cannot be programmed and read in the same time. When programming or erasing the flash memory, the programming data will be copied to the RAM first; and then executing programming or erasing the flash memory in the RAM. This keeps programming and erasing the flash memory as simple as a writing operation. • Register Flash Control Register (FMCS) 7 Address: 0000AEH Read/write Initial value 6 5 4 INTE RDYINT WE RDY (R/W) (0) (R/W) (0) (R/W) (0) (W) (X) 3 2 Reserved LPM1 (W) (0) (R/W) (0) 1 0 Reserved LPM0 (W) (0) (R/W) (0) Bit Number FMCS C.2 Sector Structure of 1M Bit Flash Memory C.2 Sector Structure of 1M Bit Flash Memory Sector structure of 1M bit flash memory in MB90F583 is shown in Figure C.2a. The address in the Figure C.2a shows upper and lower address of each sector. When accessing from CPU, SA0 is set in the FE bank register and SA1~4 are set in the FF Bank register. Flash Memory CPU Address Programmer Address* FFFFFFH 7FFFFFH FFC0000H FFBFFFFH 7FC0000H 7FBFFFFH FFA0000H FF9FFFFH 7FA0000H 7F9FFFFH FF80000H FF7FFFFH 7F80000H 7F7FFFFH FF00000H FEFFFFH 7F00000H 7EFFFFH FEFFFFH 7EFFFFH SA4 (16K Bytes) SA3 (8K Bytes) SA2 (8K Bytes) SA1 (32K Bytes) SA0 (64K Bytes) *Programmer address: The programmer address is equivalent to the CPU address map where data is programmed to or erased from flash memory by the parallel writer (Minato Electronic: Model 1890A). When programmed to or erased from the flash memory by a general-purpose programmer, this address is needed to specified. Figure C.2a Sector structure of 1M bit flash memory 358 Appendix C: The Flash Memory in the MB90F583 MB90580 Series C.3 Flash Control Register (FMCS) C.3 Flash Control Register (FMCS) Flash control register (FMCS) is a register which is used during programming or erasing the flash memory. Flash Control Register (FMCS) 7 Address: 0000AEH Read/write Initial value 6 5 4 INTE RDYINT WE RDY (R/W) (0) (R/W) (0) (R/W) (0) (W) (X) 3 2 Reserved LPM1 (W) (0) (R/W) (0) 1 0 Reserved LPM0 (W) (0) Bit Number FMCS (R/W) (0) [bit 7] INTE (INTerrupt Enable) This bit is used to enable an interrupt to the CPU when the operation of programming/erasing the flash memory is completed. An interrupt to the CPU will be generated when the INTE bit is “1” and the RDYINT bit is a “1”. When the INTE bit is “0”, an interrupt will not be generated. INTE Interrupt Enable 0 Interrupt enable when program/erase cycle is completed 1 Interrupt disable when program/erase cycle is completed [bit 6] RDYINT (ReaDY INTerrupt) This bit is used to show the programming/erasing operation status of the flash memory. This bit will be set to “1” when the flash memory program/erase cycle is completed. After flash memory program/erase cycle is completed and the bit is still “0”, programing/erasing the flash memory is not allowed. Only when this bit is changed to “1”, programming/erasing the flash memory is allowed. Writing “0” will clear this bit to “0” and writing “1” to this bit will be ignored. When Automatic Algorithm (refer to Section C.4, Automatic Algorithm Initiation Method) is completed, this bit will be set to “1”. “1” is always read when read modify write (RWM) is operated. RDYINT Ready interrupt 0 Programming/Erasing operation is on-going 1 Programming/Erasing operation is completed (interrupt request generated) [bit 5] WE (Write Enable) This bit is “write enable” for the flash memory. When this bit is set to “1”, the flash memory can be programed/erased right after the command sequence to FE~FF bank is issued. Furthermore, this bit is used to start the command for programming/erasing the flash memory. It is recommended to always keep this bit set to “0”, so that the flash memory will not be programmed or erased accidentally. WE Write Enable 0 Disable programming/erasing flash memory 1 Enable programming/erasing flash memory MB90580 Series Appendix C: The Flash Memory in the MB90F583 359 C.3 Flash Control Register (FMCS) [bit 4] RDY (ReaDY) This bit is used to indicate whether the flash memory is ready for programming/erasing. When this bit is set to “0”, programming or erasing the flash memory is not allowed. However, it is possible to issue read/reset command and sector erase suspend command when this bit is “0”. RDY Ready 0 Programming/erasing is operating 1 Programming/erasing is completed (next data programming/erasing is enabled. [bit 3] Reserved bit This bit is reserved. It is recommended to always set this bit to “0” during normal operation. [bit 0] Reserved bit This bit is reserved. It is recommended to always set this bit to “0” during normal operation. [bit 2, 0] LPM1, LPM0 (Low Power Mode) When accessing flash memory, these two bits are used to control the power consumption of the flash memory. This bit cannot be set to “00”. After reset, these bit must be set to “01”, “10” or “11”. Since the flash memory access time by the CPU will be changed according to the frequency of the operating clock, it is recommended to set these bit according to the operating clock frequency of the CPU. LMP0 LMP1 Low Power Mode 0 0 Initial value (Access prohibited) 0 1 Low power mode (Internal operation frequency < 4 MHz) 1 0 Low power mode (Internal operation frequency < 8 MHz) 1 1 Low power mode (Internal operation frequency < 16 MHz) Note: RDYINT bit and RDY bit cannot be changed in the same time. Either one of these two bits should be changed when writing the control software. Automatic program algorithm is completed RDYINT bit RDY bit 1 machine cycle Figure C.3a Timing of RDYINT and RDY 360 Appendix C: The Flash Memory in the MB90F583 MB90580 Series C.4 Automatic Algorithm Initiation Method C.4 Automatic Algorithm Initiation Method To start the Automatic Algorithm in the flash memory, there are five types of commands, 2 types of read/reset, programming, chip erase and sector erase. For sector erase, there are the sector erase suspend and the sector erase resume command. Table C.4a shows the commands used during programming/erasing the flash memory. Although the data shown in the command are all in byte, it is necessary to use word access to write the data. At this time, the upper byte of the data will be ignored. Table C.4a Command Sequence Definitions Bus Write Cycle Req’d 1st Bus Write Cycle Read/Reset* 1 Read/Reset* Command Sequence Addr Data 2nd Bus Write Cycle 3rd Bus Write Cycle 4th Bus Write Cycle 5th Bus Write Cycle 6th Bus Write Cycle Addr Data Addr Data Addr Data Addr Data Addr Data FxXXXX XXF0 — — — — — — — — — — 3 FxAAAA XXAA Fx5554 XX55 FxAAAA XXF0 RA RD — — — — Programming 4 FxAAAA XXAA Fx5554 XX55 FxAAAA XXA0 PA (even) PD (word) — — — — Chip Erase 6 FxAAAA XXAA Fx5554 XX55 FxAAAA XX80 FxAAAA XXAA Fx5554 XX55 FxAAAA XX10 Sector Erase 6 FxAAAA XXAA Fx5554 XX55 FxAAAA XX80 FxAAAA XXAA Fx5554 XX55 Sector Erase Suspend Sector erase is suspend by inputting the address “FxXXXX”, data “xxB0H” Sector Erase Resume Sector erase is resumed by inputting the address “FxXXXX”, data “xx30H” SA (even) XX30 Note: The address Fx in Table C.4a is either FE or FF for MB90F583. When using above commands, the accessible bank value for the device must be used to replaced Fx The address found in the Table C.4a is corresponding to the CPU memory address. All address and data written in hexadecimal and “X” is arbitrary value. RA: Read address PA: Program address , only even number address can be selected SA: Sector address, refer to Section C.2, Sector Structure of 1M Bit Flash Memory. RD: Read data PD: program data, only word data can be selected * : The 2 types of read/reset command can be reset the flash memory to read mode. MB90580 Series Appendix C: The Flash Memory in the MB90F583 361 C.5 Execution Status of Automatic Algorithm In the flash memory, the programming or erasing can be done by Automatic Algorithm, so that there is a Hardware Sequence Flag in the flash memory, which indicates the operation status and the operation completion. In the Automatic Algorithm, internal flash memory operation status can be checked by the hardware sequence flag which will be discussed in this section. • Hardware Sequence Flag Hardware Sequence Flag consists of 4 flags, DQ7 (Data polling flag), DQ6 (Toggle bit flag), DQ5 (Exceeded timing limits flag) and DQ3 (Sector erase timer flag). These flag are used to check whether the programming or erasing the flash memory is completed and whether erase code are valid. Hardware sequence flag is a checking point when performing read access to the address of the sector in the flash memory and after issuing the command sequence (see Table C.4a). Table C.5a shows the bit assignment of the hardware sequence flag. Table C.5a Hardware sequence flag’s bit assignment Bit number 7 6 5 4 3 2 1 0 Hardware sequence Flag DQ7 DQ6 DQ5 — DQ3 — — — To check whether the Automatic Program/Erase Algorithm is under processing, it can be determined by either checking the hardware sequence flag or RDY bit of the flash control register (FMCS). After programming/erasing operation is completed, the flash memory will return to read/reset status. When making a control software, it is necessary to check the Automatic Program/Erase Algorithm completion by either the hardware sequence flag or RDY bit of the flash control register (FMCS) before going to other process such as reading data. It is also possible to check the next and the following sector erase code issued is valid by the hardware sequence flag. Table C.5b shows the function of each hardware sequence flag. Table C.5b Hardware Sequence Flag Status Status Change in normal operation Abnormal Operation DQ7 DQ6 DQ5 DQ3 Programming → Programming complete (When program address is indicated) DQ7 → DATA:7 Toggle → DATA:6 0 → DATA:5 0 → DATA:3 Chip/Sector erase → Erase is completed 0→1 Toggle → Stop 0→1 1 0 Toggle 0→1 1 0→1 Toggle → 1 0 1→0 Sector erase suspend → Sector erase resume (Sector being erased) 1→0 1 → Toggle 0 0→1 Sector erase suspend is in progress (Sector not being erased) DATA:7 DATA:6 DATA:5 DATA:3 Programming operation DQ7 Toggle 1 0 Chip/Sector erase 0 Toggle 1 1 Sector erase wait → Erase start Sector erase → Sector erase suspend (Sector being erased) C.5 Execution Status of Automatic Algorithm C.5.1 Data polling flag (DQ7) Data polling flag is used to indicate whether the Automatic Algorithm is executing or completed by using data polling function. Table C.5.1a shows the status change of the data polling flag. • Programming During Automatic Program Algorithm is executing, an attempt to read the flash memory will output the complement of the last written data to DQ7, rather than the value at the address specified by the current address signal. • Chip/Sector Erase During chip erase/sector erase operation is in progress, an attempt to read the flash memory will output “0” to DQ7. Upon completion of chip erase/sector erase, an attempt to read the flash memory will output “1” to DQ7. • Sector Erase Suspend During sector erase suspend is in progress, an attempt to read the flash memory will output “1” to DQ7, if the address is within the sector which is being erased. If the address is not within the sector being erased, the flash memory will output bit 7 (DATA:7) of the read value of the address which is pointed. By looking at the toggle bit flag (DQ6) together, it is possible to know whether the present sector is in sector erase suspend mode, or to know which sector is being erased. Note: An attempt to read access to the address where Automatic Algorithm is starting will be ignored. After receiving the completion status of data polling flag (DQ7), an attempt to read access will be allowed. Hence, a read access from Automatic Algorithm completion should be done after the read access of the data polling completion. Table C.5.1a Status Change of data polling flag (DQ7) • Status Change in normal operation Operation Programming Chip/sector erase Sector erase wait status → complete → complete → start DQ7 → DATA:7 DQ7 • 0→1 0 Sector erase Sector erase suspend → suspend → resume (Sector being (Sector being erased) erased) 0→1 1→0 Sector erase being suspended (Sector not being erased) DATA:7 Status Change in abnormal operation Operation Status Programming Operation Chip/sector erase operation DQ7 DQ7 0 MB90580 Series Appendix C: The Flash Memory in the MB90F583 363 C.5 Execution Status of Automatic Algorithm C.5.2 Toggle bit flag (DQ6) Toggle bit flag is used to indicate whether the Automatic Algorithm is in progress or is completed by using toggle bit function. Table C.5.2a shows status change of the toggle bit flag. • Programming, Chip and Sector Erase During Automatic Program or Erase Algorithm, successive attempts to read access to the flash memory will result in toggling DQ6 between “1” and “0”. When Automatic Program Algorithm and Automatic Chip/Sector Erase Algorithm is completed and continuous read access is attempted, the flash memory will stop the DQ6 toggling and output the value of bit 6 of the address specified by the current address signals. • Sector Erase Suspend When an attempt to read access in sector erase suspend mode, read value will be “1” if the address is specified within the sector being sector erased. If the specified address is not within to the sector being sector erased, the flash memory will output the value of bit 6 of the address specified by the current address signals. Note: In programming operation, if the sector to be programmed is write-protected, the DQ6 will be toggled for about 2 µS and then stop toggling without having the data change. In erasing operation, if all sectors are write-protected, the DQ6 will be toggled for about 100 µS and then go back into read/reset mode without having the data change. Table C.5.2a Status Change of toggle bit flag (DQ6) • Status Change in normal operation Operation Programming Chip/sector erase Sector erase wait status → complete → complete → start Toggle → DATA:6 DQ6 • Toggle → Stop Toggle → 1 1 → Toggle Sector erase being suspended (Sector not being erased) DATA:6 Status Change in abnormal operation Operation Status Programming Operation Chip/sector erase operation DQ6 Toggle Toggle 364 Toggle Sector erase Sector erase suspend → suspend → resume (Sector being (Sector being erased) erased) Appendix C: The Flash Memory in the MB90F583 MB90580 Series C.5 Execution Status of Automatic Algorithm C.5.3 Exceeded timing limits flag (DQ5) Exceeded timing limits flag is used to indicate whether Automatic Algorithm has executed beyond the time (internal pulse count) specified in the flash memory. Table C.5.3a shows status change of the exceeded timing limits flag. • Programming, Chip and Sector Erase An attempt to read access after programming or chip/sector erase operation will output “0” to DQ5 if Automatic Algorithm has executed within the time (internal pulse count) specified in the flash memory. If it is beyond the limit, “1” will be output to DQ5. With irrespective of he Automatic Algorithm operation status, It is used to determine whether the program/erase operation has suceeded. Thus, when “1” is read, it shows that programming or erasing operation is failed if Automatic Algorithm is regarded as still being executed by data polling function or toggle bit function. For an example, If the user tries to write “1” to the flash memory address where “0” is written, a failure will occur. In this case, flash memory will be locked and Automatic Algorithm will not be completed. Consequently, valid data will not be outputted from the data polling flag (DQ7). In the case of toggle bit flag (DQ6), the toggle operation on bit 6 will not stopped and bit 5 output “1” to the exceeded timing limits flag (DQ5). It means that the flash memory is not defective and it has been used incorrectly. The operation will return to normal after executing a reset command. Table C.5.3a Status Change of exceeded timing limits flag (DQ5) • Status Change in normal operation Operation Programming Chip/sector erase Sector erase wait status → complete → complete → start 0 → DATA5 DQ5 • 0→1 0 Sector erase Sector erase suspend → suspend → resume (Sector being (Sector being erased) erased) 0 0 Sector erase being suspended (Sector not being erased) DATA:5 Status Change in abnormal operation Operation Status Programming Operation Chip/sector erase operation DQ5 1 1 MB90580 Series Appendix C: The Flash Memory in the MB90F583 365 C.5 Execution Status of Automatic Algorithm C.5.4 Sector erase timer flag (DQ3) Sector erase timer flag is used to indicate whether the Automatic Algorithm is executed beyond the sector erase wait time after the sector erase command is issued. Table C.5.4a shows status change of the sector erase timer flag. • During sector erase operation An attempt to read access after sector erase command is issued will output “0” to DQ3 if Automatic Algorithm is executed within the sector erase wait time. “1” will be output to DQ3 if the Automatic Algorithm is executed beyond the sector erase wait time. If the data polling flag or toggle bit flag indicates that the Automatic Erase Algorithm is operating and DQ3 is “1”, internally controlled erasing is started. Attempts to issue erase code and command other than sector erase suspend to the sector will be ignored until the erasing is completed. When DQ3 is “0”, issuing the additional sector erase code will be accepted. To ensure the command has been accepted, the control software should check the status of DQ3 prior to each subsequent sector erase command. If DQ3 was “1” on the status checking, the command may not be accepted. • During sector erase suspend When read accessing during sector erase suspend, “1” will be output to DQ3 if the specified address is within the sector which is being erased. If it does not within the sector being erased, the flash memory will output the value of bit 3 (DATA:3) at the address specified by the current address signals. Table C.5.4a Status Change of sector erase timer flag (DQ3) • Status Change in normal operation Operation Programming Chip/sector erase Sector erase wait status → complete → complete → start 0 → DATA:3 DQ3 • 1 1→0 0→1 Sector erase being suspended (Sector not being erased) DATA:3 Status Change in abnormal operation Operation Status Programming Operation Chip/sector erase operation DQ3 0 1 366 0→1 Sector erase Sector erase suspend → suspend → resume (Sector being (Sector being erased) erased) Appendix C: The Flash Memory in the MB90F583 MB90580 Series C.6 Details of Flash Memory Programming/Erasing C.6 Details of Flash Memory Programming/Erasing This section describes the following: command generated for initiating Automatic Algorithm, read/reset of flash memory, programming, chip erase, sector erase suspend and sector erase resume. Flash memory can execute Automatic Algorithm when repeating the bus write cycle in read/reset, programming, chip erase, sector erase, sector erase suspend and sector erase resume command sequence. The bus write cycle must be sent continuously. Completion of the Automatic Algorithm can be determined by checking the hardware sequence flag such as data polling function. If it is completed correctly, the flash memory will return to read/reset status. C.6.1 Read/reset status This section describes how to isssue read/reset command to make flash memory returning to read/reset status. To make the flash memory returning to read/reset status, the command sequence of the read/reset command found in command sequence table (refer to Section C.4, Automatic Algorithm Initiation Method, Table C.4a) can be used and it needs to be continuously sent to the target sector in the flash memory. There are two kinds of bus write cycles in read/reset command, 1 and 3 bus write cycles, but there are no significant difference between them. Since read/reset is the initial state, the flash memory will always go to this state when power-on and any command is correctly implemented. Read/reset status is a waiting state for other command. Normal read access can be done in the read/reset status. Programming access is possible from the CPU. This command is not necessary for reading data in normal read access. This command is used when the operation is not completed correctly for some reasons, or when automatic algorithm needs to be reseted. MB90580 Series Appendix C: The Flash Memory in the MB90F583 367 C.6 Details of Flash Memory Programming/Erasing C.6.2 Data Programming This section will describe how to issue the programming command to program the flash memory. To initiate Automatic Program Algorithm in the flash memory, the programming command found in command sequence table (refer to Section C.4, Automatic Algorithm Initiation Method, Table C.4a) can be used and it needs to be sent continuously to the target sector in the flash memory. Automatic Algorithm will be initiated and automatic programming will start when data programming to the target address is completed at the 4th cycle. • Specifying Address Specified programming address must be even number. It is not possible to program correctly on odd numbered addresses, so that it is necessary to program by word data unit with the even numbered address. Programming can be done in any address and can go over sector boundary. However, only one word can be programmed with a single programming command. • Precautions on Data Programming It is impossible to program data from "1" to "0". When programming data from "1" to "0", data polling function (DQ7) and toggle bit function (DQ6) will not be completed. In this case, either the flash memory is considered to have error and programming timing limit will exceed making the exceeded timing limits flag (DQ5) to output an error, or "1" will be assumed to have been programmed. When reading data in the read/reset status, the data remains "0". Only erase operation can change data from "0" to "1". While automatic programming the flash memory is under processing, all other command will be ignored. If hardware reset is initiated during programming, take a good care on it. It is because the data being programmed to the address will not be guaranteed. • Data Programming Procedure Figure C.6.2a shows the example procedure of programming the flash memory. By checking the hardware sequence flag (refer to Section C.5, Execution Status of Automatic Algorithm), the status of Automatic Algorithm in flash Memory can be determined. Data polling flag (DQ7) is used to check whether programming is completed. The data read from DQ7 is the data found in the next programming address. It is necessary to re-check the data polling flag bit (DQ7) even if the exceeded timing limits flag (DQ5) is "1". It is because data polling flag (DQ7) and the exceed time limit flag (DQ5) will change in the same time. Furthermore, it is not need to re-check the toggle bit flag(DQ6) since it will stop at the same time when exceeded timing limits flag (DQ5) changes to "1". 368 Appendix C: The Flash Memory in the MB90F583 MB90580 Series C.6 Details of Flash Memory Programming/Erasing Start Enable Flash memory write FMCS:WE (bit 5) Write command sequence (1) FxAAAA ← XXAA ← XX55 (2) Fx5555 (3) FxAAAA ← XXA0 (4) Write addr ← Write data Next address Internal address read Data polling (DQ7) Data Data 0 Time limits (DQ5) 1 Internal address read Data Data polling (DQ7) Data Last Address No Yes Disable Flash memory write FMCS:WE (bit 5) Checking hardware sequence flag Error Stop Figure C.6.2a Example procedure of programming the flash memory MB90580 Series Appendix C: The Flash Memory in the MB90F583 369 C.6 Details of Flash Memory Programming/Erasing C.6.3 Chip Erase This section will describe how to issue the chip erase command to erase the whole chip. To erase all data from the flash memory, the chip erase command found in command sequence table (refer to Section C.4, Automatic Algorithm Initiation Method, Table C.4a) can be used and needs to be send continuously to the target address in the flash memory. Chip erase command is executed by six bus write cycles. Chip erase operation will start after 6th bus write cycle is finished. It is no necessary for the user to program the flash memory before erasing the chip. During Automatic Erase Algorithm execution, flash Memory will automatically write "0" to all bits before chip erase is operated. C.6.4 Sector Erase This section will describe how to issue the sector erase command to erase any sector in the flash memory. Single sector or multiple sector can be erased in the same time. To erase a sector in the flash Memory, the sector erase command found in command sequence table (refer to Section C.4, Automatic Algorithm Initiation Method, Table C.4a) can be used and needs to be sent continuously to the target sector in the flash memory. • Specifying sector Sector erase command is executed by six bus write cycles. 50 µS of sector erase wait time will be started after issuing sector erase code (30H) to the accessible even numbered address of the sector in the 6th bus write cycle. When erasing several sectors in the same time, the erase code (30H) to the address of sectors to be erased needs to be issued. • Precautions on Specifying Multiple Sectors Sector erase operation will be started when the 50 µS of sector erase wait time is completed after the last sector erase code is issued. When erasing several sectors, it is necessary to input the address and the erase code of the following sector to erase in the 50 µS of sector erase wait time. However, the sector erase operation may not be accepted even after this wait time. It is necessary to check the sector erase timer flag (DQ3) to ensure whether the sector erase code issued was valid. At this time, the address to read the sector erase timer flag (DQ3) should be specified to the sector to be erased. • Sector Erase Procedure By checking hardware sequence flag, the status of Automatic Algorithm in flash memory can be determined (refer to 1.5 Automatic algorithm execution status). Figure C.6.4a shows the example procedure of sector erase in the Flash Memory. In this example procedure, the toggle bit flag (DQ6) is used to check erase completion Take note that the data read for DQ6 is the data in the sector that will be erased. It is not necessary to check the data polling flag (DQ7) even if the exceeded timing limits flag (DQ5) is "1". It is because data polling flag (DQ7) will change at the same time the exceed timing limits flag (DQ5) is changed. Furthermore, it is necessary to re-check the toggle bit flag (DQ6) since it will stop at the same time exceeded timing limits flag (DQ5) changes to "1". 370 Appendix C: The Flash Memory in the MB90F583 MB90580 Series C.6 Details of Flash Memory Programming/Erasing Start Enable Flash memory erase FMCS:WE (bit 5) Erase command sequence (1) FxAAAA ← XXAA ← XX55 (2) Fx5555 (3) FxAAAA ← XX80 ← XX55 (4) Fx5554 (5) sector addr ← Erase code (30H) 1 Sector erase time (DQ3) 0 (6) Input code to erase sector (30H) Internal address read Yes any other erase sector No Internal address read 1 Internal address read 2 Toggle bit (DQ6) Data1 (DQ6) = Data2 (DQ6) Yes No 0 Next sector Time limits flag (DQ5) 1 Internal address read 1 Internal address read 2 No Toggle bit (DQ6) Data1 (DQ6) = Data2 (DQ6) Yes No Last Sector Yes Disable Flash memory Erase FMCS:WE (bit 5) Error Finish Checking hardware sequence flag Figure C.6.4a Example flowchart of erasing flash memory MB90580 Series Appendix C: The Flash Memory in the MB90F583 371 C.6 Details of Flash Memory Programming/Erasing C.6.5 Suspend Sector Erase This section will describe how to issue the sector erase suspend command to suspend sector erase operation in the flash memory. During sector erase, it is possible to read data from the sector which is not being erased. To suspend sector erase in flash memory, the sector erase suspend command found in command sequence table (refer to Section C.4, Automatic Algorithm Initiation Method, Table C.4a) can be used and needs to be sent continuously to the target sector in the flash memory. During sector erase suspend command is executing, it is possible to read data from the sector that is not being erased. This enables only reading from the sector but it is not possible to programming the sector. This command is valid only during sector erasing time including the erase wait time, However, this command will be ignored when chip erase is operating or programming is operated. It will be implemented by issuing erase suspend code (B0H) to the flash memory. The address will be specified to any address within the Flash Memory. Sector erase suspend command will be ignored during another erase suspend command. If the sector erase suspend command is issued during sector erase wait, sector erase wait will be ended suddenly and sector erase will be suspended. If sector erase suspend command is issued when sector erase is operating after sector erase wait, it will go to sector erase suspend status after maximum of 15 µS. C.6.6 Resume Sector Erase This section will describe how to issue the sector erase resume command to restart the suspended sector erase in the flash memory. To restart the suspended sector erase, the sector erase resume command found in command sequence table (refer to Section C.4, Automatic Algorithm Initiation Method, Table C.4a) can be used and needs to be sent continuously to the target sector in the flash memory. Sector erase resume command is used to restart the sector erase operation form sector erase suspend status. It will be implemented by issuing the sector erase resume code (30H) to the flash memory. The address can be specified to any address within the flash memory. Sector erase resume command will be ignored during sector erase is operating. 372 Appendix C: The Flash Memory in the MB90F583 MB90580 Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9806 FUJITSU LIMITED Printed in Japan Known bugs in HM MB90580 1. Chapter 20.4.5 Output Compare Unit ===================================== The documentation refers to outputs OUT0/1 and OUT2/3. There does not exist OUT2 and OUT3 (see pinning). So compare register 0 corresponds to OUT0 only and compare register 1 to OUT1. last updated : 05-03-98 TKa