SN74CBT3384A 10-BIT FET BUS SWITCH SCDS004I – NOVEMBER 1992 – REVISED MAY 1998 D D D D DB, DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW) Functionally Equivalent to QS3384 and QS3L384 5-Ω Switch Connection Between Two Ports TTL-Compatible Input Levels Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB, DBQ), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages 1OE 1B1 1A1 1A2 1B2 1B3 1A3 1A4 1B4 1B5 1A5 GND description The SN74CBT3384A provides ten bits of high-speed TTL-compatible bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 2B5 2A5 2A4 2B4 2B3 2A3 2A2 2B2 2B1 2A1 2OE The device is organized as two 5-bit switches with separate output-enable (OE) inputs. When OE is low, the switch is on and port A is connected to port B. When OE is high, the switch is open and a high-impedance state exists between the two ports. The SN74CBT3384A is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each 5-bit bus switch) INPUTS INPUTS/OUTPUTS 1OE 2OE 1B1–1B5 2B1–2B5 L L 1A1–1A5 2A1–2A5 L H 1A1–1A5 Z H L Z 2A1–2A5 H H Z Z logic diagram (positive logic) 1A1 1A5 1OE 2A1 2A5 2OE 3 2 11 10 1B1 1B5 1 14 15 22 23 2B1 2B5 13 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74CBT3384A 10-BIT FET BUS SWITCH SCDS004I – NOVEMBER 1992 – REVISED MAY 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 3) MIN MAX VCC VIH Supply voltage 4 5.5 High-level control input voltage 2 VIL TA Low-level control input voltage Operating free-air temperature –40 UNIT V V 0.8 V 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK II ICC ∆ICC§ Control inputs Ci Control inputs Cio(OFF) TEST CONDITIONS VCC = 4.5 V, VCC = 5.5 V, II = –18 mA VI = 5.5 V or GND VCC = 5.5 V, VCC = 5.5 V, IO = 0, One input at 3.4 V, VI = 3 V or 0 VO = 3 V or 0, VCC = 4 V, TYP at VCC = 4 V ron¶ VCC = 4.5 V MIN TYP‡ VI = VCC or GND Other inputs at VCC or GND OE = VCC MAX UNIT –1.2 V ±1 µA 3 µA 2.5 mA 4 pF 4.5 pF VI = 2.4 V, II = 15 mA 14 20 VI = 0 II = 64 mA II = 30 mA 5 7 5 7 Ω VI = 2.4 V, II = 15 mA 10 15 ‡ All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. § This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. ¶ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (A or B) terminals. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74CBT3384A 10-BIT FET BUS SWITCH SCDS004I – NOVEMBER 1992 – REVISED MAY 1998 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) VCC = 4 V VCC = 5 V ± 0.5 V MIN MIN FROM (INPUT) TO (OUTPUT) tpd† A or B B or A 0.35 ten OE A or B 6.2 tdis OE A or B 5.5 PARAMETER MAX UNIT MAX 0.25 ns 1.9 5.7 ns 2.1 5.2 ns † The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test CL = 50 pF (see Note A) Open GND 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 7V Open Output Control (low-level enabling) LOAD CIRCUIT 3V 1.5 V 0V tPZL 3V Input 1.5 V 1.5 V 0V tPLH tPHL VOH Output 1.5 V 1.5 V VOL Output Waveform 1 S1 at 7 V (see Note B) Output Waveform 2 S1 at Open (see Note B) 1.5 V tPLZ 3.5 V 1.5 V tPZH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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