SN54CBT3383, SN74CBT3383 10-BIT FET BUS-EXCHANGE SWITCHES SCDS003J – NOVEMBER 1992 – REVISED MAY 1999 D D D D SN54CBT3383 . . . JT OR W PACKAGE SN74CBT3383 . . . DB, DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW) Functionally Equivalent to QS3383 and QS3L383 5-Ω Switch Connection Between Two Ports TTL-Compatible Input Levels Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB, DBQ), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic DIPs (JT), and Ceramic Flat (W) Package BE 1B1 1A1 1A2 1B2 2B1 2A1 2A2 2B2 3B1 3A1 GND description The ’CBT3383 devices provide ten bits of high-speed TTL-compatible bus switching or exchanging. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 5B2 5A2 5A1 5B1 4B2 4A2 4A1 4B1 3B2 3A2 BX The devices operate as a 10-bit bus switch or a 5-bit bus exchanger, which provides swapping of the A and B pairs of signals. The bus-exchange function is selected when BX is high. The switches are connected when BE is low. The SN54CBT3383 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74CBT3383 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS BE BX INPUTS/OUTPUTS 1A1–5A1 1A2–5A2 L L 1B1–5B1 1B2–5B2 L H 1B2–5B2 1B1–5B1 H X Z Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54CBT3383, SN74CBT3383 10-BIT FET BUS-EXCHANGE SWITCHES SCDS003J – NOVEMBER 1992 – REVISED MAY 1999 logic diagram (positive logic) 1A1 1A2 5A1 5A2 BE BX 3 2 4 5 21 20 22 23 1B1 1B2 5B1 5B2 1 13 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54CBT3383, SN74CBT3383 10-BIT FET BUS-EXCHANGE SWITCHES SCDS003J – NOVEMBER 1992 – REVISED MAY 1999 recommended operating conditions (see Note 3) SN54CBT3383 VCC VIH Supply voltage VIL TA Low-level control input voltage High-level control input voltage SN74CBT3383 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 2 2 0.8 Operating free-air temperature –55 125 0 UNIT V V 0.8 V 70 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER SN54CBT3383 TYP† MAX TEST CONDITIONS MIN VIK II VCC = 4.5 V, VCC = 5.5 V, ICC VCC = 5.5 V, IO = 0, VI = VCC or GND VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND ∆ICC‡ Control inputs Ci Control inputs VI = 3 V or 0 VI = 2.5 V VO = 3 V or 0, VO = 2.5 V, Cio(OFF) i (OFF) ron§ II = –18 mA VI = 5.5 V or GND VCC = 4.5 V SN74CBT3383 TYP† MAX MIN –1.2 –1.2 V ±5 ±1 µA 50 50 µA 2.5 2.5 mA 3 pF 5 BE = VCC 6 BE = VCC VI = 0 pF 6 II = 64 mA II = 30 mA 5 UNIT 9.2 5 7 5 7 Ω VI = 2.4 V, II = 15 mA 10 17 10 15 † All typical values are at VCC = 5 V, TA = 25°C. ‡ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. § Measured by the voltage drop between the input terminal and the output terminal at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54CBT3383 FROM (INPUT) TO (OUTPUT) tpd¶ A or B B or A tpd BX A or B 1 10.2 ten BE A or B 1 10.8 PARAMETER MIN MAX SN74CBT3383 MIN 1.5 MAX UNIT 0.25 ns 1 9.2 ns 1 8.6 ns tdis A or B 1 8.2 1 7.5 ns BE ¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54CBT3383, SN74CBT3383 10-BIT FET BUS-EXCHANGE SWITCHES SCDS003J – NOVEMBER 1992 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 7V Open 500 Ω Output Control (low-level enabling) LOAD CIRCUIT 3V 1.5 V 0V tPZL 3V Input 1.5 V 1.5 V 0V tPLH 1.5 V 1.5 V VOL 3.5 V Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ 1.5 V tPZH VOH Output Output Waveform 1 S1 at 7 V (see Note B) tPHL 1.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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